[deliverable/linux.git] / arch / x86 / kernel / acpi / cstate.c

/*
 * Copyright (C) 2005 Intel Corporation
 * 	Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
 * 	- Added _PDC for SMP C-states on Intel CPUs
 */

#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/cpu.h>
#include <linux/sched.h>

#include <acpi/processor.h>
#include <asm/acpi.h>
#include <asm/mwait.h>
#include <asm/special_insns.h>

/*
 * Initialize bm_flags based on the CPU cache properties
 * On SMP it depends on cache configuration
 * - When cache is not shared among all CPUs, we flush cache
 *   before entering C3.
 * - When cache is shared among all CPUs, we use bm_check
 *   mechanism as in UP case
 *
 * This routine is called only after all the CPUs are online
 */
void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
					unsigned int cpu)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	flags->bm_check = 0;
	if (num_online_cpus() == 1)
		flags->bm_check = 1;
	else if (c->x86_vendor == X86_VENDOR_INTEL) {
		/*
		 * Today all MP CPUs that support C3 share cache.
		 * And caches should not be flushed by software while
		 * entering C3 type state.
		 */
		flags->bm_check = 1;
	}

	/*
	 * On all recent Intel platforms, ARB_DISABLE is a nop.
	 * So, set bm_control to zero to indicate that ARB_DISABLE
	 * is not required while entering C3 type state on
	 * P4, Core and beyond CPUs
	 */
	if (c->x86_vendor == X86_VENDOR_INTEL &&
	    (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
			flags->bm_control = 0;
}
EXPORT_SYMBOL(acpi_processor_power_init_bm_check);

/* The code below handles cstate entry with monitor-mwait pair on Intel*/

struct cstate_entry {
	struct {
		unsigned int eax;
		unsigned int ecx;
	} states[ACPI_PROCESSOR_MAX_POWER];
};
static struct cstate_entry __percpu *cpu_cstate_entry;	/* per CPU ptr */

static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];

#define NATIVE_CSTATE_BEYOND_HALT	(2)

static long acpi_processor_ffh_cstate_probe_cpu(void *_cx)
{
	struct acpi_processor_cx *cx = _cx;
	long retval;
	unsigned int eax, ebx, ecx, edx;
	unsigned int edx_part;
	unsigned int cstate_type; /* C-state type and not ACPI C-state type */
	unsigned int num_cstate_subtype;

	cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);

	/* Check whether this particular cx_type (in CST) is supported or not */
	cstate_type = ((cx->address >> MWAIT_SUBSTATE_SIZE) &
			MWAIT_CSTATE_MASK) + 1;
	edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE);
	num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;

	retval = 0;
	/* If the HW does not support any sub-states in this C-state */
	if (num_cstate_subtype == 0) {
		pr_warn(FW_BUG "ACPI MWAIT C-state 0x%x not supported by HW (0x%x)\n", cx->address, edx_part);
		retval = -1;
		goto out;
	}

	/* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */
	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
	    !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) {
		retval = -1;
		goto out;
	}

	if (!mwait_supported[cstate_type]) {
		mwait_supported[cstate_type] = 1;
		printk(KERN_DEBUG
			"Monitor-Mwait will be used to enter C-%d "
			"state\n", cx->type);
	}
	snprintf(cx->desc,
			ACPI_CX_DESC_LEN, "ACPI FFH INTEL MWAIT 0x%x",
			cx->address);
out:
	return retval;
}

int acpi_processor_ffh_cstate_probe(unsigned int cpu,
		struct acpi_processor_cx *cx, struct acpi_power_register *reg)
{
	struct cstate_entry *percpu_entry;
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	long retval;

	if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF)
		return -1;

	if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
		return -1;

	percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
	percpu_entry->states[cx->index].eax = 0;
	percpu_entry->states[cx->index].ecx = 0;

	/* Make sure we are running on right CPU */

	retval = work_on_cpu(cpu, acpi_processor_ffh_cstate_probe_cpu, cx);
	if (retval == 0) {
		/* Use the hint in CST */
		percpu_entry->states[cx->index].eax = cx->address;
		percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
	}

	/*
	 * For _CST FFH on Intel, if GAS.access_size bit 1 is cleared,
	 * then we should skip checking BM_STS for this C-state.
	 * ref: "Intel Processor Vendor-Specific ACPI Interface Specification"
	 */
	if ((c->x86_vendor == X86_VENDOR_INTEL) && !(reg->access_size & 0x2))
		cx->bm_sts_skip = 1;

	return retval;
}
EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);

void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx)
{
	unsigned int cpu = smp_processor_id();
	struct cstate_entry *percpu_entry;

	percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
	mwait_idle_with_hints(percpu_entry->states[cx->index].eax,
	                      percpu_entry->states[cx->index].ecx);
}
EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter);

static int __init ffh_cstate_init(void)
{
	struct cpuinfo_x86 *c = &boot_cpu_data;
	if (c->x86_vendor != X86_VENDOR_INTEL)
		return -1;

	cpu_cstate_entry = alloc_percpu(struct cstate_entry);
	return 0;
}

static void __exit ffh_cstate_exit(void)
{
	free_percpu(cpu_cstate_entry);
	cpu_cstate_entry = NULL;
}

arch_initcall(ffh_cstate_init);
__exitcall(ffh_cstate_exit);
Commit	Line	Data
02df8b93	1	/*
02df8b93 VP	2	* Copyright (C) 2005 Intel Corporation
	3	* Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
	4	* - Added _PDC for SMP C-states on Intel CPUs
	5	*/
	6
	7	#include <linux/kernel.h>
186f4360	8	#include <linux/export.h>
02df8b93 VP	9	#include <linux/init.h>
02df8b93 VP	10	#include <linux/acpi.h>
991528d7	11	#include <linux/cpu.h>
914e2637	12	#include <linux/sched.h>
02df8b93 VP	13
	14	#include <acpi/processor.h>
	15	#include <asm/acpi.h>
bc83cccc	16	#include <asm/mwait.h>
f05e798a	17	#include <asm/special_insns.h>
02df8b93	18
02df8b93 VP	19	/*
	20	* Initialize bm_flags based on the CPU cache properties
	21	* On SMP it depends on cache configuration
	22	* - When cache is not shared among all CPUs, we flush cache
	23	* before entering C3.
	24	* - When cache is shared among all CPUs, we use bm_check
	25	* mechanism as in UP case
	26	*
	27	* This routine is called only after all the CPUs are online
	28	*/
	29	void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
	30	unsigned int cpu)
	31	{
92cb7612	32	struct cpuinfo_x86 *c = &cpu_data(cpu);
02df8b93 VP	33
	34	flags->bm_check = 0;
	35	if (num_online_cpus() == 1)
	36	flags->bm_check = 1;
	37	else if (c->x86_vendor == X86_VENDOR_INTEL) {
	38	/*
ee1ca48f PV	39	* Today all MP CPUs that support C3 share cache.
	40	* And caches should not be flushed by software while
	41	* entering C3 type state.
02df8b93 VP	42	*/
	43	flags->bm_check = 1;
	44	}
ee1ca48f PV	45
	46	/*
	47	* On all recent Intel platforms, ARB_DISABLE is a nop.
	48	* So, set bm_control to zero to indicate that ARB_DISABLE
	49	* is not required while entering C3 type state on
	50	* P4, Core and beyond CPUs
	51	*/
	52	if (c->x86_vendor == X86_VENDOR_INTEL &&
03a05ed1	53	(c->x86 > 0xf \|\| (c->x86 == 6 && c->x86_model >= 0x0f)))
ee1ca48f	54	flags->bm_control = 0;
02df8b93	55	}
02df8b93	56	EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
991528d7 VP	57
	58	/* The code below handles cstate entry with monitor-mwait pair on Intel*/
	59
5d65131f	60	struct cstate_entry {
991528d7 VP	61	struct {
	62	unsigned int eax;
	63	unsigned int ecx;
	64	} states[ACPI_PROCESSOR_MAX_POWER];
	65	};
bd126b23	66	static struct cstate_entry __percpu cpu_cstate_entry; / per CPU ptr */
991528d7 VP	67
	68	static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
	69
991528d7 VP	70	#define NATIVE_CSTATE_BEYOND_HALT (2)
991528d7 VP	71
c74f31c0	72	static long acpi_processor_ffh_cstate_probe_cpu(void *_cx)
991528d7	73	{
c74f31c0 MT	74	struct acpi_processor_cx *cx = _cx;
c74f31c0 MT	75	long retval;
991528d7 VP	76	unsigned int eax, ebx, ecx, edx;
	77	unsigned int edx_part;
	78	unsigned int cstate_type; /* C-state type and not ACPI C-state type */
	79	unsigned int num_cstate_subtype;
	80
991528d7 VP	81	cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
	82
	83	/* Check whether this particular cx_type (in CST) is supported or not */
13b40a1a ZY	84	cstate_type = ((cx->address >> MWAIT_SUBSTATE_SIZE) &
13b40a1a ZY	85	MWAIT_CSTATE_MASK) + 1;
991528d7 VP	86	edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE);
	87	num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
	88
	89	retval = 0;
2194324d LB	90	/* If the HW does not support any sub-states in this C-state */
	91	if (num_cstate_subtype == 0) {
	92	pr_warn(FW_BUG "ACPI MWAIT C-state 0x%x not supported by HW (0x%x)\n", cx->address, edx_part);
991528d7 VP	93	retval = -1;
	94	goto out;
	95	}
	96
	97	/* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */
	98	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) \|\|
	99	!(ecx & CPUID5_ECX_INTERRUPT_BREAK)) {
	100	retval = -1;
	101	goto out;
	102	}
991528d7 VP	103
	104	if (!mwait_supported[cstate_type]) {
	105	mwait_supported[cstate_type] = 1;
c74f31c0 MT	106	printk(KERN_DEBUG
	107	"Monitor-Mwait will be used to enter C-%d "
	108	"state\n", cx->type);
991528d7	109	}
c74f31c0 MT	110	snprintf(cx->desc,
	111	ACPI_CX_DESC_LEN, "ACPI FFH INTEL MWAIT 0x%x",
	112	cx->address);
991528d7	113	out:
c74f31c0 MT	114	return retval;
	115	}
	116
	117	int acpi_processor_ffh_cstate_probe(unsigned int cpu,
	118	struct acpi_processor_cx cx, struct acpi_power_register reg)
	119	{
	120	struct cstate_entry *percpu_entry;
	121	struct cpuinfo_x86 *c = &cpu_data(cpu);
	122	long retval;
	123
	124	if (!cpu_cstate_entry \|\| c->cpuid_level < CPUID_MWAIT_LEAF)
	125	return -1;
	126
	127	if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
	128	return -1;
	129
	130	percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
	131	percpu_entry->states[cx->index].eax = 0;
	132	percpu_entry->states[cx->index].ecx = 0;
	133
	134	/* Make sure we are running on right CPU */
	135
	136	retval = work_on_cpu(cpu, acpi_processor_ffh_cstate_probe_cpu, cx);
	137	if (retval == 0) {
	138	/* Use the hint in CST */
	139	percpu_entry->states[cx->index].eax = cx->address;
	140	percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
	141	}
718be4aa LB	142
	143	/*
	144	* For _CST FFH on Intel, if GAS.access_size bit 1 is cleared,
	145	* then we should skip checking BM_STS for this C-state.
	146	* ref: "Intel Processor Vendor-Specific ACPI Interface Specification"
	147	*/
	148	if ((c->x86_vendor == X86_VENDOR_INTEL) && !(reg->access_size & 0x2))
	149	cx->bm_sts_skip = 1;
	150
991528d7 VP	151	return retval;
	152	}
	153	EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
	154
	155	void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx)
	156	{
	157	unsigned int cpu = smp_processor_id();
5d65131f	158	struct cstate_entry *percpu_entry;
991528d7 VP	159
	160	percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
	161	mwait_idle_with_hints(percpu_entry->states[cx->index].eax,
	162	percpu_entry->states[cx->index].ecx);
	163	}
	164	EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter);
	165
	166	static int __init ffh_cstate_init(void)
	167	{
	168	struct cpuinfo_x86 *c = &boot_cpu_data;
	169	if (c->x86_vendor != X86_VENDOR_INTEL)
	170	return -1;
	171
5d65131f	172	cpu_cstate_entry = alloc_percpu(struct cstate_entry);
991528d7 VP	173	return 0;
	174	}
	175
	176	static void __exit ffh_cstate_exit(void)
	177	{
a1205868 AS	178	free_percpu(cpu_cstate_entry);
a1205868 AS	179	cpu_cstate_entry = NULL;
991528d7 VP	180	}
	181
	182	arch_initcall(ffh_cstate_init);
	183	__exitcall(ffh_cstate_exit);