Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support for AMD Hammer. | |
05fccb0e | 3 | * |
1da177e4 LT |
4 | * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI. |
5 | * This allows to use PCI devices that only support 32bit addresses on systems | |
05fccb0e | 6 | * with more than 4GB. |
1da177e4 | 7 | * |
395cf969 | 8 | * See Documentation/DMA-API-HOWTO.txt for the interface specification. |
05fccb0e | 9 | * |
1da177e4 | 10 | * Copyright 2002 Andi Kleen, SuSE Labs. |
ff7f3649 | 11 | * Subject to the GNU General Public License v2 only. |
1da177e4 LT |
12 | */ |
13 | ||
1da177e4 LT |
14 | #include <linux/types.h> |
15 | #include <linux/ctype.h> | |
16 | #include <linux/agp_backend.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/mm.h> | |
d43c36dc | 19 | #include <linux/sched.h> |
1da177e4 LT |
20 | #include <linux/string.h> |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/pci.h> | |
1da177e4 LT |
23 | #include <linux/topology.h> |
24 | #include <linux/interrupt.h> | |
a66022c4 | 25 | #include <linux/bitmap.h> |
1eeb66a1 | 26 | #include <linux/kdebug.h> |
9ee1bea4 | 27 | #include <linux/scatterlist.h> |
fde9a109 | 28 | #include <linux/iommu-helper.h> |
f3c6ea1b | 29 | #include <linux/syscore_ops.h> |
237a6224 | 30 | #include <linux/io.h> |
5a0e3ad6 | 31 | #include <linux/gfp.h> |
60063497 | 32 | #include <linux/atomic.h> |
1da177e4 LT |
33 | #include <asm/mtrr.h> |
34 | #include <asm/pgtable.h> | |
35 | #include <asm/proto.h> | |
46a7fa27 | 36 | #include <asm/iommu.h> |
395624fc | 37 | #include <asm/gart.h> |
1da177e4 | 38 | #include <asm/cacheflush.h> |
17a941d8 MBY |
39 | #include <asm/swiotlb.h> |
40 | #include <asm/dma.h> | |
23ac4ae8 | 41 | #include <asm/amd_nb.h> |
338bac52 | 42 | #include <asm/x86_init.h> |
22e6daf4 | 43 | #include <asm/iommu_table.h> |
1da177e4 | 44 | |
79da0874 | 45 | static unsigned long iommu_bus_base; /* GART remapping area (physical) */ |
05fccb0e | 46 | static unsigned long iommu_size; /* size of remapping area bytes */ |
1da177e4 LT |
47 | static unsigned long iommu_pages; /* .. and in pages */ |
48 | ||
05fccb0e | 49 | static u32 *iommu_gatt_base; /* Remapping table */ |
1da177e4 | 50 | |
42109197 FT |
51 | static dma_addr_t bad_dma_addr; |
52 | ||
05fccb0e IM |
53 | /* |
54 | * If this is disabled the IOMMU will use an optimized flushing strategy | |
55 | * of only flushing when an mapping is reused. With it true the GART is | |
56 | * flushed for every mapping. Problem is that doing the lazy flush seems | |
57 | * to trigger bugs with some popular PCI cards, in particular 3ware (but | |
58 | * has been also also seen with Qlogic at least). | |
59 | */ | |
c854c919 | 60 | static int iommu_fullflush = 1; |
1da177e4 | 61 | |
05fccb0e | 62 | /* Allocation bitmap for the remapping area: */ |
1da177e4 | 63 | static DEFINE_SPINLOCK(iommu_bitmap_lock); |
05fccb0e IM |
64 | /* Guarded by iommu_bitmap_lock: */ |
65 | static unsigned long *iommu_gart_bitmap; | |
1da177e4 | 66 | |
05fccb0e | 67 | static u32 gart_unmapped_entry; |
1da177e4 LT |
68 | |
69 | #define GPTE_VALID 1 | |
70 | #define GPTE_COHERENT 2 | |
71 | #define GPTE_ENCODE(x) \ | |
72 | (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT) | |
73 | #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28)) | |
74 | ||
05fccb0e | 75 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
1da177e4 LT |
76 | |
77 | #ifdef CONFIG_AGP | |
78 | #define AGPEXTERN extern | |
79 | #else | |
80 | #define AGPEXTERN | |
81 | #endif | |
82 | ||
665d3e2a JR |
83 | /* GART can only remap to physical addresses < 1TB */ |
84 | #define GART_MAX_PHYS_ADDR (1ULL << 40) | |
85 | ||
1da177e4 LT |
86 | /* backdoor interface to AGP driver */ |
87 | AGPEXTERN int agp_memory_reserved; | |
88 | AGPEXTERN __u32 *agp_gatt_table; | |
89 | ||
90 | static unsigned long next_bit; /* protected by iommu_bitmap_lock */ | |
3610f211 | 91 | static bool need_flush; /* global flush state. set for each gart wrap */ |
1da177e4 | 92 | |
7b22ff53 FT |
93 | static unsigned long alloc_iommu(struct device *dev, int size, |
94 | unsigned long align_mask) | |
05fccb0e | 95 | { |
1da177e4 | 96 | unsigned long offset, flags; |
fde9a109 FT |
97 | unsigned long boundary_size; |
98 | unsigned long base_index; | |
99 | ||
100 | base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev), | |
101 | PAGE_SIZE) >> PAGE_SHIFT; | |
123bf0e2 | 102 | boundary_size = ALIGN((u64)dma_get_seg_boundary(dev) + 1, |
fde9a109 | 103 | PAGE_SIZE) >> PAGE_SHIFT; |
1da177e4 | 104 | |
05fccb0e | 105 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 | 106 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit, |
7b22ff53 | 107 | size, base_index, boundary_size, align_mask); |
1da177e4 | 108 | if (offset == -1) { |
3610f211 | 109 | need_flush = true; |
fde9a109 | 110 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0, |
7b22ff53 FT |
111 | size, base_index, boundary_size, |
112 | align_mask); | |
1da177e4 | 113 | } |
05fccb0e | 114 | if (offset != -1) { |
05fccb0e IM |
115 | next_bit = offset+size; |
116 | if (next_bit >= iommu_pages) { | |
1da177e4 | 117 | next_bit = 0; |
3610f211 | 118 | need_flush = true; |
05fccb0e IM |
119 | } |
120 | } | |
1da177e4 | 121 | if (iommu_fullflush) |
3610f211 | 122 | need_flush = true; |
05fccb0e IM |
123 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
124 | ||
1da177e4 | 125 | return offset; |
05fccb0e | 126 | } |
1da177e4 LT |
127 | |
128 | static void free_iommu(unsigned long offset, int size) | |
05fccb0e | 129 | { |
1da177e4 | 130 | unsigned long flags; |
05fccb0e | 131 | |
1da177e4 | 132 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
a66022c4 | 133 | bitmap_clear(iommu_gart_bitmap, offset, size); |
70d7d357 JR |
134 | if (offset >= next_bit) |
135 | next_bit = offset + size; | |
1da177e4 | 136 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 137 | } |
1da177e4 | 138 | |
05fccb0e | 139 | /* |
1da177e4 LT |
140 | * Use global flush state to avoid races with multiple flushers. |
141 | */ | |
a32073bf | 142 | static void flush_gart(void) |
05fccb0e | 143 | { |
1da177e4 | 144 | unsigned long flags; |
05fccb0e | 145 | |
1da177e4 | 146 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
a32073bf | 147 | if (need_flush) { |
eec1d4fa | 148 | amd_flush_garts(); |
3610f211 | 149 | need_flush = false; |
05fccb0e | 150 | } |
1da177e4 | 151 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 152 | } |
1da177e4 | 153 | |
1da177e4 | 154 | #ifdef CONFIG_IOMMU_LEAK |
1da177e4 | 155 | /* Debugging aid for drivers that don't free their IOMMU tables */ |
1da177e4 | 156 | static int leak_trace; |
79da0874 | 157 | static int iommu_leak_pages = 20; |
05fccb0e | 158 | |
79da0874 | 159 | static void dump_leak(void) |
1da177e4 | 160 | { |
05fccb0e IM |
161 | static int dump; |
162 | ||
19c1a6f5 | 163 | if (dump) |
05fccb0e | 164 | return; |
1da177e4 | 165 | dump = 1; |
05fccb0e | 166 | |
19c1a6f5 FT |
167 | show_stack(NULL, NULL); |
168 | debug_dma_dump_mappings(NULL); | |
1da177e4 | 169 | } |
1da177e4 LT |
170 | #endif |
171 | ||
17a941d8 | 172 | static void iommu_full(struct device *dev, size_t size, int dir) |
1da177e4 | 173 | { |
05fccb0e | 174 | /* |
1da177e4 LT |
175 | * Ran out of IOMMU space for this operation. This is very bad. |
176 | * Unfortunately the drivers cannot handle this operation properly. | |
05fccb0e | 177 | * Return some non mapped prereserved space in the aperture and |
1da177e4 LT |
178 | * let the Northbridge deal with it. This will result in garbage |
179 | * in the IO operation. When the size exceeds the prereserved space | |
05fccb0e | 180 | * memory corruption will occur or random memory will be DMAed |
1da177e4 | 181 | * out. Hopefully no network devices use single mappings that big. |
05fccb0e IM |
182 | */ |
183 | ||
fc3a8828 | 184 | dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size); |
1da177e4 | 185 | |
17a941d8 | 186 | if (size > PAGE_SIZE*EMERGENCY_PAGES) { |
1da177e4 LT |
187 | if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
188 | panic("PCI-DMA: Memory would be corrupted\n"); | |
05fccb0e IM |
189 | if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
190 | panic(KERN_ERR | |
191 | "PCI-DMA: Random memory would be DMAed\n"); | |
192 | } | |
1da177e4 | 193 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 194 | dump_leak(); |
1da177e4 | 195 | #endif |
05fccb0e | 196 | } |
1da177e4 | 197 | |
05fccb0e IM |
198 | static inline int |
199 | need_iommu(struct device *dev, unsigned long addr, size_t size) | |
200 | { | |
a4c2baa6 | 201 | return force_iommu || !dma_capable(dev, addr, size); |
1da177e4 LT |
202 | } |
203 | ||
05fccb0e IM |
204 | static inline int |
205 | nonforced_iommu(struct device *dev, unsigned long addr, size_t size) | |
206 | { | |
a4c2baa6 | 207 | return !dma_capable(dev, addr, size); |
1da177e4 LT |
208 | } |
209 | ||
210 | /* Map a single continuous physical area into the IOMMU. | |
211 | * Caller needs to check if the iommu is needed and flush. | |
212 | */ | |
17a941d8 | 213 | static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, |
7b22ff53 | 214 | size_t size, int dir, unsigned long align_mask) |
05fccb0e | 215 | { |
1477b8e5 | 216 | unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE); |
665d3e2a | 217 | unsigned long iommu_page; |
1da177e4 | 218 | int i; |
05fccb0e | 219 | |
665d3e2a JR |
220 | if (unlikely(phys_mem + size > GART_MAX_PHYS_ADDR)) |
221 | return bad_dma_addr; | |
222 | ||
223 | iommu_page = alloc_iommu(dev, npages, align_mask); | |
1da177e4 LT |
224 | if (iommu_page == -1) { |
225 | if (!nonforced_iommu(dev, phys_mem, size)) | |
05fccb0e | 226 | return phys_mem; |
1da177e4 LT |
227 | if (panic_on_overflow) |
228 | panic("dma_map_area overflow %lu bytes\n", size); | |
17a941d8 | 229 | iommu_full(dev, size, dir); |
42109197 | 230 | return bad_dma_addr; |
1da177e4 LT |
231 | } |
232 | ||
233 | for (i = 0; i < npages; i++) { | |
234 | iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem); | |
1da177e4 LT |
235 | phys_mem += PAGE_SIZE; |
236 | } | |
237 | return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK); | |
238 | } | |
239 | ||
240 | /* Map a single area into the IOMMU */ | |
052aedbf FT |
241 | static dma_addr_t gart_map_page(struct device *dev, struct page *page, |
242 | unsigned long offset, size_t size, | |
243 | enum dma_data_direction dir, | |
244 | struct dma_attrs *attrs) | |
1da177e4 | 245 | { |
2be62149 | 246 | unsigned long bus; |
052aedbf | 247 | phys_addr_t paddr = page_to_phys(page) + offset; |
1da177e4 | 248 | |
1da177e4 | 249 | if (!dev) |
6c505ce3 | 250 | dev = &x86_dma_fallback_dev; |
1da177e4 | 251 | |
2be62149 IM |
252 | if (!need_iommu(dev, paddr, size)) |
253 | return paddr; | |
1da177e4 | 254 | |
7b22ff53 FT |
255 | bus = dma_map_area(dev, paddr, size, dir, 0); |
256 | flush_gart(); | |
05fccb0e IM |
257 | |
258 | return bus; | |
17a941d8 MBY |
259 | } |
260 | ||
7c2d9cd2 JM |
261 | /* |
262 | * Free a DMA mapping. | |
263 | */ | |
052aedbf FT |
264 | static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr, |
265 | size_t size, enum dma_data_direction dir, | |
266 | struct dma_attrs *attrs) | |
7c2d9cd2 JM |
267 | { |
268 | unsigned long iommu_page; | |
269 | int npages; | |
270 | int i; | |
271 | ||
272 | if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE || | |
273 | dma_addr >= iommu_bus_base + iommu_size) | |
274 | return; | |
05fccb0e | 275 | |
7c2d9cd2 | 276 | iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT; |
1477b8e5 | 277 | npages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
7c2d9cd2 JM |
278 | for (i = 0; i < npages; i++) { |
279 | iommu_gatt_base[iommu_page + i] = gart_unmapped_entry; | |
7c2d9cd2 JM |
280 | } |
281 | free_iommu(iommu_page, npages); | |
282 | } | |
283 | ||
17a941d8 MBY |
284 | /* |
285 | * Wrapper for pci_unmap_single working with scatterlists. | |
286 | */ | |
160c1d8e FT |
287 | static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
288 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
17a941d8 | 289 | { |
9ee1bea4 | 290 | struct scatterlist *s; |
17a941d8 MBY |
291 | int i; |
292 | ||
9ee1bea4 | 293 | for_each_sg(sg, s, nents, i) { |
60b08c67 | 294 | if (!s->dma_length || !s->length) |
17a941d8 | 295 | break; |
d7dff840 | 296 | gart_unmap_page(dev, s->dma_address, s->dma_length, dir, NULL); |
17a941d8 MBY |
297 | } |
298 | } | |
1da177e4 LT |
299 | |
300 | /* Fallback for dma_map_sg in case of overflow */ | |
301 | static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg, | |
302 | int nents, int dir) | |
303 | { | |
9ee1bea4 | 304 | struct scatterlist *s; |
1da177e4 LT |
305 | int i; |
306 | ||
307 | #ifdef CONFIG_IOMMU_DEBUG | |
123bf0e2 | 308 | pr_debug("dma_map_sg overflow\n"); |
1da177e4 LT |
309 | #endif |
310 | ||
9ee1bea4 | 311 | for_each_sg(sg, s, nents, i) { |
58b053e4 | 312 | unsigned long addr = sg_phys(s); |
05fccb0e IM |
313 | |
314 | if (nonforced_iommu(dev, addr, s->length)) { | |
7b22ff53 | 315 | addr = dma_map_area(dev, addr, s->length, dir, 0); |
42109197 | 316 | if (addr == bad_dma_addr) { |
05fccb0e | 317 | if (i > 0) |
160c1d8e | 318 | gart_unmap_sg(dev, sg, i, dir, NULL); |
05fccb0e | 319 | nents = 0; |
1da177e4 LT |
320 | sg[0].dma_length = 0; |
321 | break; | |
322 | } | |
323 | } | |
324 | s->dma_address = addr; | |
325 | s->dma_length = s->length; | |
326 | } | |
a32073bf | 327 | flush_gart(); |
05fccb0e | 328 | |
1da177e4 LT |
329 | return nents; |
330 | } | |
331 | ||
332 | /* Map multiple scatterlist entries continuous into the first. */ | |
fde9a109 FT |
333 | static int __dma_map_cont(struct device *dev, struct scatterlist *start, |
334 | int nelems, struct scatterlist *sout, | |
335 | unsigned long pages) | |
1da177e4 | 336 | { |
7b22ff53 | 337 | unsigned long iommu_start = alloc_iommu(dev, pages, 0); |
05fccb0e | 338 | unsigned long iommu_page = iommu_start; |
9ee1bea4 | 339 | struct scatterlist *s; |
1da177e4 LT |
340 | int i; |
341 | ||
342 | if (iommu_start == -1) | |
343 | return -1; | |
9ee1bea4 JA |
344 | |
345 | for_each_sg(start, s, nelems, i) { | |
1da177e4 LT |
346 | unsigned long pages, addr; |
347 | unsigned long phys_addr = s->dma_address; | |
05fccb0e | 348 | |
9ee1bea4 JA |
349 | BUG_ON(s != start && s->offset); |
350 | if (s == start) { | |
1da177e4 LT |
351 | sout->dma_address = iommu_bus_base; |
352 | sout->dma_address += iommu_page*PAGE_SIZE + s->offset; | |
353 | sout->dma_length = s->length; | |
05fccb0e IM |
354 | } else { |
355 | sout->dma_length += s->length; | |
1da177e4 LT |
356 | } |
357 | ||
358 | addr = phys_addr; | |
1477b8e5 | 359 | pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE); |
05fccb0e IM |
360 | while (pages--) { |
361 | iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr); | |
1da177e4 LT |
362 | addr += PAGE_SIZE; |
363 | iommu_page++; | |
0d541064 | 364 | } |
05fccb0e IM |
365 | } |
366 | BUG_ON(iommu_page - iommu_start != pages); | |
367 | ||
1da177e4 LT |
368 | return 0; |
369 | } | |
370 | ||
05fccb0e | 371 | static inline int |
fde9a109 FT |
372 | dma_map_cont(struct device *dev, struct scatterlist *start, int nelems, |
373 | struct scatterlist *sout, unsigned long pages, int need) | |
1da177e4 | 374 | { |
9ee1bea4 JA |
375 | if (!need) { |
376 | BUG_ON(nelems != 1); | |
e88a39de | 377 | sout->dma_address = start->dma_address; |
9ee1bea4 | 378 | sout->dma_length = start->length; |
1da177e4 | 379 | return 0; |
9ee1bea4 | 380 | } |
fde9a109 | 381 | return __dma_map_cont(dev, start, nelems, sout, pages); |
1da177e4 | 382 | } |
05fccb0e | 383 | |
1da177e4 LT |
384 | /* |
385 | * DMA map all entries in a scatterlist. | |
05fccb0e | 386 | * Merge chunks that have page aligned sizes into a continuous mapping. |
1da177e4 | 387 | */ |
160c1d8e FT |
388 | static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
389 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1da177e4 | 390 | { |
9ee1bea4 | 391 | struct scatterlist *s, *ps, *start_sg, *sgmap; |
05fccb0e IM |
392 | int need = 0, nextneed, i, out, start; |
393 | unsigned long pages = 0; | |
42d00284 FT |
394 | unsigned int seg_size; |
395 | unsigned int max_seg_size; | |
1da177e4 | 396 | |
05fccb0e | 397 | if (nents == 0) |
1da177e4 LT |
398 | return 0; |
399 | ||
1da177e4 | 400 | if (!dev) |
6c505ce3 | 401 | dev = &x86_dma_fallback_dev; |
1da177e4 | 402 | |
123bf0e2 IM |
403 | out = 0; |
404 | start = 0; | |
405 | start_sg = sg; | |
406 | sgmap = sg; | |
407 | seg_size = 0; | |
408 | max_seg_size = dma_get_max_seg_size(dev); | |
409 | ps = NULL; /* shut up gcc */ | |
410 | ||
9ee1bea4 | 411 | for_each_sg(sg, s, nents, i) { |
58b053e4 | 412 | dma_addr_t addr = sg_phys(s); |
05fccb0e | 413 | |
1da177e4 | 414 | s->dma_address = addr; |
05fccb0e | 415 | BUG_ON(s->length == 0); |
1da177e4 | 416 | |
05fccb0e | 417 | nextneed = need_iommu(dev, addr, s->length); |
1da177e4 LT |
418 | |
419 | /* Handle the previous not yet processed entries */ | |
420 | if (i > start) { | |
05fccb0e IM |
421 | /* |
422 | * Can only merge when the last chunk ends on a | |
423 | * page boundary and the new one doesn't have an | |
424 | * offset. | |
425 | */ | |
1da177e4 | 426 | if (!iommu_merge || !nextneed || !need || s->offset || |
42d00284 | 427 | (s->length + seg_size > max_seg_size) || |
9ee1bea4 | 428 | (ps->offset + ps->length) % PAGE_SIZE) { |
fde9a109 FT |
429 | if (dma_map_cont(dev, start_sg, i - start, |
430 | sgmap, pages, need) < 0) | |
1da177e4 LT |
431 | goto error; |
432 | out++; | |
123bf0e2 IM |
433 | |
434 | seg_size = 0; | |
435 | sgmap = sg_next(sgmap); | |
436 | pages = 0; | |
437 | start = i; | |
438 | start_sg = s; | |
1da177e4 LT |
439 | } |
440 | } | |
441 | ||
42d00284 | 442 | seg_size += s->length; |
1da177e4 | 443 | need = nextneed; |
1477b8e5 | 444 | pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE); |
9ee1bea4 | 445 | ps = s; |
1da177e4 | 446 | } |
fde9a109 | 447 | if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0) |
1da177e4 LT |
448 | goto error; |
449 | out++; | |
a32073bf | 450 | flush_gart(); |
9ee1bea4 JA |
451 | if (out < nents) { |
452 | sgmap = sg_next(sgmap); | |
453 | sgmap->dma_length = 0; | |
454 | } | |
1da177e4 LT |
455 | return out; |
456 | ||
457 | error: | |
a32073bf | 458 | flush_gart(); |
160c1d8e | 459 | gart_unmap_sg(dev, sg, out, dir, NULL); |
05fccb0e | 460 | |
a1002a48 KV |
461 | /* When it was forced or merged try again in a dumb way */ |
462 | if (force_iommu || iommu_merge) { | |
463 | out = dma_map_sg_nonforce(dev, sg, nents, dir); | |
464 | if (out > 0) | |
465 | return out; | |
466 | } | |
1da177e4 LT |
467 | if (panic_on_overflow) |
468 | panic("dma_map_sg: overflow on %lu pages\n", pages); | |
05fccb0e | 469 | |
17a941d8 | 470 | iommu_full(dev, pages << PAGE_SHIFT, dir); |
9ee1bea4 | 471 | for_each_sg(sg, s, nents, i) |
42109197 | 472 | s->dma_address = bad_dma_addr; |
1da177e4 | 473 | return 0; |
05fccb0e | 474 | } |
1da177e4 | 475 | |
94581094 JR |
476 | /* allocate and map a coherent mapping */ |
477 | static void * | |
478 | gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr, | |
baa676fc | 479 | gfp_t flag, struct dma_attrs *attrs) |
94581094 | 480 | { |
f6a32a36 | 481 | dma_addr_t paddr; |
421076e2 | 482 | unsigned long align_mask; |
1d990882 FT |
483 | struct page *page; |
484 | ||
485 | if (force_iommu && !(flag & GFP_DMA)) { | |
486 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
487 | page = alloc_pages(flag | __GFP_ZERO, get_order(size)); | |
488 | if (!page) | |
489 | return NULL; | |
490 | ||
491 | align_mask = (1UL << get_order(size)) - 1; | |
492 | paddr = dma_map_area(dev, page_to_phys(page), size, | |
493 | DMA_BIDIRECTIONAL, align_mask); | |
494 | ||
495 | flush_gart(); | |
42109197 | 496 | if (paddr != bad_dma_addr) { |
1d990882 FT |
497 | *dma_addr = paddr; |
498 | return page_address(page); | |
499 | } | |
500 | __free_pages(page, get_order(size)); | |
501 | } else | |
baa676fc AP |
502 | return dma_generic_alloc_coherent(dev, size, dma_addr, flag, |
503 | attrs); | |
94581094 JR |
504 | |
505 | return NULL; | |
506 | } | |
507 | ||
43a5a5a0 JR |
508 | /* free a coherent mapping */ |
509 | static void | |
510 | gart_free_coherent(struct device *dev, size_t size, void *vaddr, | |
baa676fc | 511 | dma_addr_t dma_addr, struct dma_attrs *attrs) |
43a5a5a0 | 512 | { |
d7dff840 | 513 | gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, NULL); |
9c5a3621 | 514 | dma_generic_free_coherent(dev, size, vaddr, dma_addr, attrs); |
43a5a5a0 JR |
515 | } |
516 | ||
42109197 FT |
517 | static int gart_mapping_error(struct device *dev, dma_addr_t dma_addr) |
518 | { | |
519 | return (dma_addr == bad_dma_addr); | |
520 | } | |
521 | ||
17a941d8 | 522 | static int no_agp; |
1da177e4 LT |
523 | |
524 | static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size) | |
05fccb0e IM |
525 | { |
526 | unsigned long a; | |
527 | ||
528 | if (!iommu_size) { | |
529 | iommu_size = aper_size; | |
530 | if (!no_agp) | |
531 | iommu_size /= 2; | |
532 | } | |
533 | ||
534 | a = aper + iommu_size; | |
31422c51 | 535 | iommu_size -= round_up(a, PMD_PAGE_SIZE) - a; |
1da177e4 | 536 | |
05fccb0e | 537 | if (iommu_size < 64*1024*1024) { |
123bf0e2 | 538 | pr_warning( |
05fccb0e IM |
539 | "PCI-DMA: Warning: Small IOMMU %luMB." |
540 | " Consider increasing the AGP aperture in BIOS\n", | |
541 | iommu_size >> 20); | |
542 | } | |
543 | ||
1da177e4 | 544 | return iommu_size; |
05fccb0e | 545 | } |
1da177e4 | 546 | |
05fccb0e IM |
547 | static __init unsigned read_aperture(struct pci_dev *dev, u32 *size) |
548 | { | |
549 | unsigned aper_size = 0, aper_base_32, aper_order; | |
1da177e4 | 550 | u64 aper_base; |
1da177e4 | 551 | |
3bb6fbf9 PM |
552 | pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32); |
553 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order); | |
05fccb0e | 554 | aper_order = (aper_order >> 1) & 7; |
1da177e4 | 555 | |
05fccb0e | 556 | aper_base = aper_base_32 & 0x7fff; |
1da177e4 LT |
557 | aper_base <<= 25; |
558 | ||
05fccb0e IM |
559 | aper_size = (32 * 1024 * 1024) << aper_order; |
560 | if (aper_base + aper_size > 0x100000000UL || !aper_size) | |
1da177e4 LT |
561 | aper_base = 0; |
562 | ||
563 | *size = aper_size; | |
564 | return aper_base; | |
05fccb0e | 565 | } |
1da177e4 | 566 | |
6703f6d1 RW |
567 | static void enable_gart_translations(void) |
568 | { | |
569 | int i; | |
570 | ||
9653a5c7 | 571 | if (!amd_nb_has_feature(AMD_NB_GART)) |
900f9ac9 AH |
572 | return; |
573 | ||
9653a5c7 HR |
574 | for (i = 0; i < amd_nb_num(); i++) { |
575 | struct pci_dev *dev = node_to_amd_nb(i)->misc; | |
6703f6d1 RW |
576 | |
577 | enable_gart_translation(dev, __pa(agp_gatt_table)); | |
578 | } | |
4b83873d JR |
579 | |
580 | /* Flush the GART-TLB to remove stale entries */ | |
eec1d4fa | 581 | amd_flush_garts(); |
6703f6d1 RW |
582 | } |
583 | ||
584 | /* | |
585 | * If fix_up_north_bridges is set, the north bridges have to be fixed up on | |
586 | * resume in the same way as they are handled in gart_iommu_hole_init(). | |
587 | */ | |
588 | static bool fix_up_north_bridges; | |
589 | static u32 aperture_order; | |
590 | static u32 aperture_alloc; | |
591 | ||
592 | void set_up_gart_resume(u32 aper_order, u32 aper_alloc) | |
593 | { | |
594 | fix_up_north_bridges = true; | |
595 | aperture_order = aper_order; | |
596 | aperture_alloc = aper_alloc; | |
597 | } | |
598 | ||
f3c6ea1b | 599 | static void gart_fixup_northbridges(void) |
cd76374e | 600 | { |
123bf0e2 | 601 | int i; |
6703f6d1 | 602 | |
123bf0e2 IM |
603 | if (!fix_up_north_bridges) |
604 | return; | |
6703f6d1 | 605 | |
9653a5c7 | 606 | if (!amd_nb_has_feature(AMD_NB_GART)) |
900f9ac9 AH |
607 | return; |
608 | ||
123bf0e2 | 609 | pr_info("PCI-DMA: Restoring GART aperture settings\n"); |
6703f6d1 | 610 | |
9653a5c7 HR |
611 | for (i = 0; i < amd_nb_num(); i++) { |
612 | struct pci_dev *dev = node_to_amd_nb(i)->misc; | |
6703f6d1 | 613 | |
123bf0e2 IM |
614 | /* |
615 | * Don't enable translations just yet. That is the next | |
616 | * step. Restore the pre-suspend aperture settings. | |
617 | */ | |
260133ab | 618 | gart_set_size_and_enable(dev, aperture_order); |
123bf0e2 | 619 | pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, aperture_alloc >> 25); |
6703f6d1 | 620 | } |
123bf0e2 IM |
621 | } |
622 | ||
f3c6ea1b | 623 | static void gart_resume(void) |
123bf0e2 IM |
624 | { |
625 | pr_info("PCI-DMA: Resuming GART IOMMU\n"); | |
626 | ||
f3c6ea1b | 627 | gart_fixup_northbridges(); |
6703f6d1 RW |
628 | |
629 | enable_gart_translations(); | |
cd76374e PM |
630 | } |
631 | ||
f3c6ea1b | 632 | static struct syscore_ops gart_syscore_ops = { |
123bf0e2 | 633 | .resume = gart_resume, |
cd76374e PM |
634 | |
635 | }; | |
636 | ||
05fccb0e | 637 | /* |
1da177e4 | 638 | * Private Northbridge GATT initialization in case we cannot use the |
05fccb0e | 639 | * AGP driver for some reason. |
1da177e4 | 640 | */ |
eec1d4fa | 641 | static __init int init_amd_gatt(struct agp_kern_info *info) |
05fccb0e IM |
642 | { |
643 | unsigned aper_size, gatt_size, new_aper_size; | |
644 | unsigned aper_base, new_aper_base; | |
1da177e4 LT |
645 | struct pci_dev *dev; |
646 | void *gatt; | |
f3c6ea1b | 647 | int i; |
a32073bf | 648 | |
123bf0e2 IM |
649 | pr_info("PCI-DMA: Disabling AGP.\n"); |
650 | ||
1da177e4 | 651 | aper_size = aper_base = info->aper_size = 0; |
a32073bf | 652 | dev = NULL; |
9653a5c7 HR |
653 | for (i = 0; i < amd_nb_num(); i++) { |
654 | dev = node_to_amd_nb(i)->misc; | |
05fccb0e IM |
655 | new_aper_base = read_aperture(dev, &new_aper_size); |
656 | if (!new_aper_base) | |
657 | goto nommu; | |
658 | ||
659 | if (!aper_base) { | |
1da177e4 LT |
660 | aper_size = new_aper_size; |
661 | aper_base = new_aper_base; | |
05fccb0e IM |
662 | } |
663 | if (aper_size != new_aper_size || aper_base != new_aper_base) | |
1da177e4 LT |
664 | goto nommu; |
665 | } | |
666 | if (!aper_base) | |
05fccb0e | 667 | goto nommu; |
123bf0e2 | 668 | |
1da177e4 | 669 | info->aper_base = aper_base; |
05fccb0e | 670 | info->aper_size = aper_size >> 20; |
1da177e4 | 671 | |
05fccb0e | 672 | gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32); |
0114267b JR |
673 | gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
674 | get_order(gatt_size)); | |
05fccb0e | 675 | if (!gatt) |
cf6387da | 676 | panic("Cannot allocate GATT table"); |
6d238cc4 | 677 | if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT)) |
cf6387da | 678 | panic("Could not set GART PTEs to uncacheable pages"); |
cf6387da | 679 | |
1da177e4 | 680 | agp_gatt_table = gatt; |
a32073bf | 681 | |
f3c6ea1b | 682 | register_syscore_ops(&gart_syscore_ops); |
6703f6d1 | 683 | |
a32073bf | 684 | flush_gart(); |
05fccb0e | 685 | |
123bf0e2 | 686 | pr_info("PCI-DMA: aperture base @ %x size %u KB\n", |
05fccb0e | 687 | aper_base, aper_size>>10); |
7ab073b6 | 688 | |
1da177e4 LT |
689 | return 0; |
690 | ||
691 | nommu: | |
05fccb0e | 692 | /* Should not happen anymore */ |
123bf0e2 | 693 | pr_warning("PCI-DMA: More than 4GB of RAM and no IOMMU\n" |
ad361c98 | 694 | "falling back to iommu=soft.\n"); |
05fccb0e IM |
695 | return -1; |
696 | } | |
1da177e4 | 697 | |
160c1d8e | 698 | static struct dma_map_ops gart_dma_ops = { |
05fccb0e IM |
699 | .map_sg = gart_map_sg, |
700 | .unmap_sg = gart_unmap_sg, | |
052aedbf FT |
701 | .map_page = gart_map_page, |
702 | .unmap_page = gart_unmap_page, | |
baa676fc AP |
703 | .alloc = gart_alloc_coherent, |
704 | .free = gart_free_coherent, | |
42109197 | 705 | .mapping_error = gart_mapping_error, |
17a941d8 MBY |
706 | }; |
707 | ||
338bac52 | 708 | static void gart_iommu_shutdown(void) |
bc2cea6a YL |
709 | { |
710 | struct pci_dev *dev; | |
711 | int i; | |
712 | ||
f3eee542 YL |
713 | /* don't shutdown it if there is AGP installed */ |
714 | if (!no_agp) | |
bc2cea6a YL |
715 | return; |
716 | ||
9653a5c7 | 717 | if (!amd_nb_has_feature(AMD_NB_GART)) |
900f9ac9 AH |
718 | return; |
719 | ||
9653a5c7 | 720 | for (i = 0; i < amd_nb_num(); i++) { |
05fccb0e | 721 | u32 ctl; |
bc2cea6a | 722 | |
9653a5c7 | 723 | dev = node_to_amd_nb(i)->misc; |
3bb6fbf9 | 724 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); |
bc2cea6a | 725 | |
3bb6fbf9 | 726 | ctl &= ~GARTEN; |
bc2cea6a | 727 | |
3bb6fbf9 | 728 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
05fccb0e | 729 | } |
bc2cea6a YL |
730 | } |
731 | ||
de957628 | 732 | int __init gart_iommu_init(void) |
05fccb0e | 733 | { |
1da177e4 | 734 | struct agp_kern_info info; |
1da177e4 | 735 | unsigned long iommu_start; |
d99e9016 YL |
736 | unsigned long aper_base, aper_size; |
737 | unsigned long start_pfn, end_pfn; | |
1da177e4 LT |
738 | unsigned long scratch; |
739 | long i; | |
740 | ||
9653a5c7 | 741 | if (!amd_nb_has_feature(AMD_NB_GART)) |
de957628 | 742 | return 0; |
a32073bf | 743 | |
1da177e4 | 744 | #ifndef CONFIG_AGP_AMD64 |
05fccb0e | 745 | no_agp = 1; |
1da177e4 LT |
746 | #else |
747 | /* Makefile puts PCI initialization via subsys_initcall first. */ | |
eec1d4fa | 748 | /* Add other AMD AGP bridge drivers here */ |
05fccb0e IM |
749 | no_agp = no_agp || |
750 | (agp_amd64_init() < 0) || | |
1da177e4 | 751 | (agp_copy_info(agp_bridge, &info) < 0); |
05fccb0e | 752 | #endif |
1da177e4 | 753 | |
1da177e4 | 754 | if (no_iommu || |
c987d12f | 755 | (!force_iommu && max_pfn <= MAX_DMA32_PFN) || |
0440d4c0 | 756 | !gart_iommu_aperture || |
eec1d4fa | 757 | (no_agp && init_amd_gatt(&info) < 0)) { |
c987d12f | 758 | if (max_pfn > MAX_DMA32_PFN) { |
123bf0e2 IM |
759 | pr_warning("More than 4GB of memory but GART IOMMU not available.\n"); |
760 | pr_warning("falling back to iommu=soft.\n"); | |
5b7b644c | 761 | } |
de957628 | 762 | return 0; |
1da177e4 LT |
763 | } |
764 | ||
d99e9016 | 765 | /* need to map that range */ |
123bf0e2 IM |
766 | aper_size = info.aper_size << 20; |
767 | aper_base = info.aper_base; | |
768 | end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT); | |
769 | ||
5101730c YL |
770 | start_pfn = PFN_DOWN(aper_base); |
771 | if (!pfn_range_is_mapped(start_pfn, end_pfn)) | |
d99e9016 | 772 | init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT); |
d99e9016 | 773 | |
123bf0e2 | 774 | pr_info("PCI-DMA: using GART IOMMU.\n"); |
05fccb0e IM |
775 | iommu_size = check_iommu_size(info.aper_base, aper_size); |
776 | iommu_pages = iommu_size >> PAGE_SHIFT; | |
777 | ||
0114267b | 778 | iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO, |
05fccb0e IM |
779 | get_order(iommu_pages/8)); |
780 | if (!iommu_gart_bitmap) | |
781 | panic("Cannot allocate iommu bitmap\n"); | |
1da177e4 LT |
782 | |
783 | #ifdef CONFIG_IOMMU_LEAK | |
05fccb0e | 784 | if (leak_trace) { |
19c1a6f5 FT |
785 | int ret; |
786 | ||
787 | ret = dma_debug_resize_entries(iommu_pages); | |
788 | if (ret) | |
123bf0e2 | 789 | pr_debug("PCI-DMA: Cannot trace all the entries\n"); |
05fccb0e | 790 | } |
1da177e4 LT |
791 | #endif |
792 | ||
05fccb0e | 793 | /* |
1da177e4 | 794 | * Out of IOMMU space handling. |
05fccb0e IM |
795 | * Reserve some invalid pages at the beginning of the GART. |
796 | */ | |
a66022c4 | 797 | bitmap_set(iommu_gart_bitmap, 0, EMERGENCY_PAGES); |
1da177e4 | 798 | |
123bf0e2 | 799 | pr_info("PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n", |
05fccb0e | 800 | iommu_size >> 20); |
1da177e4 | 801 | |
123bf0e2 IM |
802 | agp_memory_reserved = iommu_size; |
803 | iommu_start = aper_size - iommu_size; | |
804 | iommu_bus_base = info.aper_base + iommu_start; | |
805 | bad_dma_addr = iommu_bus_base; | |
806 | iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT); | |
1da177e4 | 807 | |
05fccb0e | 808 | /* |
1da177e4 LT |
809 | * Unmap the IOMMU part of the GART. The alias of the page is |
810 | * always mapped with cache enabled and there is no full cache | |
811 | * coherency across the GART remapping. The unmapping avoids | |
812 | * automatic prefetches from the CPU allocating cache lines in | |
813 | * there. All CPU accesses are done via the direct mapping to | |
814 | * the backing memory. The GART address is only used by PCI | |
05fccb0e | 815 | * devices. |
1da177e4 | 816 | */ |
28d6ee41 AK |
817 | set_memory_np((unsigned long)__va(iommu_bus_base), |
818 | iommu_size >> PAGE_SHIFT); | |
184652eb IM |
819 | /* |
820 | * Tricky. The GART table remaps the physical memory range, | |
821 | * so the CPU wont notice potential aliases and if the memory | |
822 | * is remapped to UC later on, we might surprise the PCI devices | |
823 | * with a stray writeout of a cacheline. So play it sure and | |
824 | * do an explicit, full-scale wbinvd() _after_ having marked all | |
825 | * the pages as Not-Present: | |
826 | */ | |
827 | wbinvd(); | |
123bf0e2 | 828 | |
fe2245c9 ML |
829 | /* |
830 | * Now all caches are flushed and we can safely enable | |
831 | * GART hardware. Doing it early leaves the possibility | |
832 | * of stale cache entries that can lead to GART PTE | |
833 | * errors. | |
834 | */ | |
835 | enable_gart_translations(); | |
1da177e4 | 836 | |
05fccb0e | 837 | /* |
fa3d319a | 838 | * Try to workaround a bug (thanks to BenH): |
05fccb0e | 839 | * Set unmapped entries to a scratch page instead of 0. |
1da177e4 | 840 | * Any prefetches that hit unmapped entries won't get an bus abort |
fa3d319a | 841 | * then. (P2P bridge may be prefetching on DMA reads). |
1da177e4 | 842 | */ |
05fccb0e IM |
843 | scratch = get_zeroed_page(GFP_KERNEL); |
844 | if (!scratch) | |
1da177e4 LT |
845 | panic("Cannot allocate iommu scratch page"); |
846 | gart_unmapped_entry = GPTE_ENCODE(__pa(scratch)); | |
05fccb0e | 847 | for (i = EMERGENCY_PAGES; i < iommu_pages; i++) |
1da177e4 LT |
848 | iommu_gatt_base[i] = gart_unmapped_entry; |
849 | ||
a32073bf | 850 | flush_gart(); |
17a941d8 | 851 | dma_ops = &gart_dma_ops; |
338bac52 | 852 | x86_platform.iommu_shutdown = gart_iommu_shutdown; |
75f1cdf1 | 853 | swiotlb = 0; |
de957628 FT |
854 | |
855 | return 0; | |
05fccb0e | 856 | } |
1da177e4 | 857 | |
43999d9e | 858 | void __init gart_parse_options(char *p) |
17a941d8 MBY |
859 | { |
860 | int arg; | |
861 | ||
1da177e4 | 862 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 863 | if (!strncmp(p, "leak", 4)) { |
17a941d8 MBY |
864 | leak_trace = 1; |
865 | p += 4; | |
237a6224 JR |
866 | if (*p == '=') |
867 | ++p; | |
17a941d8 MBY |
868 | if (isdigit(*p) && get_option(&p, &arg)) |
869 | iommu_leak_pages = arg; | |
870 | } | |
1da177e4 | 871 | #endif |
17a941d8 MBY |
872 | if (isdigit(*p) && get_option(&p, &arg)) |
873 | iommu_size = arg; | |
41855b77 | 874 | if (!strncmp(p, "fullflush", 9)) |
17a941d8 | 875 | iommu_fullflush = 1; |
05fccb0e | 876 | if (!strncmp(p, "nofullflush", 11)) |
17a941d8 | 877 | iommu_fullflush = 0; |
05fccb0e | 878 | if (!strncmp(p, "noagp", 5)) |
17a941d8 | 879 | no_agp = 1; |
05fccb0e | 880 | if (!strncmp(p, "noaperture", 10)) |
17a941d8 MBY |
881 | fix_aperture = 0; |
882 | /* duplicated from pci-dma.c */ | |
05fccb0e | 883 | if (!strncmp(p, "force", 5)) |
0440d4c0 | 884 | gart_iommu_aperture_allowed = 1; |
05fccb0e | 885 | if (!strncmp(p, "allowed", 7)) |
0440d4c0 | 886 | gart_iommu_aperture_allowed = 1; |
17a941d8 MBY |
887 | if (!strncmp(p, "memaper", 7)) { |
888 | fallback_aper_force = 1; | |
889 | p += 7; | |
890 | if (*p == '=') { | |
891 | ++p; | |
892 | if (get_option(&p, &arg)) | |
893 | fallback_aper_order = arg; | |
894 | } | |
895 | } | |
896 | } | |
22e6daf4 | 897 | IOMMU_INIT_POST(gart_iommu_hole_init); |