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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
23 | #include <linux/scatterlist.h> | |
24 | #include <linux/iommu-helper.h> | |
25 | #include <asm/proto.h> | |
46a7fa27 | 26 | #include <asm/iommu.h> |
b6c02715 | 27 | #include <asm/amd_iommu_types.h> |
c6da992e | 28 | #include <asm/amd_iommu.h> |
b6c02715 JR |
29 | |
30 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
31 | ||
136f78a1 JR |
32 | #define EXIT_LOOP_COUNT 10000000 |
33 | ||
b6c02715 JR |
34 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
35 | ||
bd60b735 JR |
36 | /* A list of preallocated protection domains */ |
37 | static LIST_HEAD(iommu_pd_list); | |
38 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
39 | ||
431b2a20 JR |
40 | /* |
41 | * general struct to manage commands send to an IOMMU | |
42 | */ | |
d6449536 | 43 | struct iommu_cmd { |
b6c02715 JR |
44 | u32 data[4]; |
45 | }; | |
46 | ||
bd0e5211 JR |
47 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
48 | struct unity_map_entry *e); | |
49 | ||
431b2a20 | 50 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
51 | static int iommu_has_npcache(struct amd_iommu *iommu) |
52 | { | |
ae9b9403 | 53 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
54 | } |
55 | ||
a80dc3e0 JR |
56 | /**************************************************************************** |
57 | * | |
58 | * Interrupt handling functions | |
59 | * | |
60 | ****************************************************************************/ | |
61 | ||
90008ee4 JR |
62 | static void iommu_print_event(void *__evt) |
63 | { | |
64 | u32 *event = __evt; | |
65 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
66 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
67 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
68 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
69 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
70 | ||
71 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
72 | ||
73 | switch (type) { | |
74 | case EVENT_TYPE_ILL_DEV: | |
75 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
76 | "address=0x%016llx flags=0x%04x]\n", | |
77 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
78 | address, flags); | |
79 | break; | |
80 | case EVENT_TYPE_IO_FAULT: | |
81 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
82 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
83 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
84 | domid, address, flags); | |
85 | break; | |
86 | case EVENT_TYPE_DEV_TAB_ERR: | |
87 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
88 | "address=0x%016llx flags=0x%04x]\n", | |
89 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
90 | address, flags); | |
91 | break; | |
92 | case EVENT_TYPE_PAGE_TAB_ERR: | |
93 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
94 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
95 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
96 | domid, address, flags); | |
97 | break; | |
98 | case EVENT_TYPE_ILL_CMD: | |
99 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
100 | break; | |
101 | case EVENT_TYPE_CMD_HARD_ERR: | |
102 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
103 | "flags=0x%04x]\n", address, flags); | |
104 | break; | |
105 | case EVENT_TYPE_IOTLB_INV_TO: | |
106 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
107 | "address=0x%016llx]\n", | |
108 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
109 | address); | |
110 | break; | |
111 | case EVENT_TYPE_INV_DEV_REQ: | |
112 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
113 | "address=0x%016llx flags=0x%04x]\n", | |
114 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
115 | address, flags); | |
116 | break; | |
117 | default: | |
118 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
119 | } | |
120 | } | |
121 | ||
122 | static void iommu_poll_events(struct amd_iommu *iommu) | |
123 | { | |
124 | u32 head, tail; | |
125 | unsigned long flags; | |
126 | ||
127 | spin_lock_irqsave(&iommu->lock, flags); | |
128 | ||
129 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
130 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
131 | ||
132 | while (head != tail) { | |
133 | iommu_print_event(iommu->evt_buf + head); | |
134 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
135 | } | |
136 | ||
137 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
138 | ||
139 | spin_unlock_irqrestore(&iommu->lock, flags); | |
140 | } | |
141 | ||
a80dc3e0 JR |
142 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
143 | { | |
90008ee4 JR |
144 | struct amd_iommu *iommu; |
145 | ||
146 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
147 | iommu_poll_events(iommu); | |
148 | ||
149 | return IRQ_HANDLED; | |
a80dc3e0 JR |
150 | } |
151 | ||
431b2a20 JR |
152 | /**************************************************************************** |
153 | * | |
154 | * IOMMU command queuing functions | |
155 | * | |
156 | ****************************************************************************/ | |
157 | ||
158 | /* | |
159 | * Writes the command to the IOMMUs command buffer and informs the | |
160 | * hardware about the new command. Must be called with iommu->lock held. | |
161 | */ | |
d6449536 | 162 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
163 | { |
164 | u32 tail, head; | |
165 | u8 *target; | |
166 | ||
167 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 168 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
169 | memcpy_toio(target, cmd, sizeof(*cmd)); |
170 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
171 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
172 | if (tail == head) | |
173 | return -ENOMEM; | |
174 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
431b2a20 JR |
179 | /* |
180 | * General queuing function for commands. Takes iommu->lock and calls | |
181 | * __iommu_queue_command(). | |
182 | */ | |
d6449536 | 183 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
184 | { |
185 | unsigned long flags; | |
186 | int ret; | |
187 | ||
188 | spin_lock_irqsave(&iommu->lock, flags); | |
189 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb JR |
190 | if (!ret) |
191 | iommu->need_sync = 1; | |
a19ae1ec JR |
192 | spin_unlock_irqrestore(&iommu->lock, flags); |
193 | ||
194 | return ret; | |
195 | } | |
196 | ||
431b2a20 JR |
197 | /* |
198 | * This function is called whenever we need to ensure that the IOMMU has | |
199 | * completed execution of all commands we sent. It sends a | |
200 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
201 | * us about that by writing a value to a physical address we pass with | |
202 | * the command. | |
203 | */ | |
a19ae1ec JR |
204 | static int iommu_completion_wait(struct amd_iommu *iommu) |
205 | { | |
7e4f88da | 206 | int ret = 0, ready = 0; |
519c31ba | 207 | unsigned status = 0; |
d6449536 | 208 | struct iommu_cmd cmd; |
7e4f88da | 209 | unsigned long flags, i = 0; |
a19ae1ec JR |
210 | |
211 | memset(&cmd, 0, sizeof(cmd)); | |
519c31ba | 212 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; |
a19ae1ec JR |
213 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); |
214 | ||
7e4f88da JR |
215 | spin_lock_irqsave(&iommu->lock, flags); |
216 | ||
09ee17eb JR |
217 | if (!iommu->need_sync) |
218 | goto out; | |
219 | ||
220 | iommu->need_sync = 0; | |
221 | ||
7e4f88da | 222 | ret = __iommu_queue_command(iommu, &cmd); |
a19ae1ec JR |
223 | |
224 | if (ret) | |
7e4f88da | 225 | goto out; |
a19ae1ec | 226 | |
136f78a1 JR |
227 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
228 | ++i; | |
519c31ba JR |
229 | /* wait for the bit to become one */ |
230 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
231 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
136f78a1 JR |
232 | } |
233 | ||
519c31ba JR |
234 | /* set bit back to zero */ |
235 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
236 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
237 | ||
136f78a1 JR |
238 | if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit())) |
239 | printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n"); | |
7e4f88da JR |
240 | out: |
241 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
242 | |
243 | return 0; | |
244 | } | |
245 | ||
431b2a20 JR |
246 | /* |
247 | * Command send function for invalidating a device table entry | |
248 | */ | |
a19ae1ec JR |
249 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
250 | { | |
d6449536 | 251 | struct iommu_cmd cmd; |
ee2fa743 | 252 | int ret; |
a19ae1ec JR |
253 | |
254 | BUG_ON(iommu == NULL); | |
255 | ||
256 | memset(&cmd, 0, sizeof(cmd)); | |
257 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
258 | cmd.data[0] = devid; | |
259 | ||
ee2fa743 JR |
260 | ret = iommu_queue_command(iommu, &cmd); |
261 | ||
ee2fa743 | 262 | return ret; |
a19ae1ec JR |
263 | } |
264 | ||
431b2a20 JR |
265 | /* |
266 | * Generic command send function for invalidaing TLB entries | |
267 | */ | |
a19ae1ec JR |
268 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
269 | u64 address, u16 domid, int pde, int s) | |
270 | { | |
d6449536 | 271 | struct iommu_cmd cmd; |
ee2fa743 | 272 | int ret; |
a19ae1ec JR |
273 | |
274 | memset(&cmd, 0, sizeof(cmd)); | |
275 | address &= PAGE_MASK; | |
276 | CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES); | |
277 | cmd.data[1] |= domid; | |
8a456695 | 278 | cmd.data[2] = lower_32_bits(address); |
8ea80d78 | 279 | cmd.data[3] = upper_32_bits(address); |
431b2a20 | 280 | if (s) /* size bit - we flush more than one 4kb page */ |
a19ae1ec | 281 | cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; |
431b2a20 | 282 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ |
a19ae1ec JR |
283 | cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
284 | ||
ee2fa743 JR |
285 | ret = iommu_queue_command(iommu, &cmd); |
286 | ||
ee2fa743 | 287 | return ret; |
a19ae1ec JR |
288 | } |
289 | ||
431b2a20 JR |
290 | /* |
291 | * TLB invalidation function which is called from the mapping functions. | |
292 | * It invalidates a single PTE if the range to flush is within a single | |
293 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
294 | */ | |
a19ae1ec JR |
295 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
296 | u64 address, size_t size) | |
297 | { | |
999ba417 | 298 | int s = 0; |
e3c449f5 | 299 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
300 | |
301 | address &= PAGE_MASK; | |
302 | ||
999ba417 JR |
303 | if (pages > 1) { |
304 | /* | |
305 | * If we have to flush more than one page, flush all | |
306 | * TLB entries for this domain | |
307 | */ | |
308 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
309 | s = 1; | |
a19ae1ec JR |
310 | } |
311 | ||
999ba417 JR |
312 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
313 | ||
a19ae1ec JR |
314 | return 0; |
315 | } | |
b6c02715 | 316 | |
1c655773 JR |
317 | /* Flush the whole IO/TLB for a given protection domain */ |
318 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
319 | { | |
320 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
321 | ||
322 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); | |
323 | } | |
324 | ||
431b2a20 JR |
325 | /**************************************************************************** |
326 | * | |
327 | * The functions below are used the create the page table mappings for | |
328 | * unity mapped regions. | |
329 | * | |
330 | ****************************************************************************/ | |
331 | ||
332 | /* | |
333 | * Generic mapping functions. It maps a physical address into a DMA | |
334 | * address space. It allocates the page table pages if necessary. | |
335 | * In the future it can be extended to a generic mapping function | |
336 | * supporting all features of AMD IOMMU page tables like level skipping | |
337 | * and full 64 bit address spaces. | |
338 | */ | |
bd0e5211 JR |
339 | static int iommu_map(struct protection_domain *dom, |
340 | unsigned long bus_addr, | |
341 | unsigned long phys_addr, | |
342 | int prot) | |
343 | { | |
344 | u64 __pte, *pte, *page; | |
345 | ||
346 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 347 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
348 | |
349 | /* only support 512GB address spaces for now */ | |
350 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
351 | return -EINVAL; | |
352 | ||
353 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
354 | ||
355 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
356 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
357 | if (!page) | |
358 | return -ENOMEM; | |
359 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
360 | } | |
361 | ||
362 | pte = IOMMU_PTE_PAGE(*pte); | |
363 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
364 | ||
365 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
366 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
367 | if (!page) | |
368 | return -ENOMEM; | |
369 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
370 | } | |
371 | ||
372 | pte = IOMMU_PTE_PAGE(*pte); | |
373 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
374 | ||
375 | if (IOMMU_PTE_PRESENT(*pte)) | |
376 | return -EBUSY; | |
377 | ||
378 | __pte = phys_addr | IOMMU_PTE_P; | |
379 | if (prot & IOMMU_PROT_IR) | |
380 | __pte |= IOMMU_PTE_IR; | |
381 | if (prot & IOMMU_PROT_IW) | |
382 | __pte |= IOMMU_PTE_IW; | |
383 | ||
384 | *pte = __pte; | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
431b2a20 JR |
389 | /* |
390 | * This function checks if a specific unity mapping entry is needed for | |
391 | * this specific IOMMU. | |
392 | */ | |
bd0e5211 JR |
393 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
394 | struct unity_map_entry *entry) | |
395 | { | |
396 | u16 bdf, i; | |
397 | ||
398 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
399 | bdf = amd_iommu_alias_table[i]; | |
400 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
401 | return 1; | |
402 | } | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
431b2a20 JR |
407 | /* |
408 | * Init the unity mappings for a specific IOMMU in the system | |
409 | * | |
410 | * Basically iterates over all unity mapping entries and applies them to | |
411 | * the default domain DMA of that IOMMU if necessary. | |
412 | */ | |
bd0e5211 JR |
413 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
414 | { | |
415 | struct unity_map_entry *entry; | |
416 | int ret; | |
417 | ||
418 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
419 | if (!iommu_for_unity_map(iommu, entry)) | |
420 | continue; | |
421 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
422 | if (ret) | |
423 | return ret; | |
424 | } | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
431b2a20 JR |
429 | /* |
430 | * This function actually applies the mapping to the page table of the | |
431 | * dma_ops domain. | |
432 | */ | |
bd0e5211 JR |
433 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
434 | struct unity_map_entry *e) | |
435 | { | |
436 | u64 addr; | |
437 | int ret; | |
438 | ||
439 | for (addr = e->address_start; addr < e->address_end; | |
440 | addr += PAGE_SIZE) { | |
441 | ret = iommu_map(&dma_dom->domain, addr, addr, e->prot); | |
442 | if (ret) | |
443 | return ret; | |
444 | /* | |
445 | * if unity mapping is in aperture range mark the page | |
446 | * as allocated in the aperture | |
447 | */ | |
448 | if (addr < dma_dom->aperture_size) | |
449 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
450 | } | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
431b2a20 JR |
455 | /* |
456 | * Inits the unity mappings required for a specific device | |
457 | */ | |
bd0e5211 JR |
458 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
459 | u16 devid) | |
460 | { | |
461 | struct unity_map_entry *e; | |
462 | int ret; | |
463 | ||
464 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
465 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
466 | continue; | |
467 | ret = dma_ops_unity_map(dma_dom, e); | |
468 | if (ret) | |
469 | return ret; | |
470 | } | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
431b2a20 JR |
475 | /**************************************************************************** |
476 | * | |
477 | * The next functions belong to the address allocator for the dma_ops | |
478 | * interface functions. They work like the allocators in the other IOMMU | |
479 | * drivers. Its basically a bitmap which marks the allocated pages in | |
480 | * the aperture. Maybe it could be enhanced in the future to a more | |
481 | * efficient allocator. | |
482 | * | |
483 | ****************************************************************************/ | |
d3086444 | 484 | |
431b2a20 JR |
485 | /* |
486 | * The address allocator core function. | |
487 | * | |
488 | * called with domain->lock held | |
489 | */ | |
d3086444 JR |
490 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
491 | struct dma_ops_domain *dom, | |
6d4f343f | 492 | unsigned int pages, |
832a90c3 JR |
493 | unsigned long align_mask, |
494 | u64 dma_mask) | |
d3086444 | 495 | { |
40becd8d | 496 | unsigned long limit; |
d3086444 | 497 | unsigned long address; |
d3086444 JR |
498 | unsigned long boundary_size; |
499 | ||
500 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
501 | PAGE_SIZE) >> PAGE_SHIFT; | |
40becd8d FT |
502 | limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0, |
503 | dma_mask >> PAGE_SHIFT); | |
d3086444 | 504 | |
1c655773 | 505 | if (dom->next_bit >= limit) { |
d3086444 | 506 | dom->next_bit = 0; |
1c655773 JR |
507 | dom->need_flush = true; |
508 | } | |
d3086444 JR |
509 | |
510 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 511 | 0 , boundary_size, align_mask); |
1c655773 | 512 | if (address == -1) { |
d3086444 | 513 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 514 | 0, boundary_size, align_mask); |
1c655773 JR |
515 | dom->need_flush = true; |
516 | } | |
d3086444 JR |
517 | |
518 | if (likely(address != -1)) { | |
d3086444 JR |
519 | dom->next_bit = address + pages; |
520 | address <<= PAGE_SHIFT; | |
521 | } else | |
522 | address = bad_dma_address; | |
523 | ||
524 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
525 | ||
526 | return address; | |
527 | } | |
528 | ||
431b2a20 JR |
529 | /* |
530 | * The address free function. | |
531 | * | |
532 | * called with domain->lock held | |
533 | */ | |
d3086444 JR |
534 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
535 | unsigned long address, | |
536 | unsigned int pages) | |
537 | { | |
538 | address >>= PAGE_SHIFT; | |
539 | iommu_area_free(dom->bitmap, address, pages); | |
80be308d | 540 | |
8501c45c | 541 | if (address >= dom->next_bit) |
80be308d | 542 | dom->need_flush = true; |
d3086444 JR |
543 | } |
544 | ||
431b2a20 JR |
545 | /**************************************************************************** |
546 | * | |
547 | * The next functions belong to the domain allocation. A domain is | |
548 | * allocated for every IOMMU as the default domain. If device isolation | |
549 | * is enabled, every device get its own domain. The most important thing | |
550 | * about domains is the page table mapping the DMA address space they | |
551 | * contain. | |
552 | * | |
553 | ****************************************************************************/ | |
554 | ||
ec487d1a JR |
555 | static u16 domain_id_alloc(void) |
556 | { | |
557 | unsigned long flags; | |
558 | int id; | |
559 | ||
560 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
561 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
562 | BUG_ON(id == 0); | |
563 | if (id > 0 && id < MAX_DOMAIN_ID) | |
564 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
565 | else | |
566 | id = 0; | |
567 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
568 | ||
569 | return id; | |
570 | } | |
571 | ||
431b2a20 JR |
572 | /* |
573 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
574 | * ranges. | |
575 | */ | |
ec487d1a JR |
576 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
577 | unsigned long start_page, | |
578 | unsigned int pages) | |
579 | { | |
580 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
581 | ||
582 | if (start_page + pages > last_page) | |
583 | pages = last_page - start_page; | |
584 | ||
d26dbc5c | 585 | iommu_area_reserve(dom->bitmap, start_page, pages); |
ec487d1a JR |
586 | } |
587 | ||
588 | static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom) | |
589 | { | |
590 | int i, j; | |
591 | u64 *p1, *p2, *p3; | |
592 | ||
593 | p1 = dma_dom->domain.pt_root; | |
594 | ||
595 | if (!p1) | |
596 | return; | |
597 | ||
598 | for (i = 0; i < 512; ++i) { | |
599 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
600 | continue; | |
601 | ||
602 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 603 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
604 | if (!IOMMU_PTE_PRESENT(p2[j])) |
605 | continue; | |
606 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
607 | free_page((unsigned long)p3); | |
608 | } | |
609 | ||
610 | free_page((unsigned long)p2); | |
611 | } | |
612 | ||
613 | free_page((unsigned long)p1); | |
614 | } | |
615 | ||
431b2a20 JR |
616 | /* |
617 | * Free a domain, only used if something went wrong in the | |
618 | * allocation path and we need to free an already allocated page table | |
619 | */ | |
ec487d1a JR |
620 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
621 | { | |
622 | if (!dom) | |
623 | return; | |
624 | ||
625 | dma_ops_free_pagetable(dom); | |
626 | ||
627 | kfree(dom->pte_pages); | |
628 | ||
629 | kfree(dom->bitmap); | |
630 | ||
631 | kfree(dom); | |
632 | } | |
633 | ||
431b2a20 JR |
634 | /* |
635 | * Allocates a new protection domain usable for the dma_ops functions. | |
636 | * It also intializes the page table and the address allocator data | |
637 | * structures required for the dma_ops interface | |
638 | */ | |
ec487d1a JR |
639 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
640 | unsigned order) | |
641 | { | |
642 | struct dma_ops_domain *dma_dom; | |
643 | unsigned i, num_pte_pages; | |
644 | u64 *l2_pde; | |
645 | u64 address; | |
646 | ||
647 | /* | |
648 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
649 | */ | |
650 | if ((order < 25) || (order > 30)) | |
651 | return NULL; | |
652 | ||
653 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
654 | if (!dma_dom) | |
655 | return NULL; | |
656 | ||
657 | spin_lock_init(&dma_dom->domain.lock); | |
658 | ||
659 | dma_dom->domain.id = domain_id_alloc(); | |
660 | if (dma_dom->domain.id == 0) | |
661 | goto free_dma_dom; | |
662 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
663 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
664 | dma_dom->domain.priv = dma_dom; | |
665 | if (!dma_dom->domain.pt_root) | |
666 | goto free_dma_dom; | |
667 | dma_dom->aperture_size = (1ULL << order); | |
668 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
669 | GFP_KERNEL); | |
670 | if (!dma_dom->bitmap) | |
671 | goto free_dma_dom; | |
672 | /* | |
673 | * mark the first page as allocated so we never return 0 as | |
674 | * a valid dma-address. So we can use 0 as error value | |
675 | */ | |
676 | dma_dom->bitmap[0] = 1; | |
677 | dma_dom->next_bit = 0; | |
678 | ||
1c655773 | 679 | dma_dom->need_flush = false; |
bd60b735 | 680 | dma_dom->target_dev = 0xffff; |
1c655773 | 681 | |
431b2a20 | 682 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
683 | if (iommu->exclusion_start && |
684 | iommu->exclusion_start < dma_dom->aperture_size) { | |
685 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
e3c449f5 JR |
686 | int pages = iommu_num_pages(iommu->exclusion_start, |
687 | iommu->exclusion_length, | |
688 | PAGE_SIZE); | |
ec487d1a JR |
689 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
690 | } | |
691 | ||
431b2a20 JR |
692 | /* |
693 | * At the last step, build the page tables so we don't need to | |
694 | * allocate page table pages in the dma_ops mapping/unmapping | |
695 | * path. | |
696 | */ | |
ec487d1a JR |
697 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
698 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
699 | GFP_KERNEL); | |
700 | if (!dma_dom->pte_pages) | |
701 | goto free_dma_dom; | |
702 | ||
703 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
704 | if (l2_pde == NULL) | |
705 | goto free_dma_dom; | |
706 | ||
707 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
708 | ||
709 | for (i = 0; i < num_pte_pages; ++i) { | |
710 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
711 | if (!dma_dom->pte_pages[i]) | |
712 | goto free_dma_dom; | |
713 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
714 | l2_pde[i] = IOMMU_L1_PDE(address); | |
715 | } | |
716 | ||
717 | return dma_dom; | |
718 | ||
719 | free_dma_dom: | |
720 | dma_ops_domain_free(dma_dom); | |
721 | ||
722 | return NULL; | |
723 | } | |
724 | ||
431b2a20 JR |
725 | /* |
726 | * Find out the protection domain structure for a given PCI device. This | |
727 | * will give us the pointer to the page table root for example. | |
728 | */ | |
b20ac0d4 JR |
729 | static struct protection_domain *domain_for_device(u16 devid) |
730 | { | |
731 | struct protection_domain *dom; | |
732 | unsigned long flags; | |
733 | ||
734 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
735 | dom = amd_iommu_pd_table[devid]; | |
736 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
737 | ||
738 | return dom; | |
739 | } | |
740 | ||
431b2a20 JR |
741 | /* |
742 | * If a device is not yet associated with a domain, this function does | |
743 | * assigns it visible for the hardware | |
744 | */ | |
b20ac0d4 JR |
745 | static void set_device_domain(struct amd_iommu *iommu, |
746 | struct protection_domain *domain, | |
747 | u16 devid) | |
748 | { | |
749 | unsigned long flags; | |
750 | ||
751 | u64 pte_root = virt_to_phys(domain->pt_root); | |
752 | ||
38ddf41b JR |
753 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
754 | << DEV_ENTRY_MODE_SHIFT; | |
755 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
756 | |
757 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
758 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
759 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
760 | amd_iommu_dev_table[devid].data[2] = domain->id; |
761 | ||
762 | amd_iommu_pd_table[devid] = domain; | |
763 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
764 | ||
765 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
766 | } |
767 | ||
431b2a20 JR |
768 | /***************************************************************************** |
769 | * | |
770 | * The next functions belong to the dma_ops mapping/unmapping code. | |
771 | * | |
772 | *****************************************************************************/ | |
773 | ||
dbcc112e JR |
774 | /* |
775 | * This function checks if the driver got a valid device from the caller to | |
776 | * avoid dereferencing invalid pointers. | |
777 | */ | |
778 | static bool check_device(struct device *dev) | |
779 | { | |
780 | if (!dev || !dev->dma_mask) | |
781 | return false; | |
782 | ||
783 | return true; | |
784 | } | |
785 | ||
bd60b735 JR |
786 | /* |
787 | * In this function the list of preallocated protection domains is traversed to | |
788 | * find the domain for a specific device | |
789 | */ | |
790 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
791 | { | |
792 | struct dma_ops_domain *entry, *ret = NULL; | |
793 | unsigned long flags; | |
794 | ||
795 | if (list_empty(&iommu_pd_list)) | |
796 | return NULL; | |
797 | ||
798 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
799 | ||
800 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
801 | if (entry->target_dev == devid) { | |
802 | ret = entry; | |
803 | list_del(&ret->list); | |
804 | break; | |
805 | } | |
806 | } | |
807 | ||
808 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
809 | ||
810 | return ret; | |
811 | } | |
812 | ||
431b2a20 JR |
813 | /* |
814 | * In the dma_ops path we only have the struct device. This function | |
815 | * finds the corresponding IOMMU, the protection domain and the | |
816 | * requestor id for a given device. | |
817 | * If the device is not yet associated with a domain this is also done | |
818 | * in this function. | |
819 | */ | |
b20ac0d4 JR |
820 | static int get_device_resources(struct device *dev, |
821 | struct amd_iommu **iommu, | |
822 | struct protection_domain **domain, | |
823 | u16 *bdf) | |
824 | { | |
825 | struct dma_ops_domain *dma_dom; | |
826 | struct pci_dev *pcidev; | |
827 | u16 _bdf; | |
828 | ||
dbcc112e JR |
829 | *iommu = NULL; |
830 | *domain = NULL; | |
831 | *bdf = 0xffff; | |
832 | ||
833 | if (dev->bus != &pci_bus_type) | |
834 | return 0; | |
b20ac0d4 JR |
835 | |
836 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 837 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 838 | |
431b2a20 | 839 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 840 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 841 | return 0; |
b20ac0d4 JR |
842 | |
843 | *bdf = amd_iommu_alias_table[_bdf]; | |
844 | ||
845 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
846 | if (*iommu == NULL) | |
847 | return 0; | |
b20ac0d4 JR |
848 | *domain = domain_for_device(*bdf); |
849 | if (*domain == NULL) { | |
bd60b735 JR |
850 | dma_dom = find_protection_domain(*bdf); |
851 | if (!dma_dom) | |
852 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 JR |
853 | *domain = &dma_dom->domain; |
854 | set_device_domain(*iommu, *domain, *bdf); | |
855 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
856 | "device ", (*domain)->id); | |
857 | print_devid(_bdf, 1); | |
858 | } | |
859 | ||
f91ba190 JR |
860 | if (domain_for_device(_bdf) == NULL) |
861 | set_device_domain(*iommu, *domain, _bdf); | |
862 | ||
b20ac0d4 JR |
863 | return 1; |
864 | } | |
865 | ||
431b2a20 JR |
866 | /* |
867 | * This is the generic map function. It maps one 4kb page at paddr to | |
868 | * the given address in the DMA address space for the domain. | |
869 | */ | |
cb76c322 JR |
870 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
871 | struct dma_ops_domain *dom, | |
872 | unsigned long address, | |
873 | phys_addr_t paddr, | |
874 | int direction) | |
875 | { | |
876 | u64 *pte, __pte; | |
877 | ||
878 | WARN_ON(address > dom->aperture_size); | |
879 | ||
880 | paddr &= PAGE_MASK; | |
881 | ||
882 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
883 | pte += IOMMU_PTE_L0_INDEX(address); | |
884 | ||
885 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
886 | ||
887 | if (direction == DMA_TO_DEVICE) | |
888 | __pte |= IOMMU_PTE_IR; | |
889 | else if (direction == DMA_FROM_DEVICE) | |
890 | __pte |= IOMMU_PTE_IW; | |
891 | else if (direction == DMA_BIDIRECTIONAL) | |
892 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
893 | ||
894 | WARN_ON(*pte); | |
895 | ||
896 | *pte = __pte; | |
897 | ||
898 | return (dma_addr_t)address; | |
899 | } | |
900 | ||
431b2a20 JR |
901 | /* |
902 | * The generic unmapping function for on page in the DMA address space. | |
903 | */ | |
cb76c322 JR |
904 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
905 | struct dma_ops_domain *dom, | |
906 | unsigned long address) | |
907 | { | |
908 | u64 *pte; | |
909 | ||
910 | if (address >= dom->aperture_size) | |
911 | return; | |
912 | ||
913 | WARN_ON(address & 0xfffULL || address > dom->aperture_size); | |
914 | ||
915 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
916 | pte += IOMMU_PTE_L0_INDEX(address); | |
917 | ||
918 | WARN_ON(!*pte); | |
919 | ||
920 | *pte = 0ULL; | |
921 | } | |
922 | ||
431b2a20 JR |
923 | /* |
924 | * This function contains common code for mapping of a physically | |
925 | * contiguous memory region into DMA address space. It is uses by all | |
926 | * mapping functions provided by this IOMMU driver. | |
927 | * Must be called with the domain lock held. | |
928 | */ | |
cb76c322 JR |
929 | static dma_addr_t __map_single(struct device *dev, |
930 | struct amd_iommu *iommu, | |
931 | struct dma_ops_domain *dma_dom, | |
932 | phys_addr_t paddr, | |
933 | size_t size, | |
6d4f343f | 934 | int dir, |
832a90c3 JR |
935 | bool align, |
936 | u64 dma_mask) | |
cb76c322 JR |
937 | { |
938 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
939 | dma_addr_t address, start; | |
940 | unsigned int pages; | |
6d4f343f | 941 | unsigned long align_mask = 0; |
cb76c322 JR |
942 | int i; |
943 | ||
e3c449f5 | 944 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
945 | paddr &= PAGE_MASK; |
946 | ||
6d4f343f JR |
947 | if (align) |
948 | align_mask = (1UL << get_order(size)) - 1; | |
949 | ||
832a90c3 JR |
950 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
951 | dma_mask); | |
cb76c322 JR |
952 | if (unlikely(address == bad_dma_address)) |
953 | goto out; | |
954 | ||
955 | start = address; | |
956 | for (i = 0; i < pages; ++i) { | |
957 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
958 | paddr += PAGE_SIZE; | |
959 | start += PAGE_SIZE; | |
960 | } | |
961 | address += offset; | |
962 | ||
afa9fdc2 | 963 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
964 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
965 | dma_dom->need_flush = false; | |
966 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
967 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
968 | ||
cb76c322 JR |
969 | out: |
970 | return address; | |
971 | } | |
972 | ||
431b2a20 JR |
973 | /* |
974 | * Does the reverse of the __map_single function. Must be called with | |
975 | * the domain lock held too | |
976 | */ | |
cb76c322 JR |
977 | static void __unmap_single(struct amd_iommu *iommu, |
978 | struct dma_ops_domain *dma_dom, | |
979 | dma_addr_t dma_addr, | |
980 | size_t size, | |
981 | int dir) | |
982 | { | |
983 | dma_addr_t i, start; | |
984 | unsigned int pages; | |
985 | ||
986 | if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size)) | |
987 | return; | |
988 | ||
e3c449f5 | 989 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
990 | dma_addr &= PAGE_MASK; |
991 | start = dma_addr; | |
992 | ||
993 | for (i = 0; i < pages; ++i) { | |
994 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
995 | start += PAGE_SIZE; | |
996 | } | |
997 | ||
998 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
270cab24 | 999 | |
80be308d | 1000 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1001 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1002 | dma_dom->need_flush = false; |
1003 | } | |
cb76c322 JR |
1004 | } |
1005 | ||
431b2a20 JR |
1006 | /* |
1007 | * The exported map_single function for dma_ops. | |
1008 | */ | |
4da70b9e JR |
1009 | static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, |
1010 | size_t size, int dir) | |
1011 | { | |
1012 | unsigned long flags; | |
1013 | struct amd_iommu *iommu; | |
1014 | struct protection_domain *domain; | |
1015 | u16 devid; | |
1016 | dma_addr_t addr; | |
832a90c3 | 1017 | u64 dma_mask; |
4da70b9e | 1018 | |
dbcc112e JR |
1019 | if (!check_device(dev)) |
1020 | return bad_dma_address; | |
1021 | ||
832a90c3 | 1022 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1023 | |
1024 | get_device_resources(dev, &iommu, &domain, &devid); | |
1025 | ||
1026 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1027 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1028 | return (dma_addr_t)paddr; |
1029 | ||
1030 | spin_lock_irqsave(&domain->lock, flags); | |
832a90c3 JR |
1031 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1032 | dma_mask); | |
4da70b9e JR |
1033 | if (addr == bad_dma_address) |
1034 | goto out; | |
1035 | ||
09ee17eb | 1036 | iommu_completion_wait(iommu); |
4da70b9e JR |
1037 | |
1038 | out: | |
1039 | spin_unlock_irqrestore(&domain->lock, flags); | |
1040 | ||
1041 | return addr; | |
1042 | } | |
1043 | ||
431b2a20 JR |
1044 | /* |
1045 | * The exported unmap_single function for dma_ops. | |
1046 | */ | |
4da70b9e JR |
1047 | static void unmap_single(struct device *dev, dma_addr_t dma_addr, |
1048 | size_t size, int dir) | |
1049 | { | |
1050 | unsigned long flags; | |
1051 | struct amd_iommu *iommu; | |
1052 | struct protection_domain *domain; | |
1053 | u16 devid; | |
1054 | ||
dbcc112e JR |
1055 | if (!check_device(dev) || |
1056 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1057 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1058 | return; |
1059 | ||
1060 | spin_lock_irqsave(&domain->lock, flags); | |
1061 | ||
1062 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1063 | ||
09ee17eb | 1064 | iommu_completion_wait(iommu); |
4da70b9e JR |
1065 | |
1066 | spin_unlock_irqrestore(&domain->lock, flags); | |
1067 | } | |
1068 | ||
431b2a20 JR |
1069 | /* |
1070 | * This is a special map_sg function which is used if we should map a | |
1071 | * device which is not handled by an AMD IOMMU in the system. | |
1072 | */ | |
65b050ad JR |
1073 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1074 | int nelems, int dir) | |
1075 | { | |
1076 | struct scatterlist *s; | |
1077 | int i; | |
1078 | ||
1079 | for_each_sg(sglist, s, nelems, i) { | |
1080 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1081 | s->dma_length = s->length; | |
1082 | } | |
1083 | ||
1084 | return nelems; | |
1085 | } | |
1086 | ||
431b2a20 JR |
1087 | /* |
1088 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1089 | * lists). | |
1090 | */ | |
65b050ad JR |
1091 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
1092 | int nelems, int dir) | |
1093 | { | |
1094 | unsigned long flags; | |
1095 | struct amd_iommu *iommu; | |
1096 | struct protection_domain *domain; | |
1097 | u16 devid; | |
1098 | int i; | |
1099 | struct scatterlist *s; | |
1100 | phys_addr_t paddr; | |
1101 | int mapped_elems = 0; | |
832a90c3 | 1102 | u64 dma_mask; |
65b050ad | 1103 | |
dbcc112e JR |
1104 | if (!check_device(dev)) |
1105 | return 0; | |
1106 | ||
832a90c3 | 1107 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1108 | |
1109 | get_device_resources(dev, &iommu, &domain, &devid); | |
1110 | ||
1111 | if (!iommu || !domain) | |
1112 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1113 | ||
1114 | spin_lock_irqsave(&domain->lock, flags); | |
1115 | ||
1116 | for_each_sg(sglist, s, nelems, i) { | |
1117 | paddr = sg_phys(s); | |
1118 | ||
1119 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1120 | paddr, s->length, dir, false, |
1121 | dma_mask); | |
65b050ad JR |
1122 | |
1123 | if (s->dma_address) { | |
1124 | s->dma_length = s->length; | |
1125 | mapped_elems++; | |
1126 | } else | |
1127 | goto unmap; | |
65b050ad JR |
1128 | } |
1129 | ||
09ee17eb | 1130 | iommu_completion_wait(iommu); |
65b050ad JR |
1131 | |
1132 | out: | |
1133 | spin_unlock_irqrestore(&domain->lock, flags); | |
1134 | ||
1135 | return mapped_elems; | |
1136 | unmap: | |
1137 | for_each_sg(sglist, s, mapped_elems, i) { | |
1138 | if (s->dma_address) | |
1139 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1140 | s->dma_length, dir); | |
1141 | s->dma_address = s->dma_length = 0; | |
1142 | } | |
1143 | ||
1144 | mapped_elems = 0; | |
1145 | ||
1146 | goto out; | |
1147 | } | |
1148 | ||
431b2a20 JR |
1149 | /* |
1150 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1151 | * lists). | |
1152 | */ | |
65b050ad JR |
1153 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
1154 | int nelems, int dir) | |
1155 | { | |
1156 | unsigned long flags; | |
1157 | struct amd_iommu *iommu; | |
1158 | struct protection_domain *domain; | |
1159 | struct scatterlist *s; | |
1160 | u16 devid; | |
1161 | int i; | |
1162 | ||
dbcc112e JR |
1163 | if (!check_device(dev) || |
1164 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1165 | return; |
1166 | ||
1167 | spin_lock_irqsave(&domain->lock, flags); | |
1168 | ||
1169 | for_each_sg(sglist, s, nelems, i) { | |
1170 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1171 | s->dma_length, dir); | |
65b050ad JR |
1172 | s->dma_address = s->dma_length = 0; |
1173 | } | |
1174 | ||
09ee17eb | 1175 | iommu_completion_wait(iommu); |
65b050ad JR |
1176 | |
1177 | spin_unlock_irqrestore(&domain->lock, flags); | |
1178 | } | |
1179 | ||
431b2a20 JR |
1180 | /* |
1181 | * The exported alloc_coherent function for dma_ops. | |
1182 | */ | |
5d8b53cf JR |
1183 | static void *alloc_coherent(struct device *dev, size_t size, |
1184 | dma_addr_t *dma_addr, gfp_t flag) | |
1185 | { | |
1186 | unsigned long flags; | |
1187 | void *virt_addr; | |
1188 | struct amd_iommu *iommu; | |
1189 | struct protection_domain *domain; | |
1190 | u16 devid; | |
1191 | phys_addr_t paddr; | |
832a90c3 | 1192 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1193 | |
dbcc112e JR |
1194 | if (!check_device(dev)) |
1195 | return NULL; | |
5d8b53cf | 1196 | |
13d9fead FT |
1197 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1198 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1199 | |
c97ac535 | 1200 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1201 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1202 | if (!virt_addr) | |
1203 | return 0; | |
1204 | ||
5d8b53cf JR |
1205 | paddr = virt_to_phys(virt_addr); |
1206 | ||
5d8b53cf JR |
1207 | if (!iommu || !domain) { |
1208 | *dma_addr = (dma_addr_t)paddr; | |
1209 | return virt_addr; | |
1210 | } | |
1211 | ||
832a90c3 JR |
1212 | if (!dma_mask) |
1213 | dma_mask = *dev->dma_mask; | |
1214 | ||
5d8b53cf JR |
1215 | spin_lock_irqsave(&domain->lock, flags); |
1216 | ||
1217 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1218 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf JR |
1219 | |
1220 | if (*dma_addr == bad_dma_address) { | |
1221 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1222 | virt_addr = NULL; | |
1223 | goto out; | |
1224 | } | |
1225 | ||
09ee17eb | 1226 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1227 | |
1228 | out: | |
1229 | spin_unlock_irqrestore(&domain->lock, flags); | |
1230 | ||
1231 | return virt_addr; | |
1232 | } | |
1233 | ||
431b2a20 JR |
1234 | /* |
1235 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1236 | */ |
5d8b53cf JR |
1237 | static void free_coherent(struct device *dev, size_t size, |
1238 | void *virt_addr, dma_addr_t dma_addr) | |
1239 | { | |
1240 | unsigned long flags; | |
1241 | struct amd_iommu *iommu; | |
1242 | struct protection_domain *domain; | |
1243 | u16 devid; | |
1244 | ||
dbcc112e JR |
1245 | if (!check_device(dev)) |
1246 | return; | |
1247 | ||
5d8b53cf JR |
1248 | get_device_resources(dev, &iommu, &domain, &devid); |
1249 | ||
1250 | if (!iommu || !domain) | |
1251 | goto free_mem; | |
1252 | ||
1253 | spin_lock_irqsave(&domain->lock, flags); | |
1254 | ||
1255 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1256 | |
09ee17eb | 1257 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1258 | |
1259 | spin_unlock_irqrestore(&domain->lock, flags); | |
1260 | ||
1261 | free_mem: | |
1262 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1263 | } | |
1264 | ||
b39ba6ad JR |
1265 | /* |
1266 | * This function is called by the DMA layer to find out if we can handle a | |
1267 | * particular device. It is part of the dma_ops. | |
1268 | */ | |
1269 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1270 | { | |
1271 | u16 bdf; | |
1272 | struct pci_dev *pcidev; | |
1273 | ||
1274 | /* No device or no PCI device */ | |
1275 | if (!dev || dev->bus != &pci_bus_type) | |
1276 | return 0; | |
1277 | ||
1278 | pcidev = to_pci_dev(dev); | |
1279 | ||
1280 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1281 | ||
1282 | /* Out of our scope? */ | |
1283 | if (bdf > amd_iommu_last_bdf) | |
1284 | return 0; | |
1285 | ||
1286 | return 1; | |
1287 | } | |
1288 | ||
c432f3df | 1289 | /* |
431b2a20 JR |
1290 | * The function for pre-allocating protection domains. |
1291 | * | |
c432f3df JR |
1292 | * If the driver core informs the DMA layer if a driver grabs a device |
1293 | * we don't need to preallocate the protection domains anymore. | |
1294 | * For now we have to. | |
1295 | */ | |
1296 | void prealloc_protection_domains(void) | |
1297 | { | |
1298 | struct pci_dev *dev = NULL; | |
1299 | struct dma_ops_domain *dma_dom; | |
1300 | struct amd_iommu *iommu; | |
1301 | int order = amd_iommu_aperture_order; | |
1302 | u16 devid; | |
1303 | ||
1304 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1305 | devid = (dev->bus->number << 8) | dev->devfn; | |
3a61ec38 | 1306 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1307 | continue; |
1308 | devid = amd_iommu_alias_table[devid]; | |
1309 | if (domain_for_device(devid)) | |
1310 | continue; | |
1311 | iommu = amd_iommu_rlookup_table[devid]; | |
1312 | if (!iommu) | |
1313 | continue; | |
1314 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1315 | if (!dma_dom) | |
1316 | continue; | |
1317 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1318 | dma_dom->target_dev = devid; |
1319 | ||
1320 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1321 | } |
1322 | } | |
1323 | ||
6631ee9d JR |
1324 | static struct dma_mapping_ops amd_iommu_dma_ops = { |
1325 | .alloc_coherent = alloc_coherent, | |
1326 | .free_coherent = free_coherent, | |
1327 | .map_single = map_single, | |
1328 | .unmap_single = unmap_single, | |
1329 | .map_sg = map_sg, | |
1330 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1331 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1332 | }; |
1333 | ||
431b2a20 JR |
1334 | /* |
1335 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1336 | */ | |
6631ee9d JR |
1337 | int __init amd_iommu_init_dma_ops(void) |
1338 | { | |
1339 | struct amd_iommu *iommu; | |
1340 | int order = amd_iommu_aperture_order; | |
1341 | int ret; | |
1342 | ||
431b2a20 JR |
1343 | /* |
1344 | * first allocate a default protection domain for every IOMMU we | |
1345 | * found in the system. Devices not assigned to any other | |
1346 | * protection domain will be assigned to the default one. | |
1347 | */ | |
6631ee9d JR |
1348 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1349 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1350 | if (iommu->default_dom == NULL) | |
1351 | return -ENOMEM; | |
1352 | ret = iommu_init_unity_mappings(iommu); | |
1353 | if (ret) | |
1354 | goto free_domains; | |
1355 | } | |
1356 | ||
431b2a20 JR |
1357 | /* |
1358 | * If device isolation is enabled, pre-allocate the protection | |
1359 | * domains for each device. | |
1360 | */ | |
6631ee9d JR |
1361 | if (amd_iommu_isolate) |
1362 | prealloc_protection_domains(); | |
1363 | ||
1364 | iommu_detected = 1; | |
1365 | force_iommu = 1; | |
1366 | bad_dma_address = 0; | |
92af4e29 | 1367 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1368 | gart_iommu_aperture_disabled = 1; |
1369 | gart_iommu_aperture = 0; | |
92af4e29 | 1370 | #endif |
6631ee9d | 1371 | |
431b2a20 | 1372 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1373 | dma_ops = &amd_iommu_dma_ops; |
1374 | ||
1375 | return 0; | |
1376 | ||
1377 | free_domains: | |
1378 | ||
1379 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1380 | if (iommu->default_dom) | |
1381 | dma_ops_domain_free(iommu->default_dom); | |
1382 | } | |
1383 | ||
1384 | return ret; | |
1385 | } |