Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
bf3118c1 | 2 | * Copyright (C) 2007-2009 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
6a9401a7 | 31 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
0feae533 JR |
45 | /* |
46 | * Domain for untranslated devices - only allocated | |
47 | * if iommu=pt passed on kernel cmd line. | |
48 | */ | |
49 | static struct protection_domain *pt_domain; | |
50 | ||
26961efe | 51 | static struct iommu_ops amd_iommu_ops; |
26961efe | 52 | |
431b2a20 JR |
53 | /* |
54 | * general struct to manage commands send to an IOMMU | |
55 | */ | |
d6449536 | 56 | struct iommu_cmd { |
b6c02715 JR |
57 | u32 data[4]; |
58 | }; | |
59 | ||
a345b23b | 60 | static void reset_iommu_command_buffer(struct amd_iommu *iommu); |
04bfdd84 | 61 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 62 | |
15898bbc JR |
63 | /**************************************************************************** |
64 | * | |
65 | * Helper functions | |
66 | * | |
67 | ****************************************************************************/ | |
68 | ||
69 | static inline u16 get_device_id(struct device *dev) | |
70 | { | |
71 | struct pci_dev *pdev = to_pci_dev(dev); | |
72 | ||
73 | return calc_devid(pdev->bus->number, pdev->devfn); | |
74 | } | |
75 | ||
657cbb6b JR |
76 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
77 | { | |
78 | return dev->archdata.iommu; | |
79 | } | |
80 | ||
71c70984 JR |
81 | /* |
82 | * In this function the list of preallocated protection domains is traversed to | |
83 | * find the domain for a specific device | |
84 | */ | |
85 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
86 | { | |
87 | struct dma_ops_domain *entry, *ret = NULL; | |
88 | unsigned long flags; | |
89 | u16 alias = amd_iommu_alias_table[devid]; | |
90 | ||
91 | if (list_empty(&iommu_pd_list)) | |
92 | return NULL; | |
93 | ||
94 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
95 | ||
96 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
97 | if (entry->target_dev == devid || | |
98 | entry->target_dev == alias) { | |
99 | ret = entry; | |
100 | break; | |
101 | } | |
102 | } | |
103 | ||
104 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
105 | ||
106 | return ret; | |
107 | } | |
108 | ||
98fc5a69 JR |
109 | /* |
110 | * This function checks if the driver got a valid device from the caller to | |
111 | * avoid dereferencing invalid pointers. | |
112 | */ | |
113 | static bool check_device(struct device *dev) | |
114 | { | |
115 | u16 devid; | |
116 | ||
117 | if (!dev || !dev->dma_mask) | |
118 | return false; | |
119 | ||
120 | /* No device or no PCI device */ | |
121 | if (!dev || dev->bus != &pci_bus_type) | |
122 | return false; | |
123 | ||
124 | devid = get_device_id(dev); | |
125 | ||
126 | /* Out of our scope? */ | |
127 | if (devid > amd_iommu_last_bdf) | |
128 | return false; | |
129 | ||
130 | if (amd_iommu_rlookup_table[devid] == NULL) | |
131 | return false; | |
132 | ||
133 | return true; | |
134 | } | |
135 | ||
657cbb6b JR |
136 | static int iommu_init_device(struct device *dev) |
137 | { | |
138 | struct iommu_dev_data *dev_data; | |
139 | struct pci_dev *pdev; | |
140 | u16 devid, alias; | |
141 | ||
142 | if (dev->archdata.iommu) | |
143 | return 0; | |
144 | ||
145 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
146 | if (!dev_data) | |
147 | return -ENOMEM; | |
148 | ||
149 | devid = get_device_id(dev); | |
150 | alias = amd_iommu_alias_table[devid]; | |
151 | pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff); | |
152 | if (pdev) | |
153 | dev_data->alias = &pdev->dev; | |
154 | ||
155 | dev->archdata.iommu = dev_data; | |
156 | ||
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
161 | static void iommu_uninit_device(struct device *dev) | |
162 | { | |
163 | kfree(dev->archdata.iommu); | |
164 | } | |
7f26508b JR |
165 | #ifdef CONFIG_AMD_IOMMU_STATS |
166 | ||
167 | /* | |
168 | * Initialization code for statistics collection | |
169 | */ | |
170 | ||
da49f6df | 171 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 172 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 173 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 174 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 175 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 176 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 177 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 178 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 179 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 180 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 181 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 182 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 183 | |
7f26508b | 184 | static struct dentry *stats_dir; |
7f26508b JR |
185 | static struct dentry *de_fflush; |
186 | ||
187 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
188 | { | |
189 | if (stats_dir == NULL) | |
190 | return; | |
191 | ||
192 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
193 | &cnt->value); | |
194 | } | |
195 | ||
196 | static void amd_iommu_stats_init(void) | |
197 | { | |
198 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
199 | if (stats_dir == NULL) | |
200 | return; | |
201 | ||
7f26508b JR |
202 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
203 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
204 | |
205 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 206 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 207 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 208 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 209 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 210 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 211 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 212 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 213 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 214 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 215 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 216 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
217 | } |
218 | ||
219 | #endif | |
220 | ||
a80dc3e0 JR |
221 | /**************************************************************************** |
222 | * | |
223 | * Interrupt handling functions | |
224 | * | |
225 | ****************************************************************************/ | |
226 | ||
e3e59876 JR |
227 | static void dump_dte_entry(u16 devid) |
228 | { | |
229 | int i; | |
230 | ||
231 | for (i = 0; i < 8; ++i) | |
232 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
233 | amd_iommu_dev_table[devid].data[i]); | |
234 | } | |
235 | ||
945b4ac4 JR |
236 | static void dump_command(unsigned long phys_addr) |
237 | { | |
238 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
239 | int i; | |
240 | ||
241 | for (i = 0; i < 4; ++i) | |
242 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
243 | } | |
244 | ||
a345b23b | 245 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
246 | { |
247 | u32 *event = __evt; | |
248 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
249 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
250 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
251 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
252 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
253 | ||
4c6f40d4 | 254 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
255 | |
256 | switch (type) { | |
257 | case EVENT_TYPE_ILL_DEV: | |
258 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
259 | "address=0x%016llx flags=0x%04x]\n", | |
260 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
261 | address, flags); | |
e3e59876 | 262 | dump_dte_entry(devid); |
90008ee4 JR |
263 | break; |
264 | case EVENT_TYPE_IO_FAULT: | |
265 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
266 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
267 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
268 | domid, address, flags); | |
269 | break; | |
270 | case EVENT_TYPE_DEV_TAB_ERR: | |
271 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
272 | "address=0x%016llx flags=0x%04x]\n", | |
273 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
274 | address, flags); | |
275 | break; | |
276 | case EVENT_TYPE_PAGE_TAB_ERR: | |
277 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
278 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
279 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
280 | domid, address, flags); | |
281 | break; | |
282 | case EVENT_TYPE_ILL_CMD: | |
283 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
a345b23b | 284 | reset_iommu_command_buffer(iommu); |
945b4ac4 | 285 | dump_command(address); |
90008ee4 JR |
286 | break; |
287 | case EVENT_TYPE_CMD_HARD_ERR: | |
288 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
289 | "flags=0x%04x]\n", address, flags); | |
290 | break; | |
291 | case EVENT_TYPE_IOTLB_INV_TO: | |
292 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
293 | "address=0x%016llx]\n", | |
294 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
295 | address); | |
296 | break; | |
297 | case EVENT_TYPE_INV_DEV_REQ: | |
298 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
299 | "address=0x%016llx flags=0x%04x]\n", | |
300 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
301 | address, flags); | |
302 | break; | |
303 | default: | |
304 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
305 | } | |
306 | } | |
307 | ||
308 | static void iommu_poll_events(struct amd_iommu *iommu) | |
309 | { | |
310 | u32 head, tail; | |
311 | unsigned long flags; | |
312 | ||
313 | spin_lock_irqsave(&iommu->lock, flags); | |
314 | ||
315 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
316 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
317 | ||
318 | while (head != tail) { | |
a345b23b | 319 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
320 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
321 | } | |
322 | ||
323 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
324 | ||
325 | spin_unlock_irqrestore(&iommu->lock, flags); | |
326 | } | |
327 | ||
a80dc3e0 JR |
328 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
329 | { | |
90008ee4 JR |
330 | struct amd_iommu *iommu; |
331 | ||
3bd22172 | 332 | for_each_iommu(iommu) |
90008ee4 JR |
333 | iommu_poll_events(iommu); |
334 | ||
335 | return IRQ_HANDLED; | |
a80dc3e0 JR |
336 | } |
337 | ||
431b2a20 JR |
338 | /**************************************************************************** |
339 | * | |
340 | * IOMMU command queuing functions | |
341 | * | |
342 | ****************************************************************************/ | |
343 | ||
344 | /* | |
345 | * Writes the command to the IOMMUs command buffer and informs the | |
346 | * hardware about the new command. Must be called with iommu->lock held. | |
347 | */ | |
d6449536 | 348 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
349 | { |
350 | u32 tail, head; | |
351 | u8 *target; | |
352 | ||
353 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 354 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
355 | memcpy_toio(target, cmd, sizeof(*cmd)); |
356 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
357 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
358 | if (tail == head) | |
359 | return -ENOMEM; | |
360 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
431b2a20 JR |
365 | /* |
366 | * General queuing function for commands. Takes iommu->lock and calls | |
367 | * __iommu_queue_command(). | |
368 | */ | |
d6449536 | 369 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
370 | { |
371 | unsigned long flags; | |
372 | int ret; | |
373 | ||
374 | spin_lock_irqsave(&iommu->lock, flags); | |
375 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 376 | if (!ret) |
0cfd7aa9 | 377 | iommu->need_sync = true; |
a19ae1ec JR |
378 | spin_unlock_irqrestore(&iommu->lock, flags); |
379 | ||
380 | return ret; | |
381 | } | |
382 | ||
8d201968 JR |
383 | /* |
384 | * This function waits until an IOMMU has completed a completion | |
385 | * wait command | |
386 | */ | |
387 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
388 | { | |
389 | int ready = 0; | |
390 | unsigned status = 0; | |
391 | unsigned long i = 0; | |
392 | ||
da49f6df JR |
393 | INC_STATS_COUNTER(compl_wait); |
394 | ||
8d201968 JR |
395 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
396 | ++i; | |
397 | /* wait for the bit to become one */ | |
398 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
399 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
400 | } | |
401 | ||
402 | /* set bit back to zero */ | |
403 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
404 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
405 | ||
6a1eddd2 JR |
406 | if (unlikely(i == EXIT_LOOP_COUNT)) { |
407 | spin_unlock(&iommu->lock); | |
408 | reset_iommu_command_buffer(iommu); | |
409 | spin_lock(&iommu->lock); | |
410 | } | |
8d201968 JR |
411 | } |
412 | ||
413 | /* | |
414 | * This function queues a completion wait command into the command | |
415 | * buffer of an IOMMU | |
416 | */ | |
417 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
418 | { | |
419 | struct iommu_cmd cmd; | |
420 | ||
421 | memset(&cmd, 0, sizeof(cmd)); | |
422 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
423 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
424 | ||
425 | return __iommu_queue_command(iommu, &cmd); | |
426 | } | |
427 | ||
431b2a20 JR |
428 | /* |
429 | * This function is called whenever we need to ensure that the IOMMU has | |
430 | * completed execution of all commands we sent. It sends a | |
431 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
432 | * us about that by writing a value to a physical address we pass with | |
433 | * the command. | |
434 | */ | |
a19ae1ec JR |
435 | static int iommu_completion_wait(struct amd_iommu *iommu) |
436 | { | |
8d201968 JR |
437 | int ret = 0; |
438 | unsigned long flags; | |
a19ae1ec | 439 | |
7e4f88da JR |
440 | spin_lock_irqsave(&iommu->lock, flags); |
441 | ||
09ee17eb JR |
442 | if (!iommu->need_sync) |
443 | goto out; | |
444 | ||
8d201968 | 445 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 446 | |
0cfd7aa9 | 447 | iommu->need_sync = false; |
a19ae1ec JR |
448 | |
449 | if (ret) | |
7e4f88da | 450 | goto out; |
a19ae1ec | 451 | |
8d201968 | 452 | __iommu_wait_for_completion(iommu); |
84df8175 | 453 | |
7e4f88da JR |
454 | out: |
455 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
456 | |
457 | return 0; | |
458 | } | |
459 | ||
0518a3a4 JR |
460 | static void iommu_flush_complete(struct protection_domain *domain) |
461 | { | |
462 | int i; | |
463 | ||
464 | for (i = 0; i < amd_iommus_present; ++i) { | |
465 | if (!domain->dev_iommu[i]) | |
466 | continue; | |
467 | ||
468 | /* | |
469 | * Devices of this domain are behind this IOMMU | |
470 | * We need to wait for completion of all commands. | |
471 | */ | |
472 | iommu_completion_wait(amd_iommus[i]); | |
473 | } | |
474 | } | |
475 | ||
431b2a20 JR |
476 | /* |
477 | * Command send function for invalidating a device table entry | |
478 | */ | |
a19ae1ec JR |
479 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
480 | { | |
d6449536 | 481 | struct iommu_cmd cmd; |
ee2fa743 | 482 | int ret; |
a19ae1ec JR |
483 | |
484 | BUG_ON(iommu == NULL); | |
485 | ||
486 | memset(&cmd, 0, sizeof(cmd)); | |
487 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
488 | cmd.data[0] = devid; | |
489 | ||
ee2fa743 JR |
490 | ret = iommu_queue_command(iommu, &cmd); |
491 | ||
ee2fa743 | 492 | return ret; |
a19ae1ec JR |
493 | } |
494 | ||
237b6f33 JR |
495 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
496 | u16 domid, int pde, int s) | |
497 | { | |
498 | memset(cmd, 0, sizeof(*cmd)); | |
499 | address &= PAGE_MASK; | |
500 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
501 | cmd->data[1] |= domid; | |
502 | cmd->data[2] = lower_32_bits(address); | |
503 | cmd->data[3] = upper_32_bits(address); | |
504 | if (s) /* size bit - we flush more than one 4kb page */ | |
505 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
506 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
507 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
508 | } | |
509 | ||
431b2a20 JR |
510 | /* |
511 | * Generic command send function for invalidaing TLB entries | |
512 | */ | |
a19ae1ec JR |
513 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
514 | u64 address, u16 domid, int pde, int s) | |
515 | { | |
d6449536 | 516 | struct iommu_cmd cmd; |
ee2fa743 | 517 | int ret; |
a19ae1ec | 518 | |
237b6f33 | 519 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 520 | |
ee2fa743 JR |
521 | ret = iommu_queue_command(iommu, &cmd); |
522 | ||
ee2fa743 | 523 | return ret; |
a19ae1ec JR |
524 | } |
525 | ||
431b2a20 JR |
526 | /* |
527 | * TLB invalidation function which is called from the mapping functions. | |
528 | * It invalidates a single PTE if the range to flush is within a single | |
529 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
530 | */ | |
6de8ad9b JR |
531 | static void __iommu_flush_pages(struct protection_domain *domain, |
532 | u64 address, size_t size, int pde) | |
a19ae1ec | 533 | { |
6de8ad9b | 534 | int s = 0, i; |
dcd1e92e | 535 | unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
536 | |
537 | address &= PAGE_MASK; | |
538 | ||
999ba417 JR |
539 | if (pages > 1) { |
540 | /* | |
541 | * If we have to flush more than one page, flush all | |
542 | * TLB entries for this domain | |
543 | */ | |
544 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
545 | s = 1; | |
a19ae1ec JR |
546 | } |
547 | ||
999ba417 | 548 | |
6de8ad9b JR |
549 | for (i = 0; i < amd_iommus_present; ++i) { |
550 | if (!domain->dev_iommu[i]) | |
551 | continue; | |
552 | ||
553 | /* | |
554 | * Devices of this domain are behind this IOMMU | |
555 | * We need a TLB flush | |
556 | */ | |
557 | iommu_queue_inv_iommu_pages(amd_iommus[i], address, | |
558 | domain->id, pde, s); | |
559 | } | |
560 | ||
561 | return; | |
562 | } | |
563 | ||
564 | static void iommu_flush_pages(struct protection_domain *domain, | |
565 | u64 address, size_t size) | |
566 | { | |
567 | __iommu_flush_pages(domain, address, size, 0); | |
a19ae1ec | 568 | } |
b6c02715 | 569 | |
1c655773 | 570 | /* Flush the whole IO/TLB for a given protection domain */ |
dcd1e92e | 571 | static void iommu_flush_tlb(struct protection_domain *domain) |
1c655773 | 572 | { |
dcd1e92e | 573 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
574 | } |
575 | ||
42a49f96 | 576 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
dcd1e92e | 577 | static void iommu_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 578 | { |
dcd1e92e | 579 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
580 | } |
581 | ||
43f49609 | 582 | /* |
09b42804 | 583 | * This function flushes all domains that have devices on the given IOMMU |
43f49609 | 584 | */ |
09b42804 | 585 | static void flush_all_domains_on_iommu(struct amd_iommu *iommu) |
43f49609 | 586 | { |
09b42804 JR |
587 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; |
588 | struct protection_domain *domain; | |
e394d72a | 589 | unsigned long flags; |
18811f55 | 590 | |
09b42804 | 591 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); |
bfd1be18 | 592 | |
09b42804 JR |
593 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
594 | if (domain->dev_iommu[iommu->index] == 0) | |
bfd1be18 | 595 | continue; |
09b42804 JR |
596 | |
597 | spin_lock(&domain->lock); | |
598 | iommu_queue_inv_iommu_pages(iommu, address, domain->id, 1, 1); | |
599 | iommu_flush_complete(domain); | |
600 | spin_unlock(&domain->lock); | |
bfd1be18 | 601 | } |
e394d72a | 602 | |
09b42804 | 603 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); |
e394d72a JR |
604 | } |
605 | ||
09b42804 JR |
606 | /* |
607 | * This function uses heavy locking and may disable irqs for some time. But | |
608 | * this is no issue because it is only called during resume. | |
609 | */ | |
bfd1be18 | 610 | void amd_iommu_flush_all_domains(void) |
e394d72a | 611 | { |
e3306664 | 612 | struct protection_domain *domain; |
09b42804 JR |
613 | unsigned long flags; |
614 | ||
615 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
e394d72a | 616 | |
e3306664 | 617 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
09b42804 | 618 | spin_lock(&domain->lock); |
e3306664 JR |
619 | iommu_flush_tlb_pde(domain); |
620 | iommu_flush_complete(domain); | |
09b42804 | 621 | spin_unlock(&domain->lock); |
e3306664 | 622 | } |
09b42804 JR |
623 | |
624 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
bfd1be18 JR |
625 | } |
626 | ||
d586d785 | 627 | static void flush_all_devices_for_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
628 | { |
629 | int i; | |
630 | ||
d586d785 JR |
631 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { |
632 | if (iommu != amd_iommu_rlookup_table[i]) | |
bfd1be18 | 633 | continue; |
d586d785 JR |
634 | |
635 | iommu_queue_inv_dev_entry(iommu, i); | |
636 | iommu_completion_wait(iommu); | |
bfd1be18 JR |
637 | } |
638 | } | |
639 | ||
6a0dbcbe | 640 | static void flush_devices_by_domain(struct protection_domain *domain) |
7d7a110c JR |
641 | { |
642 | struct amd_iommu *iommu; | |
643 | int i; | |
644 | ||
645 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
6a0dbcbe JR |
646 | if ((domain == NULL && amd_iommu_pd_table[i] == NULL) || |
647 | (amd_iommu_pd_table[i] != domain)) | |
7d7a110c JR |
648 | continue; |
649 | ||
650 | iommu = amd_iommu_rlookup_table[i]; | |
651 | if (!iommu) | |
652 | continue; | |
653 | ||
654 | iommu_queue_inv_dev_entry(iommu, i); | |
655 | iommu_completion_wait(iommu); | |
656 | } | |
657 | } | |
658 | ||
a345b23b JR |
659 | static void reset_iommu_command_buffer(struct amd_iommu *iommu) |
660 | { | |
661 | pr_err("AMD-Vi: Resetting IOMMU command buffer\n"); | |
662 | ||
b26e81b8 JR |
663 | if (iommu->reset_in_progress) |
664 | panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n"); | |
665 | ||
666 | iommu->reset_in_progress = true; | |
667 | ||
a345b23b JR |
668 | amd_iommu_reset_cmd_buffer(iommu); |
669 | flush_all_devices_for_iommu(iommu); | |
670 | flush_all_domains_on_iommu(iommu); | |
b26e81b8 JR |
671 | |
672 | iommu->reset_in_progress = false; | |
a345b23b JR |
673 | } |
674 | ||
6a0dbcbe JR |
675 | void amd_iommu_flush_all_devices(void) |
676 | { | |
677 | flush_devices_by_domain(NULL); | |
678 | } | |
679 | ||
431b2a20 JR |
680 | /**************************************************************************** |
681 | * | |
682 | * The functions below are used the create the page table mappings for | |
683 | * unity mapped regions. | |
684 | * | |
685 | ****************************************************************************/ | |
686 | ||
308973d3 JR |
687 | /* |
688 | * This function is used to add another level to an IO page table. Adding | |
689 | * another level increases the size of the address space by 9 bits to a size up | |
690 | * to 64 bits. | |
691 | */ | |
692 | static bool increase_address_space(struct protection_domain *domain, | |
693 | gfp_t gfp) | |
694 | { | |
695 | u64 *pte; | |
696 | ||
697 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
698 | /* address space already 64 bit large */ | |
699 | return false; | |
700 | ||
701 | pte = (void *)get_zeroed_page(gfp); | |
702 | if (!pte) | |
703 | return false; | |
704 | ||
705 | *pte = PM_LEVEL_PDE(domain->mode, | |
706 | virt_to_phys(domain->pt_root)); | |
707 | domain->pt_root = pte; | |
708 | domain->mode += 1; | |
709 | domain->updated = true; | |
710 | ||
711 | return true; | |
712 | } | |
713 | ||
714 | static u64 *alloc_pte(struct protection_domain *domain, | |
715 | unsigned long address, | |
716 | int end_lvl, | |
717 | u64 **pte_page, | |
718 | gfp_t gfp) | |
719 | { | |
720 | u64 *pte, *page; | |
721 | int level; | |
722 | ||
723 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
724 | increase_address_space(domain, gfp); | |
725 | ||
726 | level = domain->mode - 1; | |
727 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
728 | ||
729 | while (level > end_lvl) { | |
730 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
731 | page = (u64 *)get_zeroed_page(gfp); | |
732 | if (!page) | |
733 | return NULL; | |
734 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
735 | } | |
736 | ||
737 | level -= 1; | |
738 | ||
739 | pte = IOMMU_PTE_PAGE(*pte); | |
740 | ||
741 | if (pte_page && level == end_lvl) | |
742 | *pte_page = pte; | |
743 | ||
744 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
745 | } | |
746 | ||
747 | return pte; | |
748 | } | |
749 | ||
750 | /* | |
751 | * This function checks if there is a PTE for a given dma address. If | |
752 | * there is one, it returns the pointer to it. | |
753 | */ | |
754 | static u64 *fetch_pte(struct protection_domain *domain, | |
755 | unsigned long address, int map_size) | |
756 | { | |
757 | int level; | |
758 | u64 *pte; | |
759 | ||
760 | level = domain->mode - 1; | |
761 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
762 | ||
763 | while (level > map_size) { | |
764 | if (!IOMMU_PTE_PRESENT(*pte)) | |
765 | return NULL; | |
766 | ||
767 | level -= 1; | |
768 | ||
769 | pte = IOMMU_PTE_PAGE(*pte); | |
770 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
771 | ||
772 | if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) { | |
773 | pte = NULL; | |
774 | break; | |
775 | } | |
776 | } | |
777 | ||
778 | return pte; | |
779 | } | |
780 | ||
431b2a20 JR |
781 | /* |
782 | * Generic mapping functions. It maps a physical address into a DMA | |
783 | * address space. It allocates the page table pages if necessary. | |
784 | * In the future it can be extended to a generic mapping function | |
785 | * supporting all features of AMD IOMMU page tables like level skipping | |
786 | * and full 64 bit address spaces. | |
787 | */ | |
38e817fe JR |
788 | static int iommu_map_page(struct protection_domain *dom, |
789 | unsigned long bus_addr, | |
790 | unsigned long phys_addr, | |
abdc5eb3 JR |
791 | int prot, |
792 | int map_size) | |
bd0e5211 | 793 | { |
8bda3092 | 794 | u64 __pte, *pte; |
bd0e5211 JR |
795 | |
796 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 797 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 | 798 | |
abdc5eb3 JR |
799 | BUG_ON(!PM_ALIGNED(map_size, bus_addr)); |
800 | BUG_ON(!PM_ALIGNED(map_size, phys_addr)); | |
801 | ||
bad1cac2 | 802 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
803 | return -EINVAL; |
804 | ||
abdc5eb3 | 805 | pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL); |
bd0e5211 JR |
806 | |
807 | if (IOMMU_PTE_PRESENT(*pte)) | |
808 | return -EBUSY; | |
809 | ||
810 | __pte = phys_addr | IOMMU_PTE_P; | |
811 | if (prot & IOMMU_PROT_IR) | |
812 | __pte |= IOMMU_PTE_IR; | |
813 | if (prot & IOMMU_PROT_IW) | |
814 | __pte |= IOMMU_PTE_IW; | |
815 | ||
816 | *pte = __pte; | |
817 | ||
04bfdd84 JR |
818 | update_domain(dom); |
819 | ||
bd0e5211 JR |
820 | return 0; |
821 | } | |
822 | ||
eb74ff6c | 823 | static void iommu_unmap_page(struct protection_domain *dom, |
a6b256b4 | 824 | unsigned long bus_addr, int map_size) |
eb74ff6c | 825 | { |
a6b256b4 | 826 | u64 *pte = fetch_pte(dom, bus_addr, map_size); |
eb74ff6c | 827 | |
38a76eee JR |
828 | if (pte) |
829 | *pte = 0; | |
eb74ff6c | 830 | } |
eb74ff6c | 831 | |
431b2a20 JR |
832 | /* |
833 | * This function checks if a specific unity mapping entry is needed for | |
834 | * this specific IOMMU. | |
835 | */ | |
bd0e5211 JR |
836 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
837 | struct unity_map_entry *entry) | |
838 | { | |
839 | u16 bdf, i; | |
840 | ||
841 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
842 | bdf = amd_iommu_alias_table[i]; | |
843 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
844 | return 1; | |
845 | } | |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
431b2a20 JR |
850 | /* |
851 | * This function actually applies the mapping to the page table of the | |
852 | * dma_ops domain. | |
853 | */ | |
bd0e5211 JR |
854 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
855 | struct unity_map_entry *e) | |
856 | { | |
857 | u64 addr; | |
858 | int ret; | |
859 | ||
860 | for (addr = e->address_start; addr < e->address_end; | |
861 | addr += PAGE_SIZE) { | |
abdc5eb3 JR |
862 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
863 | PM_MAP_4k); | |
bd0e5211 JR |
864 | if (ret) |
865 | return ret; | |
866 | /* | |
867 | * if unity mapping is in aperture range mark the page | |
868 | * as allocated in the aperture | |
869 | */ | |
870 | if (addr < dma_dom->aperture_size) | |
c3239567 | 871 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 872 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
873 | } |
874 | ||
875 | return 0; | |
876 | } | |
877 | ||
171e7b37 JR |
878 | /* |
879 | * Init the unity mappings for a specific IOMMU in the system | |
880 | * | |
881 | * Basically iterates over all unity mapping entries and applies them to | |
882 | * the default domain DMA of that IOMMU if necessary. | |
883 | */ | |
884 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
885 | { | |
886 | struct unity_map_entry *entry; | |
887 | int ret; | |
888 | ||
889 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
890 | if (!iommu_for_unity_map(iommu, entry)) | |
891 | continue; | |
892 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
893 | if (ret) | |
894 | return ret; | |
895 | } | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
431b2a20 JR |
900 | /* |
901 | * Inits the unity mappings required for a specific device | |
902 | */ | |
bd0e5211 JR |
903 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
904 | u16 devid) | |
905 | { | |
906 | struct unity_map_entry *e; | |
907 | int ret; | |
908 | ||
909 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
910 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
911 | continue; | |
912 | ret = dma_ops_unity_map(dma_dom, e); | |
913 | if (ret) | |
914 | return ret; | |
915 | } | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
431b2a20 JR |
920 | /**************************************************************************** |
921 | * | |
922 | * The next functions belong to the address allocator for the dma_ops | |
923 | * interface functions. They work like the allocators in the other IOMMU | |
924 | * drivers. Its basically a bitmap which marks the allocated pages in | |
925 | * the aperture. Maybe it could be enhanced in the future to a more | |
926 | * efficient allocator. | |
927 | * | |
928 | ****************************************************************************/ | |
d3086444 | 929 | |
431b2a20 | 930 | /* |
384de729 | 931 | * The address allocator core functions. |
431b2a20 JR |
932 | * |
933 | * called with domain->lock held | |
934 | */ | |
384de729 | 935 | |
171e7b37 JR |
936 | /* |
937 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
938 | * ranges. | |
939 | */ | |
940 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
941 | unsigned long start_page, | |
942 | unsigned int pages) | |
943 | { | |
944 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
945 | ||
946 | if (start_page + pages > last_page) | |
947 | pages = last_page - start_page; | |
948 | ||
949 | for (i = start_page; i < start_page + pages; ++i) { | |
950 | int index = i / APERTURE_RANGE_PAGES; | |
951 | int page = i % APERTURE_RANGE_PAGES; | |
952 | __set_bit(page, dom->aperture[index]->bitmap); | |
953 | } | |
954 | } | |
955 | ||
9cabe89b JR |
956 | /* |
957 | * This function is used to add a new aperture range to an existing | |
958 | * aperture in case of dma_ops domain allocation or address allocation | |
959 | * failure. | |
960 | */ | |
576175c2 | 961 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
962 | bool populate, gfp_t gfp) |
963 | { | |
964 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 965 | struct amd_iommu *iommu; |
00cd122a | 966 | int i; |
9cabe89b | 967 | |
f5e9705c JR |
968 | #ifdef CONFIG_IOMMU_STRESS |
969 | populate = false; | |
970 | #endif | |
971 | ||
9cabe89b JR |
972 | if (index >= APERTURE_MAX_RANGES) |
973 | return -ENOMEM; | |
974 | ||
975 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
976 | if (!dma_dom->aperture[index]) | |
977 | return -ENOMEM; | |
978 | ||
979 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
980 | if (!dma_dom->aperture[index]->bitmap) | |
981 | goto out_free; | |
982 | ||
983 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
984 | ||
985 | if (populate) { | |
986 | unsigned long address = dma_dom->aperture_size; | |
987 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
988 | u64 *pte, *pte_page; | |
989 | ||
990 | for (i = 0; i < num_ptes; ++i) { | |
abdc5eb3 | 991 | pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k, |
9cabe89b JR |
992 | &pte_page, gfp); |
993 | if (!pte) | |
994 | goto out_free; | |
995 | ||
996 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
997 | ||
998 | address += APERTURE_RANGE_SIZE / 64; | |
999 | } | |
1000 | } | |
1001 | ||
1002 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
1003 | ||
00cd122a | 1004 | /* Intialize the exclusion range if necessary */ |
576175c2 JR |
1005 | for_each_iommu(iommu) { |
1006 | if (iommu->exclusion_start && | |
1007 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1008 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1009 | unsigned long startpage; | |
1010 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1011 | iommu->exclusion_length, | |
1012 | PAGE_SIZE); | |
1013 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1014 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1015 | } | |
00cd122a JR |
1016 | } |
1017 | ||
1018 | /* | |
1019 | * Check for areas already mapped as present in the new aperture | |
1020 | * range and mark those pages as reserved in the allocator. Such | |
1021 | * mappings may already exist as a result of requested unity | |
1022 | * mappings for devices. | |
1023 | */ | |
1024 | for (i = dma_dom->aperture[index]->offset; | |
1025 | i < dma_dom->aperture_size; | |
1026 | i += PAGE_SIZE) { | |
a6b256b4 | 1027 | u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k); |
00cd122a JR |
1028 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1029 | continue; | |
1030 | ||
1031 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
1032 | } | |
1033 | ||
04bfdd84 JR |
1034 | update_domain(&dma_dom->domain); |
1035 | ||
9cabe89b JR |
1036 | return 0; |
1037 | ||
1038 | out_free: | |
04bfdd84 JR |
1039 | update_domain(&dma_dom->domain); |
1040 | ||
9cabe89b JR |
1041 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1042 | ||
1043 | kfree(dma_dom->aperture[index]); | |
1044 | dma_dom->aperture[index] = NULL; | |
1045 | ||
1046 | return -ENOMEM; | |
1047 | } | |
1048 | ||
384de729 JR |
1049 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1050 | struct dma_ops_domain *dom, | |
1051 | unsigned int pages, | |
1052 | unsigned long align_mask, | |
1053 | u64 dma_mask, | |
1054 | unsigned long start) | |
1055 | { | |
803b8cb4 | 1056 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1057 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1058 | int i = start >> APERTURE_RANGE_SHIFT; | |
1059 | unsigned long boundary_size; | |
1060 | unsigned long address = -1; | |
1061 | unsigned long limit; | |
1062 | ||
803b8cb4 JR |
1063 | next_bit >>= PAGE_SHIFT; |
1064 | ||
384de729 JR |
1065 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1066 | PAGE_SIZE) >> PAGE_SHIFT; | |
1067 | ||
1068 | for (;i < max_index; ++i) { | |
1069 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1070 | ||
1071 | if (dom->aperture[i]->offset >= dma_mask) | |
1072 | break; | |
1073 | ||
1074 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1075 | dma_mask >> PAGE_SHIFT); | |
1076 | ||
1077 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1078 | limit, next_bit, pages, 0, | |
1079 | boundary_size, align_mask); | |
1080 | if (address != -1) { | |
1081 | address = dom->aperture[i]->offset + | |
1082 | (address << PAGE_SHIFT); | |
803b8cb4 | 1083 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1084 | break; |
1085 | } | |
1086 | ||
1087 | next_bit = 0; | |
1088 | } | |
1089 | ||
1090 | return address; | |
1091 | } | |
1092 | ||
d3086444 JR |
1093 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1094 | struct dma_ops_domain *dom, | |
6d4f343f | 1095 | unsigned int pages, |
832a90c3 JR |
1096 | unsigned long align_mask, |
1097 | u64 dma_mask) | |
d3086444 | 1098 | { |
d3086444 | 1099 | unsigned long address; |
d3086444 | 1100 | |
fe16f088 JR |
1101 | #ifdef CONFIG_IOMMU_STRESS |
1102 | dom->next_address = 0; | |
1103 | dom->need_flush = true; | |
1104 | #endif | |
d3086444 | 1105 | |
384de729 | 1106 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1107 | dma_mask, dom->next_address); |
d3086444 | 1108 | |
1c655773 | 1109 | if (address == -1) { |
803b8cb4 | 1110 | dom->next_address = 0; |
384de729 JR |
1111 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1112 | dma_mask, 0); | |
1c655773 JR |
1113 | dom->need_flush = true; |
1114 | } | |
d3086444 | 1115 | |
384de729 | 1116 | if (unlikely(address == -1)) |
8fd524b3 | 1117 | address = DMA_ERROR_CODE; |
d3086444 JR |
1118 | |
1119 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1120 | ||
1121 | return address; | |
1122 | } | |
1123 | ||
431b2a20 JR |
1124 | /* |
1125 | * The address free function. | |
1126 | * | |
1127 | * called with domain->lock held | |
1128 | */ | |
d3086444 JR |
1129 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1130 | unsigned long address, | |
1131 | unsigned int pages) | |
1132 | { | |
384de729 JR |
1133 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1134 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1135 | |
384de729 JR |
1136 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1137 | ||
47bccd6b JR |
1138 | #ifdef CONFIG_IOMMU_STRESS |
1139 | if (i < 4) | |
1140 | return; | |
1141 | #endif | |
80be308d | 1142 | |
803b8cb4 | 1143 | if (address >= dom->next_address) |
80be308d | 1144 | dom->need_flush = true; |
384de729 JR |
1145 | |
1146 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1147 | |
384de729 JR |
1148 | iommu_area_free(range->bitmap, address, pages); |
1149 | ||
d3086444 JR |
1150 | } |
1151 | ||
431b2a20 JR |
1152 | /**************************************************************************** |
1153 | * | |
1154 | * The next functions belong to the domain allocation. A domain is | |
1155 | * allocated for every IOMMU as the default domain. If device isolation | |
1156 | * is enabled, every device get its own domain. The most important thing | |
1157 | * about domains is the page table mapping the DMA address space they | |
1158 | * contain. | |
1159 | * | |
1160 | ****************************************************************************/ | |
1161 | ||
aeb26f55 JR |
1162 | /* |
1163 | * This function adds a protection domain to the global protection domain list | |
1164 | */ | |
1165 | static void add_domain_to_list(struct protection_domain *domain) | |
1166 | { | |
1167 | unsigned long flags; | |
1168 | ||
1169 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1170 | list_add(&domain->list, &amd_iommu_pd_list); | |
1171 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1172 | } | |
1173 | ||
1174 | /* | |
1175 | * This function removes a protection domain to the global | |
1176 | * protection domain list | |
1177 | */ | |
1178 | static void del_domain_from_list(struct protection_domain *domain) | |
1179 | { | |
1180 | unsigned long flags; | |
1181 | ||
1182 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1183 | list_del(&domain->list); | |
1184 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1185 | } | |
1186 | ||
ec487d1a JR |
1187 | static u16 domain_id_alloc(void) |
1188 | { | |
1189 | unsigned long flags; | |
1190 | int id; | |
1191 | ||
1192 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1193 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1194 | BUG_ON(id == 0); | |
1195 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1196 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1197 | else | |
1198 | id = 0; | |
1199 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1200 | ||
1201 | return id; | |
1202 | } | |
1203 | ||
a2acfb75 JR |
1204 | static void domain_id_free(int id) |
1205 | { | |
1206 | unsigned long flags; | |
1207 | ||
1208 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1209 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1210 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1211 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1212 | } | |
a2acfb75 | 1213 | |
86db2e5d | 1214 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1215 | { |
1216 | int i, j; | |
1217 | u64 *p1, *p2, *p3; | |
1218 | ||
86db2e5d | 1219 | p1 = domain->pt_root; |
ec487d1a JR |
1220 | |
1221 | if (!p1) | |
1222 | return; | |
1223 | ||
1224 | for (i = 0; i < 512; ++i) { | |
1225 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1226 | continue; | |
1227 | ||
1228 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1229 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1230 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1231 | continue; | |
1232 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1233 | free_page((unsigned long)p3); | |
1234 | } | |
1235 | ||
1236 | free_page((unsigned long)p2); | |
1237 | } | |
1238 | ||
1239 | free_page((unsigned long)p1); | |
86db2e5d JR |
1240 | |
1241 | domain->pt_root = NULL; | |
ec487d1a JR |
1242 | } |
1243 | ||
431b2a20 JR |
1244 | /* |
1245 | * Free a domain, only used if something went wrong in the | |
1246 | * allocation path and we need to free an already allocated page table | |
1247 | */ | |
ec487d1a JR |
1248 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1249 | { | |
384de729 JR |
1250 | int i; |
1251 | ||
ec487d1a JR |
1252 | if (!dom) |
1253 | return; | |
1254 | ||
aeb26f55 JR |
1255 | del_domain_from_list(&dom->domain); |
1256 | ||
86db2e5d | 1257 | free_pagetable(&dom->domain); |
ec487d1a | 1258 | |
384de729 JR |
1259 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1260 | if (!dom->aperture[i]) | |
1261 | continue; | |
1262 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1263 | kfree(dom->aperture[i]); | |
1264 | } | |
ec487d1a JR |
1265 | |
1266 | kfree(dom); | |
1267 | } | |
1268 | ||
431b2a20 JR |
1269 | /* |
1270 | * Allocates a new protection domain usable for the dma_ops functions. | |
1271 | * It also intializes the page table and the address allocator data | |
1272 | * structures required for the dma_ops interface | |
1273 | */ | |
87a64d52 | 1274 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1275 | { |
1276 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1277 | |
1278 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1279 | if (!dma_dom) | |
1280 | return NULL; | |
1281 | ||
1282 | spin_lock_init(&dma_dom->domain.lock); | |
1283 | ||
1284 | dma_dom->domain.id = domain_id_alloc(); | |
1285 | if (dma_dom->domain.id == 0) | |
1286 | goto free_dma_dom; | |
8f7a017c | 1287 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1288 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1289 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1290 | dma_dom->domain.priv = dma_dom; |
1291 | if (!dma_dom->domain.pt_root) | |
1292 | goto free_dma_dom; | |
ec487d1a | 1293 | |
1c655773 | 1294 | dma_dom->need_flush = false; |
bd60b735 | 1295 | dma_dom->target_dev = 0xffff; |
1c655773 | 1296 | |
aeb26f55 JR |
1297 | add_domain_to_list(&dma_dom->domain); |
1298 | ||
576175c2 | 1299 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1300 | goto free_dma_dom; |
ec487d1a | 1301 | |
431b2a20 | 1302 | /* |
ec487d1a JR |
1303 | * mark the first page as allocated so we never return 0 as |
1304 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1305 | */ |
384de729 | 1306 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1307 | dma_dom->next_address = 0; |
ec487d1a | 1308 | |
ec487d1a JR |
1309 | |
1310 | return dma_dom; | |
1311 | ||
1312 | free_dma_dom: | |
1313 | dma_ops_domain_free(dma_dom); | |
1314 | ||
1315 | return NULL; | |
1316 | } | |
1317 | ||
5b28df6f JR |
1318 | /* |
1319 | * little helper function to check whether a given protection domain is a | |
1320 | * dma_ops domain | |
1321 | */ | |
1322 | static bool dma_ops_domain(struct protection_domain *domain) | |
1323 | { | |
1324 | return domain->flags & PD_DMA_OPS_MASK; | |
1325 | } | |
1326 | ||
407d733e | 1327 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1328 | { |
15898bbc | 1329 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
b20ac0d4 | 1330 | u64 pte_root = virt_to_phys(domain->pt_root); |
863c74eb | 1331 | |
15898bbc JR |
1332 | BUG_ON(amd_iommu_pd_table[devid] != NULL); |
1333 | ||
38ddf41b JR |
1334 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1335 | << DEV_ENTRY_MODE_SHIFT; | |
1336 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1337 | |
b20ac0d4 | 1338 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1339 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1340 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
b20ac0d4 JR |
1341 | |
1342 | amd_iommu_pd_table[devid] = domain; | |
15898bbc JR |
1343 | |
1344 | /* Do reference counting */ | |
1345 | domain->dev_iommu[iommu->index] += 1; | |
1346 | domain->dev_cnt += 1; | |
1347 | ||
1348 | /* Flush the changes DTE entry */ | |
1349 | iommu_queue_inv_dev_entry(iommu, devid); | |
1350 | } | |
1351 | ||
1352 | static void clear_dte_entry(u16 devid) | |
1353 | { | |
1354 | struct protection_domain *domain = amd_iommu_pd_table[devid]; | |
1355 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
1356 | ||
1357 | BUG_ON(domain == NULL); | |
1358 | ||
1359 | /* remove domain from the lookup table */ | |
1360 | amd_iommu_pd_table[devid] = NULL; | |
1361 | ||
1362 | /* remove entry from the device table seen by the hardware */ | |
1363 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1364 | amd_iommu_dev_table[devid].data[1] = 0; | |
1365 | amd_iommu_dev_table[devid].data[2] = 0; | |
1366 | ||
1367 | amd_iommu_apply_erratum_63(devid); | |
1368 | ||
1369 | /* decrease reference counters */ | |
1370 | domain->dev_iommu[iommu->index] -= 1; | |
1371 | domain->dev_cnt -= 1; | |
1372 | ||
1373 | iommu_queue_inv_dev_entry(iommu, devid); | |
2b681faf JR |
1374 | } |
1375 | ||
1376 | /* | |
1377 | * If a device is not yet associated with a domain, this function does | |
1378 | * assigns it visible for the hardware | |
1379 | */ | |
15898bbc JR |
1380 | static int __attach_device(struct device *dev, |
1381 | struct protection_domain *domain) | |
2b681faf | 1382 | { |
657cbb6b JR |
1383 | struct iommu_dev_data *dev_data, *alias_data; |
1384 | u16 devid, alias; | |
1385 | ||
1386 | devid = get_device_id(dev); | |
1387 | alias = amd_iommu_alias_table[devid]; | |
1388 | dev_data = get_dev_data(dev); | |
1389 | alias_data = get_dev_data(dev_data->alias); | |
1390 | if (!alias_data) | |
1391 | return -EINVAL; | |
15898bbc | 1392 | |
2b681faf JR |
1393 | /* lock domain */ |
1394 | spin_lock(&domain->lock); | |
1395 | ||
15898bbc | 1396 | /* Some sanity checks */ |
657cbb6b JR |
1397 | if (alias_data->domain != NULL && |
1398 | alias_data->domain != domain) | |
15898bbc | 1399 | return -EBUSY; |
eba6ac60 | 1400 | |
657cbb6b JR |
1401 | if (dev_data->domain != NULL && |
1402 | dev_data->domain != domain) | |
15898bbc JR |
1403 | return -EBUSY; |
1404 | ||
1405 | /* Do real assignment */ | |
1406 | if (alias != devid && | |
657cbb6b JR |
1407 | alias_data->domain == NULL) { |
1408 | alias_data->domain = domain; | |
15898bbc | 1409 | set_dte_entry(alias, domain); |
657cbb6b | 1410 | } |
15898bbc | 1411 | |
657cbb6b JR |
1412 | if (dev_data->domain == NULL) { |
1413 | dev_data->domain = domain; | |
15898bbc | 1414 | set_dte_entry(devid, domain); |
657cbb6b | 1415 | } |
eba6ac60 JR |
1416 | |
1417 | /* ready */ | |
1418 | spin_unlock(&domain->lock); | |
15898bbc JR |
1419 | |
1420 | return 0; | |
0feae533 | 1421 | } |
b20ac0d4 | 1422 | |
407d733e JR |
1423 | /* |
1424 | * If a device is not yet associated with a domain, this function does | |
1425 | * assigns it visible for the hardware | |
1426 | */ | |
15898bbc JR |
1427 | static int attach_device(struct device *dev, |
1428 | struct protection_domain *domain) | |
0feae533 | 1429 | { |
eba6ac60 | 1430 | unsigned long flags; |
15898bbc | 1431 | int ret; |
eba6ac60 JR |
1432 | |
1433 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1434 | ret = __attach_device(dev, domain); |
b20ac0d4 JR |
1435 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1436 | ||
0feae533 JR |
1437 | /* |
1438 | * We might boot into a crash-kernel here. The crashed kernel | |
1439 | * left the caches in the IOMMU dirty. So we have to flush | |
1440 | * here to evict all dirty stuff. | |
1441 | */ | |
dcd1e92e | 1442 | iommu_flush_tlb_pde(domain); |
15898bbc JR |
1443 | |
1444 | return ret; | |
b20ac0d4 JR |
1445 | } |
1446 | ||
355bf553 JR |
1447 | /* |
1448 | * Removes a device from a protection domain (unlocked) | |
1449 | */ | |
15898bbc | 1450 | static void __detach_device(struct device *dev) |
355bf553 | 1451 | { |
15898bbc | 1452 | u16 devid = get_device_id(dev); |
c4596114 | 1453 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
657cbb6b | 1454 | struct iommu_dev_data *dev_data = get_dev_data(dev); |
c4596114 JR |
1455 | |
1456 | BUG_ON(!iommu); | |
355bf553 | 1457 | |
15898bbc | 1458 | clear_dte_entry(devid); |
657cbb6b | 1459 | dev_data->domain = NULL; |
21129f78 JR |
1460 | |
1461 | /* | |
1462 | * If we run in passthrough mode the device must be assigned to the | |
1463 | * passthrough domain if it is detached from any other domain | |
1464 | */ | |
15898bbc JR |
1465 | if (iommu_pass_through) |
1466 | __attach_device(dev, pt_domain); | |
355bf553 JR |
1467 | } |
1468 | ||
1469 | /* | |
1470 | * Removes a device from a protection domain (with devtable_lock held) | |
1471 | */ | |
15898bbc | 1472 | static void detach_device(struct device *dev) |
355bf553 JR |
1473 | { |
1474 | unsigned long flags; | |
1475 | ||
1476 | /* lock device table */ | |
1477 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1478 | __detach_device(dev); |
355bf553 JR |
1479 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1480 | } | |
e275a2a0 | 1481 | |
15898bbc JR |
1482 | /* |
1483 | * Find out the protection domain structure for a given PCI device. This | |
1484 | * will give us the pointer to the page table root for example. | |
1485 | */ | |
1486 | static struct protection_domain *domain_for_device(struct device *dev) | |
1487 | { | |
1488 | struct protection_domain *dom; | |
657cbb6b | 1489 | struct iommu_dev_data *dev_data, *alias_data; |
15898bbc JR |
1490 | unsigned long flags; |
1491 | u16 devid, alias; | |
1492 | ||
657cbb6b JR |
1493 | devid = get_device_id(dev); |
1494 | alias = amd_iommu_alias_table[devid]; | |
1495 | dev_data = get_dev_data(dev); | |
1496 | alias_data = get_dev_data(dev_data->alias); | |
1497 | if (!alias_data) | |
1498 | return NULL; | |
15898bbc JR |
1499 | |
1500 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
657cbb6b | 1501 | dom = dev_data->domain; |
15898bbc | 1502 | if (dom == NULL && |
657cbb6b JR |
1503 | alias_data->domain != NULL) { |
1504 | __attach_device(dev, alias_data->domain); | |
1505 | dom = alias_data->domain; | |
15898bbc JR |
1506 | } |
1507 | ||
1508 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1509 | ||
1510 | return dom; | |
1511 | } | |
1512 | ||
e275a2a0 JR |
1513 | static int device_change_notifier(struct notifier_block *nb, |
1514 | unsigned long action, void *data) | |
1515 | { | |
1516 | struct device *dev = data; | |
98fc5a69 | 1517 | u16 devid; |
e275a2a0 JR |
1518 | struct protection_domain *domain; |
1519 | struct dma_ops_domain *dma_domain; | |
1520 | struct amd_iommu *iommu; | |
1ac4cbbc | 1521 | unsigned long flags; |
e275a2a0 | 1522 | |
98fc5a69 JR |
1523 | if (!check_device(dev)) |
1524 | return 0; | |
e275a2a0 | 1525 | |
98fc5a69 JR |
1526 | devid = get_device_id(dev); |
1527 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1528 | |
1529 | switch (action) { | |
c1eee67b | 1530 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1531 | |
1532 | domain = domain_for_device(dev); | |
1533 | ||
e275a2a0 JR |
1534 | if (!domain) |
1535 | goto out; | |
a1ca331c JR |
1536 | if (iommu_pass_through) |
1537 | break; | |
15898bbc | 1538 | detach_device(dev); |
1ac4cbbc JR |
1539 | break; |
1540 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1541 | |
1542 | iommu_init_device(dev); | |
1543 | ||
1544 | domain = domain_for_device(dev); | |
1545 | ||
1ac4cbbc JR |
1546 | /* allocate a protection domain if a device is added */ |
1547 | dma_domain = find_protection_domain(devid); | |
1548 | if (dma_domain) | |
1549 | goto out; | |
87a64d52 | 1550 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1551 | if (!dma_domain) |
1552 | goto out; | |
1553 | dma_domain->target_dev = devid; | |
1554 | ||
1555 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1556 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1557 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1558 | ||
e275a2a0 | 1559 | break; |
657cbb6b JR |
1560 | case BUS_NOTIFY_DEL_DEVICE: |
1561 | ||
1562 | iommu_uninit_device(dev); | |
1563 | ||
e275a2a0 JR |
1564 | default: |
1565 | goto out; | |
1566 | } | |
1567 | ||
1568 | iommu_queue_inv_dev_entry(iommu, devid); | |
1569 | iommu_completion_wait(iommu); | |
1570 | ||
1571 | out: | |
1572 | return 0; | |
1573 | } | |
1574 | ||
b25ae679 | 1575 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1576 | .notifier_call = device_change_notifier, |
1577 | }; | |
355bf553 | 1578 | |
431b2a20 JR |
1579 | /***************************************************************************** |
1580 | * | |
1581 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1582 | * | |
1583 | *****************************************************************************/ | |
1584 | ||
1585 | /* | |
1586 | * In the dma_ops path we only have the struct device. This function | |
1587 | * finds the corresponding IOMMU, the protection domain and the | |
1588 | * requestor id for a given device. | |
1589 | * If the device is not yet associated with a domain this is also done | |
1590 | * in this function. | |
1591 | */ | |
94f6d190 | 1592 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1593 | { |
94f6d190 | 1594 | struct protection_domain *domain; |
b20ac0d4 | 1595 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1596 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1597 | |
f99c0f1c | 1598 | if (!check_device(dev)) |
94f6d190 | 1599 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1600 | |
94f6d190 JR |
1601 | domain = domain_for_device(dev); |
1602 | if (domain != NULL && !dma_ops_domain(domain)) | |
1603 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1604 | |
94f6d190 JR |
1605 | if (domain != NULL) |
1606 | return domain; | |
b20ac0d4 | 1607 | |
15898bbc | 1608 | /* Device not bount yet - bind it */ |
94f6d190 | 1609 | dma_dom = find_protection_domain(devid); |
15898bbc | 1610 | if (!dma_dom) |
94f6d190 JR |
1611 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1612 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1613 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1614 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1615 | |
94f6d190 | 1616 | return &dma_dom->domain; |
b20ac0d4 JR |
1617 | } |
1618 | ||
04bfdd84 JR |
1619 | static void update_device_table(struct protection_domain *domain) |
1620 | { | |
2b681faf | 1621 | unsigned long flags; |
04bfdd84 JR |
1622 | int i; |
1623 | ||
1624 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
1625 | if (amd_iommu_pd_table[i] != domain) | |
1626 | continue; | |
2b681faf | 1627 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
04bfdd84 | 1628 | set_dte_entry(i, domain); |
2b681faf | 1629 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
04bfdd84 JR |
1630 | } |
1631 | } | |
1632 | ||
1633 | static void update_domain(struct protection_domain *domain) | |
1634 | { | |
1635 | if (!domain->updated) | |
1636 | return; | |
1637 | ||
1638 | update_device_table(domain); | |
1639 | flush_devices_by_domain(domain); | |
601367d7 | 1640 | iommu_flush_tlb_pde(domain); |
04bfdd84 JR |
1641 | |
1642 | domain->updated = false; | |
1643 | } | |
1644 | ||
8bda3092 JR |
1645 | /* |
1646 | * This function fetches the PTE for a given address in the aperture | |
1647 | */ | |
1648 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1649 | unsigned long address) | |
1650 | { | |
384de729 | 1651 | struct aperture_range *aperture; |
8bda3092 JR |
1652 | u64 *pte, *pte_page; |
1653 | ||
384de729 JR |
1654 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1655 | if (!aperture) | |
1656 | return NULL; | |
1657 | ||
1658 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1659 | if (!pte) { |
abdc5eb3 JR |
1660 | pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page, |
1661 | GFP_ATOMIC); | |
384de729 JR |
1662 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1663 | } else | |
8c8c143c | 1664 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1665 | |
04bfdd84 | 1666 | update_domain(&dom->domain); |
8bda3092 JR |
1667 | |
1668 | return pte; | |
1669 | } | |
1670 | ||
431b2a20 JR |
1671 | /* |
1672 | * This is the generic map function. It maps one 4kb page at paddr to | |
1673 | * the given address in the DMA address space for the domain. | |
1674 | */ | |
680525e0 | 1675 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1676 | unsigned long address, |
1677 | phys_addr_t paddr, | |
1678 | int direction) | |
1679 | { | |
1680 | u64 *pte, __pte; | |
1681 | ||
1682 | WARN_ON(address > dom->aperture_size); | |
1683 | ||
1684 | paddr &= PAGE_MASK; | |
1685 | ||
8bda3092 | 1686 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1687 | if (!pte) |
8fd524b3 | 1688 | return DMA_ERROR_CODE; |
cb76c322 JR |
1689 | |
1690 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1691 | ||
1692 | if (direction == DMA_TO_DEVICE) | |
1693 | __pte |= IOMMU_PTE_IR; | |
1694 | else if (direction == DMA_FROM_DEVICE) | |
1695 | __pte |= IOMMU_PTE_IW; | |
1696 | else if (direction == DMA_BIDIRECTIONAL) | |
1697 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1698 | ||
1699 | WARN_ON(*pte); | |
1700 | ||
1701 | *pte = __pte; | |
1702 | ||
1703 | return (dma_addr_t)address; | |
1704 | } | |
1705 | ||
431b2a20 JR |
1706 | /* |
1707 | * The generic unmapping function for on page in the DMA address space. | |
1708 | */ | |
680525e0 | 1709 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1710 | unsigned long address) |
1711 | { | |
384de729 | 1712 | struct aperture_range *aperture; |
cb76c322 JR |
1713 | u64 *pte; |
1714 | ||
1715 | if (address >= dom->aperture_size) | |
1716 | return; | |
1717 | ||
384de729 JR |
1718 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1719 | if (!aperture) | |
1720 | return; | |
1721 | ||
1722 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1723 | if (!pte) | |
1724 | return; | |
cb76c322 | 1725 | |
8c8c143c | 1726 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1727 | |
1728 | WARN_ON(!*pte); | |
1729 | ||
1730 | *pte = 0ULL; | |
1731 | } | |
1732 | ||
431b2a20 JR |
1733 | /* |
1734 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1735 | * contiguous memory region into DMA address space. It is used by all |
1736 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1737 | * Must be called with the domain lock held. |
1738 | */ | |
cb76c322 | 1739 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
1740 | struct dma_ops_domain *dma_dom, |
1741 | phys_addr_t paddr, | |
1742 | size_t size, | |
6d4f343f | 1743 | int dir, |
832a90c3 JR |
1744 | bool align, |
1745 | u64 dma_mask) | |
cb76c322 JR |
1746 | { |
1747 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1748 | dma_addr_t address, start, ret; |
cb76c322 | 1749 | unsigned int pages; |
6d4f343f | 1750 | unsigned long align_mask = 0; |
cb76c322 JR |
1751 | int i; |
1752 | ||
e3c449f5 | 1753 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1754 | paddr &= PAGE_MASK; |
1755 | ||
8ecaf8f1 JR |
1756 | INC_STATS_COUNTER(total_map_requests); |
1757 | ||
c1858976 JR |
1758 | if (pages > 1) |
1759 | INC_STATS_COUNTER(cross_page); | |
1760 | ||
6d4f343f JR |
1761 | if (align) |
1762 | align_mask = (1UL << get_order(size)) - 1; | |
1763 | ||
11b83888 | 1764 | retry: |
832a90c3 JR |
1765 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1766 | dma_mask); | |
8fd524b3 | 1767 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1768 | /* |
1769 | * setting next_address here will let the address | |
1770 | * allocator only scan the new allocated range in the | |
1771 | * first run. This is a small optimization. | |
1772 | */ | |
1773 | dma_dom->next_address = dma_dom->aperture_size; | |
1774 | ||
576175c2 | 1775 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
1776 | goto out; |
1777 | ||
1778 | /* | |
1779 | * aperture was sucessfully enlarged by 128 MB, try | |
1780 | * allocation again | |
1781 | */ | |
1782 | goto retry; | |
1783 | } | |
cb76c322 JR |
1784 | |
1785 | start = address; | |
1786 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1787 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 1788 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
1789 | goto out_unmap; |
1790 | ||
cb76c322 JR |
1791 | paddr += PAGE_SIZE; |
1792 | start += PAGE_SIZE; | |
1793 | } | |
1794 | address += offset; | |
1795 | ||
5774f7c5 JR |
1796 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1797 | ||
afa9fdc2 | 1798 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
dcd1e92e | 1799 | iommu_flush_tlb(&dma_dom->domain); |
1c655773 | 1800 | dma_dom->need_flush = false; |
318afd41 | 1801 | } else if (unlikely(amd_iommu_np_cache)) |
6de8ad9b | 1802 | iommu_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 1803 | |
cb76c322 JR |
1804 | out: |
1805 | return address; | |
53812c11 JR |
1806 | |
1807 | out_unmap: | |
1808 | ||
1809 | for (--i; i >= 0; --i) { | |
1810 | start -= PAGE_SIZE; | |
680525e0 | 1811 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
1812 | } |
1813 | ||
1814 | dma_ops_free_addresses(dma_dom, address, pages); | |
1815 | ||
8fd524b3 | 1816 | return DMA_ERROR_CODE; |
cb76c322 JR |
1817 | } |
1818 | ||
431b2a20 JR |
1819 | /* |
1820 | * Does the reverse of the __map_single function. Must be called with | |
1821 | * the domain lock held too | |
1822 | */ | |
cd8c82e8 | 1823 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
1824 | dma_addr_t dma_addr, |
1825 | size_t size, | |
1826 | int dir) | |
1827 | { | |
1828 | dma_addr_t i, start; | |
1829 | unsigned int pages; | |
1830 | ||
8fd524b3 | 1831 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 1832 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
1833 | return; |
1834 | ||
e3c449f5 | 1835 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1836 | dma_addr &= PAGE_MASK; |
1837 | start = dma_addr; | |
1838 | ||
1839 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1840 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
1841 | start += PAGE_SIZE; |
1842 | } | |
1843 | ||
5774f7c5 JR |
1844 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1845 | ||
cb76c322 | 1846 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1847 | |
80be308d | 1848 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
6de8ad9b | 1849 | iommu_flush_pages(&dma_dom->domain, dma_addr, size); |
80be308d JR |
1850 | dma_dom->need_flush = false; |
1851 | } | |
cb76c322 JR |
1852 | } |
1853 | ||
431b2a20 JR |
1854 | /* |
1855 | * The exported map_single function for dma_ops. | |
1856 | */ | |
51491367 FT |
1857 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1858 | unsigned long offset, size_t size, | |
1859 | enum dma_data_direction dir, | |
1860 | struct dma_attrs *attrs) | |
4da70b9e JR |
1861 | { |
1862 | unsigned long flags; | |
4da70b9e | 1863 | struct protection_domain *domain; |
4da70b9e | 1864 | dma_addr_t addr; |
832a90c3 | 1865 | u64 dma_mask; |
51491367 | 1866 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1867 | |
0f2a86f2 JR |
1868 | INC_STATS_COUNTER(cnt_map_single); |
1869 | ||
94f6d190 JR |
1870 | domain = get_domain(dev); |
1871 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 1872 | return (dma_addr_t)paddr; |
94f6d190 JR |
1873 | else if (IS_ERR(domain)) |
1874 | return DMA_ERROR_CODE; | |
4da70b9e | 1875 | |
f99c0f1c JR |
1876 | dma_mask = *dev->dma_mask; |
1877 | ||
4da70b9e | 1878 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 1879 | |
cd8c82e8 | 1880 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 1881 | dma_mask); |
8fd524b3 | 1882 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
1883 | goto out; |
1884 | ||
0518a3a4 | 1885 | iommu_flush_complete(domain); |
4da70b9e JR |
1886 | |
1887 | out: | |
1888 | spin_unlock_irqrestore(&domain->lock, flags); | |
1889 | ||
1890 | return addr; | |
1891 | } | |
1892 | ||
431b2a20 JR |
1893 | /* |
1894 | * The exported unmap_single function for dma_ops. | |
1895 | */ | |
51491367 FT |
1896 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1897 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1898 | { |
1899 | unsigned long flags; | |
4da70b9e | 1900 | struct protection_domain *domain; |
4da70b9e | 1901 | |
146a6917 JR |
1902 | INC_STATS_COUNTER(cnt_unmap_single); |
1903 | ||
94f6d190 JR |
1904 | domain = get_domain(dev); |
1905 | if (IS_ERR(domain)) | |
5b28df6f JR |
1906 | return; |
1907 | ||
4da70b9e JR |
1908 | spin_lock_irqsave(&domain->lock, flags); |
1909 | ||
cd8c82e8 | 1910 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 1911 | |
0518a3a4 | 1912 | iommu_flush_complete(domain); |
4da70b9e JR |
1913 | |
1914 | spin_unlock_irqrestore(&domain->lock, flags); | |
1915 | } | |
1916 | ||
431b2a20 JR |
1917 | /* |
1918 | * This is a special map_sg function which is used if we should map a | |
1919 | * device which is not handled by an AMD IOMMU in the system. | |
1920 | */ | |
65b050ad JR |
1921 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1922 | int nelems, int dir) | |
1923 | { | |
1924 | struct scatterlist *s; | |
1925 | int i; | |
1926 | ||
1927 | for_each_sg(sglist, s, nelems, i) { | |
1928 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1929 | s->dma_length = s->length; | |
1930 | } | |
1931 | ||
1932 | return nelems; | |
1933 | } | |
1934 | ||
431b2a20 JR |
1935 | /* |
1936 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1937 | * lists). | |
1938 | */ | |
65b050ad | 1939 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1940 | int nelems, enum dma_data_direction dir, |
1941 | struct dma_attrs *attrs) | |
65b050ad JR |
1942 | { |
1943 | unsigned long flags; | |
65b050ad | 1944 | struct protection_domain *domain; |
65b050ad JR |
1945 | int i; |
1946 | struct scatterlist *s; | |
1947 | phys_addr_t paddr; | |
1948 | int mapped_elems = 0; | |
832a90c3 | 1949 | u64 dma_mask; |
65b050ad | 1950 | |
d03f067a JR |
1951 | INC_STATS_COUNTER(cnt_map_sg); |
1952 | ||
94f6d190 JR |
1953 | domain = get_domain(dev); |
1954 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 1955 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
1956 | else if (IS_ERR(domain)) |
1957 | return 0; | |
dbcc112e | 1958 | |
832a90c3 | 1959 | dma_mask = *dev->dma_mask; |
65b050ad | 1960 | |
65b050ad JR |
1961 | spin_lock_irqsave(&domain->lock, flags); |
1962 | ||
1963 | for_each_sg(sglist, s, nelems, i) { | |
1964 | paddr = sg_phys(s); | |
1965 | ||
cd8c82e8 | 1966 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
1967 | paddr, s->length, dir, false, |
1968 | dma_mask); | |
65b050ad JR |
1969 | |
1970 | if (s->dma_address) { | |
1971 | s->dma_length = s->length; | |
1972 | mapped_elems++; | |
1973 | } else | |
1974 | goto unmap; | |
65b050ad JR |
1975 | } |
1976 | ||
0518a3a4 | 1977 | iommu_flush_complete(domain); |
65b050ad JR |
1978 | |
1979 | out: | |
1980 | spin_unlock_irqrestore(&domain->lock, flags); | |
1981 | ||
1982 | return mapped_elems; | |
1983 | unmap: | |
1984 | for_each_sg(sglist, s, mapped_elems, i) { | |
1985 | if (s->dma_address) | |
cd8c82e8 | 1986 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
1987 | s->dma_length, dir); |
1988 | s->dma_address = s->dma_length = 0; | |
1989 | } | |
1990 | ||
1991 | mapped_elems = 0; | |
1992 | ||
1993 | goto out; | |
1994 | } | |
1995 | ||
431b2a20 JR |
1996 | /* |
1997 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1998 | * lists). | |
1999 | */ | |
65b050ad | 2000 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2001 | int nelems, enum dma_data_direction dir, |
2002 | struct dma_attrs *attrs) | |
65b050ad JR |
2003 | { |
2004 | unsigned long flags; | |
65b050ad JR |
2005 | struct protection_domain *domain; |
2006 | struct scatterlist *s; | |
65b050ad JR |
2007 | int i; |
2008 | ||
55877a6b JR |
2009 | INC_STATS_COUNTER(cnt_unmap_sg); |
2010 | ||
94f6d190 JR |
2011 | domain = get_domain(dev); |
2012 | if (IS_ERR(domain)) | |
5b28df6f JR |
2013 | return; |
2014 | ||
65b050ad JR |
2015 | spin_lock_irqsave(&domain->lock, flags); |
2016 | ||
2017 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2018 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2019 | s->dma_length, dir); |
65b050ad JR |
2020 | s->dma_address = s->dma_length = 0; |
2021 | } | |
2022 | ||
0518a3a4 | 2023 | iommu_flush_complete(domain); |
65b050ad JR |
2024 | |
2025 | spin_unlock_irqrestore(&domain->lock, flags); | |
2026 | } | |
2027 | ||
431b2a20 JR |
2028 | /* |
2029 | * The exported alloc_coherent function for dma_ops. | |
2030 | */ | |
5d8b53cf JR |
2031 | static void *alloc_coherent(struct device *dev, size_t size, |
2032 | dma_addr_t *dma_addr, gfp_t flag) | |
2033 | { | |
2034 | unsigned long flags; | |
2035 | void *virt_addr; | |
5d8b53cf | 2036 | struct protection_domain *domain; |
5d8b53cf | 2037 | phys_addr_t paddr; |
832a90c3 | 2038 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2039 | |
c8f0fb36 JR |
2040 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2041 | ||
94f6d190 JR |
2042 | domain = get_domain(dev); |
2043 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2044 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2045 | *dma_addr = __pa(virt_addr); | |
2046 | return virt_addr; | |
94f6d190 JR |
2047 | } else if (IS_ERR(domain)) |
2048 | return NULL; | |
5d8b53cf | 2049 | |
f99c0f1c JR |
2050 | dma_mask = dev->coherent_dma_mask; |
2051 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2052 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2053 | |
2054 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2055 | if (!virt_addr) | |
b25ae679 | 2056 | return NULL; |
5d8b53cf | 2057 | |
5d8b53cf JR |
2058 | paddr = virt_to_phys(virt_addr); |
2059 | ||
832a90c3 JR |
2060 | if (!dma_mask) |
2061 | dma_mask = *dev->dma_mask; | |
2062 | ||
5d8b53cf JR |
2063 | spin_lock_irqsave(&domain->lock, flags); |
2064 | ||
cd8c82e8 | 2065 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2066 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2067 | |
8fd524b3 | 2068 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2069 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2070 | goto out_free; |
367d04c4 | 2071 | } |
5d8b53cf | 2072 | |
0518a3a4 | 2073 | iommu_flush_complete(domain); |
5d8b53cf | 2074 | |
5d8b53cf JR |
2075 | spin_unlock_irqrestore(&domain->lock, flags); |
2076 | ||
2077 | return virt_addr; | |
5b28df6f JR |
2078 | |
2079 | out_free: | |
2080 | ||
2081 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2082 | ||
2083 | return NULL; | |
5d8b53cf JR |
2084 | } |
2085 | ||
431b2a20 JR |
2086 | /* |
2087 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2088 | */ |
5d8b53cf JR |
2089 | static void free_coherent(struct device *dev, size_t size, |
2090 | void *virt_addr, dma_addr_t dma_addr) | |
2091 | { | |
2092 | unsigned long flags; | |
5d8b53cf | 2093 | struct protection_domain *domain; |
5d8b53cf | 2094 | |
5d31ee7e JR |
2095 | INC_STATS_COUNTER(cnt_free_coherent); |
2096 | ||
94f6d190 JR |
2097 | domain = get_domain(dev); |
2098 | if (IS_ERR(domain)) | |
5b28df6f JR |
2099 | goto free_mem; |
2100 | ||
5d8b53cf JR |
2101 | spin_lock_irqsave(&domain->lock, flags); |
2102 | ||
cd8c82e8 | 2103 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2104 | |
0518a3a4 | 2105 | iommu_flush_complete(domain); |
5d8b53cf JR |
2106 | |
2107 | spin_unlock_irqrestore(&domain->lock, flags); | |
2108 | ||
2109 | free_mem: | |
2110 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2111 | } | |
2112 | ||
b39ba6ad JR |
2113 | /* |
2114 | * This function is called by the DMA layer to find out if we can handle a | |
2115 | * particular device. It is part of the dma_ops. | |
2116 | */ | |
2117 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2118 | { | |
420aef8a | 2119 | return check_device(dev); |
b39ba6ad JR |
2120 | } |
2121 | ||
c432f3df | 2122 | /* |
431b2a20 JR |
2123 | * The function for pre-allocating protection domains. |
2124 | * | |
c432f3df JR |
2125 | * If the driver core informs the DMA layer if a driver grabs a device |
2126 | * we don't need to preallocate the protection domains anymore. | |
2127 | * For now we have to. | |
2128 | */ | |
0e93dd88 | 2129 | static void prealloc_protection_domains(void) |
c432f3df JR |
2130 | { |
2131 | struct pci_dev *dev = NULL; | |
2132 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2133 | u16 devid; |
c432f3df JR |
2134 | |
2135 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
98fc5a69 JR |
2136 | |
2137 | /* Do we handle this device? */ | |
2138 | if (!check_device(&dev->dev)) | |
c432f3df | 2139 | continue; |
98fc5a69 | 2140 | |
657cbb6b JR |
2141 | iommu_init_device(&dev->dev); |
2142 | ||
98fc5a69 | 2143 | /* Is there already any domain for it? */ |
15898bbc | 2144 | if (domain_for_device(&dev->dev)) |
c432f3df | 2145 | continue; |
98fc5a69 JR |
2146 | |
2147 | devid = get_device_id(&dev->dev); | |
2148 | ||
87a64d52 | 2149 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2150 | if (!dma_dom) |
2151 | continue; | |
2152 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2153 | dma_dom->target_dev = devid; |
2154 | ||
15898bbc | 2155 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2156 | |
bd60b735 | 2157 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2158 | } |
2159 | } | |
2160 | ||
160c1d8e | 2161 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2162 | .alloc_coherent = alloc_coherent, |
2163 | .free_coherent = free_coherent, | |
51491367 FT |
2164 | .map_page = map_page, |
2165 | .unmap_page = unmap_page, | |
6631ee9d JR |
2166 | .map_sg = map_sg, |
2167 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2168 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2169 | }; |
2170 | ||
431b2a20 JR |
2171 | /* |
2172 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2173 | */ | |
6631ee9d JR |
2174 | int __init amd_iommu_init_dma_ops(void) |
2175 | { | |
2176 | struct amd_iommu *iommu; | |
6631ee9d JR |
2177 | int ret; |
2178 | ||
431b2a20 JR |
2179 | /* |
2180 | * first allocate a default protection domain for every IOMMU we | |
2181 | * found in the system. Devices not assigned to any other | |
2182 | * protection domain will be assigned to the default one. | |
2183 | */ | |
3bd22172 | 2184 | for_each_iommu(iommu) { |
87a64d52 | 2185 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2186 | if (iommu->default_dom == NULL) |
2187 | return -ENOMEM; | |
e2dc14a2 | 2188 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2189 | ret = iommu_init_unity_mappings(iommu); |
2190 | if (ret) | |
2191 | goto free_domains; | |
2192 | } | |
2193 | ||
431b2a20 | 2194 | /* |
8793abeb | 2195 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2196 | */ |
8793abeb | 2197 | prealloc_protection_domains(); |
6631ee9d JR |
2198 | |
2199 | iommu_detected = 1; | |
75f1cdf1 | 2200 | swiotlb = 0; |
92af4e29 | 2201 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
2202 | gart_iommu_aperture_disabled = 1; |
2203 | gart_iommu_aperture = 0; | |
92af4e29 | 2204 | #endif |
6631ee9d | 2205 | |
431b2a20 | 2206 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2207 | dma_ops = &amd_iommu_dma_ops; |
2208 | ||
26961efe | 2209 | register_iommu(&amd_iommu_ops); |
26961efe | 2210 | |
e275a2a0 JR |
2211 | bus_register_notifier(&pci_bus_type, &device_nb); |
2212 | ||
7f26508b JR |
2213 | amd_iommu_stats_init(); |
2214 | ||
6631ee9d JR |
2215 | return 0; |
2216 | ||
2217 | free_domains: | |
2218 | ||
3bd22172 | 2219 | for_each_iommu(iommu) { |
6631ee9d JR |
2220 | if (iommu->default_dom) |
2221 | dma_ops_domain_free(iommu->default_dom); | |
2222 | } | |
2223 | ||
2224 | return ret; | |
2225 | } | |
6d98cd80 JR |
2226 | |
2227 | /***************************************************************************** | |
2228 | * | |
2229 | * The following functions belong to the exported interface of AMD IOMMU | |
2230 | * | |
2231 | * This interface allows access to lower level functions of the IOMMU | |
2232 | * like protection domain handling and assignement of devices to domains | |
2233 | * which is not possible with the dma_ops interface. | |
2234 | * | |
2235 | *****************************************************************************/ | |
2236 | ||
6d98cd80 JR |
2237 | static void cleanup_domain(struct protection_domain *domain) |
2238 | { | |
2239 | unsigned long flags; | |
2240 | u16 devid; | |
2241 | ||
2242 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2243 | ||
2244 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
2245 | if (amd_iommu_pd_table[devid] == domain) | |
15898bbc | 2246 | clear_dte_entry(devid); |
6d98cd80 JR |
2247 | |
2248 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2249 | } | |
2250 | ||
2650815f JR |
2251 | static void protection_domain_free(struct protection_domain *domain) |
2252 | { | |
2253 | if (!domain) | |
2254 | return; | |
2255 | ||
aeb26f55 JR |
2256 | del_domain_from_list(domain); |
2257 | ||
2650815f JR |
2258 | if (domain->id) |
2259 | domain_id_free(domain->id); | |
2260 | ||
2261 | kfree(domain); | |
2262 | } | |
2263 | ||
2264 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2265 | { |
2266 | struct protection_domain *domain; | |
2267 | ||
2268 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2269 | if (!domain) | |
2650815f | 2270 | return NULL; |
c156e347 JR |
2271 | |
2272 | spin_lock_init(&domain->lock); | |
c156e347 JR |
2273 | domain->id = domain_id_alloc(); |
2274 | if (!domain->id) | |
2650815f JR |
2275 | goto out_err; |
2276 | ||
aeb26f55 JR |
2277 | add_domain_to_list(domain); |
2278 | ||
2650815f JR |
2279 | return domain; |
2280 | ||
2281 | out_err: | |
2282 | kfree(domain); | |
2283 | ||
2284 | return NULL; | |
2285 | } | |
2286 | ||
2287 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2288 | { | |
2289 | struct protection_domain *domain; | |
2290 | ||
2291 | domain = protection_domain_alloc(); | |
2292 | if (!domain) | |
c156e347 | 2293 | goto out_free; |
2650815f JR |
2294 | |
2295 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2296 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2297 | if (!domain->pt_root) | |
2298 | goto out_free; | |
2299 | ||
2300 | dom->priv = domain; | |
2301 | ||
2302 | return 0; | |
2303 | ||
2304 | out_free: | |
2650815f | 2305 | protection_domain_free(domain); |
c156e347 JR |
2306 | |
2307 | return -ENOMEM; | |
2308 | } | |
2309 | ||
98383fc3 JR |
2310 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2311 | { | |
2312 | struct protection_domain *domain = dom->priv; | |
2313 | ||
2314 | if (!domain) | |
2315 | return; | |
2316 | ||
2317 | if (domain->dev_cnt > 0) | |
2318 | cleanup_domain(domain); | |
2319 | ||
2320 | BUG_ON(domain->dev_cnt != 0); | |
2321 | ||
2322 | free_pagetable(domain); | |
2323 | ||
2324 | domain_id_free(domain->id); | |
2325 | ||
2326 | kfree(domain); | |
2327 | ||
2328 | dom->priv = NULL; | |
2329 | } | |
2330 | ||
684f2888 JR |
2331 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2332 | struct device *dev) | |
2333 | { | |
657cbb6b | 2334 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2335 | struct amd_iommu *iommu; |
684f2888 JR |
2336 | u16 devid; |
2337 | ||
98fc5a69 | 2338 | if (!check_device(dev)) |
684f2888 JR |
2339 | return; |
2340 | ||
98fc5a69 | 2341 | devid = get_device_id(dev); |
684f2888 | 2342 | |
657cbb6b | 2343 | if (dev_data->domain != NULL) |
15898bbc | 2344 | detach_device(dev); |
684f2888 JR |
2345 | |
2346 | iommu = amd_iommu_rlookup_table[devid]; | |
2347 | if (!iommu) | |
2348 | return; | |
2349 | ||
2350 | iommu_queue_inv_dev_entry(iommu, devid); | |
2351 | iommu_completion_wait(iommu); | |
2352 | } | |
2353 | ||
01106066 JR |
2354 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2355 | struct device *dev) | |
2356 | { | |
2357 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2358 | struct iommu_dev_data *dev_data; |
01106066 | 2359 | struct amd_iommu *iommu; |
15898bbc | 2360 | int ret; |
01106066 JR |
2361 | u16 devid; |
2362 | ||
98fc5a69 | 2363 | if (!check_device(dev)) |
01106066 JR |
2364 | return -EINVAL; |
2365 | ||
657cbb6b JR |
2366 | dev_data = dev->archdata.iommu; |
2367 | ||
98fc5a69 | 2368 | devid = get_device_id(dev); |
01106066 JR |
2369 | |
2370 | iommu = amd_iommu_rlookup_table[devid]; | |
2371 | if (!iommu) | |
2372 | return -EINVAL; | |
2373 | ||
657cbb6b | 2374 | if (dev_data->domain) |
15898bbc | 2375 | detach_device(dev); |
01106066 | 2376 | |
15898bbc | 2377 | ret = attach_device(dev, domain); |
01106066 JR |
2378 | |
2379 | iommu_completion_wait(iommu); | |
2380 | ||
15898bbc | 2381 | return ret; |
01106066 JR |
2382 | } |
2383 | ||
c6229ca6 JR |
2384 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2385 | unsigned long iova, phys_addr_t paddr, | |
2386 | size_t size, int iommu_prot) | |
2387 | { | |
2388 | struct protection_domain *domain = dom->priv; | |
2389 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2390 | int prot = 0; | |
2391 | int ret; | |
2392 | ||
2393 | if (iommu_prot & IOMMU_READ) | |
2394 | prot |= IOMMU_PROT_IR; | |
2395 | if (iommu_prot & IOMMU_WRITE) | |
2396 | prot |= IOMMU_PROT_IW; | |
2397 | ||
2398 | iova &= PAGE_MASK; | |
2399 | paddr &= PAGE_MASK; | |
2400 | ||
2401 | for (i = 0; i < npages; ++i) { | |
abdc5eb3 | 2402 | ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k); |
c6229ca6 JR |
2403 | if (ret) |
2404 | return ret; | |
2405 | ||
2406 | iova += PAGE_SIZE; | |
2407 | paddr += PAGE_SIZE; | |
2408 | } | |
2409 | ||
2410 | return 0; | |
2411 | } | |
2412 | ||
eb74ff6c JR |
2413 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2414 | unsigned long iova, size_t size) | |
2415 | { | |
2416 | ||
2417 | struct protection_domain *domain = dom->priv; | |
2418 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2419 | ||
2420 | iova &= PAGE_MASK; | |
2421 | ||
2422 | for (i = 0; i < npages; ++i) { | |
a6b256b4 | 2423 | iommu_unmap_page(domain, iova, PM_MAP_4k); |
eb74ff6c JR |
2424 | iova += PAGE_SIZE; |
2425 | } | |
2426 | ||
601367d7 | 2427 | iommu_flush_tlb_pde(domain); |
eb74ff6c JR |
2428 | } |
2429 | ||
645c4c8d JR |
2430 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2431 | unsigned long iova) | |
2432 | { | |
2433 | struct protection_domain *domain = dom->priv; | |
2434 | unsigned long offset = iova & ~PAGE_MASK; | |
2435 | phys_addr_t paddr; | |
2436 | u64 *pte; | |
2437 | ||
a6b256b4 | 2438 | pte = fetch_pte(domain, iova, PM_MAP_4k); |
645c4c8d | 2439 | |
a6d41a40 | 2440 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2441 | return 0; |
2442 | ||
2443 | paddr = *pte & IOMMU_PAGE_MASK; | |
2444 | paddr |= offset; | |
2445 | ||
2446 | return paddr; | |
2447 | } | |
2448 | ||
dbb9fd86 SY |
2449 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2450 | unsigned long cap) | |
2451 | { | |
2452 | return 0; | |
2453 | } | |
2454 | ||
26961efe JR |
2455 | static struct iommu_ops amd_iommu_ops = { |
2456 | .domain_init = amd_iommu_domain_init, | |
2457 | .domain_destroy = amd_iommu_domain_destroy, | |
2458 | .attach_dev = amd_iommu_attach_device, | |
2459 | .detach_dev = amd_iommu_detach_device, | |
2460 | .map = amd_iommu_map_range, | |
2461 | .unmap = amd_iommu_unmap_range, | |
2462 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2463 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2464 | }; |
2465 | ||
0feae533 JR |
2466 | /***************************************************************************** |
2467 | * | |
2468 | * The next functions do a basic initialization of IOMMU for pass through | |
2469 | * mode | |
2470 | * | |
2471 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2472 | * DMA-API translation. | |
2473 | * | |
2474 | *****************************************************************************/ | |
2475 | ||
2476 | int __init amd_iommu_init_passthrough(void) | |
2477 | { | |
15898bbc | 2478 | struct amd_iommu *iommu; |
0feae533 | 2479 | struct pci_dev *dev = NULL; |
15898bbc | 2480 | u16 devid; |
0feae533 JR |
2481 | |
2482 | /* allocate passthroug domain */ | |
2483 | pt_domain = protection_domain_alloc(); | |
2484 | if (!pt_domain) | |
2485 | return -ENOMEM; | |
2486 | ||
2487 | pt_domain->mode |= PAGE_MODE_NONE; | |
2488 | ||
2489 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
0feae533 | 2490 | |
98fc5a69 | 2491 | if (!check_device(&dev->dev)) |
0feae533 JR |
2492 | continue; |
2493 | ||
98fc5a69 JR |
2494 | devid = get_device_id(&dev->dev); |
2495 | ||
15898bbc | 2496 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2497 | if (!iommu) |
2498 | continue; | |
2499 | ||
15898bbc | 2500 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2501 | } |
2502 | ||
2503 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2504 | ||
2505 | return 0; | |
2506 | } |