Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
bf3118c1 | 2 | * Copyright (C) 2007-2009 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
6a9401a7 | 31 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
0feae533 JR |
45 | /* |
46 | * Domain for untranslated devices - only allocated | |
47 | * if iommu=pt passed on kernel cmd line. | |
48 | */ | |
49 | static struct protection_domain *pt_domain; | |
50 | ||
26961efe | 51 | static struct iommu_ops amd_iommu_ops; |
26961efe | 52 | |
431b2a20 JR |
53 | /* |
54 | * general struct to manage commands send to an IOMMU | |
55 | */ | |
d6449536 | 56 | struct iommu_cmd { |
b6c02715 JR |
57 | u32 data[4]; |
58 | }; | |
59 | ||
bd0e5211 JR |
60 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
61 | struct unity_map_entry *e); | |
e275a2a0 | 62 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bc3e127 | 63 | static u64 *alloc_pte(struct protection_domain *domain, |
abdc5eb3 JR |
64 | unsigned long address, int end_lvl, |
65 | u64 **pte_page, gfp_t gfp); | |
00cd122a JR |
66 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
67 | unsigned long start_page, | |
68 | unsigned int pages); | |
a345b23b | 69 | static void reset_iommu_command_buffer(struct amd_iommu *iommu); |
9355a081 | 70 | static u64 *fetch_pte(struct protection_domain *domain, |
a6b256b4 | 71 | unsigned long address, int map_size); |
04bfdd84 | 72 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 73 | |
7f26508b JR |
74 | #ifdef CONFIG_AMD_IOMMU_STATS |
75 | ||
76 | /* | |
77 | * Initialization code for statistics collection | |
78 | */ | |
79 | ||
da49f6df | 80 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 81 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 82 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 83 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 84 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 85 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 86 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 87 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 88 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 89 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 90 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 91 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 92 | |
7f26508b JR |
93 | static struct dentry *stats_dir; |
94 | static struct dentry *de_isolate; | |
95 | static struct dentry *de_fflush; | |
96 | ||
97 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
98 | { | |
99 | if (stats_dir == NULL) | |
100 | return; | |
101 | ||
102 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
103 | &cnt->value); | |
104 | } | |
105 | ||
106 | static void amd_iommu_stats_init(void) | |
107 | { | |
108 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
109 | if (stats_dir == NULL) | |
110 | return; | |
111 | ||
112 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
113 | (u32 *)&amd_iommu_isolate); | |
114 | ||
115 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
116 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
117 | |
118 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 119 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 120 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 121 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 122 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 123 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 124 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 125 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 126 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 127 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 128 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 129 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
130 | } |
131 | ||
132 | #endif | |
133 | ||
431b2a20 | 134 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
135 | static int iommu_has_npcache(struct amd_iommu *iommu) |
136 | { | |
ae9b9403 | 137 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
138 | } |
139 | ||
a80dc3e0 JR |
140 | /**************************************************************************** |
141 | * | |
142 | * Interrupt handling functions | |
143 | * | |
144 | ****************************************************************************/ | |
145 | ||
e3e59876 JR |
146 | static void dump_dte_entry(u16 devid) |
147 | { | |
148 | int i; | |
149 | ||
150 | for (i = 0; i < 8; ++i) | |
151 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
152 | amd_iommu_dev_table[devid].data[i]); | |
153 | } | |
154 | ||
945b4ac4 JR |
155 | static void dump_command(unsigned long phys_addr) |
156 | { | |
157 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
158 | int i; | |
159 | ||
160 | for (i = 0; i < 4; ++i) | |
161 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
162 | } | |
163 | ||
a345b23b | 164 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
165 | { |
166 | u32 *event = __evt; | |
167 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
168 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
169 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
170 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
171 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
172 | ||
4c6f40d4 | 173 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
174 | |
175 | switch (type) { | |
176 | case EVENT_TYPE_ILL_DEV: | |
177 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
178 | "address=0x%016llx flags=0x%04x]\n", | |
179 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
180 | address, flags); | |
e3e59876 | 181 | dump_dte_entry(devid); |
90008ee4 JR |
182 | break; |
183 | case EVENT_TYPE_IO_FAULT: | |
184 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
185 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
186 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
187 | domid, address, flags); | |
188 | break; | |
189 | case EVENT_TYPE_DEV_TAB_ERR: | |
190 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
191 | "address=0x%016llx flags=0x%04x]\n", | |
192 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
193 | address, flags); | |
194 | break; | |
195 | case EVENT_TYPE_PAGE_TAB_ERR: | |
196 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
197 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
198 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
199 | domid, address, flags); | |
200 | break; | |
201 | case EVENT_TYPE_ILL_CMD: | |
202 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
a345b23b | 203 | reset_iommu_command_buffer(iommu); |
945b4ac4 | 204 | dump_command(address); |
90008ee4 JR |
205 | break; |
206 | case EVENT_TYPE_CMD_HARD_ERR: | |
207 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
208 | "flags=0x%04x]\n", address, flags); | |
209 | break; | |
210 | case EVENT_TYPE_IOTLB_INV_TO: | |
211 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
212 | "address=0x%016llx]\n", | |
213 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
214 | address); | |
215 | break; | |
216 | case EVENT_TYPE_INV_DEV_REQ: | |
217 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
218 | "address=0x%016llx flags=0x%04x]\n", | |
219 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
220 | address, flags); | |
221 | break; | |
222 | default: | |
223 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
224 | } | |
225 | } | |
226 | ||
227 | static void iommu_poll_events(struct amd_iommu *iommu) | |
228 | { | |
229 | u32 head, tail; | |
230 | unsigned long flags; | |
231 | ||
232 | spin_lock_irqsave(&iommu->lock, flags); | |
233 | ||
234 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
235 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
236 | ||
237 | while (head != tail) { | |
a345b23b | 238 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
239 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
240 | } | |
241 | ||
242 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
243 | ||
244 | spin_unlock_irqrestore(&iommu->lock, flags); | |
245 | } | |
246 | ||
a80dc3e0 JR |
247 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
248 | { | |
90008ee4 JR |
249 | struct amd_iommu *iommu; |
250 | ||
3bd22172 | 251 | for_each_iommu(iommu) |
90008ee4 JR |
252 | iommu_poll_events(iommu); |
253 | ||
254 | return IRQ_HANDLED; | |
a80dc3e0 JR |
255 | } |
256 | ||
431b2a20 JR |
257 | /**************************************************************************** |
258 | * | |
259 | * IOMMU command queuing functions | |
260 | * | |
261 | ****************************************************************************/ | |
262 | ||
263 | /* | |
264 | * Writes the command to the IOMMUs command buffer and informs the | |
265 | * hardware about the new command. Must be called with iommu->lock held. | |
266 | */ | |
d6449536 | 267 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
268 | { |
269 | u32 tail, head; | |
270 | u8 *target; | |
271 | ||
272 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 273 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
274 | memcpy_toio(target, cmd, sizeof(*cmd)); |
275 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
276 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
277 | if (tail == head) | |
278 | return -ENOMEM; | |
279 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
431b2a20 JR |
284 | /* |
285 | * General queuing function for commands. Takes iommu->lock and calls | |
286 | * __iommu_queue_command(). | |
287 | */ | |
d6449536 | 288 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
289 | { |
290 | unsigned long flags; | |
291 | int ret; | |
292 | ||
293 | spin_lock_irqsave(&iommu->lock, flags); | |
294 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 295 | if (!ret) |
0cfd7aa9 | 296 | iommu->need_sync = true; |
a19ae1ec JR |
297 | spin_unlock_irqrestore(&iommu->lock, flags); |
298 | ||
299 | return ret; | |
300 | } | |
301 | ||
8d201968 JR |
302 | /* |
303 | * This function waits until an IOMMU has completed a completion | |
304 | * wait command | |
305 | */ | |
306 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
307 | { | |
308 | int ready = 0; | |
309 | unsigned status = 0; | |
310 | unsigned long i = 0; | |
311 | ||
da49f6df JR |
312 | INC_STATS_COUNTER(compl_wait); |
313 | ||
8d201968 JR |
314 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
315 | ++i; | |
316 | /* wait for the bit to become one */ | |
317 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
318 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
319 | } | |
320 | ||
321 | /* set bit back to zero */ | |
322 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
323 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
324 | ||
6a1eddd2 JR |
325 | if (unlikely(i == EXIT_LOOP_COUNT)) { |
326 | spin_unlock(&iommu->lock); | |
327 | reset_iommu_command_buffer(iommu); | |
328 | spin_lock(&iommu->lock); | |
329 | } | |
8d201968 JR |
330 | } |
331 | ||
332 | /* | |
333 | * This function queues a completion wait command into the command | |
334 | * buffer of an IOMMU | |
335 | */ | |
336 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
337 | { | |
338 | struct iommu_cmd cmd; | |
339 | ||
340 | memset(&cmd, 0, sizeof(cmd)); | |
341 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
342 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
343 | ||
344 | return __iommu_queue_command(iommu, &cmd); | |
345 | } | |
346 | ||
431b2a20 JR |
347 | /* |
348 | * This function is called whenever we need to ensure that the IOMMU has | |
349 | * completed execution of all commands we sent. It sends a | |
350 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
351 | * us about that by writing a value to a physical address we pass with | |
352 | * the command. | |
353 | */ | |
a19ae1ec JR |
354 | static int iommu_completion_wait(struct amd_iommu *iommu) |
355 | { | |
8d201968 JR |
356 | int ret = 0; |
357 | unsigned long flags; | |
a19ae1ec | 358 | |
7e4f88da JR |
359 | spin_lock_irqsave(&iommu->lock, flags); |
360 | ||
09ee17eb JR |
361 | if (!iommu->need_sync) |
362 | goto out; | |
363 | ||
8d201968 | 364 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 365 | |
0cfd7aa9 | 366 | iommu->need_sync = false; |
a19ae1ec JR |
367 | |
368 | if (ret) | |
7e4f88da | 369 | goto out; |
a19ae1ec | 370 | |
8d201968 | 371 | __iommu_wait_for_completion(iommu); |
84df8175 | 372 | |
7e4f88da JR |
373 | out: |
374 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
375 | |
376 | return 0; | |
377 | } | |
378 | ||
0518a3a4 JR |
379 | static void iommu_flush_complete(struct protection_domain *domain) |
380 | { | |
381 | int i; | |
382 | ||
383 | for (i = 0; i < amd_iommus_present; ++i) { | |
384 | if (!domain->dev_iommu[i]) | |
385 | continue; | |
386 | ||
387 | /* | |
388 | * Devices of this domain are behind this IOMMU | |
389 | * We need to wait for completion of all commands. | |
390 | */ | |
391 | iommu_completion_wait(amd_iommus[i]); | |
392 | } | |
393 | } | |
394 | ||
431b2a20 JR |
395 | /* |
396 | * Command send function for invalidating a device table entry | |
397 | */ | |
a19ae1ec JR |
398 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
399 | { | |
d6449536 | 400 | struct iommu_cmd cmd; |
ee2fa743 | 401 | int ret; |
a19ae1ec JR |
402 | |
403 | BUG_ON(iommu == NULL); | |
404 | ||
405 | memset(&cmd, 0, sizeof(cmd)); | |
406 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
407 | cmd.data[0] = devid; | |
408 | ||
ee2fa743 JR |
409 | ret = iommu_queue_command(iommu, &cmd); |
410 | ||
ee2fa743 | 411 | return ret; |
a19ae1ec JR |
412 | } |
413 | ||
237b6f33 JR |
414 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
415 | u16 domid, int pde, int s) | |
416 | { | |
417 | memset(cmd, 0, sizeof(*cmd)); | |
418 | address &= PAGE_MASK; | |
419 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
420 | cmd->data[1] |= domid; | |
421 | cmd->data[2] = lower_32_bits(address); | |
422 | cmd->data[3] = upper_32_bits(address); | |
423 | if (s) /* size bit - we flush more than one 4kb page */ | |
424 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
425 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
426 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
427 | } | |
428 | ||
431b2a20 JR |
429 | /* |
430 | * Generic command send function for invalidaing TLB entries | |
431 | */ | |
a19ae1ec JR |
432 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
433 | u64 address, u16 domid, int pde, int s) | |
434 | { | |
d6449536 | 435 | struct iommu_cmd cmd; |
ee2fa743 | 436 | int ret; |
a19ae1ec | 437 | |
237b6f33 | 438 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 439 | |
ee2fa743 JR |
440 | ret = iommu_queue_command(iommu, &cmd); |
441 | ||
ee2fa743 | 442 | return ret; |
a19ae1ec JR |
443 | } |
444 | ||
431b2a20 JR |
445 | /* |
446 | * TLB invalidation function which is called from the mapping functions. | |
447 | * It invalidates a single PTE if the range to flush is within a single | |
448 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
449 | */ | |
6de8ad9b JR |
450 | static void __iommu_flush_pages(struct protection_domain *domain, |
451 | u64 address, size_t size, int pde) | |
a19ae1ec | 452 | { |
6de8ad9b | 453 | int s = 0, i; |
e3c449f5 | 454 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
455 | |
456 | address &= PAGE_MASK; | |
457 | ||
999ba417 JR |
458 | if (pages > 1) { |
459 | /* | |
460 | * If we have to flush more than one page, flush all | |
461 | * TLB entries for this domain | |
462 | */ | |
463 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
464 | s = 1; | |
a19ae1ec JR |
465 | } |
466 | ||
999ba417 | 467 | |
6de8ad9b JR |
468 | for (i = 0; i < amd_iommus_present; ++i) { |
469 | if (!domain->dev_iommu[i]) | |
470 | continue; | |
471 | ||
472 | /* | |
473 | * Devices of this domain are behind this IOMMU | |
474 | * We need a TLB flush | |
475 | */ | |
476 | iommu_queue_inv_iommu_pages(amd_iommus[i], address, | |
477 | domain->id, pde, s); | |
478 | } | |
479 | ||
480 | return; | |
481 | } | |
482 | ||
483 | static void iommu_flush_pages(struct protection_domain *domain, | |
484 | u64 address, size_t size) | |
485 | { | |
486 | __iommu_flush_pages(domain, address, size, 0); | |
a19ae1ec | 487 | } |
b6c02715 | 488 | |
1c655773 JR |
489 | /* Flush the whole IO/TLB for a given protection domain */ |
490 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
491 | { | |
492 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
493 | ||
f57d98ae JR |
494 | INC_STATS_COUNTER(domain_flush_single); |
495 | ||
1c655773 JR |
496 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
497 | } | |
498 | ||
42a49f96 CW |
499 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
500 | static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid) | |
501 | { | |
502 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
503 | ||
504 | INC_STATS_COUNTER(domain_flush_single); | |
505 | ||
506 | iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1); | |
507 | } | |
508 | ||
43f49609 | 509 | /* |
e394d72a | 510 | * This function flushes one domain on one IOMMU |
43f49609 | 511 | */ |
e394d72a | 512 | static void flush_domain_on_iommu(struct amd_iommu *iommu, u16 domid) |
43f49609 | 513 | { |
43f49609 | 514 | struct iommu_cmd cmd; |
e394d72a | 515 | unsigned long flags; |
18811f55 | 516 | |
43f49609 JR |
517 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
518 | domid, 1, 1); | |
519 | ||
e394d72a JR |
520 | spin_lock_irqsave(&iommu->lock, flags); |
521 | __iommu_queue_command(iommu, &cmd); | |
522 | __iommu_completion_wait(iommu); | |
523 | __iommu_wait_for_completion(iommu); | |
524 | spin_unlock_irqrestore(&iommu->lock, flags); | |
43f49609 | 525 | } |
43f49609 | 526 | |
e394d72a | 527 | static void flush_all_domains_on_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
528 | { |
529 | int i; | |
530 | ||
531 | for (i = 1; i < MAX_DOMAIN_ID; ++i) { | |
532 | if (!test_bit(i, amd_iommu_pd_alloc_bitmap)) | |
533 | continue; | |
e394d72a | 534 | flush_domain_on_iommu(iommu, i); |
bfd1be18 | 535 | } |
e394d72a JR |
536 | |
537 | } | |
538 | ||
43f49609 JR |
539 | /* |
540 | * This function is used to flush the IO/TLB for a given protection domain | |
541 | * on every IOMMU in the system | |
542 | */ | |
543 | static void iommu_flush_domain(u16 domid) | |
544 | { | |
43f49609 | 545 | struct amd_iommu *iommu; |
43f49609 | 546 | |
18811f55 JR |
547 | INC_STATS_COUNTER(domain_flush_all); |
548 | ||
e394d72a JR |
549 | for_each_iommu(iommu) |
550 | flush_domain_on_iommu(iommu, domid); | |
43f49609 | 551 | } |
43f49609 | 552 | |
bfd1be18 | 553 | void amd_iommu_flush_all_domains(void) |
e394d72a JR |
554 | { |
555 | struct amd_iommu *iommu; | |
556 | ||
557 | for_each_iommu(iommu) | |
558 | flush_all_domains_on_iommu(iommu); | |
bfd1be18 JR |
559 | } |
560 | ||
d586d785 | 561 | static void flush_all_devices_for_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
562 | { |
563 | int i; | |
564 | ||
d586d785 JR |
565 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { |
566 | if (iommu != amd_iommu_rlookup_table[i]) | |
bfd1be18 | 567 | continue; |
d586d785 JR |
568 | |
569 | iommu_queue_inv_dev_entry(iommu, i); | |
570 | iommu_completion_wait(iommu); | |
bfd1be18 JR |
571 | } |
572 | } | |
573 | ||
6a0dbcbe | 574 | static void flush_devices_by_domain(struct protection_domain *domain) |
7d7a110c JR |
575 | { |
576 | struct amd_iommu *iommu; | |
577 | int i; | |
578 | ||
579 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
6a0dbcbe JR |
580 | if ((domain == NULL && amd_iommu_pd_table[i] == NULL) || |
581 | (amd_iommu_pd_table[i] != domain)) | |
7d7a110c JR |
582 | continue; |
583 | ||
584 | iommu = amd_iommu_rlookup_table[i]; | |
585 | if (!iommu) | |
586 | continue; | |
587 | ||
588 | iommu_queue_inv_dev_entry(iommu, i); | |
589 | iommu_completion_wait(iommu); | |
590 | } | |
591 | } | |
592 | ||
a345b23b JR |
593 | static void reset_iommu_command_buffer(struct amd_iommu *iommu) |
594 | { | |
595 | pr_err("AMD-Vi: Resetting IOMMU command buffer\n"); | |
596 | ||
b26e81b8 JR |
597 | if (iommu->reset_in_progress) |
598 | panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n"); | |
599 | ||
600 | iommu->reset_in_progress = true; | |
601 | ||
a345b23b JR |
602 | amd_iommu_reset_cmd_buffer(iommu); |
603 | flush_all_devices_for_iommu(iommu); | |
604 | flush_all_domains_on_iommu(iommu); | |
b26e81b8 JR |
605 | |
606 | iommu->reset_in_progress = false; | |
a345b23b JR |
607 | } |
608 | ||
6a0dbcbe JR |
609 | void amd_iommu_flush_all_devices(void) |
610 | { | |
611 | flush_devices_by_domain(NULL); | |
612 | } | |
613 | ||
431b2a20 JR |
614 | /**************************************************************************** |
615 | * | |
616 | * The functions below are used the create the page table mappings for | |
617 | * unity mapped regions. | |
618 | * | |
619 | ****************************************************************************/ | |
620 | ||
621 | /* | |
622 | * Generic mapping functions. It maps a physical address into a DMA | |
623 | * address space. It allocates the page table pages if necessary. | |
624 | * In the future it can be extended to a generic mapping function | |
625 | * supporting all features of AMD IOMMU page tables like level skipping | |
626 | * and full 64 bit address spaces. | |
627 | */ | |
38e817fe JR |
628 | static int iommu_map_page(struct protection_domain *dom, |
629 | unsigned long bus_addr, | |
630 | unsigned long phys_addr, | |
abdc5eb3 JR |
631 | int prot, |
632 | int map_size) | |
bd0e5211 | 633 | { |
8bda3092 | 634 | u64 __pte, *pte; |
bd0e5211 JR |
635 | |
636 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 637 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 | 638 | |
abdc5eb3 JR |
639 | BUG_ON(!PM_ALIGNED(map_size, bus_addr)); |
640 | BUG_ON(!PM_ALIGNED(map_size, phys_addr)); | |
641 | ||
bad1cac2 | 642 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
643 | return -EINVAL; |
644 | ||
abdc5eb3 | 645 | pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL); |
bd0e5211 JR |
646 | |
647 | if (IOMMU_PTE_PRESENT(*pte)) | |
648 | return -EBUSY; | |
649 | ||
650 | __pte = phys_addr | IOMMU_PTE_P; | |
651 | if (prot & IOMMU_PROT_IR) | |
652 | __pte |= IOMMU_PTE_IR; | |
653 | if (prot & IOMMU_PROT_IW) | |
654 | __pte |= IOMMU_PTE_IW; | |
655 | ||
656 | *pte = __pte; | |
657 | ||
04bfdd84 JR |
658 | update_domain(dom); |
659 | ||
bd0e5211 JR |
660 | return 0; |
661 | } | |
662 | ||
eb74ff6c | 663 | static void iommu_unmap_page(struct protection_domain *dom, |
a6b256b4 | 664 | unsigned long bus_addr, int map_size) |
eb74ff6c | 665 | { |
a6b256b4 | 666 | u64 *pte = fetch_pte(dom, bus_addr, map_size); |
eb74ff6c | 667 | |
38a76eee JR |
668 | if (pte) |
669 | *pte = 0; | |
eb74ff6c | 670 | } |
eb74ff6c | 671 | |
431b2a20 JR |
672 | /* |
673 | * This function checks if a specific unity mapping entry is needed for | |
674 | * this specific IOMMU. | |
675 | */ | |
bd0e5211 JR |
676 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
677 | struct unity_map_entry *entry) | |
678 | { | |
679 | u16 bdf, i; | |
680 | ||
681 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
682 | bdf = amd_iommu_alias_table[i]; | |
683 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
684 | return 1; | |
685 | } | |
686 | ||
687 | return 0; | |
688 | } | |
689 | ||
431b2a20 JR |
690 | /* |
691 | * Init the unity mappings for a specific IOMMU in the system | |
692 | * | |
693 | * Basically iterates over all unity mapping entries and applies them to | |
694 | * the default domain DMA of that IOMMU if necessary. | |
695 | */ | |
bd0e5211 JR |
696 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
697 | { | |
698 | struct unity_map_entry *entry; | |
699 | int ret; | |
700 | ||
701 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
702 | if (!iommu_for_unity_map(iommu, entry)) | |
703 | continue; | |
704 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
705 | if (ret) | |
706 | return ret; | |
707 | } | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
431b2a20 JR |
712 | /* |
713 | * This function actually applies the mapping to the page table of the | |
714 | * dma_ops domain. | |
715 | */ | |
bd0e5211 JR |
716 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
717 | struct unity_map_entry *e) | |
718 | { | |
719 | u64 addr; | |
720 | int ret; | |
721 | ||
722 | for (addr = e->address_start; addr < e->address_end; | |
723 | addr += PAGE_SIZE) { | |
abdc5eb3 JR |
724 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
725 | PM_MAP_4k); | |
bd0e5211 JR |
726 | if (ret) |
727 | return ret; | |
728 | /* | |
729 | * if unity mapping is in aperture range mark the page | |
730 | * as allocated in the aperture | |
731 | */ | |
732 | if (addr < dma_dom->aperture_size) | |
c3239567 | 733 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 734 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
735 | } |
736 | ||
737 | return 0; | |
738 | } | |
739 | ||
431b2a20 JR |
740 | /* |
741 | * Inits the unity mappings required for a specific device | |
742 | */ | |
bd0e5211 JR |
743 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
744 | u16 devid) | |
745 | { | |
746 | struct unity_map_entry *e; | |
747 | int ret; | |
748 | ||
749 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
750 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
751 | continue; | |
752 | ret = dma_ops_unity_map(dma_dom, e); | |
753 | if (ret) | |
754 | return ret; | |
755 | } | |
756 | ||
757 | return 0; | |
758 | } | |
759 | ||
431b2a20 JR |
760 | /**************************************************************************** |
761 | * | |
762 | * The next functions belong to the address allocator for the dma_ops | |
763 | * interface functions. They work like the allocators in the other IOMMU | |
764 | * drivers. Its basically a bitmap which marks the allocated pages in | |
765 | * the aperture. Maybe it could be enhanced in the future to a more | |
766 | * efficient allocator. | |
767 | * | |
768 | ****************************************************************************/ | |
d3086444 | 769 | |
431b2a20 | 770 | /* |
384de729 | 771 | * The address allocator core functions. |
431b2a20 JR |
772 | * |
773 | * called with domain->lock held | |
774 | */ | |
384de729 | 775 | |
00cd122a JR |
776 | /* |
777 | * This function checks if there is a PTE for a given dma address. If | |
778 | * there is one, it returns the pointer to it. | |
779 | */ | |
9355a081 | 780 | static u64 *fetch_pte(struct protection_domain *domain, |
a6b256b4 | 781 | unsigned long address, int map_size) |
00cd122a | 782 | { |
9355a081 | 783 | int level; |
00cd122a JR |
784 | u64 *pte; |
785 | ||
9355a081 JR |
786 | level = domain->mode - 1; |
787 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
00cd122a | 788 | |
a6b256b4 | 789 | while (level > map_size) { |
9355a081 JR |
790 | if (!IOMMU_PTE_PRESENT(*pte)) |
791 | return NULL; | |
00cd122a | 792 | |
9355a081 | 793 | level -= 1; |
00cd122a | 794 | |
9355a081 JR |
795 | pte = IOMMU_PTE_PAGE(*pte); |
796 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
00cd122a | 797 | |
a6b256b4 JR |
798 | if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) { |
799 | pte = NULL; | |
800 | break; | |
801 | } | |
9355a081 | 802 | } |
00cd122a JR |
803 | |
804 | return pte; | |
805 | } | |
806 | ||
9cabe89b JR |
807 | /* |
808 | * This function is used to add a new aperture range to an existing | |
809 | * aperture in case of dma_ops domain allocation or address allocation | |
810 | * failure. | |
811 | */ | |
00cd122a JR |
812 | static int alloc_new_range(struct amd_iommu *iommu, |
813 | struct dma_ops_domain *dma_dom, | |
9cabe89b JR |
814 | bool populate, gfp_t gfp) |
815 | { | |
816 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
00cd122a | 817 | int i; |
9cabe89b | 818 | |
f5e9705c JR |
819 | #ifdef CONFIG_IOMMU_STRESS |
820 | populate = false; | |
821 | #endif | |
822 | ||
9cabe89b JR |
823 | if (index >= APERTURE_MAX_RANGES) |
824 | return -ENOMEM; | |
825 | ||
826 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
827 | if (!dma_dom->aperture[index]) | |
828 | return -ENOMEM; | |
829 | ||
830 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
831 | if (!dma_dom->aperture[index]->bitmap) | |
832 | goto out_free; | |
833 | ||
834 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
835 | ||
836 | if (populate) { | |
837 | unsigned long address = dma_dom->aperture_size; | |
838 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
839 | u64 *pte, *pte_page; | |
840 | ||
841 | for (i = 0; i < num_ptes; ++i) { | |
abdc5eb3 | 842 | pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k, |
9cabe89b JR |
843 | &pte_page, gfp); |
844 | if (!pte) | |
845 | goto out_free; | |
846 | ||
847 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
848 | ||
849 | address += APERTURE_RANGE_SIZE / 64; | |
850 | } | |
851 | } | |
852 | ||
853 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
854 | ||
00cd122a JR |
855 | /* Intialize the exclusion range if necessary */ |
856 | if (iommu->exclusion_start && | |
857 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
858 | iommu->exclusion_start < dma_dom->aperture_size) { | |
859 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
860 | int pages = iommu_num_pages(iommu->exclusion_start, | |
861 | iommu->exclusion_length, | |
862 | PAGE_SIZE); | |
863 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
864 | } | |
865 | ||
866 | /* | |
867 | * Check for areas already mapped as present in the new aperture | |
868 | * range and mark those pages as reserved in the allocator. Such | |
869 | * mappings may already exist as a result of requested unity | |
870 | * mappings for devices. | |
871 | */ | |
872 | for (i = dma_dom->aperture[index]->offset; | |
873 | i < dma_dom->aperture_size; | |
874 | i += PAGE_SIZE) { | |
a6b256b4 | 875 | u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k); |
00cd122a JR |
876 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
877 | continue; | |
878 | ||
879 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
880 | } | |
881 | ||
04bfdd84 JR |
882 | update_domain(&dma_dom->domain); |
883 | ||
9cabe89b JR |
884 | return 0; |
885 | ||
886 | out_free: | |
04bfdd84 JR |
887 | update_domain(&dma_dom->domain); |
888 | ||
9cabe89b JR |
889 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
890 | ||
891 | kfree(dma_dom->aperture[index]); | |
892 | dma_dom->aperture[index] = NULL; | |
893 | ||
894 | return -ENOMEM; | |
895 | } | |
896 | ||
384de729 JR |
897 | static unsigned long dma_ops_area_alloc(struct device *dev, |
898 | struct dma_ops_domain *dom, | |
899 | unsigned int pages, | |
900 | unsigned long align_mask, | |
901 | u64 dma_mask, | |
902 | unsigned long start) | |
903 | { | |
803b8cb4 | 904 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
905 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
906 | int i = start >> APERTURE_RANGE_SHIFT; | |
907 | unsigned long boundary_size; | |
908 | unsigned long address = -1; | |
909 | unsigned long limit; | |
910 | ||
803b8cb4 JR |
911 | next_bit >>= PAGE_SHIFT; |
912 | ||
384de729 JR |
913 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
914 | PAGE_SIZE) >> PAGE_SHIFT; | |
915 | ||
916 | for (;i < max_index; ++i) { | |
917 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
918 | ||
919 | if (dom->aperture[i]->offset >= dma_mask) | |
920 | break; | |
921 | ||
922 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
923 | dma_mask >> PAGE_SHIFT); | |
924 | ||
925 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
926 | limit, next_bit, pages, 0, | |
927 | boundary_size, align_mask); | |
928 | if (address != -1) { | |
929 | address = dom->aperture[i]->offset + | |
930 | (address << PAGE_SHIFT); | |
803b8cb4 | 931 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
932 | break; |
933 | } | |
934 | ||
935 | next_bit = 0; | |
936 | } | |
937 | ||
938 | return address; | |
939 | } | |
940 | ||
d3086444 JR |
941 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
942 | struct dma_ops_domain *dom, | |
6d4f343f | 943 | unsigned int pages, |
832a90c3 JR |
944 | unsigned long align_mask, |
945 | u64 dma_mask) | |
d3086444 | 946 | { |
d3086444 | 947 | unsigned long address; |
d3086444 | 948 | |
fe16f088 JR |
949 | #ifdef CONFIG_IOMMU_STRESS |
950 | dom->next_address = 0; | |
951 | dom->need_flush = true; | |
952 | #endif | |
d3086444 | 953 | |
384de729 | 954 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 955 | dma_mask, dom->next_address); |
d3086444 | 956 | |
1c655773 | 957 | if (address == -1) { |
803b8cb4 | 958 | dom->next_address = 0; |
384de729 JR |
959 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
960 | dma_mask, 0); | |
1c655773 JR |
961 | dom->need_flush = true; |
962 | } | |
d3086444 | 963 | |
384de729 | 964 | if (unlikely(address == -1)) |
8fd524b3 | 965 | address = DMA_ERROR_CODE; |
d3086444 JR |
966 | |
967 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
968 | ||
969 | return address; | |
970 | } | |
971 | ||
431b2a20 JR |
972 | /* |
973 | * The address free function. | |
974 | * | |
975 | * called with domain->lock held | |
976 | */ | |
d3086444 JR |
977 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
978 | unsigned long address, | |
979 | unsigned int pages) | |
980 | { | |
384de729 JR |
981 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
982 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 983 | |
384de729 JR |
984 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
985 | ||
47bccd6b JR |
986 | #ifdef CONFIG_IOMMU_STRESS |
987 | if (i < 4) | |
988 | return; | |
989 | #endif | |
80be308d | 990 | |
803b8cb4 | 991 | if (address >= dom->next_address) |
80be308d | 992 | dom->need_flush = true; |
384de729 JR |
993 | |
994 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 995 | |
384de729 JR |
996 | iommu_area_free(range->bitmap, address, pages); |
997 | ||
d3086444 JR |
998 | } |
999 | ||
431b2a20 JR |
1000 | /**************************************************************************** |
1001 | * | |
1002 | * The next functions belong to the domain allocation. A domain is | |
1003 | * allocated for every IOMMU as the default domain. If device isolation | |
1004 | * is enabled, every device get its own domain. The most important thing | |
1005 | * about domains is the page table mapping the DMA address space they | |
1006 | * contain. | |
1007 | * | |
1008 | ****************************************************************************/ | |
1009 | ||
ec487d1a JR |
1010 | static u16 domain_id_alloc(void) |
1011 | { | |
1012 | unsigned long flags; | |
1013 | int id; | |
1014 | ||
1015 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1016 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1017 | BUG_ON(id == 0); | |
1018 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1019 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1020 | else | |
1021 | id = 0; | |
1022 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1023 | ||
1024 | return id; | |
1025 | } | |
1026 | ||
a2acfb75 JR |
1027 | static void domain_id_free(int id) |
1028 | { | |
1029 | unsigned long flags; | |
1030 | ||
1031 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1032 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1033 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1034 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1035 | } | |
a2acfb75 | 1036 | |
431b2a20 JR |
1037 | /* |
1038 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1039 | * ranges. | |
1040 | */ | |
ec487d1a JR |
1041 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
1042 | unsigned long start_page, | |
1043 | unsigned int pages) | |
1044 | { | |
384de729 | 1045 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
1046 | |
1047 | if (start_page + pages > last_page) | |
1048 | pages = last_page - start_page; | |
1049 | ||
384de729 JR |
1050 | for (i = start_page; i < start_page + pages; ++i) { |
1051 | int index = i / APERTURE_RANGE_PAGES; | |
1052 | int page = i % APERTURE_RANGE_PAGES; | |
1053 | __set_bit(page, dom->aperture[index]->bitmap); | |
1054 | } | |
ec487d1a JR |
1055 | } |
1056 | ||
86db2e5d | 1057 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1058 | { |
1059 | int i, j; | |
1060 | u64 *p1, *p2, *p3; | |
1061 | ||
86db2e5d | 1062 | p1 = domain->pt_root; |
ec487d1a JR |
1063 | |
1064 | if (!p1) | |
1065 | return; | |
1066 | ||
1067 | for (i = 0; i < 512; ++i) { | |
1068 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1069 | continue; | |
1070 | ||
1071 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1072 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1073 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1074 | continue; | |
1075 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1076 | free_page((unsigned long)p3); | |
1077 | } | |
1078 | ||
1079 | free_page((unsigned long)p2); | |
1080 | } | |
1081 | ||
1082 | free_page((unsigned long)p1); | |
86db2e5d JR |
1083 | |
1084 | domain->pt_root = NULL; | |
ec487d1a JR |
1085 | } |
1086 | ||
431b2a20 JR |
1087 | /* |
1088 | * Free a domain, only used if something went wrong in the | |
1089 | * allocation path and we need to free an already allocated page table | |
1090 | */ | |
ec487d1a JR |
1091 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1092 | { | |
384de729 JR |
1093 | int i; |
1094 | ||
ec487d1a JR |
1095 | if (!dom) |
1096 | return; | |
1097 | ||
86db2e5d | 1098 | free_pagetable(&dom->domain); |
ec487d1a | 1099 | |
384de729 JR |
1100 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1101 | if (!dom->aperture[i]) | |
1102 | continue; | |
1103 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1104 | kfree(dom->aperture[i]); | |
1105 | } | |
ec487d1a JR |
1106 | |
1107 | kfree(dom); | |
1108 | } | |
1109 | ||
431b2a20 JR |
1110 | /* |
1111 | * Allocates a new protection domain usable for the dma_ops functions. | |
1112 | * It also intializes the page table and the address allocator data | |
1113 | * structures required for the dma_ops interface | |
1114 | */ | |
d9cfed92 | 1115 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
1116 | { |
1117 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1118 | |
1119 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1120 | if (!dma_dom) | |
1121 | return NULL; | |
1122 | ||
1123 | spin_lock_init(&dma_dom->domain.lock); | |
1124 | ||
1125 | dma_dom->domain.id = domain_id_alloc(); | |
1126 | if (dma_dom->domain.id == 0) | |
1127 | goto free_dma_dom; | |
8f7a017c | 1128 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1129 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1130 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1131 | dma_dom->domain.priv = dma_dom; |
1132 | if (!dma_dom->domain.pt_root) | |
1133 | goto free_dma_dom; | |
ec487d1a | 1134 | |
1c655773 | 1135 | dma_dom->need_flush = false; |
bd60b735 | 1136 | dma_dom->target_dev = 0xffff; |
1c655773 | 1137 | |
00cd122a | 1138 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1139 | goto free_dma_dom; |
ec487d1a | 1140 | |
431b2a20 | 1141 | /* |
ec487d1a JR |
1142 | * mark the first page as allocated so we never return 0 as |
1143 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1144 | */ |
384de729 | 1145 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1146 | dma_dom->next_address = 0; |
ec487d1a | 1147 | |
ec487d1a JR |
1148 | |
1149 | return dma_dom; | |
1150 | ||
1151 | free_dma_dom: | |
1152 | dma_ops_domain_free(dma_dom); | |
1153 | ||
1154 | return NULL; | |
1155 | } | |
1156 | ||
5b28df6f JR |
1157 | /* |
1158 | * little helper function to check whether a given protection domain is a | |
1159 | * dma_ops domain | |
1160 | */ | |
1161 | static bool dma_ops_domain(struct protection_domain *domain) | |
1162 | { | |
1163 | return domain->flags & PD_DMA_OPS_MASK; | |
1164 | } | |
1165 | ||
431b2a20 JR |
1166 | /* |
1167 | * Find out the protection domain structure for a given PCI device. This | |
1168 | * will give us the pointer to the page table root for example. | |
1169 | */ | |
b20ac0d4 JR |
1170 | static struct protection_domain *domain_for_device(u16 devid) |
1171 | { | |
1172 | struct protection_domain *dom; | |
1173 | unsigned long flags; | |
1174 | ||
1175 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1176 | dom = amd_iommu_pd_table[devid]; | |
1177 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1178 | ||
1179 | return dom; | |
1180 | } | |
1181 | ||
407d733e | 1182 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1183 | { |
b20ac0d4 | 1184 | u64 pte_root = virt_to_phys(domain->pt_root); |
863c74eb | 1185 | |
38ddf41b JR |
1186 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1187 | << DEV_ENTRY_MODE_SHIFT; | |
1188 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1189 | |
b20ac0d4 | 1190 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1191 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1192 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
b20ac0d4 JR |
1193 | |
1194 | amd_iommu_pd_table[devid] = domain; | |
2b681faf JR |
1195 | } |
1196 | ||
1197 | /* | |
1198 | * If a device is not yet associated with a domain, this function does | |
1199 | * assigns it visible for the hardware | |
1200 | */ | |
1201 | static void __attach_device(struct amd_iommu *iommu, | |
1202 | struct protection_domain *domain, | |
1203 | u16 devid) | |
1204 | { | |
1205 | /* lock domain */ | |
1206 | spin_lock(&domain->lock); | |
1207 | ||
1208 | /* update DTE entry */ | |
1209 | set_dte_entry(devid, domain); | |
eba6ac60 | 1210 | |
c4596114 JR |
1211 | /* Do reference counting */ |
1212 | domain->dev_iommu[iommu->index] += 1; | |
1213 | domain->dev_cnt += 1; | |
eba6ac60 JR |
1214 | |
1215 | /* ready */ | |
1216 | spin_unlock(&domain->lock); | |
0feae533 | 1217 | } |
b20ac0d4 | 1218 | |
407d733e JR |
1219 | /* |
1220 | * If a device is not yet associated with a domain, this function does | |
1221 | * assigns it visible for the hardware | |
1222 | */ | |
0feae533 JR |
1223 | static void attach_device(struct amd_iommu *iommu, |
1224 | struct protection_domain *domain, | |
1225 | u16 devid) | |
1226 | { | |
eba6ac60 JR |
1227 | unsigned long flags; |
1228 | ||
1229 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
0feae533 | 1230 | __attach_device(iommu, domain, devid); |
b20ac0d4 JR |
1231 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1232 | ||
0feae533 JR |
1233 | /* |
1234 | * We might boot into a crash-kernel here. The crashed kernel | |
1235 | * left the caches in the IOMMU dirty. So we have to flush | |
1236 | * here to evict all dirty stuff. | |
1237 | */ | |
b20ac0d4 | 1238 | iommu_queue_inv_dev_entry(iommu, devid); |
42a49f96 | 1239 | iommu_flush_tlb_pde(iommu, domain->id); |
b20ac0d4 JR |
1240 | } |
1241 | ||
355bf553 JR |
1242 | /* |
1243 | * Removes a device from a protection domain (unlocked) | |
1244 | */ | |
1245 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1246 | { | |
c4596114 JR |
1247 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
1248 | ||
1249 | BUG_ON(!iommu); | |
355bf553 JR |
1250 | |
1251 | /* lock domain */ | |
1252 | spin_lock(&domain->lock); | |
1253 | ||
1254 | /* remove domain from the lookup table */ | |
1255 | amd_iommu_pd_table[devid] = NULL; | |
1256 | ||
1257 | /* remove entry from the device table seen by the hardware */ | |
1258 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1259 | amd_iommu_dev_table[devid].data[1] = 0; | |
1260 | amd_iommu_dev_table[devid].data[2] = 0; | |
1261 | ||
c5cca146 JR |
1262 | amd_iommu_apply_erratum_63(devid); |
1263 | ||
c4596114 JR |
1264 | /* decrease reference counters */ |
1265 | domain->dev_iommu[iommu->index] -= 1; | |
1266 | domain->dev_cnt -= 1; | |
355bf553 JR |
1267 | |
1268 | /* ready */ | |
1269 | spin_unlock(&domain->lock); | |
21129f78 JR |
1270 | |
1271 | /* | |
1272 | * If we run in passthrough mode the device must be assigned to the | |
1273 | * passthrough domain if it is detached from any other domain | |
1274 | */ | |
1275 | if (iommu_pass_through) { | |
1276 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
1277 | __attach_device(iommu, pt_domain, devid); | |
1278 | } | |
355bf553 JR |
1279 | } |
1280 | ||
1281 | /* | |
1282 | * Removes a device from a protection domain (with devtable_lock held) | |
1283 | */ | |
1284 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1285 | { | |
1286 | unsigned long flags; | |
1287 | ||
1288 | /* lock device table */ | |
1289 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1290 | __detach_device(domain, devid); | |
1291 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1292 | } | |
e275a2a0 JR |
1293 | |
1294 | static int device_change_notifier(struct notifier_block *nb, | |
1295 | unsigned long action, void *data) | |
1296 | { | |
1297 | struct device *dev = data; | |
1298 | struct pci_dev *pdev = to_pci_dev(dev); | |
1299 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1300 | struct protection_domain *domain; | |
1301 | struct dma_ops_domain *dma_domain; | |
1302 | struct amd_iommu *iommu; | |
1ac4cbbc | 1303 | unsigned long flags; |
e275a2a0 JR |
1304 | |
1305 | if (devid > amd_iommu_last_bdf) | |
1306 | goto out; | |
1307 | ||
1308 | devid = amd_iommu_alias_table[devid]; | |
1309 | ||
1310 | iommu = amd_iommu_rlookup_table[devid]; | |
1311 | if (iommu == NULL) | |
1312 | goto out; | |
1313 | ||
1314 | domain = domain_for_device(devid); | |
1315 | ||
1316 | if (domain && !dma_ops_domain(domain)) | |
1317 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1318 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1319 | ||
1320 | switch (action) { | |
c1eee67b | 1321 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1322 | if (!domain) |
1323 | goto out; | |
a1ca331c JR |
1324 | if (iommu_pass_through) |
1325 | break; | |
e275a2a0 | 1326 | detach_device(domain, devid); |
1ac4cbbc JR |
1327 | break; |
1328 | case BUS_NOTIFY_ADD_DEVICE: | |
1329 | /* allocate a protection domain if a device is added */ | |
1330 | dma_domain = find_protection_domain(devid); | |
1331 | if (dma_domain) | |
1332 | goto out; | |
d9cfed92 | 1333 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1334 | if (!dma_domain) |
1335 | goto out; | |
1336 | dma_domain->target_dev = devid; | |
1337 | ||
1338 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1339 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1340 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1341 | ||
e275a2a0 JR |
1342 | break; |
1343 | default: | |
1344 | goto out; | |
1345 | } | |
1346 | ||
1347 | iommu_queue_inv_dev_entry(iommu, devid); | |
1348 | iommu_completion_wait(iommu); | |
1349 | ||
1350 | out: | |
1351 | return 0; | |
1352 | } | |
1353 | ||
b25ae679 | 1354 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1355 | .notifier_call = device_change_notifier, |
1356 | }; | |
355bf553 | 1357 | |
431b2a20 JR |
1358 | /***************************************************************************** |
1359 | * | |
1360 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1361 | * | |
1362 | *****************************************************************************/ | |
1363 | ||
dbcc112e JR |
1364 | /* |
1365 | * This function checks if the driver got a valid device from the caller to | |
1366 | * avoid dereferencing invalid pointers. | |
1367 | */ | |
1368 | static bool check_device(struct device *dev) | |
1369 | { | |
1370 | if (!dev || !dev->dma_mask) | |
1371 | return false; | |
1372 | ||
1373 | return true; | |
1374 | } | |
1375 | ||
bd60b735 JR |
1376 | /* |
1377 | * In this function the list of preallocated protection domains is traversed to | |
1378 | * find the domain for a specific device | |
1379 | */ | |
1380 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1381 | { | |
1382 | struct dma_ops_domain *entry, *ret = NULL; | |
1383 | unsigned long flags; | |
1384 | ||
1385 | if (list_empty(&iommu_pd_list)) | |
1386 | return NULL; | |
1387 | ||
1388 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1389 | ||
1390 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1391 | if (entry->target_dev == devid) { | |
1392 | ret = entry; | |
bd60b735 JR |
1393 | break; |
1394 | } | |
1395 | } | |
1396 | ||
1397 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1398 | ||
1399 | return ret; | |
1400 | } | |
1401 | ||
431b2a20 JR |
1402 | /* |
1403 | * In the dma_ops path we only have the struct device. This function | |
1404 | * finds the corresponding IOMMU, the protection domain and the | |
1405 | * requestor id for a given device. | |
1406 | * If the device is not yet associated with a domain this is also done | |
1407 | * in this function. | |
1408 | */ | |
b20ac0d4 JR |
1409 | static int get_device_resources(struct device *dev, |
1410 | struct amd_iommu **iommu, | |
1411 | struct protection_domain **domain, | |
1412 | u16 *bdf) | |
1413 | { | |
1414 | struct dma_ops_domain *dma_dom; | |
1415 | struct pci_dev *pcidev; | |
1416 | u16 _bdf; | |
1417 | ||
dbcc112e JR |
1418 | *iommu = NULL; |
1419 | *domain = NULL; | |
1420 | *bdf = 0xffff; | |
1421 | ||
1422 | if (dev->bus != &pci_bus_type) | |
1423 | return 0; | |
b20ac0d4 JR |
1424 | |
1425 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1426 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1427 | |
431b2a20 | 1428 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1429 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1430 | return 0; |
b20ac0d4 JR |
1431 | |
1432 | *bdf = amd_iommu_alias_table[_bdf]; | |
1433 | ||
1434 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1435 | if (*iommu == NULL) | |
1436 | return 0; | |
b20ac0d4 JR |
1437 | *domain = domain_for_device(*bdf); |
1438 | if (*domain == NULL) { | |
bd60b735 JR |
1439 | dma_dom = find_protection_domain(*bdf); |
1440 | if (!dma_dom) | |
1441 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1442 | *domain = &dma_dom->domain; |
f1179dc0 | 1443 | attach_device(*iommu, *domain, *bdf); |
e9a22a13 JR |
1444 | DUMP_printk("Using protection domain %d for device %s\n", |
1445 | (*domain)->id, dev_name(dev)); | |
b20ac0d4 JR |
1446 | } |
1447 | ||
f91ba190 | 1448 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1449 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1450 | |
b20ac0d4 JR |
1451 | return 1; |
1452 | } | |
1453 | ||
04bfdd84 JR |
1454 | static void update_device_table(struct protection_domain *domain) |
1455 | { | |
2b681faf | 1456 | unsigned long flags; |
04bfdd84 JR |
1457 | int i; |
1458 | ||
1459 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
1460 | if (amd_iommu_pd_table[i] != domain) | |
1461 | continue; | |
2b681faf | 1462 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
04bfdd84 | 1463 | set_dte_entry(i, domain); |
2b681faf | 1464 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
04bfdd84 JR |
1465 | } |
1466 | } | |
1467 | ||
1468 | static void update_domain(struct protection_domain *domain) | |
1469 | { | |
1470 | if (!domain->updated) | |
1471 | return; | |
1472 | ||
1473 | update_device_table(domain); | |
1474 | flush_devices_by_domain(domain); | |
1475 | iommu_flush_domain(domain->id); | |
1476 | ||
1477 | domain->updated = false; | |
1478 | } | |
1479 | ||
8bda3092 | 1480 | /* |
50020fb6 JR |
1481 | * This function is used to add another level to an IO page table. Adding |
1482 | * another level increases the size of the address space by 9 bits to a size up | |
1483 | * to 64 bits. | |
8bda3092 | 1484 | */ |
50020fb6 JR |
1485 | static bool increase_address_space(struct protection_domain *domain, |
1486 | gfp_t gfp) | |
1487 | { | |
1488 | u64 *pte; | |
1489 | ||
1490 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1491 | /* address space already 64 bit large */ | |
1492 | return false; | |
1493 | ||
1494 | pte = (void *)get_zeroed_page(gfp); | |
1495 | if (!pte) | |
1496 | return false; | |
1497 | ||
1498 | *pte = PM_LEVEL_PDE(domain->mode, | |
1499 | virt_to_phys(domain->pt_root)); | |
1500 | domain->pt_root = pte; | |
1501 | domain->mode += 1; | |
1502 | domain->updated = true; | |
1503 | ||
1504 | return true; | |
1505 | } | |
1506 | ||
8bc3e127 | 1507 | static u64 *alloc_pte(struct protection_domain *domain, |
abdc5eb3 JR |
1508 | unsigned long address, |
1509 | int end_lvl, | |
1510 | u64 **pte_page, | |
1511 | gfp_t gfp) | |
8bda3092 JR |
1512 | { |
1513 | u64 *pte, *page; | |
8bc3e127 | 1514 | int level; |
8bda3092 | 1515 | |
8bc3e127 JR |
1516 | while (address > PM_LEVEL_SIZE(domain->mode)) |
1517 | increase_address_space(domain, gfp); | |
8bda3092 | 1518 | |
8bc3e127 JR |
1519 | level = domain->mode - 1; |
1520 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
8bda3092 | 1521 | |
abdc5eb3 | 1522 | while (level > end_lvl) { |
8bc3e127 JR |
1523 | if (!IOMMU_PTE_PRESENT(*pte)) { |
1524 | page = (u64 *)get_zeroed_page(gfp); | |
1525 | if (!page) | |
1526 | return NULL; | |
1527 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1528 | } | |
8bda3092 | 1529 | |
8bc3e127 | 1530 | level -= 1; |
8bda3092 | 1531 | |
8bc3e127 | 1532 | pte = IOMMU_PTE_PAGE(*pte); |
8bda3092 | 1533 | |
abdc5eb3 | 1534 | if (pte_page && level == end_lvl) |
8bc3e127 | 1535 | *pte_page = pte; |
8bda3092 | 1536 | |
8bc3e127 JR |
1537 | pte = &pte[PM_LEVEL_INDEX(level, address)]; |
1538 | } | |
8bda3092 JR |
1539 | |
1540 | return pte; | |
1541 | } | |
1542 | ||
1543 | /* | |
1544 | * This function fetches the PTE for a given address in the aperture | |
1545 | */ | |
1546 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1547 | unsigned long address) | |
1548 | { | |
384de729 | 1549 | struct aperture_range *aperture; |
8bda3092 JR |
1550 | u64 *pte, *pte_page; |
1551 | ||
384de729 JR |
1552 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1553 | if (!aperture) | |
1554 | return NULL; | |
1555 | ||
1556 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1557 | if (!pte) { |
abdc5eb3 JR |
1558 | pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page, |
1559 | GFP_ATOMIC); | |
384de729 JR |
1560 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1561 | } else | |
8c8c143c | 1562 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1563 | |
04bfdd84 | 1564 | update_domain(&dom->domain); |
8bda3092 JR |
1565 | |
1566 | return pte; | |
1567 | } | |
1568 | ||
431b2a20 JR |
1569 | /* |
1570 | * This is the generic map function. It maps one 4kb page at paddr to | |
1571 | * the given address in the DMA address space for the domain. | |
1572 | */ | |
cb76c322 JR |
1573 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1574 | struct dma_ops_domain *dom, | |
1575 | unsigned long address, | |
1576 | phys_addr_t paddr, | |
1577 | int direction) | |
1578 | { | |
1579 | u64 *pte, __pte; | |
1580 | ||
1581 | WARN_ON(address > dom->aperture_size); | |
1582 | ||
1583 | paddr &= PAGE_MASK; | |
1584 | ||
8bda3092 | 1585 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1586 | if (!pte) |
8fd524b3 | 1587 | return DMA_ERROR_CODE; |
cb76c322 JR |
1588 | |
1589 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1590 | ||
1591 | if (direction == DMA_TO_DEVICE) | |
1592 | __pte |= IOMMU_PTE_IR; | |
1593 | else if (direction == DMA_FROM_DEVICE) | |
1594 | __pte |= IOMMU_PTE_IW; | |
1595 | else if (direction == DMA_BIDIRECTIONAL) | |
1596 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1597 | ||
1598 | WARN_ON(*pte); | |
1599 | ||
1600 | *pte = __pte; | |
1601 | ||
1602 | return (dma_addr_t)address; | |
1603 | } | |
1604 | ||
431b2a20 JR |
1605 | /* |
1606 | * The generic unmapping function for on page in the DMA address space. | |
1607 | */ | |
cb76c322 JR |
1608 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1609 | struct dma_ops_domain *dom, | |
1610 | unsigned long address) | |
1611 | { | |
384de729 | 1612 | struct aperture_range *aperture; |
cb76c322 JR |
1613 | u64 *pte; |
1614 | ||
1615 | if (address >= dom->aperture_size) | |
1616 | return; | |
1617 | ||
384de729 JR |
1618 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1619 | if (!aperture) | |
1620 | return; | |
1621 | ||
1622 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1623 | if (!pte) | |
1624 | return; | |
cb76c322 | 1625 | |
8c8c143c | 1626 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1627 | |
1628 | WARN_ON(!*pte); | |
1629 | ||
1630 | *pte = 0ULL; | |
1631 | } | |
1632 | ||
431b2a20 JR |
1633 | /* |
1634 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1635 | * contiguous memory region into DMA address space. It is used by all |
1636 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1637 | * Must be called with the domain lock held. |
1638 | */ | |
cb76c322 JR |
1639 | static dma_addr_t __map_single(struct device *dev, |
1640 | struct amd_iommu *iommu, | |
1641 | struct dma_ops_domain *dma_dom, | |
1642 | phys_addr_t paddr, | |
1643 | size_t size, | |
6d4f343f | 1644 | int dir, |
832a90c3 JR |
1645 | bool align, |
1646 | u64 dma_mask) | |
cb76c322 JR |
1647 | { |
1648 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1649 | dma_addr_t address, start, ret; |
cb76c322 | 1650 | unsigned int pages; |
6d4f343f | 1651 | unsigned long align_mask = 0; |
cb76c322 JR |
1652 | int i; |
1653 | ||
e3c449f5 | 1654 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1655 | paddr &= PAGE_MASK; |
1656 | ||
8ecaf8f1 JR |
1657 | INC_STATS_COUNTER(total_map_requests); |
1658 | ||
c1858976 JR |
1659 | if (pages > 1) |
1660 | INC_STATS_COUNTER(cross_page); | |
1661 | ||
6d4f343f JR |
1662 | if (align) |
1663 | align_mask = (1UL << get_order(size)) - 1; | |
1664 | ||
11b83888 | 1665 | retry: |
832a90c3 JR |
1666 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1667 | dma_mask); | |
8fd524b3 | 1668 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1669 | /* |
1670 | * setting next_address here will let the address | |
1671 | * allocator only scan the new allocated range in the | |
1672 | * first run. This is a small optimization. | |
1673 | */ | |
1674 | dma_dom->next_address = dma_dom->aperture_size; | |
1675 | ||
1676 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1677 | goto out; | |
1678 | ||
1679 | /* | |
1680 | * aperture was sucessfully enlarged by 128 MB, try | |
1681 | * allocation again | |
1682 | */ | |
1683 | goto retry; | |
1684 | } | |
cb76c322 JR |
1685 | |
1686 | start = address; | |
1687 | for (i = 0; i < pages; ++i) { | |
53812c11 | 1688 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
8fd524b3 | 1689 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
1690 | goto out_unmap; |
1691 | ||
cb76c322 JR |
1692 | paddr += PAGE_SIZE; |
1693 | start += PAGE_SIZE; | |
1694 | } | |
1695 | address += offset; | |
1696 | ||
5774f7c5 JR |
1697 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1698 | ||
afa9fdc2 | 1699 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1700 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1701 | dma_dom->need_flush = false; | |
1702 | } else if (unlikely(iommu_has_npcache(iommu))) | |
6de8ad9b | 1703 | iommu_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 1704 | |
cb76c322 JR |
1705 | out: |
1706 | return address; | |
53812c11 JR |
1707 | |
1708 | out_unmap: | |
1709 | ||
1710 | for (--i; i >= 0; --i) { | |
1711 | start -= PAGE_SIZE; | |
1712 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1713 | } | |
1714 | ||
1715 | dma_ops_free_addresses(dma_dom, address, pages); | |
1716 | ||
8fd524b3 | 1717 | return DMA_ERROR_CODE; |
cb76c322 JR |
1718 | } |
1719 | ||
431b2a20 JR |
1720 | /* |
1721 | * Does the reverse of the __map_single function. Must be called with | |
1722 | * the domain lock held too | |
1723 | */ | |
cb76c322 JR |
1724 | static void __unmap_single(struct amd_iommu *iommu, |
1725 | struct dma_ops_domain *dma_dom, | |
1726 | dma_addr_t dma_addr, | |
1727 | size_t size, | |
1728 | int dir) | |
1729 | { | |
1730 | dma_addr_t i, start; | |
1731 | unsigned int pages; | |
1732 | ||
8fd524b3 | 1733 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 1734 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
1735 | return; |
1736 | ||
e3c449f5 | 1737 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1738 | dma_addr &= PAGE_MASK; |
1739 | start = dma_addr; | |
1740 | ||
1741 | for (i = 0; i < pages; ++i) { | |
1742 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1743 | start += PAGE_SIZE; | |
1744 | } | |
1745 | ||
5774f7c5 JR |
1746 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1747 | ||
cb76c322 | 1748 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1749 | |
80be308d | 1750 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
6de8ad9b | 1751 | iommu_flush_pages(&dma_dom->domain, dma_addr, size); |
80be308d JR |
1752 | dma_dom->need_flush = false; |
1753 | } | |
cb76c322 JR |
1754 | } |
1755 | ||
431b2a20 JR |
1756 | /* |
1757 | * The exported map_single function for dma_ops. | |
1758 | */ | |
51491367 FT |
1759 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1760 | unsigned long offset, size_t size, | |
1761 | enum dma_data_direction dir, | |
1762 | struct dma_attrs *attrs) | |
4da70b9e JR |
1763 | { |
1764 | unsigned long flags; | |
1765 | struct amd_iommu *iommu; | |
1766 | struct protection_domain *domain; | |
1767 | u16 devid; | |
1768 | dma_addr_t addr; | |
832a90c3 | 1769 | u64 dma_mask; |
51491367 | 1770 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1771 | |
0f2a86f2 JR |
1772 | INC_STATS_COUNTER(cnt_map_single); |
1773 | ||
dbcc112e | 1774 | if (!check_device(dev)) |
8fd524b3 | 1775 | return DMA_ERROR_CODE; |
dbcc112e | 1776 | |
832a90c3 | 1777 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1778 | |
1779 | get_device_resources(dev, &iommu, &domain, &devid); | |
1780 | ||
1781 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1782 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1783 | return (dma_addr_t)paddr; |
1784 | ||
5b28df6f | 1785 | if (!dma_ops_domain(domain)) |
8fd524b3 | 1786 | return DMA_ERROR_CODE; |
5b28df6f | 1787 | |
4da70b9e | 1788 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1789 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1790 | dma_mask); | |
8fd524b3 | 1791 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
1792 | goto out; |
1793 | ||
0518a3a4 | 1794 | iommu_flush_complete(domain); |
4da70b9e JR |
1795 | |
1796 | out: | |
1797 | spin_unlock_irqrestore(&domain->lock, flags); | |
1798 | ||
1799 | return addr; | |
1800 | } | |
1801 | ||
431b2a20 JR |
1802 | /* |
1803 | * The exported unmap_single function for dma_ops. | |
1804 | */ | |
51491367 FT |
1805 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1806 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1807 | { |
1808 | unsigned long flags; | |
1809 | struct amd_iommu *iommu; | |
1810 | struct protection_domain *domain; | |
1811 | u16 devid; | |
1812 | ||
146a6917 JR |
1813 | INC_STATS_COUNTER(cnt_unmap_single); |
1814 | ||
dbcc112e JR |
1815 | if (!check_device(dev) || |
1816 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1817 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1818 | return; |
1819 | ||
5b28df6f JR |
1820 | if (!dma_ops_domain(domain)) |
1821 | return; | |
1822 | ||
4da70b9e JR |
1823 | spin_lock_irqsave(&domain->lock, flags); |
1824 | ||
1825 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1826 | ||
0518a3a4 | 1827 | iommu_flush_complete(domain); |
4da70b9e JR |
1828 | |
1829 | spin_unlock_irqrestore(&domain->lock, flags); | |
1830 | } | |
1831 | ||
431b2a20 JR |
1832 | /* |
1833 | * This is a special map_sg function which is used if we should map a | |
1834 | * device which is not handled by an AMD IOMMU in the system. | |
1835 | */ | |
65b050ad JR |
1836 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1837 | int nelems, int dir) | |
1838 | { | |
1839 | struct scatterlist *s; | |
1840 | int i; | |
1841 | ||
1842 | for_each_sg(sglist, s, nelems, i) { | |
1843 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1844 | s->dma_length = s->length; | |
1845 | } | |
1846 | ||
1847 | return nelems; | |
1848 | } | |
1849 | ||
431b2a20 JR |
1850 | /* |
1851 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1852 | * lists). | |
1853 | */ | |
65b050ad | 1854 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1855 | int nelems, enum dma_data_direction dir, |
1856 | struct dma_attrs *attrs) | |
65b050ad JR |
1857 | { |
1858 | unsigned long flags; | |
1859 | struct amd_iommu *iommu; | |
1860 | struct protection_domain *domain; | |
1861 | u16 devid; | |
1862 | int i; | |
1863 | struct scatterlist *s; | |
1864 | phys_addr_t paddr; | |
1865 | int mapped_elems = 0; | |
832a90c3 | 1866 | u64 dma_mask; |
65b050ad | 1867 | |
d03f067a JR |
1868 | INC_STATS_COUNTER(cnt_map_sg); |
1869 | ||
dbcc112e JR |
1870 | if (!check_device(dev)) |
1871 | return 0; | |
1872 | ||
832a90c3 | 1873 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1874 | |
1875 | get_device_resources(dev, &iommu, &domain, &devid); | |
1876 | ||
1877 | if (!iommu || !domain) | |
1878 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1879 | ||
5b28df6f JR |
1880 | if (!dma_ops_domain(domain)) |
1881 | return 0; | |
1882 | ||
65b050ad JR |
1883 | spin_lock_irqsave(&domain->lock, flags); |
1884 | ||
1885 | for_each_sg(sglist, s, nelems, i) { | |
1886 | paddr = sg_phys(s); | |
1887 | ||
1888 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1889 | paddr, s->length, dir, false, |
1890 | dma_mask); | |
65b050ad JR |
1891 | |
1892 | if (s->dma_address) { | |
1893 | s->dma_length = s->length; | |
1894 | mapped_elems++; | |
1895 | } else | |
1896 | goto unmap; | |
65b050ad JR |
1897 | } |
1898 | ||
0518a3a4 | 1899 | iommu_flush_complete(domain); |
65b050ad JR |
1900 | |
1901 | out: | |
1902 | spin_unlock_irqrestore(&domain->lock, flags); | |
1903 | ||
1904 | return mapped_elems; | |
1905 | unmap: | |
1906 | for_each_sg(sglist, s, mapped_elems, i) { | |
1907 | if (s->dma_address) | |
1908 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1909 | s->dma_length, dir); | |
1910 | s->dma_address = s->dma_length = 0; | |
1911 | } | |
1912 | ||
1913 | mapped_elems = 0; | |
1914 | ||
1915 | goto out; | |
1916 | } | |
1917 | ||
431b2a20 JR |
1918 | /* |
1919 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1920 | * lists). | |
1921 | */ | |
65b050ad | 1922 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1923 | int nelems, enum dma_data_direction dir, |
1924 | struct dma_attrs *attrs) | |
65b050ad JR |
1925 | { |
1926 | unsigned long flags; | |
1927 | struct amd_iommu *iommu; | |
1928 | struct protection_domain *domain; | |
1929 | struct scatterlist *s; | |
1930 | u16 devid; | |
1931 | int i; | |
1932 | ||
55877a6b JR |
1933 | INC_STATS_COUNTER(cnt_unmap_sg); |
1934 | ||
dbcc112e JR |
1935 | if (!check_device(dev) || |
1936 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1937 | return; |
1938 | ||
5b28df6f JR |
1939 | if (!dma_ops_domain(domain)) |
1940 | return; | |
1941 | ||
65b050ad JR |
1942 | spin_lock_irqsave(&domain->lock, flags); |
1943 | ||
1944 | for_each_sg(sglist, s, nelems, i) { | |
1945 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1946 | s->dma_length, dir); | |
65b050ad JR |
1947 | s->dma_address = s->dma_length = 0; |
1948 | } | |
1949 | ||
0518a3a4 | 1950 | iommu_flush_complete(domain); |
65b050ad JR |
1951 | |
1952 | spin_unlock_irqrestore(&domain->lock, flags); | |
1953 | } | |
1954 | ||
431b2a20 JR |
1955 | /* |
1956 | * The exported alloc_coherent function for dma_ops. | |
1957 | */ | |
5d8b53cf JR |
1958 | static void *alloc_coherent(struct device *dev, size_t size, |
1959 | dma_addr_t *dma_addr, gfp_t flag) | |
1960 | { | |
1961 | unsigned long flags; | |
1962 | void *virt_addr; | |
1963 | struct amd_iommu *iommu; | |
1964 | struct protection_domain *domain; | |
1965 | u16 devid; | |
1966 | phys_addr_t paddr; | |
832a90c3 | 1967 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1968 | |
c8f0fb36 JR |
1969 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1970 | ||
dbcc112e JR |
1971 | if (!check_device(dev)) |
1972 | return NULL; | |
5d8b53cf | 1973 | |
13d9fead FT |
1974 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1975 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1976 | |
c97ac535 | 1977 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1978 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1979 | if (!virt_addr) | |
b25ae679 | 1980 | return NULL; |
5d8b53cf | 1981 | |
5d8b53cf JR |
1982 | paddr = virt_to_phys(virt_addr); |
1983 | ||
5d8b53cf JR |
1984 | if (!iommu || !domain) { |
1985 | *dma_addr = (dma_addr_t)paddr; | |
1986 | return virt_addr; | |
1987 | } | |
1988 | ||
5b28df6f JR |
1989 | if (!dma_ops_domain(domain)) |
1990 | goto out_free; | |
1991 | ||
832a90c3 JR |
1992 | if (!dma_mask) |
1993 | dma_mask = *dev->dma_mask; | |
1994 | ||
5d8b53cf JR |
1995 | spin_lock_irqsave(&domain->lock, flags); |
1996 | ||
1997 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1998 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1999 | |
8fd524b3 | 2000 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2001 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2002 | goto out_free; |
367d04c4 | 2003 | } |
5d8b53cf | 2004 | |
0518a3a4 | 2005 | iommu_flush_complete(domain); |
5d8b53cf | 2006 | |
5d8b53cf JR |
2007 | spin_unlock_irqrestore(&domain->lock, flags); |
2008 | ||
2009 | return virt_addr; | |
5b28df6f JR |
2010 | |
2011 | out_free: | |
2012 | ||
2013 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2014 | ||
2015 | return NULL; | |
5d8b53cf JR |
2016 | } |
2017 | ||
431b2a20 JR |
2018 | /* |
2019 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2020 | */ |
5d8b53cf JR |
2021 | static void free_coherent(struct device *dev, size_t size, |
2022 | void *virt_addr, dma_addr_t dma_addr) | |
2023 | { | |
2024 | unsigned long flags; | |
2025 | struct amd_iommu *iommu; | |
2026 | struct protection_domain *domain; | |
2027 | u16 devid; | |
2028 | ||
5d31ee7e JR |
2029 | INC_STATS_COUNTER(cnt_free_coherent); |
2030 | ||
dbcc112e JR |
2031 | if (!check_device(dev)) |
2032 | return; | |
2033 | ||
5d8b53cf JR |
2034 | get_device_resources(dev, &iommu, &domain, &devid); |
2035 | ||
2036 | if (!iommu || !domain) | |
2037 | goto free_mem; | |
2038 | ||
5b28df6f JR |
2039 | if (!dma_ops_domain(domain)) |
2040 | goto free_mem; | |
2041 | ||
5d8b53cf JR |
2042 | spin_lock_irqsave(&domain->lock, flags); |
2043 | ||
2044 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 2045 | |
0518a3a4 | 2046 | iommu_flush_complete(domain); |
5d8b53cf JR |
2047 | |
2048 | spin_unlock_irqrestore(&domain->lock, flags); | |
2049 | ||
2050 | free_mem: | |
2051 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2052 | } | |
2053 | ||
b39ba6ad JR |
2054 | /* |
2055 | * This function is called by the DMA layer to find out if we can handle a | |
2056 | * particular device. It is part of the dma_ops. | |
2057 | */ | |
2058 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2059 | { | |
2060 | u16 bdf; | |
2061 | struct pci_dev *pcidev; | |
2062 | ||
2063 | /* No device or no PCI device */ | |
2064 | if (!dev || dev->bus != &pci_bus_type) | |
2065 | return 0; | |
2066 | ||
2067 | pcidev = to_pci_dev(dev); | |
2068 | ||
2069 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
2070 | ||
2071 | /* Out of our scope? */ | |
2072 | if (bdf > amd_iommu_last_bdf) | |
2073 | return 0; | |
2074 | ||
2075 | return 1; | |
2076 | } | |
2077 | ||
c432f3df | 2078 | /* |
431b2a20 JR |
2079 | * The function for pre-allocating protection domains. |
2080 | * | |
c432f3df JR |
2081 | * If the driver core informs the DMA layer if a driver grabs a device |
2082 | * we don't need to preallocate the protection domains anymore. | |
2083 | * For now we have to. | |
2084 | */ | |
0e93dd88 | 2085 | static void prealloc_protection_domains(void) |
c432f3df JR |
2086 | { |
2087 | struct pci_dev *dev = NULL; | |
2088 | struct dma_ops_domain *dma_dom; | |
2089 | struct amd_iommu *iommu; | |
be831297 | 2090 | u16 devid, __devid; |
c432f3df JR |
2091 | |
2092 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
be831297 | 2093 | __devid = devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 2094 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
2095 | continue; |
2096 | devid = amd_iommu_alias_table[devid]; | |
2097 | if (domain_for_device(devid)) | |
2098 | continue; | |
2099 | iommu = amd_iommu_rlookup_table[devid]; | |
2100 | if (!iommu) | |
2101 | continue; | |
d9cfed92 | 2102 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
2103 | if (!dma_dom) |
2104 | continue; | |
2105 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2106 | dma_dom->target_dev = devid; |
2107 | ||
be831297 JR |
2108 | attach_device(iommu, &dma_dom->domain, devid); |
2109 | if (__devid != devid) | |
2110 | attach_device(iommu, &dma_dom->domain, __devid); | |
2111 | ||
bd60b735 | 2112 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2113 | } |
2114 | } | |
2115 | ||
160c1d8e | 2116 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2117 | .alloc_coherent = alloc_coherent, |
2118 | .free_coherent = free_coherent, | |
51491367 FT |
2119 | .map_page = map_page, |
2120 | .unmap_page = unmap_page, | |
6631ee9d JR |
2121 | .map_sg = map_sg, |
2122 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2123 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2124 | }; |
2125 | ||
431b2a20 JR |
2126 | /* |
2127 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2128 | */ | |
6631ee9d JR |
2129 | int __init amd_iommu_init_dma_ops(void) |
2130 | { | |
2131 | struct amd_iommu *iommu; | |
6631ee9d JR |
2132 | int ret; |
2133 | ||
431b2a20 JR |
2134 | /* |
2135 | * first allocate a default protection domain for every IOMMU we | |
2136 | * found in the system. Devices not assigned to any other | |
2137 | * protection domain will be assigned to the default one. | |
2138 | */ | |
3bd22172 | 2139 | for_each_iommu(iommu) { |
d9cfed92 | 2140 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
2141 | if (iommu->default_dom == NULL) |
2142 | return -ENOMEM; | |
e2dc14a2 | 2143 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2144 | ret = iommu_init_unity_mappings(iommu); |
2145 | if (ret) | |
2146 | goto free_domains; | |
2147 | } | |
2148 | ||
431b2a20 JR |
2149 | /* |
2150 | * If device isolation is enabled, pre-allocate the protection | |
2151 | * domains for each device. | |
2152 | */ | |
6631ee9d JR |
2153 | if (amd_iommu_isolate) |
2154 | prealloc_protection_domains(); | |
2155 | ||
2156 | iommu_detected = 1; | |
75f1cdf1 | 2157 | swiotlb = 0; |
92af4e29 | 2158 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
2159 | gart_iommu_aperture_disabled = 1; |
2160 | gart_iommu_aperture = 0; | |
92af4e29 | 2161 | #endif |
6631ee9d | 2162 | |
431b2a20 | 2163 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2164 | dma_ops = &amd_iommu_dma_ops; |
2165 | ||
26961efe | 2166 | register_iommu(&amd_iommu_ops); |
26961efe | 2167 | |
e275a2a0 JR |
2168 | bus_register_notifier(&pci_bus_type, &device_nb); |
2169 | ||
7f26508b JR |
2170 | amd_iommu_stats_init(); |
2171 | ||
6631ee9d JR |
2172 | return 0; |
2173 | ||
2174 | free_domains: | |
2175 | ||
3bd22172 | 2176 | for_each_iommu(iommu) { |
6631ee9d JR |
2177 | if (iommu->default_dom) |
2178 | dma_ops_domain_free(iommu->default_dom); | |
2179 | } | |
2180 | ||
2181 | return ret; | |
2182 | } | |
6d98cd80 JR |
2183 | |
2184 | /***************************************************************************** | |
2185 | * | |
2186 | * The following functions belong to the exported interface of AMD IOMMU | |
2187 | * | |
2188 | * This interface allows access to lower level functions of the IOMMU | |
2189 | * like protection domain handling and assignement of devices to domains | |
2190 | * which is not possible with the dma_ops interface. | |
2191 | * | |
2192 | *****************************************************************************/ | |
2193 | ||
6d98cd80 JR |
2194 | static void cleanup_domain(struct protection_domain *domain) |
2195 | { | |
2196 | unsigned long flags; | |
2197 | u16 devid; | |
2198 | ||
2199 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2200 | ||
2201 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
2202 | if (amd_iommu_pd_table[devid] == domain) | |
2203 | __detach_device(domain, devid); | |
2204 | ||
2205 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2206 | } | |
2207 | ||
2650815f JR |
2208 | static void protection_domain_free(struct protection_domain *domain) |
2209 | { | |
2210 | if (!domain) | |
2211 | return; | |
2212 | ||
2213 | if (domain->id) | |
2214 | domain_id_free(domain->id); | |
2215 | ||
2216 | kfree(domain); | |
2217 | } | |
2218 | ||
2219 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2220 | { |
2221 | struct protection_domain *domain; | |
2222 | ||
2223 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2224 | if (!domain) | |
2650815f | 2225 | return NULL; |
c156e347 JR |
2226 | |
2227 | spin_lock_init(&domain->lock); | |
c156e347 JR |
2228 | domain->id = domain_id_alloc(); |
2229 | if (!domain->id) | |
2650815f JR |
2230 | goto out_err; |
2231 | ||
2232 | return domain; | |
2233 | ||
2234 | out_err: | |
2235 | kfree(domain); | |
2236 | ||
2237 | return NULL; | |
2238 | } | |
2239 | ||
2240 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2241 | { | |
2242 | struct protection_domain *domain; | |
2243 | ||
2244 | domain = protection_domain_alloc(); | |
2245 | if (!domain) | |
c156e347 | 2246 | goto out_free; |
2650815f JR |
2247 | |
2248 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2249 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2250 | if (!domain->pt_root) | |
2251 | goto out_free; | |
2252 | ||
2253 | dom->priv = domain; | |
2254 | ||
2255 | return 0; | |
2256 | ||
2257 | out_free: | |
2650815f | 2258 | protection_domain_free(domain); |
c156e347 JR |
2259 | |
2260 | return -ENOMEM; | |
2261 | } | |
2262 | ||
98383fc3 JR |
2263 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2264 | { | |
2265 | struct protection_domain *domain = dom->priv; | |
2266 | ||
2267 | if (!domain) | |
2268 | return; | |
2269 | ||
2270 | if (domain->dev_cnt > 0) | |
2271 | cleanup_domain(domain); | |
2272 | ||
2273 | BUG_ON(domain->dev_cnt != 0); | |
2274 | ||
2275 | free_pagetable(domain); | |
2276 | ||
2277 | domain_id_free(domain->id); | |
2278 | ||
2279 | kfree(domain); | |
2280 | ||
2281 | dom->priv = NULL; | |
2282 | } | |
2283 | ||
684f2888 JR |
2284 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2285 | struct device *dev) | |
2286 | { | |
2287 | struct protection_domain *domain = dom->priv; | |
2288 | struct amd_iommu *iommu; | |
2289 | struct pci_dev *pdev; | |
2290 | u16 devid; | |
2291 | ||
2292 | if (dev->bus != &pci_bus_type) | |
2293 | return; | |
2294 | ||
2295 | pdev = to_pci_dev(dev); | |
2296 | ||
2297 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2298 | ||
2299 | if (devid > 0) | |
2300 | detach_device(domain, devid); | |
2301 | ||
2302 | iommu = amd_iommu_rlookup_table[devid]; | |
2303 | if (!iommu) | |
2304 | return; | |
2305 | ||
2306 | iommu_queue_inv_dev_entry(iommu, devid); | |
2307 | iommu_completion_wait(iommu); | |
2308 | } | |
2309 | ||
01106066 JR |
2310 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2311 | struct device *dev) | |
2312 | { | |
2313 | struct protection_domain *domain = dom->priv; | |
2314 | struct protection_domain *old_domain; | |
2315 | struct amd_iommu *iommu; | |
2316 | struct pci_dev *pdev; | |
2317 | u16 devid; | |
2318 | ||
2319 | if (dev->bus != &pci_bus_type) | |
2320 | return -EINVAL; | |
2321 | ||
2322 | pdev = to_pci_dev(dev); | |
2323 | ||
2324 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2325 | ||
2326 | if (devid >= amd_iommu_last_bdf || | |
2327 | devid != amd_iommu_alias_table[devid]) | |
2328 | return -EINVAL; | |
2329 | ||
2330 | iommu = amd_iommu_rlookup_table[devid]; | |
2331 | if (!iommu) | |
2332 | return -EINVAL; | |
2333 | ||
2334 | old_domain = domain_for_device(devid); | |
2335 | if (old_domain) | |
71ff3bca | 2336 | detach_device(old_domain, devid); |
01106066 JR |
2337 | |
2338 | attach_device(iommu, domain, devid); | |
2339 | ||
2340 | iommu_completion_wait(iommu); | |
2341 | ||
2342 | return 0; | |
2343 | } | |
2344 | ||
c6229ca6 JR |
2345 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2346 | unsigned long iova, phys_addr_t paddr, | |
2347 | size_t size, int iommu_prot) | |
2348 | { | |
2349 | struct protection_domain *domain = dom->priv; | |
2350 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2351 | int prot = 0; | |
2352 | int ret; | |
2353 | ||
2354 | if (iommu_prot & IOMMU_READ) | |
2355 | prot |= IOMMU_PROT_IR; | |
2356 | if (iommu_prot & IOMMU_WRITE) | |
2357 | prot |= IOMMU_PROT_IW; | |
2358 | ||
2359 | iova &= PAGE_MASK; | |
2360 | paddr &= PAGE_MASK; | |
2361 | ||
2362 | for (i = 0; i < npages; ++i) { | |
abdc5eb3 | 2363 | ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k); |
c6229ca6 JR |
2364 | if (ret) |
2365 | return ret; | |
2366 | ||
2367 | iova += PAGE_SIZE; | |
2368 | paddr += PAGE_SIZE; | |
2369 | } | |
2370 | ||
2371 | return 0; | |
2372 | } | |
2373 | ||
eb74ff6c JR |
2374 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2375 | unsigned long iova, size_t size) | |
2376 | { | |
2377 | ||
2378 | struct protection_domain *domain = dom->priv; | |
2379 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2380 | ||
2381 | iova &= PAGE_MASK; | |
2382 | ||
2383 | for (i = 0; i < npages; ++i) { | |
a6b256b4 | 2384 | iommu_unmap_page(domain, iova, PM_MAP_4k); |
eb74ff6c JR |
2385 | iova += PAGE_SIZE; |
2386 | } | |
2387 | ||
2388 | iommu_flush_domain(domain->id); | |
2389 | } | |
2390 | ||
645c4c8d JR |
2391 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2392 | unsigned long iova) | |
2393 | { | |
2394 | struct protection_domain *domain = dom->priv; | |
2395 | unsigned long offset = iova & ~PAGE_MASK; | |
2396 | phys_addr_t paddr; | |
2397 | u64 *pte; | |
2398 | ||
a6b256b4 | 2399 | pte = fetch_pte(domain, iova, PM_MAP_4k); |
645c4c8d | 2400 | |
a6d41a40 | 2401 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2402 | return 0; |
2403 | ||
2404 | paddr = *pte & IOMMU_PAGE_MASK; | |
2405 | paddr |= offset; | |
2406 | ||
2407 | return paddr; | |
2408 | } | |
2409 | ||
dbb9fd86 SY |
2410 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2411 | unsigned long cap) | |
2412 | { | |
2413 | return 0; | |
2414 | } | |
2415 | ||
26961efe JR |
2416 | static struct iommu_ops amd_iommu_ops = { |
2417 | .domain_init = amd_iommu_domain_init, | |
2418 | .domain_destroy = amd_iommu_domain_destroy, | |
2419 | .attach_dev = amd_iommu_attach_device, | |
2420 | .detach_dev = amd_iommu_detach_device, | |
2421 | .map = amd_iommu_map_range, | |
2422 | .unmap = amd_iommu_unmap_range, | |
2423 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2424 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2425 | }; |
2426 | ||
0feae533 JR |
2427 | /***************************************************************************** |
2428 | * | |
2429 | * The next functions do a basic initialization of IOMMU for pass through | |
2430 | * mode | |
2431 | * | |
2432 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2433 | * DMA-API translation. | |
2434 | * | |
2435 | *****************************************************************************/ | |
2436 | ||
2437 | int __init amd_iommu_init_passthrough(void) | |
2438 | { | |
2439 | struct pci_dev *dev = NULL; | |
2440 | u16 devid, devid2; | |
2441 | ||
2442 | /* allocate passthroug domain */ | |
2443 | pt_domain = protection_domain_alloc(); | |
2444 | if (!pt_domain) | |
2445 | return -ENOMEM; | |
2446 | ||
2447 | pt_domain->mode |= PAGE_MODE_NONE; | |
2448 | ||
2449 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
2450 | struct amd_iommu *iommu; | |
2451 | ||
2452 | devid = calc_devid(dev->bus->number, dev->devfn); | |
2453 | if (devid > amd_iommu_last_bdf) | |
2454 | continue; | |
2455 | ||
2456 | devid2 = amd_iommu_alias_table[devid]; | |
2457 | ||
2458 | iommu = amd_iommu_rlookup_table[devid2]; | |
2459 | if (!iommu) | |
2460 | continue; | |
2461 | ||
2462 | __attach_device(iommu, pt_domain, devid); | |
2463 | __attach_device(iommu, pt_domain, devid2); | |
2464 | } | |
2465 | ||
2466 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2467 | ||
2468 | return 0; | |
2469 | } |