Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
bf3118c1 | 2 | * Copyright (C) 2007-2009 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
6a9401a7 | 31 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
0feae533 JR |
45 | /* |
46 | * Domain for untranslated devices - only allocated | |
47 | * if iommu=pt passed on kernel cmd line. | |
48 | */ | |
49 | static struct protection_domain *pt_domain; | |
50 | ||
26961efe | 51 | static struct iommu_ops amd_iommu_ops; |
26961efe | 52 | |
431b2a20 JR |
53 | /* |
54 | * general struct to manage commands send to an IOMMU | |
55 | */ | |
d6449536 | 56 | struct iommu_cmd { |
b6c02715 JR |
57 | u32 data[4]; |
58 | }; | |
59 | ||
a345b23b | 60 | static void reset_iommu_command_buffer(struct amd_iommu *iommu); |
04bfdd84 | 61 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 62 | |
15898bbc JR |
63 | /**************************************************************************** |
64 | * | |
65 | * Helper functions | |
66 | * | |
67 | ****************************************************************************/ | |
68 | ||
69 | static inline u16 get_device_id(struct device *dev) | |
70 | { | |
71 | struct pci_dev *pdev = to_pci_dev(dev); | |
72 | ||
73 | return calc_devid(pdev->bus->number, pdev->devfn); | |
74 | } | |
75 | ||
71c70984 JR |
76 | /* |
77 | * In this function the list of preallocated protection domains is traversed to | |
78 | * find the domain for a specific device | |
79 | */ | |
80 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
81 | { | |
82 | struct dma_ops_domain *entry, *ret = NULL; | |
83 | unsigned long flags; | |
84 | u16 alias = amd_iommu_alias_table[devid]; | |
85 | ||
86 | if (list_empty(&iommu_pd_list)) | |
87 | return NULL; | |
88 | ||
89 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
90 | ||
91 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
92 | if (entry->target_dev == devid || | |
93 | entry->target_dev == alias) { | |
94 | ret = entry; | |
95 | break; | |
96 | } | |
97 | } | |
98 | ||
99 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
100 | ||
101 | return ret; | |
102 | } | |
103 | ||
98fc5a69 JR |
104 | /* |
105 | * This function checks if the driver got a valid device from the caller to | |
106 | * avoid dereferencing invalid pointers. | |
107 | */ | |
108 | static bool check_device(struct device *dev) | |
109 | { | |
110 | u16 devid; | |
111 | ||
112 | if (!dev || !dev->dma_mask) | |
113 | return false; | |
114 | ||
115 | /* No device or no PCI device */ | |
116 | if (!dev || dev->bus != &pci_bus_type) | |
117 | return false; | |
118 | ||
119 | devid = get_device_id(dev); | |
120 | ||
121 | /* Out of our scope? */ | |
122 | if (devid > amd_iommu_last_bdf) | |
123 | return false; | |
124 | ||
125 | if (amd_iommu_rlookup_table[devid] == NULL) | |
126 | return false; | |
127 | ||
128 | return true; | |
129 | } | |
130 | ||
7f26508b JR |
131 | #ifdef CONFIG_AMD_IOMMU_STATS |
132 | ||
133 | /* | |
134 | * Initialization code for statistics collection | |
135 | */ | |
136 | ||
da49f6df | 137 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 138 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 139 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 140 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 141 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 142 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 143 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 144 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 145 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 146 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 147 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 148 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 149 | |
7f26508b | 150 | static struct dentry *stats_dir; |
7f26508b JR |
151 | static struct dentry *de_fflush; |
152 | ||
153 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
154 | { | |
155 | if (stats_dir == NULL) | |
156 | return; | |
157 | ||
158 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
159 | &cnt->value); | |
160 | } | |
161 | ||
162 | static void amd_iommu_stats_init(void) | |
163 | { | |
164 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
165 | if (stats_dir == NULL) | |
166 | return; | |
167 | ||
7f26508b JR |
168 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
169 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
170 | |
171 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 172 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 173 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 174 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 175 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 176 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 177 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 178 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 179 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 180 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 181 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 182 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
183 | } |
184 | ||
185 | #endif | |
186 | ||
a80dc3e0 JR |
187 | /**************************************************************************** |
188 | * | |
189 | * Interrupt handling functions | |
190 | * | |
191 | ****************************************************************************/ | |
192 | ||
e3e59876 JR |
193 | static void dump_dte_entry(u16 devid) |
194 | { | |
195 | int i; | |
196 | ||
197 | for (i = 0; i < 8; ++i) | |
198 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
199 | amd_iommu_dev_table[devid].data[i]); | |
200 | } | |
201 | ||
945b4ac4 JR |
202 | static void dump_command(unsigned long phys_addr) |
203 | { | |
204 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
205 | int i; | |
206 | ||
207 | for (i = 0; i < 4; ++i) | |
208 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
209 | } | |
210 | ||
a345b23b | 211 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
212 | { |
213 | u32 *event = __evt; | |
214 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
215 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
216 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
217 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
218 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
219 | ||
4c6f40d4 | 220 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
221 | |
222 | switch (type) { | |
223 | case EVENT_TYPE_ILL_DEV: | |
224 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
225 | "address=0x%016llx flags=0x%04x]\n", | |
226 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
227 | address, flags); | |
e3e59876 | 228 | dump_dte_entry(devid); |
90008ee4 JR |
229 | break; |
230 | case EVENT_TYPE_IO_FAULT: | |
231 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
232 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
233 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
234 | domid, address, flags); | |
235 | break; | |
236 | case EVENT_TYPE_DEV_TAB_ERR: | |
237 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
238 | "address=0x%016llx flags=0x%04x]\n", | |
239 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
240 | address, flags); | |
241 | break; | |
242 | case EVENT_TYPE_PAGE_TAB_ERR: | |
243 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
244 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
245 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
246 | domid, address, flags); | |
247 | break; | |
248 | case EVENT_TYPE_ILL_CMD: | |
249 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
a345b23b | 250 | reset_iommu_command_buffer(iommu); |
945b4ac4 | 251 | dump_command(address); |
90008ee4 JR |
252 | break; |
253 | case EVENT_TYPE_CMD_HARD_ERR: | |
254 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
255 | "flags=0x%04x]\n", address, flags); | |
256 | break; | |
257 | case EVENT_TYPE_IOTLB_INV_TO: | |
258 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
259 | "address=0x%016llx]\n", | |
260 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
261 | address); | |
262 | break; | |
263 | case EVENT_TYPE_INV_DEV_REQ: | |
264 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
265 | "address=0x%016llx flags=0x%04x]\n", | |
266 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
267 | address, flags); | |
268 | break; | |
269 | default: | |
270 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
271 | } | |
272 | } | |
273 | ||
274 | static void iommu_poll_events(struct amd_iommu *iommu) | |
275 | { | |
276 | u32 head, tail; | |
277 | unsigned long flags; | |
278 | ||
279 | spin_lock_irqsave(&iommu->lock, flags); | |
280 | ||
281 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
282 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
283 | ||
284 | while (head != tail) { | |
a345b23b | 285 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
286 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
287 | } | |
288 | ||
289 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
290 | ||
291 | spin_unlock_irqrestore(&iommu->lock, flags); | |
292 | } | |
293 | ||
a80dc3e0 JR |
294 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
295 | { | |
90008ee4 JR |
296 | struct amd_iommu *iommu; |
297 | ||
3bd22172 | 298 | for_each_iommu(iommu) |
90008ee4 JR |
299 | iommu_poll_events(iommu); |
300 | ||
301 | return IRQ_HANDLED; | |
a80dc3e0 JR |
302 | } |
303 | ||
431b2a20 JR |
304 | /**************************************************************************** |
305 | * | |
306 | * IOMMU command queuing functions | |
307 | * | |
308 | ****************************************************************************/ | |
309 | ||
310 | /* | |
311 | * Writes the command to the IOMMUs command buffer and informs the | |
312 | * hardware about the new command. Must be called with iommu->lock held. | |
313 | */ | |
d6449536 | 314 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
315 | { |
316 | u32 tail, head; | |
317 | u8 *target; | |
318 | ||
319 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 320 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
321 | memcpy_toio(target, cmd, sizeof(*cmd)); |
322 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
323 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
324 | if (tail == head) | |
325 | return -ENOMEM; | |
326 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
431b2a20 JR |
331 | /* |
332 | * General queuing function for commands. Takes iommu->lock and calls | |
333 | * __iommu_queue_command(). | |
334 | */ | |
d6449536 | 335 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
336 | { |
337 | unsigned long flags; | |
338 | int ret; | |
339 | ||
340 | spin_lock_irqsave(&iommu->lock, flags); | |
341 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 342 | if (!ret) |
0cfd7aa9 | 343 | iommu->need_sync = true; |
a19ae1ec JR |
344 | spin_unlock_irqrestore(&iommu->lock, flags); |
345 | ||
346 | return ret; | |
347 | } | |
348 | ||
8d201968 JR |
349 | /* |
350 | * This function waits until an IOMMU has completed a completion | |
351 | * wait command | |
352 | */ | |
353 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
354 | { | |
355 | int ready = 0; | |
356 | unsigned status = 0; | |
357 | unsigned long i = 0; | |
358 | ||
da49f6df JR |
359 | INC_STATS_COUNTER(compl_wait); |
360 | ||
8d201968 JR |
361 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
362 | ++i; | |
363 | /* wait for the bit to become one */ | |
364 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
365 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
366 | } | |
367 | ||
368 | /* set bit back to zero */ | |
369 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
370 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
371 | ||
6a1eddd2 JR |
372 | if (unlikely(i == EXIT_LOOP_COUNT)) { |
373 | spin_unlock(&iommu->lock); | |
374 | reset_iommu_command_buffer(iommu); | |
375 | spin_lock(&iommu->lock); | |
376 | } | |
8d201968 JR |
377 | } |
378 | ||
379 | /* | |
380 | * This function queues a completion wait command into the command | |
381 | * buffer of an IOMMU | |
382 | */ | |
383 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
384 | { | |
385 | struct iommu_cmd cmd; | |
386 | ||
387 | memset(&cmd, 0, sizeof(cmd)); | |
388 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
389 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
390 | ||
391 | return __iommu_queue_command(iommu, &cmd); | |
392 | } | |
393 | ||
431b2a20 JR |
394 | /* |
395 | * This function is called whenever we need to ensure that the IOMMU has | |
396 | * completed execution of all commands we sent. It sends a | |
397 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
398 | * us about that by writing a value to a physical address we pass with | |
399 | * the command. | |
400 | */ | |
a19ae1ec JR |
401 | static int iommu_completion_wait(struct amd_iommu *iommu) |
402 | { | |
8d201968 JR |
403 | int ret = 0; |
404 | unsigned long flags; | |
a19ae1ec | 405 | |
7e4f88da JR |
406 | spin_lock_irqsave(&iommu->lock, flags); |
407 | ||
09ee17eb JR |
408 | if (!iommu->need_sync) |
409 | goto out; | |
410 | ||
8d201968 | 411 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 412 | |
0cfd7aa9 | 413 | iommu->need_sync = false; |
a19ae1ec JR |
414 | |
415 | if (ret) | |
7e4f88da | 416 | goto out; |
a19ae1ec | 417 | |
8d201968 | 418 | __iommu_wait_for_completion(iommu); |
84df8175 | 419 | |
7e4f88da JR |
420 | out: |
421 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
422 | |
423 | return 0; | |
424 | } | |
425 | ||
0518a3a4 JR |
426 | static void iommu_flush_complete(struct protection_domain *domain) |
427 | { | |
428 | int i; | |
429 | ||
430 | for (i = 0; i < amd_iommus_present; ++i) { | |
431 | if (!domain->dev_iommu[i]) | |
432 | continue; | |
433 | ||
434 | /* | |
435 | * Devices of this domain are behind this IOMMU | |
436 | * We need to wait for completion of all commands. | |
437 | */ | |
438 | iommu_completion_wait(amd_iommus[i]); | |
439 | } | |
440 | } | |
441 | ||
431b2a20 JR |
442 | /* |
443 | * Command send function for invalidating a device table entry | |
444 | */ | |
a19ae1ec JR |
445 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
446 | { | |
d6449536 | 447 | struct iommu_cmd cmd; |
ee2fa743 | 448 | int ret; |
a19ae1ec JR |
449 | |
450 | BUG_ON(iommu == NULL); | |
451 | ||
452 | memset(&cmd, 0, sizeof(cmd)); | |
453 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
454 | cmd.data[0] = devid; | |
455 | ||
ee2fa743 JR |
456 | ret = iommu_queue_command(iommu, &cmd); |
457 | ||
ee2fa743 | 458 | return ret; |
a19ae1ec JR |
459 | } |
460 | ||
237b6f33 JR |
461 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
462 | u16 domid, int pde, int s) | |
463 | { | |
464 | memset(cmd, 0, sizeof(*cmd)); | |
465 | address &= PAGE_MASK; | |
466 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
467 | cmd->data[1] |= domid; | |
468 | cmd->data[2] = lower_32_bits(address); | |
469 | cmd->data[3] = upper_32_bits(address); | |
470 | if (s) /* size bit - we flush more than one 4kb page */ | |
471 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
472 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
473 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
474 | } | |
475 | ||
431b2a20 JR |
476 | /* |
477 | * Generic command send function for invalidaing TLB entries | |
478 | */ | |
a19ae1ec JR |
479 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
480 | u64 address, u16 domid, int pde, int s) | |
481 | { | |
d6449536 | 482 | struct iommu_cmd cmd; |
ee2fa743 | 483 | int ret; |
a19ae1ec | 484 | |
237b6f33 | 485 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 486 | |
ee2fa743 JR |
487 | ret = iommu_queue_command(iommu, &cmd); |
488 | ||
ee2fa743 | 489 | return ret; |
a19ae1ec JR |
490 | } |
491 | ||
431b2a20 JR |
492 | /* |
493 | * TLB invalidation function which is called from the mapping functions. | |
494 | * It invalidates a single PTE if the range to flush is within a single | |
495 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
496 | */ | |
6de8ad9b JR |
497 | static void __iommu_flush_pages(struct protection_domain *domain, |
498 | u64 address, size_t size, int pde) | |
a19ae1ec | 499 | { |
6de8ad9b | 500 | int s = 0, i; |
dcd1e92e | 501 | unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
502 | |
503 | address &= PAGE_MASK; | |
504 | ||
999ba417 JR |
505 | if (pages > 1) { |
506 | /* | |
507 | * If we have to flush more than one page, flush all | |
508 | * TLB entries for this domain | |
509 | */ | |
510 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
511 | s = 1; | |
a19ae1ec JR |
512 | } |
513 | ||
999ba417 | 514 | |
6de8ad9b JR |
515 | for (i = 0; i < amd_iommus_present; ++i) { |
516 | if (!domain->dev_iommu[i]) | |
517 | continue; | |
518 | ||
519 | /* | |
520 | * Devices of this domain are behind this IOMMU | |
521 | * We need a TLB flush | |
522 | */ | |
523 | iommu_queue_inv_iommu_pages(amd_iommus[i], address, | |
524 | domain->id, pde, s); | |
525 | } | |
526 | ||
527 | return; | |
528 | } | |
529 | ||
530 | static void iommu_flush_pages(struct protection_domain *domain, | |
531 | u64 address, size_t size) | |
532 | { | |
533 | __iommu_flush_pages(domain, address, size, 0); | |
a19ae1ec | 534 | } |
b6c02715 | 535 | |
1c655773 | 536 | /* Flush the whole IO/TLB for a given protection domain */ |
dcd1e92e | 537 | static void iommu_flush_tlb(struct protection_domain *domain) |
1c655773 | 538 | { |
dcd1e92e | 539 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
540 | } |
541 | ||
42a49f96 | 542 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
dcd1e92e | 543 | static void iommu_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 544 | { |
dcd1e92e | 545 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
546 | } |
547 | ||
43f49609 | 548 | /* |
09b42804 | 549 | * This function flushes all domains that have devices on the given IOMMU |
43f49609 | 550 | */ |
09b42804 | 551 | static void flush_all_domains_on_iommu(struct amd_iommu *iommu) |
43f49609 | 552 | { |
09b42804 JR |
553 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; |
554 | struct protection_domain *domain; | |
e394d72a | 555 | unsigned long flags; |
18811f55 | 556 | |
09b42804 | 557 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); |
bfd1be18 | 558 | |
09b42804 JR |
559 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
560 | if (domain->dev_iommu[iommu->index] == 0) | |
bfd1be18 | 561 | continue; |
09b42804 JR |
562 | |
563 | spin_lock(&domain->lock); | |
564 | iommu_queue_inv_iommu_pages(iommu, address, domain->id, 1, 1); | |
565 | iommu_flush_complete(domain); | |
566 | spin_unlock(&domain->lock); | |
bfd1be18 | 567 | } |
e394d72a | 568 | |
09b42804 | 569 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); |
e394d72a JR |
570 | } |
571 | ||
09b42804 JR |
572 | /* |
573 | * This function uses heavy locking and may disable irqs for some time. But | |
574 | * this is no issue because it is only called during resume. | |
575 | */ | |
bfd1be18 | 576 | void amd_iommu_flush_all_domains(void) |
e394d72a | 577 | { |
e3306664 | 578 | struct protection_domain *domain; |
09b42804 JR |
579 | unsigned long flags; |
580 | ||
581 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
e394d72a | 582 | |
e3306664 | 583 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
09b42804 | 584 | spin_lock(&domain->lock); |
e3306664 JR |
585 | iommu_flush_tlb_pde(domain); |
586 | iommu_flush_complete(domain); | |
09b42804 | 587 | spin_unlock(&domain->lock); |
e3306664 | 588 | } |
09b42804 JR |
589 | |
590 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
bfd1be18 JR |
591 | } |
592 | ||
d586d785 | 593 | static void flush_all_devices_for_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
594 | { |
595 | int i; | |
596 | ||
d586d785 JR |
597 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { |
598 | if (iommu != amd_iommu_rlookup_table[i]) | |
bfd1be18 | 599 | continue; |
d586d785 JR |
600 | |
601 | iommu_queue_inv_dev_entry(iommu, i); | |
602 | iommu_completion_wait(iommu); | |
bfd1be18 JR |
603 | } |
604 | } | |
605 | ||
6a0dbcbe | 606 | static void flush_devices_by_domain(struct protection_domain *domain) |
7d7a110c JR |
607 | { |
608 | struct amd_iommu *iommu; | |
609 | int i; | |
610 | ||
611 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
6a0dbcbe JR |
612 | if ((domain == NULL && amd_iommu_pd_table[i] == NULL) || |
613 | (amd_iommu_pd_table[i] != domain)) | |
7d7a110c JR |
614 | continue; |
615 | ||
616 | iommu = amd_iommu_rlookup_table[i]; | |
617 | if (!iommu) | |
618 | continue; | |
619 | ||
620 | iommu_queue_inv_dev_entry(iommu, i); | |
621 | iommu_completion_wait(iommu); | |
622 | } | |
623 | } | |
624 | ||
a345b23b JR |
625 | static void reset_iommu_command_buffer(struct amd_iommu *iommu) |
626 | { | |
627 | pr_err("AMD-Vi: Resetting IOMMU command buffer\n"); | |
628 | ||
b26e81b8 JR |
629 | if (iommu->reset_in_progress) |
630 | panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n"); | |
631 | ||
632 | iommu->reset_in_progress = true; | |
633 | ||
a345b23b JR |
634 | amd_iommu_reset_cmd_buffer(iommu); |
635 | flush_all_devices_for_iommu(iommu); | |
636 | flush_all_domains_on_iommu(iommu); | |
b26e81b8 JR |
637 | |
638 | iommu->reset_in_progress = false; | |
a345b23b JR |
639 | } |
640 | ||
6a0dbcbe JR |
641 | void amd_iommu_flush_all_devices(void) |
642 | { | |
643 | flush_devices_by_domain(NULL); | |
644 | } | |
645 | ||
431b2a20 JR |
646 | /**************************************************************************** |
647 | * | |
648 | * The functions below are used the create the page table mappings for | |
649 | * unity mapped regions. | |
650 | * | |
651 | ****************************************************************************/ | |
652 | ||
308973d3 JR |
653 | /* |
654 | * This function is used to add another level to an IO page table. Adding | |
655 | * another level increases the size of the address space by 9 bits to a size up | |
656 | * to 64 bits. | |
657 | */ | |
658 | static bool increase_address_space(struct protection_domain *domain, | |
659 | gfp_t gfp) | |
660 | { | |
661 | u64 *pte; | |
662 | ||
663 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
664 | /* address space already 64 bit large */ | |
665 | return false; | |
666 | ||
667 | pte = (void *)get_zeroed_page(gfp); | |
668 | if (!pte) | |
669 | return false; | |
670 | ||
671 | *pte = PM_LEVEL_PDE(domain->mode, | |
672 | virt_to_phys(domain->pt_root)); | |
673 | domain->pt_root = pte; | |
674 | domain->mode += 1; | |
675 | domain->updated = true; | |
676 | ||
677 | return true; | |
678 | } | |
679 | ||
680 | static u64 *alloc_pte(struct protection_domain *domain, | |
681 | unsigned long address, | |
682 | int end_lvl, | |
683 | u64 **pte_page, | |
684 | gfp_t gfp) | |
685 | { | |
686 | u64 *pte, *page; | |
687 | int level; | |
688 | ||
689 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
690 | increase_address_space(domain, gfp); | |
691 | ||
692 | level = domain->mode - 1; | |
693 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
694 | ||
695 | while (level > end_lvl) { | |
696 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
697 | page = (u64 *)get_zeroed_page(gfp); | |
698 | if (!page) | |
699 | return NULL; | |
700 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
701 | } | |
702 | ||
703 | level -= 1; | |
704 | ||
705 | pte = IOMMU_PTE_PAGE(*pte); | |
706 | ||
707 | if (pte_page && level == end_lvl) | |
708 | *pte_page = pte; | |
709 | ||
710 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
711 | } | |
712 | ||
713 | return pte; | |
714 | } | |
715 | ||
716 | /* | |
717 | * This function checks if there is a PTE for a given dma address. If | |
718 | * there is one, it returns the pointer to it. | |
719 | */ | |
720 | static u64 *fetch_pte(struct protection_domain *domain, | |
721 | unsigned long address, int map_size) | |
722 | { | |
723 | int level; | |
724 | u64 *pte; | |
725 | ||
726 | level = domain->mode - 1; | |
727 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
728 | ||
729 | while (level > map_size) { | |
730 | if (!IOMMU_PTE_PRESENT(*pte)) | |
731 | return NULL; | |
732 | ||
733 | level -= 1; | |
734 | ||
735 | pte = IOMMU_PTE_PAGE(*pte); | |
736 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
737 | ||
738 | if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) { | |
739 | pte = NULL; | |
740 | break; | |
741 | } | |
742 | } | |
743 | ||
744 | return pte; | |
745 | } | |
746 | ||
431b2a20 JR |
747 | /* |
748 | * Generic mapping functions. It maps a physical address into a DMA | |
749 | * address space. It allocates the page table pages if necessary. | |
750 | * In the future it can be extended to a generic mapping function | |
751 | * supporting all features of AMD IOMMU page tables like level skipping | |
752 | * and full 64 bit address spaces. | |
753 | */ | |
38e817fe JR |
754 | static int iommu_map_page(struct protection_domain *dom, |
755 | unsigned long bus_addr, | |
756 | unsigned long phys_addr, | |
abdc5eb3 JR |
757 | int prot, |
758 | int map_size) | |
bd0e5211 | 759 | { |
8bda3092 | 760 | u64 __pte, *pte; |
bd0e5211 JR |
761 | |
762 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 763 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 | 764 | |
abdc5eb3 JR |
765 | BUG_ON(!PM_ALIGNED(map_size, bus_addr)); |
766 | BUG_ON(!PM_ALIGNED(map_size, phys_addr)); | |
767 | ||
bad1cac2 | 768 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
769 | return -EINVAL; |
770 | ||
abdc5eb3 | 771 | pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL); |
bd0e5211 JR |
772 | |
773 | if (IOMMU_PTE_PRESENT(*pte)) | |
774 | return -EBUSY; | |
775 | ||
776 | __pte = phys_addr | IOMMU_PTE_P; | |
777 | if (prot & IOMMU_PROT_IR) | |
778 | __pte |= IOMMU_PTE_IR; | |
779 | if (prot & IOMMU_PROT_IW) | |
780 | __pte |= IOMMU_PTE_IW; | |
781 | ||
782 | *pte = __pte; | |
783 | ||
04bfdd84 JR |
784 | update_domain(dom); |
785 | ||
bd0e5211 JR |
786 | return 0; |
787 | } | |
788 | ||
eb74ff6c | 789 | static void iommu_unmap_page(struct protection_domain *dom, |
a6b256b4 | 790 | unsigned long bus_addr, int map_size) |
eb74ff6c | 791 | { |
a6b256b4 | 792 | u64 *pte = fetch_pte(dom, bus_addr, map_size); |
eb74ff6c | 793 | |
38a76eee JR |
794 | if (pte) |
795 | *pte = 0; | |
eb74ff6c | 796 | } |
eb74ff6c | 797 | |
431b2a20 JR |
798 | /* |
799 | * This function checks if a specific unity mapping entry is needed for | |
800 | * this specific IOMMU. | |
801 | */ | |
bd0e5211 JR |
802 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
803 | struct unity_map_entry *entry) | |
804 | { | |
805 | u16 bdf, i; | |
806 | ||
807 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
808 | bdf = amd_iommu_alias_table[i]; | |
809 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
810 | return 1; | |
811 | } | |
812 | ||
813 | return 0; | |
814 | } | |
815 | ||
431b2a20 JR |
816 | /* |
817 | * This function actually applies the mapping to the page table of the | |
818 | * dma_ops domain. | |
819 | */ | |
bd0e5211 JR |
820 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
821 | struct unity_map_entry *e) | |
822 | { | |
823 | u64 addr; | |
824 | int ret; | |
825 | ||
826 | for (addr = e->address_start; addr < e->address_end; | |
827 | addr += PAGE_SIZE) { | |
abdc5eb3 JR |
828 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
829 | PM_MAP_4k); | |
bd0e5211 JR |
830 | if (ret) |
831 | return ret; | |
832 | /* | |
833 | * if unity mapping is in aperture range mark the page | |
834 | * as allocated in the aperture | |
835 | */ | |
836 | if (addr < dma_dom->aperture_size) | |
c3239567 | 837 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 838 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
839 | } |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
171e7b37 JR |
844 | /* |
845 | * Init the unity mappings for a specific IOMMU in the system | |
846 | * | |
847 | * Basically iterates over all unity mapping entries and applies them to | |
848 | * the default domain DMA of that IOMMU if necessary. | |
849 | */ | |
850 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
851 | { | |
852 | struct unity_map_entry *entry; | |
853 | int ret; | |
854 | ||
855 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
856 | if (!iommu_for_unity_map(iommu, entry)) | |
857 | continue; | |
858 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
859 | if (ret) | |
860 | return ret; | |
861 | } | |
862 | ||
863 | return 0; | |
864 | } | |
865 | ||
431b2a20 JR |
866 | /* |
867 | * Inits the unity mappings required for a specific device | |
868 | */ | |
bd0e5211 JR |
869 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
870 | u16 devid) | |
871 | { | |
872 | struct unity_map_entry *e; | |
873 | int ret; | |
874 | ||
875 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
876 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
877 | continue; | |
878 | ret = dma_ops_unity_map(dma_dom, e); | |
879 | if (ret) | |
880 | return ret; | |
881 | } | |
882 | ||
883 | return 0; | |
884 | } | |
885 | ||
431b2a20 JR |
886 | /**************************************************************************** |
887 | * | |
888 | * The next functions belong to the address allocator for the dma_ops | |
889 | * interface functions. They work like the allocators in the other IOMMU | |
890 | * drivers. Its basically a bitmap which marks the allocated pages in | |
891 | * the aperture. Maybe it could be enhanced in the future to a more | |
892 | * efficient allocator. | |
893 | * | |
894 | ****************************************************************************/ | |
d3086444 | 895 | |
431b2a20 | 896 | /* |
384de729 | 897 | * The address allocator core functions. |
431b2a20 JR |
898 | * |
899 | * called with domain->lock held | |
900 | */ | |
384de729 | 901 | |
171e7b37 JR |
902 | /* |
903 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
904 | * ranges. | |
905 | */ | |
906 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
907 | unsigned long start_page, | |
908 | unsigned int pages) | |
909 | { | |
910 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
911 | ||
912 | if (start_page + pages > last_page) | |
913 | pages = last_page - start_page; | |
914 | ||
915 | for (i = start_page; i < start_page + pages; ++i) { | |
916 | int index = i / APERTURE_RANGE_PAGES; | |
917 | int page = i % APERTURE_RANGE_PAGES; | |
918 | __set_bit(page, dom->aperture[index]->bitmap); | |
919 | } | |
920 | } | |
921 | ||
9cabe89b JR |
922 | /* |
923 | * This function is used to add a new aperture range to an existing | |
924 | * aperture in case of dma_ops domain allocation or address allocation | |
925 | * failure. | |
926 | */ | |
576175c2 | 927 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
928 | bool populate, gfp_t gfp) |
929 | { | |
930 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 931 | struct amd_iommu *iommu; |
00cd122a | 932 | int i; |
9cabe89b | 933 | |
f5e9705c JR |
934 | #ifdef CONFIG_IOMMU_STRESS |
935 | populate = false; | |
936 | #endif | |
937 | ||
9cabe89b JR |
938 | if (index >= APERTURE_MAX_RANGES) |
939 | return -ENOMEM; | |
940 | ||
941 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
942 | if (!dma_dom->aperture[index]) | |
943 | return -ENOMEM; | |
944 | ||
945 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
946 | if (!dma_dom->aperture[index]->bitmap) | |
947 | goto out_free; | |
948 | ||
949 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
950 | ||
951 | if (populate) { | |
952 | unsigned long address = dma_dom->aperture_size; | |
953 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
954 | u64 *pte, *pte_page; | |
955 | ||
956 | for (i = 0; i < num_ptes; ++i) { | |
abdc5eb3 | 957 | pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k, |
9cabe89b JR |
958 | &pte_page, gfp); |
959 | if (!pte) | |
960 | goto out_free; | |
961 | ||
962 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
963 | ||
964 | address += APERTURE_RANGE_SIZE / 64; | |
965 | } | |
966 | } | |
967 | ||
968 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
969 | ||
00cd122a | 970 | /* Intialize the exclusion range if necessary */ |
576175c2 JR |
971 | for_each_iommu(iommu) { |
972 | if (iommu->exclusion_start && | |
973 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
974 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
975 | unsigned long startpage; | |
976 | int pages = iommu_num_pages(iommu->exclusion_start, | |
977 | iommu->exclusion_length, | |
978 | PAGE_SIZE); | |
979 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
980 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
981 | } | |
00cd122a JR |
982 | } |
983 | ||
984 | /* | |
985 | * Check for areas already mapped as present in the new aperture | |
986 | * range and mark those pages as reserved in the allocator. Such | |
987 | * mappings may already exist as a result of requested unity | |
988 | * mappings for devices. | |
989 | */ | |
990 | for (i = dma_dom->aperture[index]->offset; | |
991 | i < dma_dom->aperture_size; | |
992 | i += PAGE_SIZE) { | |
a6b256b4 | 993 | u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k); |
00cd122a JR |
994 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
995 | continue; | |
996 | ||
997 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
998 | } | |
999 | ||
04bfdd84 JR |
1000 | update_domain(&dma_dom->domain); |
1001 | ||
9cabe89b JR |
1002 | return 0; |
1003 | ||
1004 | out_free: | |
04bfdd84 JR |
1005 | update_domain(&dma_dom->domain); |
1006 | ||
9cabe89b JR |
1007 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1008 | ||
1009 | kfree(dma_dom->aperture[index]); | |
1010 | dma_dom->aperture[index] = NULL; | |
1011 | ||
1012 | return -ENOMEM; | |
1013 | } | |
1014 | ||
384de729 JR |
1015 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1016 | struct dma_ops_domain *dom, | |
1017 | unsigned int pages, | |
1018 | unsigned long align_mask, | |
1019 | u64 dma_mask, | |
1020 | unsigned long start) | |
1021 | { | |
803b8cb4 | 1022 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1023 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1024 | int i = start >> APERTURE_RANGE_SHIFT; | |
1025 | unsigned long boundary_size; | |
1026 | unsigned long address = -1; | |
1027 | unsigned long limit; | |
1028 | ||
803b8cb4 JR |
1029 | next_bit >>= PAGE_SHIFT; |
1030 | ||
384de729 JR |
1031 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1032 | PAGE_SIZE) >> PAGE_SHIFT; | |
1033 | ||
1034 | for (;i < max_index; ++i) { | |
1035 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1036 | ||
1037 | if (dom->aperture[i]->offset >= dma_mask) | |
1038 | break; | |
1039 | ||
1040 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1041 | dma_mask >> PAGE_SHIFT); | |
1042 | ||
1043 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1044 | limit, next_bit, pages, 0, | |
1045 | boundary_size, align_mask); | |
1046 | if (address != -1) { | |
1047 | address = dom->aperture[i]->offset + | |
1048 | (address << PAGE_SHIFT); | |
803b8cb4 | 1049 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1050 | break; |
1051 | } | |
1052 | ||
1053 | next_bit = 0; | |
1054 | } | |
1055 | ||
1056 | return address; | |
1057 | } | |
1058 | ||
d3086444 JR |
1059 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1060 | struct dma_ops_domain *dom, | |
6d4f343f | 1061 | unsigned int pages, |
832a90c3 JR |
1062 | unsigned long align_mask, |
1063 | u64 dma_mask) | |
d3086444 | 1064 | { |
d3086444 | 1065 | unsigned long address; |
d3086444 | 1066 | |
fe16f088 JR |
1067 | #ifdef CONFIG_IOMMU_STRESS |
1068 | dom->next_address = 0; | |
1069 | dom->need_flush = true; | |
1070 | #endif | |
d3086444 | 1071 | |
384de729 | 1072 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1073 | dma_mask, dom->next_address); |
d3086444 | 1074 | |
1c655773 | 1075 | if (address == -1) { |
803b8cb4 | 1076 | dom->next_address = 0; |
384de729 JR |
1077 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1078 | dma_mask, 0); | |
1c655773 JR |
1079 | dom->need_flush = true; |
1080 | } | |
d3086444 | 1081 | |
384de729 | 1082 | if (unlikely(address == -1)) |
8fd524b3 | 1083 | address = DMA_ERROR_CODE; |
d3086444 JR |
1084 | |
1085 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1086 | ||
1087 | return address; | |
1088 | } | |
1089 | ||
431b2a20 JR |
1090 | /* |
1091 | * The address free function. | |
1092 | * | |
1093 | * called with domain->lock held | |
1094 | */ | |
d3086444 JR |
1095 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1096 | unsigned long address, | |
1097 | unsigned int pages) | |
1098 | { | |
384de729 JR |
1099 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1100 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1101 | |
384de729 JR |
1102 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1103 | ||
47bccd6b JR |
1104 | #ifdef CONFIG_IOMMU_STRESS |
1105 | if (i < 4) | |
1106 | return; | |
1107 | #endif | |
80be308d | 1108 | |
803b8cb4 | 1109 | if (address >= dom->next_address) |
80be308d | 1110 | dom->need_flush = true; |
384de729 JR |
1111 | |
1112 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1113 | |
384de729 JR |
1114 | iommu_area_free(range->bitmap, address, pages); |
1115 | ||
d3086444 JR |
1116 | } |
1117 | ||
431b2a20 JR |
1118 | /**************************************************************************** |
1119 | * | |
1120 | * The next functions belong to the domain allocation. A domain is | |
1121 | * allocated for every IOMMU as the default domain. If device isolation | |
1122 | * is enabled, every device get its own domain. The most important thing | |
1123 | * about domains is the page table mapping the DMA address space they | |
1124 | * contain. | |
1125 | * | |
1126 | ****************************************************************************/ | |
1127 | ||
aeb26f55 JR |
1128 | /* |
1129 | * This function adds a protection domain to the global protection domain list | |
1130 | */ | |
1131 | static void add_domain_to_list(struct protection_domain *domain) | |
1132 | { | |
1133 | unsigned long flags; | |
1134 | ||
1135 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1136 | list_add(&domain->list, &amd_iommu_pd_list); | |
1137 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1138 | } | |
1139 | ||
1140 | /* | |
1141 | * This function removes a protection domain to the global | |
1142 | * protection domain list | |
1143 | */ | |
1144 | static void del_domain_from_list(struct protection_domain *domain) | |
1145 | { | |
1146 | unsigned long flags; | |
1147 | ||
1148 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1149 | list_del(&domain->list); | |
1150 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1151 | } | |
1152 | ||
ec487d1a JR |
1153 | static u16 domain_id_alloc(void) |
1154 | { | |
1155 | unsigned long flags; | |
1156 | int id; | |
1157 | ||
1158 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1159 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1160 | BUG_ON(id == 0); | |
1161 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1162 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1163 | else | |
1164 | id = 0; | |
1165 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1166 | ||
1167 | return id; | |
1168 | } | |
1169 | ||
a2acfb75 JR |
1170 | static void domain_id_free(int id) |
1171 | { | |
1172 | unsigned long flags; | |
1173 | ||
1174 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1175 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1176 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1177 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1178 | } | |
a2acfb75 | 1179 | |
86db2e5d | 1180 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1181 | { |
1182 | int i, j; | |
1183 | u64 *p1, *p2, *p3; | |
1184 | ||
86db2e5d | 1185 | p1 = domain->pt_root; |
ec487d1a JR |
1186 | |
1187 | if (!p1) | |
1188 | return; | |
1189 | ||
1190 | for (i = 0; i < 512; ++i) { | |
1191 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1192 | continue; | |
1193 | ||
1194 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1195 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1196 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1197 | continue; | |
1198 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1199 | free_page((unsigned long)p3); | |
1200 | } | |
1201 | ||
1202 | free_page((unsigned long)p2); | |
1203 | } | |
1204 | ||
1205 | free_page((unsigned long)p1); | |
86db2e5d JR |
1206 | |
1207 | domain->pt_root = NULL; | |
ec487d1a JR |
1208 | } |
1209 | ||
431b2a20 JR |
1210 | /* |
1211 | * Free a domain, only used if something went wrong in the | |
1212 | * allocation path and we need to free an already allocated page table | |
1213 | */ | |
ec487d1a JR |
1214 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1215 | { | |
384de729 JR |
1216 | int i; |
1217 | ||
ec487d1a JR |
1218 | if (!dom) |
1219 | return; | |
1220 | ||
aeb26f55 JR |
1221 | del_domain_from_list(&dom->domain); |
1222 | ||
86db2e5d | 1223 | free_pagetable(&dom->domain); |
ec487d1a | 1224 | |
384de729 JR |
1225 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1226 | if (!dom->aperture[i]) | |
1227 | continue; | |
1228 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1229 | kfree(dom->aperture[i]); | |
1230 | } | |
ec487d1a JR |
1231 | |
1232 | kfree(dom); | |
1233 | } | |
1234 | ||
431b2a20 JR |
1235 | /* |
1236 | * Allocates a new protection domain usable for the dma_ops functions. | |
1237 | * It also intializes the page table and the address allocator data | |
1238 | * structures required for the dma_ops interface | |
1239 | */ | |
87a64d52 | 1240 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1241 | { |
1242 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1243 | |
1244 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1245 | if (!dma_dom) | |
1246 | return NULL; | |
1247 | ||
1248 | spin_lock_init(&dma_dom->domain.lock); | |
1249 | ||
1250 | dma_dom->domain.id = domain_id_alloc(); | |
1251 | if (dma_dom->domain.id == 0) | |
1252 | goto free_dma_dom; | |
8f7a017c | 1253 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1254 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1255 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1256 | dma_dom->domain.priv = dma_dom; |
1257 | if (!dma_dom->domain.pt_root) | |
1258 | goto free_dma_dom; | |
ec487d1a | 1259 | |
1c655773 | 1260 | dma_dom->need_flush = false; |
bd60b735 | 1261 | dma_dom->target_dev = 0xffff; |
1c655773 | 1262 | |
aeb26f55 JR |
1263 | add_domain_to_list(&dma_dom->domain); |
1264 | ||
576175c2 | 1265 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1266 | goto free_dma_dom; |
ec487d1a | 1267 | |
431b2a20 | 1268 | /* |
ec487d1a JR |
1269 | * mark the first page as allocated so we never return 0 as |
1270 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1271 | */ |
384de729 | 1272 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1273 | dma_dom->next_address = 0; |
ec487d1a | 1274 | |
ec487d1a JR |
1275 | |
1276 | return dma_dom; | |
1277 | ||
1278 | free_dma_dom: | |
1279 | dma_ops_domain_free(dma_dom); | |
1280 | ||
1281 | return NULL; | |
1282 | } | |
1283 | ||
5b28df6f JR |
1284 | /* |
1285 | * little helper function to check whether a given protection domain is a | |
1286 | * dma_ops domain | |
1287 | */ | |
1288 | static bool dma_ops_domain(struct protection_domain *domain) | |
1289 | { | |
1290 | return domain->flags & PD_DMA_OPS_MASK; | |
1291 | } | |
1292 | ||
407d733e | 1293 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1294 | { |
15898bbc | 1295 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
b20ac0d4 | 1296 | u64 pte_root = virt_to_phys(domain->pt_root); |
863c74eb | 1297 | |
15898bbc JR |
1298 | BUG_ON(amd_iommu_pd_table[devid] != NULL); |
1299 | ||
38ddf41b JR |
1300 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1301 | << DEV_ENTRY_MODE_SHIFT; | |
1302 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1303 | |
b20ac0d4 | 1304 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1305 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1306 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
b20ac0d4 JR |
1307 | |
1308 | amd_iommu_pd_table[devid] = domain; | |
15898bbc JR |
1309 | |
1310 | /* Do reference counting */ | |
1311 | domain->dev_iommu[iommu->index] += 1; | |
1312 | domain->dev_cnt += 1; | |
1313 | ||
1314 | /* Flush the changes DTE entry */ | |
1315 | iommu_queue_inv_dev_entry(iommu, devid); | |
1316 | } | |
1317 | ||
1318 | static void clear_dte_entry(u16 devid) | |
1319 | { | |
1320 | struct protection_domain *domain = amd_iommu_pd_table[devid]; | |
1321 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
1322 | ||
1323 | BUG_ON(domain == NULL); | |
1324 | ||
1325 | /* remove domain from the lookup table */ | |
1326 | amd_iommu_pd_table[devid] = NULL; | |
1327 | ||
1328 | /* remove entry from the device table seen by the hardware */ | |
1329 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1330 | amd_iommu_dev_table[devid].data[1] = 0; | |
1331 | amd_iommu_dev_table[devid].data[2] = 0; | |
1332 | ||
1333 | amd_iommu_apply_erratum_63(devid); | |
1334 | ||
1335 | /* decrease reference counters */ | |
1336 | domain->dev_iommu[iommu->index] -= 1; | |
1337 | domain->dev_cnt -= 1; | |
1338 | ||
1339 | iommu_queue_inv_dev_entry(iommu, devid); | |
2b681faf JR |
1340 | } |
1341 | ||
1342 | /* | |
1343 | * If a device is not yet associated with a domain, this function does | |
1344 | * assigns it visible for the hardware | |
1345 | */ | |
15898bbc JR |
1346 | static int __attach_device(struct device *dev, |
1347 | struct protection_domain *domain) | |
2b681faf | 1348 | { |
15898bbc JR |
1349 | u16 devid = get_device_id(dev); |
1350 | u16 alias = amd_iommu_alias_table[devid]; | |
1351 | ||
2b681faf JR |
1352 | /* lock domain */ |
1353 | spin_lock(&domain->lock); | |
1354 | ||
15898bbc JR |
1355 | /* Some sanity checks */ |
1356 | if (amd_iommu_pd_table[alias] != NULL && | |
1357 | amd_iommu_pd_table[alias] != domain) | |
1358 | return -EBUSY; | |
eba6ac60 | 1359 | |
15898bbc JR |
1360 | if (amd_iommu_pd_table[devid] != NULL && |
1361 | amd_iommu_pd_table[devid] != domain) | |
1362 | return -EBUSY; | |
1363 | ||
1364 | /* Do real assignment */ | |
1365 | if (alias != devid && | |
1366 | amd_iommu_pd_table[alias] == NULL) | |
1367 | set_dte_entry(alias, domain); | |
1368 | ||
1369 | if (amd_iommu_pd_table[devid] == NULL) | |
1370 | set_dte_entry(devid, domain); | |
eba6ac60 JR |
1371 | |
1372 | /* ready */ | |
1373 | spin_unlock(&domain->lock); | |
15898bbc JR |
1374 | |
1375 | return 0; | |
0feae533 | 1376 | } |
b20ac0d4 | 1377 | |
407d733e JR |
1378 | /* |
1379 | * If a device is not yet associated with a domain, this function does | |
1380 | * assigns it visible for the hardware | |
1381 | */ | |
15898bbc JR |
1382 | static int attach_device(struct device *dev, |
1383 | struct protection_domain *domain) | |
0feae533 | 1384 | { |
eba6ac60 | 1385 | unsigned long flags; |
15898bbc | 1386 | int ret; |
eba6ac60 JR |
1387 | |
1388 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1389 | ret = __attach_device(dev, domain); |
b20ac0d4 JR |
1390 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1391 | ||
0feae533 JR |
1392 | /* |
1393 | * We might boot into a crash-kernel here. The crashed kernel | |
1394 | * left the caches in the IOMMU dirty. So we have to flush | |
1395 | * here to evict all dirty stuff. | |
1396 | */ | |
dcd1e92e | 1397 | iommu_flush_tlb_pde(domain); |
15898bbc JR |
1398 | |
1399 | return ret; | |
b20ac0d4 JR |
1400 | } |
1401 | ||
355bf553 JR |
1402 | /* |
1403 | * Removes a device from a protection domain (unlocked) | |
1404 | */ | |
15898bbc | 1405 | static void __detach_device(struct device *dev) |
355bf553 | 1406 | { |
15898bbc | 1407 | u16 devid = get_device_id(dev); |
c4596114 JR |
1408 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
1409 | ||
1410 | BUG_ON(!iommu); | |
355bf553 | 1411 | |
15898bbc | 1412 | clear_dte_entry(devid); |
21129f78 JR |
1413 | |
1414 | /* | |
1415 | * If we run in passthrough mode the device must be assigned to the | |
1416 | * passthrough domain if it is detached from any other domain | |
1417 | */ | |
15898bbc JR |
1418 | if (iommu_pass_through) |
1419 | __attach_device(dev, pt_domain); | |
355bf553 JR |
1420 | } |
1421 | ||
1422 | /* | |
1423 | * Removes a device from a protection domain (with devtable_lock held) | |
1424 | */ | |
15898bbc | 1425 | static void detach_device(struct device *dev) |
355bf553 JR |
1426 | { |
1427 | unsigned long flags; | |
1428 | ||
1429 | /* lock device table */ | |
1430 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1431 | __detach_device(dev); |
355bf553 JR |
1432 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1433 | } | |
e275a2a0 | 1434 | |
15898bbc JR |
1435 | /* |
1436 | * Find out the protection domain structure for a given PCI device. This | |
1437 | * will give us the pointer to the page table root for example. | |
1438 | */ | |
1439 | static struct protection_domain *domain_for_device(struct device *dev) | |
1440 | { | |
1441 | struct protection_domain *dom; | |
1442 | unsigned long flags; | |
1443 | u16 devid, alias; | |
1444 | ||
1445 | devid = get_device_id(dev); | |
1446 | alias = amd_iommu_alias_table[devid]; | |
1447 | ||
1448 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1449 | dom = amd_iommu_pd_table[devid]; | |
1450 | if (dom == NULL && | |
1451 | amd_iommu_pd_table[alias] != NULL) { | |
1452 | __attach_device(dev, amd_iommu_pd_table[alias]); | |
1453 | dom = amd_iommu_pd_table[devid]; | |
1454 | } | |
1455 | ||
1456 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1457 | ||
1458 | return dom; | |
1459 | } | |
1460 | ||
e275a2a0 JR |
1461 | static int device_change_notifier(struct notifier_block *nb, |
1462 | unsigned long action, void *data) | |
1463 | { | |
1464 | struct device *dev = data; | |
98fc5a69 | 1465 | u16 devid; |
e275a2a0 JR |
1466 | struct protection_domain *domain; |
1467 | struct dma_ops_domain *dma_domain; | |
1468 | struct amd_iommu *iommu; | |
1ac4cbbc | 1469 | unsigned long flags; |
e275a2a0 | 1470 | |
98fc5a69 JR |
1471 | if (!check_device(dev)) |
1472 | return 0; | |
e275a2a0 | 1473 | |
98fc5a69 JR |
1474 | devid = get_device_id(dev); |
1475 | iommu = amd_iommu_rlookup_table[devid]; | |
15898bbc | 1476 | domain = domain_for_device(dev); |
e275a2a0 JR |
1477 | |
1478 | if (domain && !dma_ops_domain(domain)) | |
1479 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1480 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1481 | ||
1482 | switch (action) { | |
c1eee67b | 1483 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1484 | if (!domain) |
1485 | goto out; | |
a1ca331c JR |
1486 | if (iommu_pass_through) |
1487 | break; | |
15898bbc | 1488 | detach_device(dev); |
1ac4cbbc JR |
1489 | break; |
1490 | case BUS_NOTIFY_ADD_DEVICE: | |
1491 | /* allocate a protection domain if a device is added */ | |
1492 | dma_domain = find_protection_domain(devid); | |
1493 | if (dma_domain) | |
1494 | goto out; | |
87a64d52 | 1495 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1496 | if (!dma_domain) |
1497 | goto out; | |
1498 | dma_domain->target_dev = devid; | |
1499 | ||
1500 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1501 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1502 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1503 | ||
e275a2a0 JR |
1504 | break; |
1505 | default: | |
1506 | goto out; | |
1507 | } | |
1508 | ||
1509 | iommu_queue_inv_dev_entry(iommu, devid); | |
1510 | iommu_completion_wait(iommu); | |
1511 | ||
1512 | out: | |
1513 | return 0; | |
1514 | } | |
1515 | ||
b25ae679 | 1516 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1517 | .notifier_call = device_change_notifier, |
1518 | }; | |
355bf553 | 1519 | |
431b2a20 JR |
1520 | /***************************************************************************** |
1521 | * | |
1522 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1523 | * | |
1524 | *****************************************************************************/ | |
1525 | ||
1526 | /* | |
1527 | * In the dma_ops path we only have the struct device. This function | |
1528 | * finds the corresponding IOMMU, the protection domain and the | |
1529 | * requestor id for a given device. | |
1530 | * If the device is not yet associated with a domain this is also done | |
1531 | * in this function. | |
1532 | */ | |
94f6d190 | 1533 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1534 | { |
94f6d190 | 1535 | struct protection_domain *domain; |
b20ac0d4 | 1536 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1537 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1538 | |
f99c0f1c | 1539 | if (!check_device(dev)) |
94f6d190 | 1540 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1541 | |
94f6d190 JR |
1542 | domain = domain_for_device(dev); |
1543 | if (domain != NULL && !dma_ops_domain(domain)) | |
1544 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1545 | |
94f6d190 JR |
1546 | if (domain != NULL) |
1547 | return domain; | |
b20ac0d4 | 1548 | |
15898bbc | 1549 | /* Device not bount yet - bind it */ |
94f6d190 | 1550 | dma_dom = find_protection_domain(devid); |
15898bbc | 1551 | if (!dma_dom) |
94f6d190 JR |
1552 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1553 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1554 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1555 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1556 | |
94f6d190 | 1557 | return &dma_dom->domain; |
b20ac0d4 JR |
1558 | } |
1559 | ||
04bfdd84 JR |
1560 | static void update_device_table(struct protection_domain *domain) |
1561 | { | |
2b681faf | 1562 | unsigned long flags; |
04bfdd84 JR |
1563 | int i; |
1564 | ||
1565 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
1566 | if (amd_iommu_pd_table[i] != domain) | |
1567 | continue; | |
2b681faf | 1568 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
04bfdd84 | 1569 | set_dte_entry(i, domain); |
2b681faf | 1570 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
04bfdd84 JR |
1571 | } |
1572 | } | |
1573 | ||
1574 | static void update_domain(struct protection_domain *domain) | |
1575 | { | |
1576 | if (!domain->updated) | |
1577 | return; | |
1578 | ||
1579 | update_device_table(domain); | |
1580 | flush_devices_by_domain(domain); | |
601367d7 | 1581 | iommu_flush_tlb_pde(domain); |
04bfdd84 JR |
1582 | |
1583 | domain->updated = false; | |
1584 | } | |
1585 | ||
8bda3092 JR |
1586 | /* |
1587 | * This function fetches the PTE for a given address in the aperture | |
1588 | */ | |
1589 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1590 | unsigned long address) | |
1591 | { | |
384de729 | 1592 | struct aperture_range *aperture; |
8bda3092 JR |
1593 | u64 *pte, *pte_page; |
1594 | ||
384de729 JR |
1595 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1596 | if (!aperture) | |
1597 | return NULL; | |
1598 | ||
1599 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1600 | if (!pte) { |
abdc5eb3 JR |
1601 | pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page, |
1602 | GFP_ATOMIC); | |
384de729 JR |
1603 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1604 | } else | |
8c8c143c | 1605 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1606 | |
04bfdd84 | 1607 | update_domain(&dom->domain); |
8bda3092 JR |
1608 | |
1609 | return pte; | |
1610 | } | |
1611 | ||
431b2a20 JR |
1612 | /* |
1613 | * This is the generic map function. It maps one 4kb page at paddr to | |
1614 | * the given address in the DMA address space for the domain. | |
1615 | */ | |
680525e0 | 1616 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1617 | unsigned long address, |
1618 | phys_addr_t paddr, | |
1619 | int direction) | |
1620 | { | |
1621 | u64 *pte, __pte; | |
1622 | ||
1623 | WARN_ON(address > dom->aperture_size); | |
1624 | ||
1625 | paddr &= PAGE_MASK; | |
1626 | ||
8bda3092 | 1627 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1628 | if (!pte) |
8fd524b3 | 1629 | return DMA_ERROR_CODE; |
cb76c322 JR |
1630 | |
1631 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1632 | ||
1633 | if (direction == DMA_TO_DEVICE) | |
1634 | __pte |= IOMMU_PTE_IR; | |
1635 | else if (direction == DMA_FROM_DEVICE) | |
1636 | __pte |= IOMMU_PTE_IW; | |
1637 | else if (direction == DMA_BIDIRECTIONAL) | |
1638 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1639 | ||
1640 | WARN_ON(*pte); | |
1641 | ||
1642 | *pte = __pte; | |
1643 | ||
1644 | return (dma_addr_t)address; | |
1645 | } | |
1646 | ||
431b2a20 JR |
1647 | /* |
1648 | * The generic unmapping function for on page in the DMA address space. | |
1649 | */ | |
680525e0 | 1650 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1651 | unsigned long address) |
1652 | { | |
384de729 | 1653 | struct aperture_range *aperture; |
cb76c322 JR |
1654 | u64 *pte; |
1655 | ||
1656 | if (address >= dom->aperture_size) | |
1657 | return; | |
1658 | ||
384de729 JR |
1659 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1660 | if (!aperture) | |
1661 | return; | |
1662 | ||
1663 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1664 | if (!pte) | |
1665 | return; | |
cb76c322 | 1666 | |
8c8c143c | 1667 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1668 | |
1669 | WARN_ON(!*pte); | |
1670 | ||
1671 | *pte = 0ULL; | |
1672 | } | |
1673 | ||
431b2a20 JR |
1674 | /* |
1675 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1676 | * contiguous memory region into DMA address space. It is used by all |
1677 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1678 | * Must be called with the domain lock held. |
1679 | */ | |
cb76c322 | 1680 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
1681 | struct dma_ops_domain *dma_dom, |
1682 | phys_addr_t paddr, | |
1683 | size_t size, | |
6d4f343f | 1684 | int dir, |
832a90c3 JR |
1685 | bool align, |
1686 | u64 dma_mask) | |
cb76c322 JR |
1687 | { |
1688 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1689 | dma_addr_t address, start, ret; |
cb76c322 | 1690 | unsigned int pages; |
6d4f343f | 1691 | unsigned long align_mask = 0; |
cb76c322 JR |
1692 | int i; |
1693 | ||
e3c449f5 | 1694 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1695 | paddr &= PAGE_MASK; |
1696 | ||
8ecaf8f1 JR |
1697 | INC_STATS_COUNTER(total_map_requests); |
1698 | ||
c1858976 JR |
1699 | if (pages > 1) |
1700 | INC_STATS_COUNTER(cross_page); | |
1701 | ||
6d4f343f JR |
1702 | if (align) |
1703 | align_mask = (1UL << get_order(size)) - 1; | |
1704 | ||
11b83888 | 1705 | retry: |
832a90c3 JR |
1706 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1707 | dma_mask); | |
8fd524b3 | 1708 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1709 | /* |
1710 | * setting next_address here will let the address | |
1711 | * allocator only scan the new allocated range in the | |
1712 | * first run. This is a small optimization. | |
1713 | */ | |
1714 | dma_dom->next_address = dma_dom->aperture_size; | |
1715 | ||
576175c2 | 1716 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
1717 | goto out; |
1718 | ||
1719 | /* | |
1720 | * aperture was sucessfully enlarged by 128 MB, try | |
1721 | * allocation again | |
1722 | */ | |
1723 | goto retry; | |
1724 | } | |
cb76c322 JR |
1725 | |
1726 | start = address; | |
1727 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1728 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 1729 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
1730 | goto out_unmap; |
1731 | ||
cb76c322 JR |
1732 | paddr += PAGE_SIZE; |
1733 | start += PAGE_SIZE; | |
1734 | } | |
1735 | address += offset; | |
1736 | ||
5774f7c5 JR |
1737 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1738 | ||
afa9fdc2 | 1739 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
dcd1e92e | 1740 | iommu_flush_tlb(&dma_dom->domain); |
1c655773 | 1741 | dma_dom->need_flush = false; |
318afd41 | 1742 | } else if (unlikely(amd_iommu_np_cache)) |
6de8ad9b | 1743 | iommu_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 1744 | |
cb76c322 JR |
1745 | out: |
1746 | return address; | |
53812c11 JR |
1747 | |
1748 | out_unmap: | |
1749 | ||
1750 | for (--i; i >= 0; --i) { | |
1751 | start -= PAGE_SIZE; | |
680525e0 | 1752 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
1753 | } |
1754 | ||
1755 | dma_ops_free_addresses(dma_dom, address, pages); | |
1756 | ||
8fd524b3 | 1757 | return DMA_ERROR_CODE; |
cb76c322 JR |
1758 | } |
1759 | ||
431b2a20 JR |
1760 | /* |
1761 | * Does the reverse of the __map_single function. Must be called with | |
1762 | * the domain lock held too | |
1763 | */ | |
cd8c82e8 | 1764 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
1765 | dma_addr_t dma_addr, |
1766 | size_t size, | |
1767 | int dir) | |
1768 | { | |
1769 | dma_addr_t i, start; | |
1770 | unsigned int pages; | |
1771 | ||
8fd524b3 | 1772 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 1773 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
1774 | return; |
1775 | ||
e3c449f5 | 1776 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1777 | dma_addr &= PAGE_MASK; |
1778 | start = dma_addr; | |
1779 | ||
1780 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1781 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
1782 | start += PAGE_SIZE; |
1783 | } | |
1784 | ||
5774f7c5 JR |
1785 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1786 | ||
cb76c322 | 1787 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1788 | |
80be308d | 1789 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
6de8ad9b | 1790 | iommu_flush_pages(&dma_dom->domain, dma_addr, size); |
80be308d JR |
1791 | dma_dom->need_flush = false; |
1792 | } | |
cb76c322 JR |
1793 | } |
1794 | ||
431b2a20 JR |
1795 | /* |
1796 | * The exported map_single function for dma_ops. | |
1797 | */ | |
51491367 FT |
1798 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1799 | unsigned long offset, size_t size, | |
1800 | enum dma_data_direction dir, | |
1801 | struct dma_attrs *attrs) | |
4da70b9e JR |
1802 | { |
1803 | unsigned long flags; | |
4da70b9e | 1804 | struct protection_domain *domain; |
4da70b9e | 1805 | dma_addr_t addr; |
832a90c3 | 1806 | u64 dma_mask; |
51491367 | 1807 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1808 | |
0f2a86f2 JR |
1809 | INC_STATS_COUNTER(cnt_map_single); |
1810 | ||
94f6d190 JR |
1811 | domain = get_domain(dev); |
1812 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 1813 | return (dma_addr_t)paddr; |
94f6d190 JR |
1814 | else if (IS_ERR(domain)) |
1815 | return DMA_ERROR_CODE; | |
4da70b9e | 1816 | |
f99c0f1c JR |
1817 | dma_mask = *dev->dma_mask; |
1818 | ||
4da70b9e | 1819 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 1820 | |
cd8c82e8 | 1821 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 1822 | dma_mask); |
8fd524b3 | 1823 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
1824 | goto out; |
1825 | ||
0518a3a4 | 1826 | iommu_flush_complete(domain); |
4da70b9e JR |
1827 | |
1828 | out: | |
1829 | spin_unlock_irqrestore(&domain->lock, flags); | |
1830 | ||
1831 | return addr; | |
1832 | } | |
1833 | ||
431b2a20 JR |
1834 | /* |
1835 | * The exported unmap_single function for dma_ops. | |
1836 | */ | |
51491367 FT |
1837 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1838 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1839 | { |
1840 | unsigned long flags; | |
4da70b9e | 1841 | struct protection_domain *domain; |
4da70b9e | 1842 | |
146a6917 JR |
1843 | INC_STATS_COUNTER(cnt_unmap_single); |
1844 | ||
94f6d190 JR |
1845 | domain = get_domain(dev); |
1846 | if (IS_ERR(domain)) | |
5b28df6f JR |
1847 | return; |
1848 | ||
4da70b9e JR |
1849 | spin_lock_irqsave(&domain->lock, flags); |
1850 | ||
cd8c82e8 | 1851 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 1852 | |
0518a3a4 | 1853 | iommu_flush_complete(domain); |
4da70b9e JR |
1854 | |
1855 | spin_unlock_irqrestore(&domain->lock, flags); | |
1856 | } | |
1857 | ||
431b2a20 JR |
1858 | /* |
1859 | * This is a special map_sg function which is used if we should map a | |
1860 | * device which is not handled by an AMD IOMMU in the system. | |
1861 | */ | |
65b050ad JR |
1862 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1863 | int nelems, int dir) | |
1864 | { | |
1865 | struct scatterlist *s; | |
1866 | int i; | |
1867 | ||
1868 | for_each_sg(sglist, s, nelems, i) { | |
1869 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1870 | s->dma_length = s->length; | |
1871 | } | |
1872 | ||
1873 | return nelems; | |
1874 | } | |
1875 | ||
431b2a20 JR |
1876 | /* |
1877 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1878 | * lists). | |
1879 | */ | |
65b050ad | 1880 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1881 | int nelems, enum dma_data_direction dir, |
1882 | struct dma_attrs *attrs) | |
65b050ad JR |
1883 | { |
1884 | unsigned long flags; | |
65b050ad | 1885 | struct protection_domain *domain; |
65b050ad JR |
1886 | int i; |
1887 | struct scatterlist *s; | |
1888 | phys_addr_t paddr; | |
1889 | int mapped_elems = 0; | |
832a90c3 | 1890 | u64 dma_mask; |
65b050ad | 1891 | |
d03f067a JR |
1892 | INC_STATS_COUNTER(cnt_map_sg); |
1893 | ||
94f6d190 JR |
1894 | domain = get_domain(dev); |
1895 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 1896 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
1897 | else if (IS_ERR(domain)) |
1898 | return 0; | |
dbcc112e | 1899 | |
832a90c3 | 1900 | dma_mask = *dev->dma_mask; |
65b050ad | 1901 | |
65b050ad JR |
1902 | spin_lock_irqsave(&domain->lock, flags); |
1903 | ||
1904 | for_each_sg(sglist, s, nelems, i) { | |
1905 | paddr = sg_phys(s); | |
1906 | ||
cd8c82e8 | 1907 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
1908 | paddr, s->length, dir, false, |
1909 | dma_mask); | |
65b050ad JR |
1910 | |
1911 | if (s->dma_address) { | |
1912 | s->dma_length = s->length; | |
1913 | mapped_elems++; | |
1914 | } else | |
1915 | goto unmap; | |
65b050ad JR |
1916 | } |
1917 | ||
0518a3a4 | 1918 | iommu_flush_complete(domain); |
65b050ad JR |
1919 | |
1920 | out: | |
1921 | spin_unlock_irqrestore(&domain->lock, flags); | |
1922 | ||
1923 | return mapped_elems; | |
1924 | unmap: | |
1925 | for_each_sg(sglist, s, mapped_elems, i) { | |
1926 | if (s->dma_address) | |
cd8c82e8 | 1927 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
1928 | s->dma_length, dir); |
1929 | s->dma_address = s->dma_length = 0; | |
1930 | } | |
1931 | ||
1932 | mapped_elems = 0; | |
1933 | ||
1934 | goto out; | |
1935 | } | |
1936 | ||
431b2a20 JR |
1937 | /* |
1938 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1939 | * lists). | |
1940 | */ | |
65b050ad | 1941 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1942 | int nelems, enum dma_data_direction dir, |
1943 | struct dma_attrs *attrs) | |
65b050ad JR |
1944 | { |
1945 | unsigned long flags; | |
65b050ad JR |
1946 | struct protection_domain *domain; |
1947 | struct scatterlist *s; | |
65b050ad JR |
1948 | int i; |
1949 | ||
55877a6b JR |
1950 | INC_STATS_COUNTER(cnt_unmap_sg); |
1951 | ||
94f6d190 JR |
1952 | domain = get_domain(dev); |
1953 | if (IS_ERR(domain)) | |
5b28df6f JR |
1954 | return; |
1955 | ||
65b050ad JR |
1956 | spin_lock_irqsave(&domain->lock, flags); |
1957 | ||
1958 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 1959 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 1960 | s->dma_length, dir); |
65b050ad JR |
1961 | s->dma_address = s->dma_length = 0; |
1962 | } | |
1963 | ||
0518a3a4 | 1964 | iommu_flush_complete(domain); |
65b050ad JR |
1965 | |
1966 | spin_unlock_irqrestore(&domain->lock, flags); | |
1967 | } | |
1968 | ||
431b2a20 JR |
1969 | /* |
1970 | * The exported alloc_coherent function for dma_ops. | |
1971 | */ | |
5d8b53cf JR |
1972 | static void *alloc_coherent(struct device *dev, size_t size, |
1973 | dma_addr_t *dma_addr, gfp_t flag) | |
1974 | { | |
1975 | unsigned long flags; | |
1976 | void *virt_addr; | |
5d8b53cf | 1977 | struct protection_domain *domain; |
5d8b53cf | 1978 | phys_addr_t paddr; |
832a90c3 | 1979 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1980 | |
c8f0fb36 JR |
1981 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1982 | ||
94f6d190 JR |
1983 | domain = get_domain(dev); |
1984 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
1985 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1986 | *dma_addr = __pa(virt_addr); | |
1987 | return virt_addr; | |
94f6d190 JR |
1988 | } else if (IS_ERR(domain)) |
1989 | return NULL; | |
5d8b53cf | 1990 | |
f99c0f1c JR |
1991 | dma_mask = dev->coherent_dma_mask; |
1992 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
1993 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
1994 | |
1995 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
1996 | if (!virt_addr) | |
b25ae679 | 1997 | return NULL; |
5d8b53cf | 1998 | |
5d8b53cf JR |
1999 | paddr = virt_to_phys(virt_addr); |
2000 | ||
832a90c3 JR |
2001 | if (!dma_mask) |
2002 | dma_mask = *dev->dma_mask; | |
2003 | ||
5d8b53cf JR |
2004 | spin_lock_irqsave(&domain->lock, flags); |
2005 | ||
cd8c82e8 | 2006 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2007 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2008 | |
8fd524b3 | 2009 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2010 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2011 | goto out_free; |
367d04c4 | 2012 | } |
5d8b53cf | 2013 | |
0518a3a4 | 2014 | iommu_flush_complete(domain); |
5d8b53cf | 2015 | |
5d8b53cf JR |
2016 | spin_unlock_irqrestore(&domain->lock, flags); |
2017 | ||
2018 | return virt_addr; | |
5b28df6f JR |
2019 | |
2020 | out_free: | |
2021 | ||
2022 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2023 | ||
2024 | return NULL; | |
5d8b53cf JR |
2025 | } |
2026 | ||
431b2a20 JR |
2027 | /* |
2028 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2029 | */ |
5d8b53cf JR |
2030 | static void free_coherent(struct device *dev, size_t size, |
2031 | void *virt_addr, dma_addr_t dma_addr) | |
2032 | { | |
2033 | unsigned long flags; | |
5d8b53cf | 2034 | struct protection_domain *domain; |
5d8b53cf | 2035 | |
5d31ee7e JR |
2036 | INC_STATS_COUNTER(cnt_free_coherent); |
2037 | ||
94f6d190 JR |
2038 | domain = get_domain(dev); |
2039 | if (IS_ERR(domain)) | |
5b28df6f JR |
2040 | goto free_mem; |
2041 | ||
5d8b53cf JR |
2042 | spin_lock_irqsave(&domain->lock, flags); |
2043 | ||
cd8c82e8 | 2044 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2045 | |
0518a3a4 | 2046 | iommu_flush_complete(domain); |
5d8b53cf JR |
2047 | |
2048 | spin_unlock_irqrestore(&domain->lock, flags); | |
2049 | ||
2050 | free_mem: | |
2051 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2052 | } | |
2053 | ||
b39ba6ad JR |
2054 | /* |
2055 | * This function is called by the DMA layer to find out if we can handle a | |
2056 | * particular device. It is part of the dma_ops. | |
2057 | */ | |
2058 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2059 | { | |
420aef8a | 2060 | return check_device(dev); |
b39ba6ad JR |
2061 | } |
2062 | ||
c432f3df | 2063 | /* |
431b2a20 JR |
2064 | * The function for pre-allocating protection domains. |
2065 | * | |
c432f3df JR |
2066 | * If the driver core informs the DMA layer if a driver grabs a device |
2067 | * we don't need to preallocate the protection domains anymore. | |
2068 | * For now we have to. | |
2069 | */ | |
0e93dd88 | 2070 | static void prealloc_protection_domains(void) |
c432f3df JR |
2071 | { |
2072 | struct pci_dev *dev = NULL; | |
2073 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2074 | u16 devid; |
c432f3df JR |
2075 | |
2076 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
98fc5a69 JR |
2077 | |
2078 | /* Do we handle this device? */ | |
2079 | if (!check_device(&dev->dev)) | |
c432f3df | 2080 | continue; |
98fc5a69 JR |
2081 | |
2082 | /* Is there already any domain for it? */ | |
15898bbc | 2083 | if (domain_for_device(&dev->dev)) |
c432f3df | 2084 | continue; |
98fc5a69 JR |
2085 | |
2086 | devid = get_device_id(&dev->dev); | |
2087 | ||
87a64d52 | 2088 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2089 | if (!dma_dom) |
2090 | continue; | |
2091 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2092 | dma_dom->target_dev = devid; |
2093 | ||
15898bbc | 2094 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2095 | |
bd60b735 | 2096 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2097 | } |
2098 | } | |
2099 | ||
160c1d8e | 2100 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2101 | .alloc_coherent = alloc_coherent, |
2102 | .free_coherent = free_coherent, | |
51491367 FT |
2103 | .map_page = map_page, |
2104 | .unmap_page = unmap_page, | |
6631ee9d JR |
2105 | .map_sg = map_sg, |
2106 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2107 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2108 | }; |
2109 | ||
431b2a20 JR |
2110 | /* |
2111 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2112 | */ | |
6631ee9d JR |
2113 | int __init amd_iommu_init_dma_ops(void) |
2114 | { | |
2115 | struct amd_iommu *iommu; | |
6631ee9d JR |
2116 | int ret; |
2117 | ||
431b2a20 JR |
2118 | /* |
2119 | * first allocate a default protection domain for every IOMMU we | |
2120 | * found in the system. Devices not assigned to any other | |
2121 | * protection domain will be assigned to the default one. | |
2122 | */ | |
3bd22172 | 2123 | for_each_iommu(iommu) { |
87a64d52 | 2124 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2125 | if (iommu->default_dom == NULL) |
2126 | return -ENOMEM; | |
e2dc14a2 | 2127 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2128 | ret = iommu_init_unity_mappings(iommu); |
2129 | if (ret) | |
2130 | goto free_domains; | |
2131 | } | |
2132 | ||
431b2a20 | 2133 | /* |
8793abeb | 2134 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2135 | */ |
8793abeb | 2136 | prealloc_protection_domains(); |
6631ee9d JR |
2137 | |
2138 | iommu_detected = 1; | |
75f1cdf1 | 2139 | swiotlb = 0; |
92af4e29 | 2140 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
2141 | gart_iommu_aperture_disabled = 1; |
2142 | gart_iommu_aperture = 0; | |
92af4e29 | 2143 | #endif |
6631ee9d | 2144 | |
431b2a20 | 2145 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2146 | dma_ops = &amd_iommu_dma_ops; |
2147 | ||
26961efe | 2148 | register_iommu(&amd_iommu_ops); |
26961efe | 2149 | |
e275a2a0 JR |
2150 | bus_register_notifier(&pci_bus_type, &device_nb); |
2151 | ||
7f26508b JR |
2152 | amd_iommu_stats_init(); |
2153 | ||
6631ee9d JR |
2154 | return 0; |
2155 | ||
2156 | free_domains: | |
2157 | ||
3bd22172 | 2158 | for_each_iommu(iommu) { |
6631ee9d JR |
2159 | if (iommu->default_dom) |
2160 | dma_ops_domain_free(iommu->default_dom); | |
2161 | } | |
2162 | ||
2163 | return ret; | |
2164 | } | |
6d98cd80 JR |
2165 | |
2166 | /***************************************************************************** | |
2167 | * | |
2168 | * The following functions belong to the exported interface of AMD IOMMU | |
2169 | * | |
2170 | * This interface allows access to lower level functions of the IOMMU | |
2171 | * like protection domain handling and assignement of devices to domains | |
2172 | * which is not possible with the dma_ops interface. | |
2173 | * | |
2174 | *****************************************************************************/ | |
2175 | ||
6d98cd80 JR |
2176 | static void cleanup_domain(struct protection_domain *domain) |
2177 | { | |
2178 | unsigned long flags; | |
2179 | u16 devid; | |
2180 | ||
2181 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2182 | ||
2183 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
2184 | if (amd_iommu_pd_table[devid] == domain) | |
15898bbc | 2185 | clear_dte_entry(devid); |
6d98cd80 JR |
2186 | |
2187 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2188 | } | |
2189 | ||
2650815f JR |
2190 | static void protection_domain_free(struct protection_domain *domain) |
2191 | { | |
2192 | if (!domain) | |
2193 | return; | |
2194 | ||
aeb26f55 JR |
2195 | del_domain_from_list(domain); |
2196 | ||
2650815f JR |
2197 | if (domain->id) |
2198 | domain_id_free(domain->id); | |
2199 | ||
2200 | kfree(domain); | |
2201 | } | |
2202 | ||
2203 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2204 | { |
2205 | struct protection_domain *domain; | |
2206 | ||
2207 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2208 | if (!domain) | |
2650815f | 2209 | return NULL; |
c156e347 JR |
2210 | |
2211 | spin_lock_init(&domain->lock); | |
c156e347 JR |
2212 | domain->id = domain_id_alloc(); |
2213 | if (!domain->id) | |
2650815f JR |
2214 | goto out_err; |
2215 | ||
aeb26f55 JR |
2216 | add_domain_to_list(domain); |
2217 | ||
2650815f JR |
2218 | return domain; |
2219 | ||
2220 | out_err: | |
2221 | kfree(domain); | |
2222 | ||
2223 | return NULL; | |
2224 | } | |
2225 | ||
2226 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2227 | { | |
2228 | struct protection_domain *domain; | |
2229 | ||
2230 | domain = protection_domain_alloc(); | |
2231 | if (!domain) | |
c156e347 | 2232 | goto out_free; |
2650815f JR |
2233 | |
2234 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2235 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2236 | if (!domain->pt_root) | |
2237 | goto out_free; | |
2238 | ||
2239 | dom->priv = domain; | |
2240 | ||
2241 | return 0; | |
2242 | ||
2243 | out_free: | |
2650815f | 2244 | protection_domain_free(domain); |
c156e347 JR |
2245 | |
2246 | return -ENOMEM; | |
2247 | } | |
2248 | ||
98383fc3 JR |
2249 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2250 | { | |
2251 | struct protection_domain *domain = dom->priv; | |
2252 | ||
2253 | if (!domain) | |
2254 | return; | |
2255 | ||
2256 | if (domain->dev_cnt > 0) | |
2257 | cleanup_domain(domain); | |
2258 | ||
2259 | BUG_ON(domain->dev_cnt != 0); | |
2260 | ||
2261 | free_pagetable(domain); | |
2262 | ||
2263 | domain_id_free(domain->id); | |
2264 | ||
2265 | kfree(domain); | |
2266 | ||
2267 | dom->priv = NULL; | |
2268 | } | |
2269 | ||
684f2888 JR |
2270 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2271 | struct device *dev) | |
2272 | { | |
684f2888 | 2273 | struct amd_iommu *iommu; |
684f2888 JR |
2274 | u16 devid; |
2275 | ||
98fc5a69 | 2276 | if (!check_device(dev)) |
684f2888 JR |
2277 | return; |
2278 | ||
98fc5a69 | 2279 | devid = get_device_id(dev); |
684f2888 | 2280 | |
98fc5a69 | 2281 | if (amd_iommu_pd_table[devid] != NULL) |
15898bbc | 2282 | detach_device(dev); |
684f2888 JR |
2283 | |
2284 | iommu = amd_iommu_rlookup_table[devid]; | |
2285 | if (!iommu) | |
2286 | return; | |
2287 | ||
2288 | iommu_queue_inv_dev_entry(iommu, devid); | |
2289 | iommu_completion_wait(iommu); | |
2290 | } | |
2291 | ||
01106066 JR |
2292 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2293 | struct device *dev) | |
2294 | { | |
2295 | struct protection_domain *domain = dom->priv; | |
2296 | struct protection_domain *old_domain; | |
2297 | struct amd_iommu *iommu; | |
15898bbc | 2298 | int ret; |
01106066 JR |
2299 | u16 devid; |
2300 | ||
98fc5a69 | 2301 | if (!check_device(dev)) |
01106066 JR |
2302 | return -EINVAL; |
2303 | ||
98fc5a69 | 2304 | devid = get_device_id(dev); |
01106066 JR |
2305 | |
2306 | iommu = amd_iommu_rlookup_table[devid]; | |
2307 | if (!iommu) | |
2308 | return -EINVAL; | |
2309 | ||
15898bbc | 2310 | old_domain = amd_iommu_pd_table[devid]; |
01106066 | 2311 | if (old_domain) |
15898bbc | 2312 | detach_device(dev); |
01106066 | 2313 | |
15898bbc | 2314 | ret = attach_device(dev, domain); |
01106066 JR |
2315 | |
2316 | iommu_completion_wait(iommu); | |
2317 | ||
15898bbc | 2318 | return ret; |
01106066 JR |
2319 | } |
2320 | ||
c6229ca6 JR |
2321 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2322 | unsigned long iova, phys_addr_t paddr, | |
2323 | size_t size, int iommu_prot) | |
2324 | { | |
2325 | struct protection_domain *domain = dom->priv; | |
2326 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2327 | int prot = 0; | |
2328 | int ret; | |
2329 | ||
2330 | if (iommu_prot & IOMMU_READ) | |
2331 | prot |= IOMMU_PROT_IR; | |
2332 | if (iommu_prot & IOMMU_WRITE) | |
2333 | prot |= IOMMU_PROT_IW; | |
2334 | ||
2335 | iova &= PAGE_MASK; | |
2336 | paddr &= PAGE_MASK; | |
2337 | ||
2338 | for (i = 0; i < npages; ++i) { | |
abdc5eb3 | 2339 | ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k); |
c6229ca6 JR |
2340 | if (ret) |
2341 | return ret; | |
2342 | ||
2343 | iova += PAGE_SIZE; | |
2344 | paddr += PAGE_SIZE; | |
2345 | } | |
2346 | ||
2347 | return 0; | |
2348 | } | |
2349 | ||
eb74ff6c JR |
2350 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2351 | unsigned long iova, size_t size) | |
2352 | { | |
2353 | ||
2354 | struct protection_domain *domain = dom->priv; | |
2355 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2356 | ||
2357 | iova &= PAGE_MASK; | |
2358 | ||
2359 | for (i = 0; i < npages; ++i) { | |
a6b256b4 | 2360 | iommu_unmap_page(domain, iova, PM_MAP_4k); |
eb74ff6c JR |
2361 | iova += PAGE_SIZE; |
2362 | } | |
2363 | ||
601367d7 | 2364 | iommu_flush_tlb_pde(domain); |
eb74ff6c JR |
2365 | } |
2366 | ||
645c4c8d JR |
2367 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2368 | unsigned long iova) | |
2369 | { | |
2370 | struct protection_domain *domain = dom->priv; | |
2371 | unsigned long offset = iova & ~PAGE_MASK; | |
2372 | phys_addr_t paddr; | |
2373 | u64 *pte; | |
2374 | ||
a6b256b4 | 2375 | pte = fetch_pte(domain, iova, PM_MAP_4k); |
645c4c8d | 2376 | |
a6d41a40 | 2377 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2378 | return 0; |
2379 | ||
2380 | paddr = *pte & IOMMU_PAGE_MASK; | |
2381 | paddr |= offset; | |
2382 | ||
2383 | return paddr; | |
2384 | } | |
2385 | ||
dbb9fd86 SY |
2386 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2387 | unsigned long cap) | |
2388 | { | |
2389 | return 0; | |
2390 | } | |
2391 | ||
26961efe JR |
2392 | static struct iommu_ops amd_iommu_ops = { |
2393 | .domain_init = amd_iommu_domain_init, | |
2394 | .domain_destroy = amd_iommu_domain_destroy, | |
2395 | .attach_dev = amd_iommu_attach_device, | |
2396 | .detach_dev = amd_iommu_detach_device, | |
2397 | .map = amd_iommu_map_range, | |
2398 | .unmap = amd_iommu_unmap_range, | |
2399 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2400 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2401 | }; |
2402 | ||
0feae533 JR |
2403 | /***************************************************************************** |
2404 | * | |
2405 | * The next functions do a basic initialization of IOMMU for pass through | |
2406 | * mode | |
2407 | * | |
2408 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2409 | * DMA-API translation. | |
2410 | * | |
2411 | *****************************************************************************/ | |
2412 | ||
2413 | int __init amd_iommu_init_passthrough(void) | |
2414 | { | |
15898bbc | 2415 | struct amd_iommu *iommu; |
0feae533 | 2416 | struct pci_dev *dev = NULL; |
15898bbc | 2417 | u16 devid; |
0feae533 JR |
2418 | |
2419 | /* allocate passthroug domain */ | |
2420 | pt_domain = protection_domain_alloc(); | |
2421 | if (!pt_domain) | |
2422 | return -ENOMEM; | |
2423 | ||
2424 | pt_domain->mode |= PAGE_MODE_NONE; | |
2425 | ||
2426 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
0feae533 | 2427 | |
98fc5a69 | 2428 | if (!check_device(&dev->dev)) |
0feae533 JR |
2429 | continue; |
2430 | ||
98fc5a69 JR |
2431 | devid = get_device_id(&dev->dev); |
2432 | ||
15898bbc | 2433 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2434 | if (!iommu) |
2435 | continue; | |
2436 | ||
15898bbc | 2437 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2438 | } |
2439 | ||
2440 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2441 | ||
2442 | return 0; | |
2443 | } |