Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
23 | #include <linux/scatterlist.h> | |
24 | #include <linux/iommu-helper.h> | |
25 | #include <asm/proto.h> | |
46a7fa27 | 26 | #include <asm/iommu.h> |
1d9b16d1 | 27 | #include <asm/gart.h> |
b6c02715 | 28 | #include <asm/amd_iommu_types.h> |
c6da992e | 29 | #include <asm/amd_iommu.h> |
b6c02715 JR |
30 | |
31 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
32 | ||
136f78a1 JR |
33 | #define EXIT_LOOP_COUNT 10000000 |
34 | ||
b6c02715 JR |
35 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
36 | ||
bd60b735 JR |
37 | /* A list of preallocated protection domains */ |
38 | static LIST_HEAD(iommu_pd_list); | |
39 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
40 | ||
431b2a20 JR |
41 | /* |
42 | * general struct to manage commands send to an IOMMU | |
43 | */ | |
d6449536 | 44 | struct iommu_cmd { |
b6c02715 JR |
45 | u32 data[4]; |
46 | }; | |
47 | ||
bd0e5211 JR |
48 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
49 | struct unity_map_entry *e); | |
50 | ||
431b2a20 | 51 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
52 | static int iommu_has_npcache(struct amd_iommu *iommu) |
53 | { | |
ae9b9403 | 54 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
55 | } |
56 | ||
a80dc3e0 JR |
57 | /**************************************************************************** |
58 | * | |
59 | * Interrupt handling functions | |
60 | * | |
61 | ****************************************************************************/ | |
62 | ||
90008ee4 JR |
63 | static void iommu_print_event(void *__evt) |
64 | { | |
65 | u32 *event = __evt; | |
66 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
67 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
68 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
69 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
70 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
71 | ||
72 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
73 | ||
74 | switch (type) { | |
75 | case EVENT_TYPE_ILL_DEV: | |
76 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
77 | "address=0x%016llx flags=0x%04x]\n", | |
78 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
79 | address, flags); | |
80 | break; | |
81 | case EVENT_TYPE_IO_FAULT: | |
82 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
83 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
84 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
85 | domid, address, flags); | |
86 | break; | |
87 | case EVENT_TYPE_DEV_TAB_ERR: | |
88 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
89 | "address=0x%016llx flags=0x%04x]\n", | |
90 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
91 | address, flags); | |
92 | break; | |
93 | case EVENT_TYPE_PAGE_TAB_ERR: | |
94 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
95 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
96 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
97 | domid, address, flags); | |
98 | break; | |
99 | case EVENT_TYPE_ILL_CMD: | |
100 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
101 | break; | |
102 | case EVENT_TYPE_CMD_HARD_ERR: | |
103 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
104 | "flags=0x%04x]\n", address, flags); | |
105 | break; | |
106 | case EVENT_TYPE_IOTLB_INV_TO: | |
107 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
108 | "address=0x%016llx]\n", | |
109 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
110 | address); | |
111 | break; | |
112 | case EVENT_TYPE_INV_DEV_REQ: | |
113 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
114 | "address=0x%016llx flags=0x%04x]\n", | |
115 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
116 | address, flags); | |
117 | break; | |
118 | default: | |
119 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
120 | } | |
121 | } | |
122 | ||
123 | static void iommu_poll_events(struct amd_iommu *iommu) | |
124 | { | |
125 | u32 head, tail; | |
126 | unsigned long flags; | |
127 | ||
128 | spin_lock_irqsave(&iommu->lock, flags); | |
129 | ||
130 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
131 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
132 | ||
133 | while (head != tail) { | |
134 | iommu_print_event(iommu->evt_buf + head); | |
135 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
136 | } | |
137 | ||
138 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
139 | ||
140 | spin_unlock_irqrestore(&iommu->lock, flags); | |
141 | } | |
142 | ||
a80dc3e0 JR |
143 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
144 | { | |
90008ee4 JR |
145 | struct amd_iommu *iommu; |
146 | ||
147 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
148 | iommu_poll_events(iommu); | |
149 | ||
150 | return IRQ_HANDLED; | |
a80dc3e0 JR |
151 | } |
152 | ||
431b2a20 JR |
153 | /**************************************************************************** |
154 | * | |
155 | * IOMMU command queuing functions | |
156 | * | |
157 | ****************************************************************************/ | |
158 | ||
159 | /* | |
160 | * Writes the command to the IOMMUs command buffer and informs the | |
161 | * hardware about the new command. Must be called with iommu->lock held. | |
162 | */ | |
d6449536 | 163 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
164 | { |
165 | u32 tail, head; | |
166 | u8 *target; | |
167 | ||
168 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 169 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
170 | memcpy_toio(target, cmd, sizeof(*cmd)); |
171 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
172 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
173 | if (tail == head) | |
174 | return -ENOMEM; | |
175 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
431b2a20 JR |
180 | /* |
181 | * General queuing function for commands. Takes iommu->lock and calls | |
182 | * __iommu_queue_command(). | |
183 | */ | |
d6449536 | 184 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
185 | { |
186 | unsigned long flags; | |
187 | int ret; | |
188 | ||
189 | spin_lock_irqsave(&iommu->lock, flags); | |
190 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb JR |
191 | if (!ret) |
192 | iommu->need_sync = 1; | |
a19ae1ec JR |
193 | spin_unlock_irqrestore(&iommu->lock, flags); |
194 | ||
195 | return ret; | |
196 | } | |
197 | ||
8d201968 JR |
198 | /* |
199 | * This function waits until an IOMMU has completed a completion | |
200 | * wait command | |
201 | */ | |
202 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
203 | { | |
204 | int ready = 0; | |
205 | unsigned status = 0; | |
206 | unsigned long i = 0; | |
207 | ||
208 | while (!ready && (i < EXIT_LOOP_COUNT)) { | |
209 | ++i; | |
210 | /* wait for the bit to become one */ | |
211 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
212 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
213 | } | |
214 | ||
215 | /* set bit back to zero */ | |
216 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
217 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
218 | ||
219 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
220 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
221 | } | |
222 | ||
223 | /* | |
224 | * This function queues a completion wait command into the command | |
225 | * buffer of an IOMMU | |
226 | */ | |
227 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
228 | { | |
229 | struct iommu_cmd cmd; | |
230 | ||
231 | memset(&cmd, 0, sizeof(cmd)); | |
232 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
233 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
234 | ||
235 | return __iommu_queue_command(iommu, &cmd); | |
236 | } | |
237 | ||
431b2a20 JR |
238 | /* |
239 | * This function is called whenever we need to ensure that the IOMMU has | |
240 | * completed execution of all commands we sent. It sends a | |
241 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
242 | * us about that by writing a value to a physical address we pass with | |
243 | * the command. | |
244 | */ | |
a19ae1ec JR |
245 | static int iommu_completion_wait(struct amd_iommu *iommu) |
246 | { | |
8d201968 JR |
247 | int ret = 0; |
248 | unsigned long flags; | |
a19ae1ec | 249 | |
7e4f88da JR |
250 | spin_lock_irqsave(&iommu->lock, flags); |
251 | ||
09ee17eb JR |
252 | if (!iommu->need_sync) |
253 | goto out; | |
254 | ||
8d201968 | 255 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 256 | |
8d201968 | 257 | iommu->need_sync = 0; |
a19ae1ec JR |
258 | |
259 | if (ret) | |
7e4f88da | 260 | goto out; |
a19ae1ec | 261 | |
8d201968 | 262 | __iommu_wait_for_completion(iommu); |
84df8175 | 263 | |
7e4f88da JR |
264 | out: |
265 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
266 | |
267 | return 0; | |
268 | } | |
269 | ||
431b2a20 JR |
270 | /* |
271 | * Command send function for invalidating a device table entry | |
272 | */ | |
a19ae1ec JR |
273 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
274 | { | |
d6449536 | 275 | struct iommu_cmd cmd; |
ee2fa743 | 276 | int ret; |
a19ae1ec JR |
277 | |
278 | BUG_ON(iommu == NULL); | |
279 | ||
280 | memset(&cmd, 0, sizeof(cmd)); | |
281 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
282 | cmd.data[0] = devid; | |
283 | ||
ee2fa743 JR |
284 | ret = iommu_queue_command(iommu, &cmd); |
285 | ||
ee2fa743 | 286 | return ret; |
a19ae1ec JR |
287 | } |
288 | ||
237b6f33 JR |
289 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
290 | u16 domid, int pde, int s) | |
291 | { | |
292 | memset(cmd, 0, sizeof(*cmd)); | |
293 | address &= PAGE_MASK; | |
294 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
295 | cmd->data[1] |= domid; | |
296 | cmd->data[2] = lower_32_bits(address); | |
297 | cmd->data[3] = upper_32_bits(address); | |
298 | if (s) /* size bit - we flush more than one 4kb page */ | |
299 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
300 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
301 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
302 | } | |
303 | ||
431b2a20 JR |
304 | /* |
305 | * Generic command send function for invalidaing TLB entries | |
306 | */ | |
a19ae1ec JR |
307 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
308 | u64 address, u16 domid, int pde, int s) | |
309 | { | |
d6449536 | 310 | struct iommu_cmd cmd; |
ee2fa743 | 311 | int ret; |
a19ae1ec | 312 | |
237b6f33 | 313 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 314 | |
ee2fa743 JR |
315 | ret = iommu_queue_command(iommu, &cmd); |
316 | ||
ee2fa743 | 317 | return ret; |
a19ae1ec JR |
318 | } |
319 | ||
431b2a20 JR |
320 | /* |
321 | * TLB invalidation function which is called from the mapping functions. | |
322 | * It invalidates a single PTE if the range to flush is within a single | |
323 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
324 | */ | |
a19ae1ec JR |
325 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
326 | u64 address, size_t size) | |
327 | { | |
999ba417 | 328 | int s = 0; |
e3c449f5 | 329 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
330 | |
331 | address &= PAGE_MASK; | |
332 | ||
999ba417 JR |
333 | if (pages > 1) { |
334 | /* | |
335 | * If we have to flush more than one page, flush all | |
336 | * TLB entries for this domain | |
337 | */ | |
338 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
339 | s = 1; | |
a19ae1ec JR |
340 | } |
341 | ||
999ba417 JR |
342 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
343 | ||
a19ae1ec JR |
344 | return 0; |
345 | } | |
b6c02715 | 346 | |
1c655773 JR |
347 | /* Flush the whole IO/TLB for a given protection domain */ |
348 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
349 | { | |
350 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
351 | ||
352 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); | |
353 | } | |
354 | ||
431b2a20 JR |
355 | /**************************************************************************** |
356 | * | |
357 | * The functions below are used the create the page table mappings for | |
358 | * unity mapped regions. | |
359 | * | |
360 | ****************************************************************************/ | |
361 | ||
362 | /* | |
363 | * Generic mapping functions. It maps a physical address into a DMA | |
364 | * address space. It allocates the page table pages if necessary. | |
365 | * In the future it can be extended to a generic mapping function | |
366 | * supporting all features of AMD IOMMU page tables like level skipping | |
367 | * and full 64 bit address spaces. | |
368 | */ | |
38e817fe JR |
369 | static int iommu_map_page(struct protection_domain *dom, |
370 | unsigned long bus_addr, | |
371 | unsigned long phys_addr, | |
372 | int prot) | |
bd0e5211 JR |
373 | { |
374 | u64 __pte, *pte, *page; | |
375 | ||
376 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 377 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
378 | |
379 | /* only support 512GB address spaces for now */ | |
380 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
381 | return -EINVAL; | |
382 | ||
383 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
384 | ||
385 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
386 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
387 | if (!page) | |
388 | return -ENOMEM; | |
389 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
390 | } | |
391 | ||
392 | pte = IOMMU_PTE_PAGE(*pte); | |
393 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
394 | ||
395 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
396 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
397 | if (!page) | |
398 | return -ENOMEM; | |
399 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
400 | } | |
401 | ||
402 | pte = IOMMU_PTE_PAGE(*pte); | |
403 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
404 | ||
405 | if (IOMMU_PTE_PRESENT(*pte)) | |
406 | return -EBUSY; | |
407 | ||
408 | __pte = phys_addr | IOMMU_PTE_P; | |
409 | if (prot & IOMMU_PROT_IR) | |
410 | __pte |= IOMMU_PTE_IR; | |
411 | if (prot & IOMMU_PROT_IW) | |
412 | __pte |= IOMMU_PTE_IW; | |
413 | ||
414 | *pte = __pte; | |
415 | ||
416 | return 0; | |
417 | } | |
418 | ||
431b2a20 JR |
419 | /* |
420 | * This function checks if a specific unity mapping entry is needed for | |
421 | * this specific IOMMU. | |
422 | */ | |
bd0e5211 JR |
423 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
424 | struct unity_map_entry *entry) | |
425 | { | |
426 | u16 bdf, i; | |
427 | ||
428 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
429 | bdf = amd_iommu_alias_table[i]; | |
430 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
431 | return 1; | |
432 | } | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
431b2a20 JR |
437 | /* |
438 | * Init the unity mappings for a specific IOMMU in the system | |
439 | * | |
440 | * Basically iterates over all unity mapping entries and applies them to | |
441 | * the default domain DMA of that IOMMU if necessary. | |
442 | */ | |
bd0e5211 JR |
443 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
444 | { | |
445 | struct unity_map_entry *entry; | |
446 | int ret; | |
447 | ||
448 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
449 | if (!iommu_for_unity_map(iommu, entry)) | |
450 | continue; | |
451 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
452 | if (ret) | |
453 | return ret; | |
454 | } | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
431b2a20 JR |
459 | /* |
460 | * This function actually applies the mapping to the page table of the | |
461 | * dma_ops domain. | |
462 | */ | |
bd0e5211 JR |
463 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
464 | struct unity_map_entry *e) | |
465 | { | |
466 | u64 addr; | |
467 | int ret; | |
468 | ||
469 | for (addr = e->address_start; addr < e->address_end; | |
470 | addr += PAGE_SIZE) { | |
38e817fe | 471 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
472 | if (ret) |
473 | return ret; | |
474 | /* | |
475 | * if unity mapping is in aperture range mark the page | |
476 | * as allocated in the aperture | |
477 | */ | |
478 | if (addr < dma_dom->aperture_size) | |
479 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
480 | } | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
431b2a20 JR |
485 | /* |
486 | * Inits the unity mappings required for a specific device | |
487 | */ | |
bd0e5211 JR |
488 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
489 | u16 devid) | |
490 | { | |
491 | struct unity_map_entry *e; | |
492 | int ret; | |
493 | ||
494 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
495 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
496 | continue; | |
497 | ret = dma_ops_unity_map(dma_dom, e); | |
498 | if (ret) | |
499 | return ret; | |
500 | } | |
501 | ||
502 | return 0; | |
503 | } | |
504 | ||
431b2a20 JR |
505 | /**************************************************************************** |
506 | * | |
507 | * The next functions belong to the address allocator for the dma_ops | |
508 | * interface functions. They work like the allocators in the other IOMMU | |
509 | * drivers. Its basically a bitmap which marks the allocated pages in | |
510 | * the aperture. Maybe it could be enhanced in the future to a more | |
511 | * efficient allocator. | |
512 | * | |
513 | ****************************************************************************/ | |
d3086444 | 514 | |
431b2a20 JR |
515 | /* |
516 | * The address allocator core function. | |
517 | * | |
518 | * called with domain->lock held | |
519 | */ | |
d3086444 JR |
520 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
521 | struct dma_ops_domain *dom, | |
6d4f343f | 522 | unsigned int pages, |
832a90c3 JR |
523 | unsigned long align_mask, |
524 | u64 dma_mask) | |
d3086444 | 525 | { |
40becd8d | 526 | unsigned long limit; |
d3086444 | 527 | unsigned long address; |
d3086444 JR |
528 | unsigned long boundary_size; |
529 | ||
530 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
531 | PAGE_SIZE) >> PAGE_SHIFT; | |
40becd8d FT |
532 | limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0, |
533 | dma_mask >> PAGE_SHIFT); | |
d3086444 | 534 | |
1c655773 | 535 | if (dom->next_bit >= limit) { |
d3086444 | 536 | dom->next_bit = 0; |
1c655773 JR |
537 | dom->need_flush = true; |
538 | } | |
d3086444 JR |
539 | |
540 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 541 | 0 , boundary_size, align_mask); |
1c655773 | 542 | if (address == -1) { |
d3086444 | 543 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 544 | 0, boundary_size, align_mask); |
1c655773 JR |
545 | dom->need_flush = true; |
546 | } | |
d3086444 JR |
547 | |
548 | if (likely(address != -1)) { | |
d3086444 JR |
549 | dom->next_bit = address + pages; |
550 | address <<= PAGE_SHIFT; | |
551 | } else | |
552 | address = bad_dma_address; | |
553 | ||
554 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
555 | ||
556 | return address; | |
557 | } | |
558 | ||
431b2a20 JR |
559 | /* |
560 | * The address free function. | |
561 | * | |
562 | * called with domain->lock held | |
563 | */ | |
d3086444 JR |
564 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
565 | unsigned long address, | |
566 | unsigned int pages) | |
567 | { | |
568 | address >>= PAGE_SHIFT; | |
569 | iommu_area_free(dom->bitmap, address, pages); | |
80be308d | 570 | |
8501c45c | 571 | if (address >= dom->next_bit) |
80be308d | 572 | dom->need_flush = true; |
d3086444 JR |
573 | } |
574 | ||
431b2a20 JR |
575 | /**************************************************************************** |
576 | * | |
577 | * The next functions belong to the domain allocation. A domain is | |
578 | * allocated for every IOMMU as the default domain. If device isolation | |
579 | * is enabled, every device get its own domain. The most important thing | |
580 | * about domains is the page table mapping the DMA address space they | |
581 | * contain. | |
582 | * | |
583 | ****************************************************************************/ | |
584 | ||
ec487d1a JR |
585 | static u16 domain_id_alloc(void) |
586 | { | |
587 | unsigned long flags; | |
588 | int id; | |
589 | ||
590 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
591 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
592 | BUG_ON(id == 0); | |
593 | if (id > 0 && id < MAX_DOMAIN_ID) | |
594 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
595 | else | |
596 | id = 0; | |
597 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
598 | ||
599 | return id; | |
600 | } | |
601 | ||
a2acfb75 JR |
602 | #ifdef CONFIG_IOMMU_API |
603 | static void domain_id_free(int id) | |
604 | { | |
605 | unsigned long flags; | |
606 | ||
607 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
608 | if (id > 0 && id < MAX_DOMAIN_ID) | |
609 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
610 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
611 | } | |
612 | #endif | |
613 | ||
431b2a20 JR |
614 | /* |
615 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
616 | * ranges. | |
617 | */ | |
ec487d1a JR |
618 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
619 | unsigned long start_page, | |
620 | unsigned int pages) | |
621 | { | |
622 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
623 | ||
624 | if (start_page + pages > last_page) | |
625 | pages = last_page - start_page; | |
626 | ||
d26dbc5c | 627 | iommu_area_reserve(dom->bitmap, start_page, pages); |
ec487d1a JR |
628 | } |
629 | ||
86db2e5d | 630 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
631 | { |
632 | int i, j; | |
633 | u64 *p1, *p2, *p3; | |
634 | ||
86db2e5d | 635 | p1 = domain->pt_root; |
ec487d1a JR |
636 | |
637 | if (!p1) | |
638 | return; | |
639 | ||
640 | for (i = 0; i < 512; ++i) { | |
641 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
642 | continue; | |
643 | ||
644 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 645 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
646 | if (!IOMMU_PTE_PRESENT(p2[j])) |
647 | continue; | |
648 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
649 | free_page((unsigned long)p3); | |
650 | } | |
651 | ||
652 | free_page((unsigned long)p2); | |
653 | } | |
654 | ||
655 | free_page((unsigned long)p1); | |
86db2e5d JR |
656 | |
657 | domain->pt_root = NULL; | |
ec487d1a JR |
658 | } |
659 | ||
431b2a20 JR |
660 | /* |
661 | * Free a domain, only used if something went wrong in the | |
662 | * allocation path and we need to free an already allocated page table | |
663 | */ | |
ec487d1a JR |
664 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
665 | { | |
666 | if (!dom) | |
667 | return; | |
668 | ||
86db2e5d | 669 | free_pagetable(&dom->domain); |
ec487d1a JR |
670 | |
671 | kfree(dom->pte_pages); | |
672 | ||
673 | kfree(dom->bitmap); | |
674 | ||
675 | kfree(dom); | |
676 | } | |
677 | ||
431b2a20 JR |
678 | /* |
679 | * Allocates a new protection domain usable for the dma_ops functions. | |
680 | * It also intializes the page table and the address allocator data | |
681 | * structures required for the dma_ops interface | |
682 | */ | |
ec487d1a JR |
683 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
684 | unsigned order) | |
685 | { | |
686 | struct dma_ops_domain *dma_dom; | |
687 | unsigned i, num_pte_pages; | |
688 | u64 *l2_pde; | |
689 | u64 address; | |
690 | ||
691 | /* | |
692 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
693 | */ | |
694 | if ((order < 25) || (order > 30)) | |
695 | return NULL; | |
696 | ||
697 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
698 | if (!dma_dom) | |
699 | return NULL; | |
700 | ||
701 | spin_lock_init(&dma_dom->domain.lock); | |
702 | ||
703 | dma_dom->domain.id = domain_id_alloc(); | |
704 | if (dma_dom->domain.id == 0) | |
705 | goto free_dma_dom; | |
706 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
707 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
708 | dma_dom->domain.priv = dma_dom; | |
709 | if (!dma_dom->domain.pt_root) | |
710 | goto free_dma_dom; | |
711 | dma_dom->aperture_size = (1ULL << order); | |
712 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
713 | GFP_KERNEL); | |
714 | if (!dma_dom->bitmap) | |
715 | goto free_dma_dom; | |
716 | /* | |
717 | * mark the first page as allocated so we never return 0 as | |
718 | * a valid dma-address. So we can use 0 as error value | |
719 | */ | |
720 | dma_dom->bitmap[0] = 1; | |
721 | dma_dom->next_bit = 0; | |
722 | ||
1c655773 | 723 | dma_dom->need_flush = false; |
bd60b735 | 724 | dma_dom->target_dev = 0xffff; |
1c655773 | 725 | |
431b2a20 | 726 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
727 | if (iommu->exclusion_start && |
728 | iommu->exclusion_start < dma_dom->aperture_size) { | |
729 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
e3c449f5 JR |
730 | int pages = iommu_num_pages(iommu->exclusion_start, |
731 | iommu->exclusion_length, | |
732 | PAGE_SIZE); | |
ec487d1a JR |
733 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
734 | } | |
735 | ||
431b2a20 JR |
736 | /* |
737 | * At the last step, build the page tables so we don't need to | |
738 | * allocate page table pages in the dma_ops mapping/unmapping | |
739 | * path. | |
740 | */ | |
ec487d1a JR |
741 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
742 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
743 | GFP_KERNEL); | |
744 | if (!dma_dom->pte_pages) | |
745 | goto free_dma_dom; | |
746 | ||
747 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
748 | if (l2_pde == NULL) | |
749 | goto free_dma_dom; | |
750 | ||
751 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
752 | ||
753 | for (i = 0; i < num_pte_pages; ++i) { | |
754 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
755 | if (!dma_dom->pte_pages[i]) | |
756 | goto free_dma_dom; | |
757 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
758 | l2_pde[i] = IOMMU_L1_PDE(address); | |
759 | } | |
760 | ||
761 | return dma_dom; | |
762 | ||
763 | free_dma_dom: | |
764 | dma_ops_domain_free(dma_dom); | |
765 | ||
766 | return NULL; | |
767 | } | |
768 | ||
431b2a20 JR |
769 | /* |
770 | * Find out the protection domain structure for a given PCI device. This | |
771 | * will give us the pointer to the page table root for example. | |
772 | */ | |
b20ac0d4 JR |
773 | static struct protection_domain *domain_for_device(u16 devid) |
774 | { | |
775 | struct protection_domain *dom; | |
776 | unsigned long flags; | |
777 | ||
778 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
779 | dom = amd_iommu_pd_table[devid]; | |
780 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
781 | ||
782 | return dom; | |
783 | } | |
784 | ||
431b2a20 JR |
785 | /* |
786 | * If a device is not yet associated with a domain, this function does | |
787 | * assigns it visible for the hardware | |
788 | */ | |
b20ac0d4 JR |
789 | static void set_device_domain(struct amd_iommu *iommu, |
790 | struct protection_domain *domain, | |
791 | u16 devid) | |
792 | { | |
793 | unsigned long flags; | |
794 | ||
795 | u64 pte_root = virt_to_phys(domain->pt_root); | |
796 | ||
38ddf41b JR |
797 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
798 | << DEV_ENTRY_MODE_SHIFT; | |
799 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
800 | |
801 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
802 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
803 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
804 | amd_iommu_dev_table[devid].data[2] = domain->id; |
805 | ||
806 | amd_iommu_pd_table[devid] = domain; | |
807 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
808 | ||
809 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
810 | } |
811 | ||
431b2a20 JR |
812 | /***************************************************************************** |
813 | * | |
814 | * The next functions belong to the dma_ops mapping/unmapping code. | |
815 | * | |
816 | *****************************************************************************/ | |
817 | ||
dbcc112e JR |
818 | /* |
819 | * This function checks if the driver got a valid device from the caller to | |
820 | * avoid dereferencing invalid pointers. | |
821 | */ | |
822 | static bool check_device(struct device *dev) | |
823 | { | |
824 | if (!dev || !dev->dma_mask) | |
825 | return false; | |
826 | ||
827 | return true; | |
828 | } | |
829 | ||
bd60b735 JR |
830 | /* |
831 | * In this function the list of preallocated protection domains is traversed to | |
832 | * find the domain for a specific device | |
833 | */ | |
834 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
835 | { | |
836 | struct dma_ops_domain *entry, *ret = NULL; | |
837 | unsigned long flags; | |
838 | ||
839 | if (list_empty(&iommu_pd_list)) | |
840 | return NULL; | |
841 | ||
842 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
843 | ||
844 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
845 | if (entry->target_dev == devid) { | |
846 | ret = entry; | |
bd60b735 JR |
847 | break; |
848 | } | |
849 | } | |
850 | ||
851 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
852 | ||
853 | return ret; | |
854 | } | |
855 | ||
431b2a20 JR |
856 | /* |
857 | * In the dma_ops path we only have the struct device. This function | |
858 | * finds the corresponding IOMMU, the protection domain and the | |
859 | * requestor id for a given device. | |
860 | * If the device is not yet associated with a domain this is also done | |
861 | * in this function. | |
862 | */ | |
b20ac0d4 JR |
863 | static int get_device_resources(struct device *dev, |
864 | struct amd_iommu **iommu, | |
865 | struct protection_domain **domain, | |
866 | u16 *bdf) | |
867 | { | |
868 | struct dma_ops_domain *dma_dom; | |
869 | struct pci_dev *pcidev; | |
870 | u16 _bdf; | |
871 | ||
dbcc112e JR |
872 | *iommu = NULL; |
873 | *domain = NULL; | |
874 | *bdf = 0xffff; | |
875 | ||
876 | if (dev->bus != &pci_bus_type) | |
877 | return 0; | |
b20ac0d4 JR |
878 | |
879 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 880 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 881 | |
431b2a20 | 882 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 883 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 884 | return 0; |
b20ac0d4 JR |
885 | |
886 | *bdf = amd_iommu_alias_table[_bdf]; | |
887 | ||
888 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
889 | if (*iommu == NULL) | |
890 | return 0; | |
b20ac0d4 JR |
891 | *domain = domain_for_device(*bdf); |
892 | if (*domain == NULL) { | |
bd60b735 JR |
893 | dma_dom = find_protection_domain(*bdf); |
894 | if (!dma_dom) | |
895 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 JR |
896 | *domain = &dma_dom->domain; |
897 | set_device_domain(*iommu, *domain, *bdf); | |
898 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
899 | "device ", (*domain)->id); | |
900 | print_devid(_bdf, 1); | |
901 | } | |
902 | ||
f91ba190 JR |
903 | if (domain_for_device(_bdf) == NULL) |
904 | set_device_domain(*iommu, *domain, _bdf); | |
905 | ||
b20ac0d4 JR |
906 | return 1; |
907 | } | |
908 | ||
431b2a20 JR |
909 | /* |
910 | * This is the generic map function. It maps one 4kb page at paddr to | |
911 | * the given address in the DMA address space for the domain. | |
912 | */ | |
cb76c322 JR |
913 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
914 | struct dma_ops_domain *dom, | |
915 | unsigned long address, | |
916 | phys_addr_t paddr, | |
917 | int direction) | |
918 | { | |
919 | u64 *pte, __pte; | |
920 | ||
921 | WARN_ON(address > dom->aperture_size); | |
922 | ||
923 | paddr &= PAGE_MASK; | |
924 | ||
925 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
926 | pte += IOMMU_PTE_L0_INDEX(address); | |
927 | ||
928 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
929 | ||
930 | if (direction == DMA_TO_DEVICE) | |
931 | __pte |= IOMMU_PTE_IR; | |
932 | else if (direction == DMA_FROM_DEVICE) | |
933 | __pte |= IOMMU_PTE_IW; | |
934 | else if (direction == DMA_BIDIRECTIONAL) | |
935 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
936 | ||
937 | WARN_ON(*pte); | |
938 | ||
939 | *pte = __pte; | |
940 | ||
941 | return (dma_addr_t)address; | |
942 | } | |
943 | ||
431b2a20 JR |
944 | /* |
945 | * The generic unmapping function for on page in the DMA address space. | |
946 | */ | |
cb76c322 JR |
947 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
948 | struct dma_ops_domain *dom, | |
949 | unsigned long address) | |
950 | { | |
951 | u64 *pte; | |
952 | ||
953 | if (address >= dom->aperture_size) | |
954 | return; | |
955 | ||
8ad909c4 | 956 | WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size); |
cb76c322 JR |
957 | |
958 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
959 | pte += IOMMU_PTE_L0_INDEX(address); | |
960 | ||
961 | WARN_ON(!*pte); | |
962 | ||
963 | *pte = 0ULL; | |
964 | } | |
965 | ||
431b2a20 JR |
966 | /* |
967 | * This function contains common code for mapping of a physically | |
24f81160 JR |
968 | * contiguous memory region into DMA address space. It is used by all |
969 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
970 | * Must be called with the domain lock held. |
971 | */ | |
cb76c322 JR |
972 | static dma_addr_t __map_single(struct device *dev, |
973 | struct amd_iommu *iommu, | |
974 | struct dma_ops_domain *dma_dom, | |
975 | phys_addr_t paddr, | |
976 | size_t size, | |
6d4f343f | 977 | int dir, |
832a90c3 JR |
978 | bool align, |
979 | u64 dma_mask) | |
cb76c322 JR |
980 | { |
981 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
982 | dma_addr_t address, start; | |
983 | unsigned int pages; | |
6d4f343f | 984 | unsigned long align_mask = 0; |
cb76c322 JR |
985 | int i; |
986 | ||
e3c449f5 | 987 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
988 | paddr &= PAGE_MASK; |
989 | ||
6d4f343f JR |
990 | if (align) |
991 | align_mask = (1UL << get_order(size)) - 1; | |
992 | ||
832a90c3 JR |
993 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
994 | dma_mask); | |
cb76c322 JR |
995 | if (unlikely(address == bad_dma_address)) |
996 | goto out; | |
997 | ||
998 | start = address; | |
999 | for (i = 0; i < pages; ++i) { | |
1000 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
1001 | paddr += PAGE_SIZE; | |
1002 | start += PAGE_SIZE; | |
1003 | } | |
1004 | address += offset; | |
1005 | ||
afa9fdc2 | 1006 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1007 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1008 | dma_dom->need_flush = false; | |
1009 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1010 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1011 | ||
cb76c322 JR |
1012 | out: |
1013 | return address; | |
1014 | } | |
1015 | ||
431b2a20 JR |
1016 | /* |
1017 | * Does the reverse of the __map_single function. Must be called with | |
1018 | * the domain lock held too | |
1019 | */ | |
cb76c322 JR |
1020 | static void __unmap_single(struct amd_iommu *iommu, |
1021 | struct dma_ops_domain *dma_dom, | |
1022 | dma_addr_t dma_addr, | |
1023 | size_t size, | |
1024 | int dir) | |
1025 | { | |
1026 | dma_addr_t i, start; | |
1027 | unsigned int pages; | |
1028 | ||
b8d9905d JR |
1029 | if ((dma_addr == bad_dma_address) || |
1030 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1031 | return; |
1032 | ||
e3c449f5 | 1033 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1034 | dma_addr &= PAGE_MASK; |
1035 | start = dma_addr; | |
1036 | ||
1037 | for (i = 0; i < pages; ++i) { | |
1038 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1039 | start += PAGE_SIZE; | |
1040 | } | |
1041 | ||
1042 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
270cab24 | 1043 | |
80be308d | 1044 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1045 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1046 | dma_dom->need_flush = false; |
1047 | } | |
cb76c322 JR |
1048 | } |
1049 | ||
431b2a20 JR |
1050 | /* |
1051 | * The exported map_single function for dma_ops. | |
1052 | */ | |
4da70b9e JR |
1053 | static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, |
1054 | size_t size, int dir) | |
1055 | { | |
1056 | unsigned long flags; | |
1057 | struct amd_iommu *iommu; | |
1058 | struct protection_domain *domain; | |
1059 | u16 devid; | |
1060 | dma_addr_t addr; | |
832a90c3 | 1061 | u64 dma_mask; |
4da70b9e | 1062 | |
dbcc112e JR |
1063 | if (!check_device(dev)) |
1064 | return bad_dma_address; | |
1065 | ||
832a90c3 | 1066 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1067 | |
1068 | get_device_resources(dev, &iommu, &domain, &devid); | |
1069 | ||
1070 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1071 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1072 | return (dma_addr_t)paddr; |
1073 | ||
1074 | spin_lock_irqsave(&domain->lock, flags); | |
832a90c3 JR |
1075 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1076 | dma_mask); | |
4da70b9e JR |
1077 | if (addr == bad_dma_address) |
1078 | goto out; | |
1079 | ||
09ee17eb | 1080 | iommu_completion_wait(iommu); |
4da70b9e JR |
1081 | |
1082 | out: | |
1083 | spin_unlock_irqrestore(&domain->lock, flags); | |
1084 | ||
1085 | return addr; | |
1086 | } | |
1087 | ||
431b2a20 JR |
1088 | /* |
1089 | * The exported unmap_single function for dma_ops. | |
1090 | */ | |
4da70b9e JR |
1091 | static void unmap_single(struct device *dev, dma_addr_t dma_addr, |
1092 | size_t size, int dir) | |
1093 | { | |
1094 | unsigned long flags; | |
1095 | struct amd_iommu *iommu; | |
1096 | struct protection_domain *domain; | |
1097 | u16 devid; | |
1098 | ||
dbcc112e JR |
1099 | if (!check_device(dev) || |
1100 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1101 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1102 | return; |
1103 | ||
1104 | spin_lock_irqsave(&domain->lock, flags); | |
1105 | ||
1106 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1107 | ||
09ee17eb | 1108 | iommu_completion_wait(iommu); |
4da70b9e JR |
1109 | |
1110 | spin_unlock_irqrestore(&domain->lock, flags); | |
1111 | } | |
1112 | ||
431b2a20 JR |
1113 | /* |
1114 | * This is a special map_sg function which is used if we should map a | |
1115 | * device which is not handled by an AMD IOMMU in the system. | |
1116 | */ | |
65b050ad JR |
1117 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1118 | int nelems, int dir) | |
1119 | { | |
1120 | struct scatterlist *s; | |
1121 | int i; | |
1122 | ||
1123 | for_each_sg(sglist, s, nelems, i) { | |
1124 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1125 | s->dma_length = s->length; | |
1126 | } | |
1127 | ||
1128 | return nelems; | |
1129 | } | |
1130 | ||
431b2a20 JR |
1131 | /* |
1132 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1133 | * lists). | |
1134 | */ | |
65b050ad JR |
1135 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
1136 | int nelems, int dir) | |
1137 | { | |
1138 | unsigned long flags; | |
1139 | struct amd_iommu *iommu; | |
1140 | struct protection_domain *domain; | |
1141 | u16 devid; | |
1142 | int i; | |
1143 | struct scatterlist *s; | |
1144 | phys_addr_t paddr; | |
1145 | int mapped_elems = 0; | |
832a90c3 | 1146 | u64 dma_mask; |
65b050ad | 1147 | |
dbcc112e JR |
1148 | if (!check_device(dev)) |
1149 | return 0; | |
1150 | ||
832a90c3 | 1151 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1152 | |
1153 | get_device_resources(dev, &iommu, &domain, &devid); | |
1154 | ||
1155 | if (!iommu || !domain) | |
1156 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1157 | ||
1158 | spin_lock_irqsave(&domain->lock, flags); | |
1159 | ||
1160 | for_each_sg(sglist, s, nelems, i) { | |
1161 | paddr = sg_phys(s); | |
1162 | ||
1163 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1164 | paddr, s->length, dir, false, |
1165 | dma_mask); | |
65b050ad JR |
1166 | |
1167 | if (s->dma_address) { | |
1168 | s->dma_length = s->length; | |
1169 | mapped_elems++; | |
1170 | } else | |
1171 | goto unmap; | |
65b050ad JR |
1172 | } |
1173 | ||
09ee17eb | 1174 | iommu_completion_wait(iommu); |
65b050ad JR |
1175 | |
1176 | out: | |
1177 | spin_unlock_irqrestore(&domain->lock, flags); | |
1178 | ||
1179 | return mapped_elems; | |
1180 | unmap: | |
1181 | for_each_sg(sglist, s, mapped_elems, i) { | |
1182 | if (s->dma_address) | |
1183 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1184 | s->dma_length, dir); | |
1185 | s->dma_address = s->dma_length = 0; | |
1186 | } | |
1187 | ||
1188 | mapped_elems = 0; | |
1189 | ||
1190 | goto out; | |
1191 | } | |
1192 | ||
431b2a20 JR |
1193 | /* |
1194 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1195 | * lists). | |
1196 | */ | |
65b050ad JR |
1197 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
1198 | int nelems, int dir) | |
1199 | { | |
1200 | unsigned long flags; | |
1201 | struct amd_iommu *iommu; | |
1202 | struct protection_domain *domain; | |
1203 | struct scatterlist *s; | |
1204 | u16 devid; | |
1205 | int i; | |
1206 | ||
dbcc112e JR |
1207 | if (!check_device(dev) || |
1208 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1209 | return; |
1210 | ||
1211 | spin_lock_irqsave(&domain->lock, flags); | |
1212 | ||
1213 | for_each_sg(sglist, s, nelems, i) { | |
1214 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1215 | s->dma_length, dir); | |
65b050ad JR |
1216 | s->dma_address = s->dma_length = 0; |
1217 | } | |
1218 | ||
09ee17eb | 1219 | iommu_completion_wait(iommu); |
65b050ad JR |
1220 | |
1221 | spin_unlock_irqrestore(&domain->lock, flags); | |
1222 | } | |
1223 | ||
431b2a20 JR |
1224 | /* |
1225 | * The exported alloc_coherent function for dma_ops. | |
1226 | */ | |
5d8b53cf JR |
1227 | static void *alloc_coherent(struct device *dev, size_t size, |
1228 | dma_addr_t *dma_addr, gfp_t flag) | |
1229 | { | |
1230 | unsigned long flags; | |
1231 | void *virt_addr; | |
1232 | struct amd_iommu *iommu; | |
1233 | struct protection_domain *domain; | |
1234 | u16 devid; | |
1235 | phys_addr_t paddr; | |
832a90c3 | 1236 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1237 | |
dbcc112e JR |
1238 | if (!check_device(dev)) |
1239 | return NULL; | |
5d8b53cf | 1240 | |
13d9fead FT |
1241 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1242 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1243 | |
c97ac535 | 1244 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1245 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1246 | if (!virt_addr) | |
1247 | return 0; | |
1248 | ||
5d8b53cf JR |
1249 | paddr = virt_to_phys(virt_addr); |
1250 | ||
5d8b53cf JR |
1251 | if (!iommu || !domain) { |
1252 | *dma_addr = (dma_addr_t)paddr; | |
1253 | return virt_addr; | |
1254 | } | |
1255 | ||
832a90c3 JR |
1256 | if (!dma_mask) |
1257 | dma_mask = *dev->dma_mask; | |
1258 | ||
5d8b53cf JR |
1259 | spin_lock_irqsave(&domain->lock, flags); |
1260 | ||
1261 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1262 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf JR |
1263 | |
1264 | if (*dma_addr == bad_dma_address) { | |
1265 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1266 | virt_addr = NULL; | |
1267 | goto out; | |
1268 | } | |
1269 | ||
09ee17eb | 1270 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1271 | |
1272 | out: | |
1273 | spin_unlock_irqrestore(&domain->lock, flags); | |
1274 | ||
1275 | return virt_addr; | |
1276 | } | |
1277 | ||
431b2a20 JR |
1278 | /* |
1279 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1280 | */ |
5d8b53cf JR |
1281 | static void free_coherent(struct device *dev, size_t size, |
1282 | void *virt_addr, dma_addr_t dma_addr) | |
1283 | { | |
1284 | unsigned long flags; | |
1285 | struct amd_iommu *iommu; | |
1286 | struct protection_domain *domain; | |
1287 | u16 devid; | |
1288 | ||
dbcc112e JR |
1289 | if (!check_device(dev)) |
1290 | return; | |
1291 | ||
5d8b53cf JR |
1292 | get_device_resources(dev, &iommu, &domain, &devid); |
1293 | ||
1294 | if (!iommu || !domain) | |
1295 | goto free_mem; | |
1296 | ||
1297 | spin_lock_irqsave(&domain->lock, flags); | |
1298 | ||
1299 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1300 | |
09ee17eb | 1301 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1302 | |
1303 | spin_unlock_irqrestore(&domain->lock, flags); | |
1304 | ||
1305 | free_mem: | |
1306 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1307 | } | |
1308 | ||
b39ba6ad JR |
1309 | /* |
1310 | * This function is called by the DMA layer to find out if we can handle a | |
1311 | * particular device. It is part of the dma_ops. | |
1312 | */ | |
1313 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1314 | { | |
1315 | u16 bdf; | |
1316 | struct pci_dev *pcidev; | |
1317 | ||
1318 | /* No device or no PCI device */ | |
1319 | if (!dev || dev->bus != &pci_bus_type) | |
1320 | return 0; | |
1321 | ||
1322 | pcidev = to_pci_dev(dev); | |
1323 | ||
1324 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1325 | ||
1326 | /* Out of our scope? */ | |
1327 | if (bdf > amd_iommu_last_bdf) | |
1328 | return 0; | |
1329 | ||
1330 | return 1; | |
1331 | } | |
1332 | ||
c432f3df | 1333 | /* |
431b2a20 JR |
1334 | * The function for pre-allocating protection domains. |
1335 | * | |
c432f3df JR |
1336 | * If the driver core informs the DMA layer if a driver grabs a device |
1337 | * we don't need to preallocate the protection domains anymore. | |
1338 | * For now we have to. | |
1339 | */ | |
1340 | void prealloc_protection_domains(void) | |
1341 | { | |
1342 | struct pci_dev *dev = NULL; | |
1343 | struct dma_ops_domain *dma_dom; | |
1344 | struct amd_iommu *iommu; | |
1345 | int order = amd_iommu_aperture_order; | |
1346 | u16 devid; | |
1347 | ||
1348 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1349 | devid = (dev->bus->number << 8) | dev->devfn; | |
3a61ec38 | 1350 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1351 | continue; |
1352 | devid = amd_iommu_alias_table[devid]; | |
1353 | if (domain_for_device(devid)) | |
1354 | continue; | |
1355 | iommu = amd_iommu_rlookup_table[devid]; | |
1356 | if (!iommu) | |
1357 | continue; | |
1358 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1359 | if (!dma_dom) | |
1360 | continue; | |
1361 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1362 | dma_dom->target_dev = devid; |
1363 | ||
1364 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1365 | } |
1366 | } | |
1367 | ||
6631ee9d JR |
1368 | static struct dma_mapping_ops amd_iommu_dma_ops = { |
1369 | .alloc_coherent = alloc_coherent, | |
1370 | .free_coherent = free_coherent, | |
1371 | .map_single = map_single, | |
1372 | .unmap_single = unmap_single, | |
1373 | .map_sg = map_sg, | |
1374 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1375 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1376 | }; |
1377 | ||
431b2a20 JR |
1378 | /* |
1379 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1380 | */ | |
6631ee9d JR |
1381 | int __init amd_iommu_init_dma_ops(void) |
1382 | { | |
1383 | struct amd_iommu *iommu; | |
1384 | int order = amd_iommu_aperture_order; | |
1385 | int ret; | |
1386 | ||
431b2a20 JR |
1387 | /* |
1388 | * first allocate a default protection domain for every IOMMU we | |
1389 | * found in the system. Devices not assigned to any other | |
1390 | * protection domain will be assigned to the default one. | |
1391 | */ | |
6631ee9d JR |
1392 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1393 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1394 | if (iommu->default_dom == NULL) | |
1395 | return -ENOMEM; | |
1396 | ret = iommu_init_unity_mappings(iommu); | |
1397 | if (ret) | |
1398 | goto free_domains; | |
1399 | } | |
1400 | ||
431b2a20 JR |
1401 | /* |
1402 | * If device isolation is enabled, pre-allocate the protection | |
1403 | * domains for each device. | |
1404 | */ | |
6631ee9d JR |
1405 | if (amd_iommu_isolate) |
1406 | prealloc_protection_domains(); | |
1407 | ||
1408 | iommu_detected = 1; | |
1409 | force_iommu = 1; | |
1410 | bad_dma_address = 0; | |
92af4e29 | 1411 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1412 | gart_iommu_aperture_disabled = 1; |
1413 | gart_iommu_aperture = 0; | |
92af4e29 | 1414 | #endif |
6631ee9d | 1415 | |
431b2a20 | 1416 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1417 | dma_ops = &amd_iommu_dma_ops; |
1418 | ||
1419 | return 0; | |
1420 | ||
1421 | free_domains: | |
1422 | ||
1423 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1424 | if (iommu->default_dom) | |
1425 | dma_ops_domain_free(iommu->default_dom); | |
1426 | } | |
1427 | ||
1428 | return ret; | |
1429 | } |