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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
23 | #include <linux/scatterlist.h> | |
24 | #include <linux/iommu-helper.h> | |
25 | #include <asm/proto.h> | |
46a7fa27 | 26 | #include <asm/iommu.h> |
b6c02715 | 27 | #include <asm/amd_iommu_types.h> |
c6da992e | 28 | #include <asm/amd_iommu.h> |
b6c02715 JR |
29 | |
30 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
31 | ||
136f78a1 JR |
32 | #define EXIT_LOOP_COUNT 10000000 |
33 | ||
b6c02715 JR |
34 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
35 | ||
431b2a20 JR |
36 | /* |
37 | * general struct to manage commands send to an IOMMU | |
38 | */ | |
d6449536 | 39 | struct iommu_cmd { |
b6c02715 JR |
40 | u32 data[4]; |
41 | }; | |
42 | ||
bd0e5211 JR |
43 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
44 | struct unity_map_entry *e); | |
45 | ||
431b2a20 | 46 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
47 | static int iommu_has_npcache(struct amd_iommu *iommu) |
48 | { | |
49 | return iommu->cap & IOMMU_CAP_NPCACHE; | |
50 | } | |
51 | ||
a80dc3e0 JR |
52 | /**************************************************************************** |
53 | * | |
54 | * Interrupt handling functions | |
55 | * | |
56 | ****************************************************************************/ | |
57 | ||
90008ee4 JR |
58 | static void iommu_print_event(void *__evt) |
59 | { | |
60 | u32 *event = __evt; | |
61 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
62 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
63 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
64 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
65 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
66 | ||
67 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
68 | ||
69 | switch (type) { | |
70 | case EVENT_TYPE_ILL_DEV: | |
71 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
72 | "address=0x%016llx flags=0x%04x]\n", | |
73 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
74 | address, flags); | |
75 | break; | |
76 | case EVENT_TYPE_IO_FAULT: | |
77 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
78 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
79 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
80 | domid, address, flags); | |
81 | break; | |
82 | case EVENT_TYPE_DEV_TAB_ERR: | |
83 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
84 | "address=0x%016llx flags=0x%04x]\n", | |
85 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
86 | address, flags); | |
87 | break; | |
88 | case EVENT_TYPE_PAGE_TAB_ERR: | |
89 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
90 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
91 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
92 | domid, address, flags); | |
93 | break; | |
94 | case EVENT_TYPE_ILL_CMD: | |
95 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
96 | break; | |
97 | case EVENT_TYPE_CMD_HARD_ERR: | |
98 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
99 | "flags=0x%04x]\n", address, flags); | |
100 | break; | |
101 | case EVENT_TYPE_IOTLB_INV_TO: | |
102 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
103 | "address=0x%016llx]\n", | |
104 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
105 | address); | |
106 | break; | |
107 | case EVENT_TYPE_INV_DEV_REQ: | |
108 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
109 | "address=0x%016llx flags=0x%04x]\n", | |
110 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
111 | address, flags); | |
112 | break; | |
113 | default: | |
114 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
115 | } | |
116 | } | |
117 | ||
118 | static void iommu_poll_events(struct amd_iommu *iommu) | |
119 | { | |
120 | u32 head, tail; | |
121 | unsigned long flags; | |
122 | ||
123 | spin_lock_irqsave(&iommu->lock, flags); | |
124 | ||
125 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
126 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
127 | ||
128 | while (head != tail) { | |
129 | iommu_print_event(iommu->evt_buf + head); | |
130 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
131 | } | |
132 | ||
133 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
134 | ||
135 | spin_unlock_irqrestore(&iommu->lock, flags); | |
136 | } | |
137 | ||
a80dc3e0 JR |
138 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
139 | { | |
90008ee4 JR |
140 | struct amd_iommu *iommu; |
141 | ||
142 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
143 | iommu_poll_events(iommu); | |
144 | ||
145 | return IRQ_HANDLED; | |
a80dc3e0 JR |
146 | } |
147 | ||
431b2a20 JR |
148 | /**************************************************************************** |
149 | * | |
150 | * IOMMU command queuing functions | |
151 | * | |
152 | ****************************************************************************/ | |
153 | ||
154 | /* | |
155 | * Writes the command to the IOMMUs command buffer and informs the | |
156 | * hardware about the new command. Must be called with iommu->lock held. | |
157 | */ | |
d6449536 | 158 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
159 | { |
160 | u32 tail, head; | |
161 | u8 *target; | |
162 | ||
163 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 164 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
165 | memcpy_toio(target, cmd, sizeof(*cmd)); |
166 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
167 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
168 | if (tail == head) | |
169 | return -ENOMEM; | |
170 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
431b2a20 JR |
175 | /* |
176 | * General queuing function for commands. Takes iommu->lock and calls | |
177 | * __iommu_queue_command(). | |
178 | */ | |
d6449536 | 179 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
180 | { |
181 | unsigned long flags; | |
182 | int ret; | |
183 | ||
184 | spin_lock_irqsave(&iommu->lock, flags); | |
185 | ret = __iommu_queue_command(iommu, cmd); | |
186 | spin_unlock_irqrestore(&iommu->lock, flags); | |
187 | ||
188 | return ret; | |
189 | } | |
190 | ||
431b2a20 JR |
191 | /* |
192 | * This function is called whenever we need to ensure that the IOMMU has | |
193 | * completed execution of all commands we sent. It sends a | |
194 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
195 | * us about that by writing a value to a physical address we pass with | |
196 | * the command. | |
197 | */ | |
a19ae1ec JR |
198 | static int iommu_completion_wait(struct amd_iommu *iommu) |
199 | { | |
519c31ba JR |
200 | int ret, ready = 0; |
201 | unsigned status = 0; | |
d6449536 | 202 | struct iommu_cmd cmd; |
136f78a1 | 203 | unsigned long i = 0; |
a19ae1ec JR |
204 | |
205 | memset(&cmd, 0, sizeof(cmd)); | |
519c31ba | 206 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; |
a19ae1ec JR |
207 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); |
208 | ||
209 | iommu->need_sync = 0; | |
210 | ||
211 | ret = iommu_queue_command(iommu, &cmd); | |
212 | ||
213 | if (ret) | |
214 | return ret; | |
215 | ||
136f78a1 JR |
216 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
217 | ++i; | |
519c31ba JR |
218 | /* wait for the bit to become one */ |
219 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
220 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
136f78a1 JR |
221 | } |
222 | ||
519c31ba JR |
223 | /* set bit back to zero */ |
224 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
225 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
226 | ||
136f78a1 JR |
227 | if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit())) |
228 | printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n"); | |
a19ae1ec JR |
229 | |
230 | return 0; | |
231 | } | |
232 | ||
431b2a20 JR |
233 | /* |
234 | * Command send function for invalidating a device table entry | |
235 | */ | |
a19ae1ec JR |
236 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
237 | { | |
d6449536 | 238 | struct iommu_cmd cmd; |
a19ae1ec JR |
239 | |
240 | BUG_ON(iommu == NULL); | |
241 | ||
242 | memset(&cmd, 0, sizeof(cmd)); | |
243 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
244 | cmd.data[0] = devid; | |
245 | ||
246 | iommu->need_sync = 1; | |
247 | ||
248 | return iommu_queue_command(iommu, &cmd); | |
249 | } | |
250 | ||
431b2a20 JR |
251 | /* |
252 | * Generic command send function for invalidaing TLB entries | |
253 | */ | |
a19ae1ec JR |
254 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
255 | u64 address, u16 domid, int pde, int s) | |
256 | { | |
d6449536 | 257 | struct iommu_cmd cmd; |
a19ae1ec JR |
258 | |
259 | memset(&cmd, 0, sizeof(cmd)); | |
260 | address &= PAGE_MASK; | |
261 | CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES); | |
262 | cmd.data[1] |= domid; | |
8a456695 | 263 | cmd.data[2] = lower_32_bits(address); |
8ea80d78 | 264 | cmd.data[3] = upper_32_bits(address); |
431b2a20 | 265 | if (s) /* size bit - we flush more than one 4kb page */ |
a19ae1ec | 266 | cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; |
431b2a20 | 267 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ |
a19ae1ec JR |
268 | cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
269 | ||
270 | iommu->need_sync = 1; | |
271 | ||
272 | return iommu_queue_command(iommu, &cmd); | |
273 | } | |
274 | ||
431b2a20 JR |
275 | /* |
276 | * TLB invalidation function which is called from the mapping functions. | |
277 | * It invalidates a single PTE if the range to flush is within a single | |
278 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
279 | */ | |
a19ae1ec JR |
280 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
281 | u64 address, size_t size) | |
282 | { | |
999ba417 | 283 | int s = 0; |
a8132e5f | 284 | unsigned pages = iommu_num_pages(address, size); |
a19ae1ec JR |
285 | |
286 | address &= PAGE_MASK; | |
287 | ||
999ba417 JR |
288 | if (pages > 1) { |
289 | /* | |
290 | * If we have to flush more than one page, flush all | |
291 | * TLB entries for this domain | |
292 | */ | |
293 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
294 | s = 1; | |
a19ae1ec JR |
295 | } |
296 | ||
999ba417 JR |
297 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
298 | ||
a19ae1ec JR |
299 | return 0; |
300 | } | |
b6c02715 | 301 | |
1c655773 JR |
302 | /* Flush the whole IO/TLB for a given protection domain */ |
303 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
304 | { | |
305 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
306 | ||
307 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); | |
308 | } | |
309 | ||
431b2a20 JR |
310 | /**************************************************************************** |
311 | * | |
312 | * The functions below are used the create the page table mappings for | |
313 | * unity mapped regions. | |
314 | * | |
315 | ****************************************************************************/ | |
316 | ||
317 | /* | |
318 | * Generic mapping functions. It maps a physical address into a DMA | |
319 | * address space. It allocates the page table pages if necessary. | |
320 | * In the future it can be extended to a generic mapping function | |
321 | * supporting all features of AMD IOMMU page tables like level skipping | |
322 | * and full 64 bit address spaces. | |
323 | */ | |
bd0e5211 JR |
324 | static int iommu_map(struct protection_domain *dom, |
325 | unsigned long bus_addr, | |
326 | unsigned long phys_addr, | |
327 | int prot) | |
328 | { | |
329 | u64 __pte, *pte, *page; | |
330 | ||
331 | bus_addr = PAGE_ALIGN(bus_addr); | |
332 | phys_addr = PAGE_ALIGN(bus_addr); | |
333 | ||
334 | /* only support 512GB address spaces for now */ | |
335 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
336 | return -EINVAL; | |
337 | ||
338 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
339 | ||
340 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
341 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
342 | if (!page) | |
343 | return -ENOMEM; | |
344 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
345 | } | |
346 | ||
347 | pte = IOMMU_PTE_PAGE(*pte); | |
348 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
349 | ||
350 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
351 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
352 | if (!page) | |
353 | return -ENOMEM; | |
354 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
355 | } | |
356 | ||
357 | pte = IOMMU_PTE_PAGE(*pte); | |
358 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
359 | ||
360 | if (IOMMU_PTE_PRESENT(*pte)) | |
361 | return -EBUSY; | |
362 | ||
363 | __pte = phys_addr | IOMMU_PTE_P; | |
364 | if (prot & IOMMU_PROT_IR) | |
365 | __pte |= IOMMU_PTE_IR; | |
366 | if (prot & IOMMU_PROT_IW) | |
367 | __pte |= IOMMU_PTE_IW; | |
368 | ||
369 | *pte = __pte; | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
431b2a20 JR |
374 | /* |
375 | * This function checks if a specific unity mapping entry is needed for | |
376 | * this specific IOMMU. | |
377 | */ | |
bd0e5211 JR |
378 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
379 | struct unity_map_entry *entry) | |
380 | { | |
381 | u16 bdf, i; | |
382 | ||
383 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
384 | bdf = amd_iommu_alias_table[i]; | |
385 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
386 | return 1; | |
387 | } | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
431b2a20 JR |
392 | /* |
393 | * Init the unity mappings for a specific IOMMU in the system | |
394 | * | |
395 | * Basically iterates over all unity mapping entries and applies them to | |
396 | * the default domain DMA of that IOMMU if necessary. | |
397 | */ | |
bd0e5211 JR |
398 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
399 | { | |
400 | struct unity_map_entry *entry; | |
401 | int ret; | |
402 | ||
403 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
404 | if (!iommu_for_unity_map(iommu, entry)) | |
405 | continue; | |
406 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
407 | if (ret) | |
408 | return ret; | |
409 | } | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
431b2a20 JR |
414 | /* |
415 | * This function actually applies the mapping to the page table of the | |
416 | * dma_ops domain. | |
417 | */ | |
bd0e5211 JR |
418 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
419 | struct unity_map_entry *e) | |
420 | { | |
421 | u64 addr; | |
422 | int ret; | |
423 | ||
424 | for (addr = e->address_start; addr < e->address_end; | |
425 | addr += PAGE_SIZE) { | |
426 | ret = iommu_map(&dma_dom->domain, addr, addr, e->prot); | |
427 | if (ret) | |
428 | return ret; | |
429 | /* | |
430 | * if unity mapping is in aperture range mark the page | |
431 | * as allocated in the aperture | |
432 | */ | |
433 | if (addr < dma_dom->aperture_size) | |
434 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
435 | } | |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
431b2a20 JR |
440 | /* |
441 | * Inits the unity mappings required for a specific device | |
442 | */ | |
bd0e5211 JR |
443 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
444 | u16 devid) | |
445 | { | |
446 | struct unity_map_entry *e; | |
447 | int ret; | |
448 | ||
449 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
450 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
451 | continue; | |
452 | ret = dma_ops_unity_map(dma_dom, e); | |
453 | if (ret) | |
454 | return ret; | |
455 | } | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
431b2a20 JR |
460 | /**************************************************************************** |
461 | * | |
462 | * The next functions belong to the address allocator for the dma_ops | |
463 | * interface functions. They work like the allocators in the other IOMMU | |
464 | * drivers. Its basically a bitmap which marks the allocated pages in | |
465 | * the aperture. Maybe it could be enhanced in the future to a more | |
466 | * efficient allocator. | |
467 | * | |
468 | ****************************************************************************/ | |
d3086444 JR |
469 | static unsigned long dma_mask_to_pages(unsigned long mask) |
470 | { | |
471 | return (mask >> PAGE_SHIFT) + | |
472 | (PAGE_ALIGN(mask & ~PAGE_MASK) >> PAGE_SHIFT); | |
473 | } | |
474 | ||
431b2a20 JR |
475 | /* |
476 | * The address allocator core function. | |
477 | * | |
478 | * called with domain->lock held | |
479 | */ | |
d3086444 JR |
480 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
481 | struct dma_ops_domain *dom, | |
6d4f343f JR |
482 | unsigned int pages, |
483 | unsigned long align_mask) | |
d3086444 JR |
484 | { |
485 | unsigned long limit = dma_mask_to_pages(*dev->dma_mask); | |
486 | unsigned long address; | |
487 | unsigned long size = dom->aperture_size >> PAGE_SHIFT; | |
488 | unsigned long boundary_size; | |
489 | ||
490 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
491 | PAGE_SIZE) >> PAGE_SHIFT; | |
492 | limit = limit < size ? limit : size; | |
493 | ||
1c655773 | 494 | if (dom->next_bit >= limit) { |
d3086444 | 495 | dom->next_bit = 0; |
1c655773 JR |
496 | dom->need_flush = true; |
497 | } | |
d3086444 JR |
498 | |
499 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 500 | 0 , boundary_size, align_mask); |
1c655773 | 501 | if (address == -1) { |
d3086444 | 502 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 503 | 0, boundary_size, align_mask); |
1c655773 JR |
504 | dom->need_flush = true; |
505 | } | |
d3086444 JR |
506 | |
507 | if (likely(address != -1)) { | |
d3086444 JR |
508 | dom->next_bit = address + pages; |
509 | address <<= PAGE_SHIFT; | |
510 | } else | |
511 | address = bad_dma_address; | |
512 | ||
513 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
514 | ||
515 | return address; | |
516 | } | |
517 | ||
431b2a20 JR |
518 | /* |
519 | * The address free function. | |
520 | * | |
521 | * called with domain->lock held | |
522 | */ | |
d3086444 JR |
523 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
524 | unsigned long address, | |
525 | unsigned int pages) | |
526 | { | |
527 | address >>= PAGE_SHIFT; | |
528 | iommu_area_free(dom->bitmap, address, pages); | |
529 | } | |
530 | ||
431b2a20 JR |
531 | /**************************************************************************** |
532 | * | |
533 | * The next functions belong to the domain allocation. A domain is | |
534 | * allocated for every IOMMU as the default domain. If device isolation | |
535 | * is enabled, every device get its own domain. The most important thing | |
536 | * about domains is the page table mapping the DMA address space they | |
537 | * contain. | |
538 | * | |
539 | ****************************************************************************/ | |
540 | ||
ec487d1a JR |
541 | static u16 domain_id_alloc(void) |
542 | { | |
543 | unsigned long flags; | |
544 | int id; | |
545 | ||
546 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
547 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
548 | BUG_ON(id == 0); | |
549 | if (id > 0 && id < MAX_DOMAIN_ID) | |
550 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
551 | else | |
552 | id = 0; | |
553 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
554 | ||
555 | return id; | |
556 | } | |
557 | ||
431b2a20 JR |
558 | /* |
559 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
560 | * ranges. | |
561 | */ | |
ec487d1a JR |
562 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
563 | unsigned long start_page, | |
564 | unsigned int pages) | |
565 | { | |
566 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
567 | ||
568 | if (start_page + pages > last_page) | |
569 | pages = last_page - start_page; | |
570 | ||
571 | set_bit_string(dom->bitmap, start_page, pages); | |
572 | } | |
573 | ||
574 | static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom) | |
575 | { | |
576 | int i, j; | |
577 | u64 *p1, *p2, *p3; | |
578 | ||
579 | p1 = dma_dom->domain.pt_root; | |
580 | ||
581 | if (!p1) | |
582 | return; | |
583 | ||
584 | for (i = 0; i < 512; ++i) { | |
585 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
586 | continue; | |
587 | ||
588 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
589 | for (j = 0; j < 512; ++i) { | |
590 | if (!IOMMU_PTE_PRESENT(p2[j])) | |
591 | continue; | |
592 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
593 | free_page((unsigned long)p3); | |
594 | } | |
595 | ||
596 | free_page((unsigned long)p2); | |
597 | } | |
598 | ||
599 | free_page((unsigned long)p1); | |
600 | } | |
601 | ||
431b2a20 JR |
602 | /* |
603 | * Free a domain, only used if something went wrong in the | |
604 | * allocation path and we need to free an already allocated page table | |
605 | */ | |
ec487d1a JR |
606 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
607 | { | |
608 | if (!dom) | |
609 | return; | |
610 | ||
611 | dma_ops_free_pagetable(dom); | |
612 | ||
613 | kfree(dom->pte_pages); | |
614 | ||
615 | kfree(dom->bitmap); | |
616 | ||
617 | kfree(dom); | |
618 | } | |
619 | ||
431b2a20 JR |
620 | /* |
621 | * Allocates a new protection domain usable for the dma_ops functions. | |
622 | * It also intializes the page table and the address allocator data | |
623 | * structures required for the dma_ops interface | |
624 | */ | |
ec487d1a JR |
625 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
626 | unsigned order) | |
627 | { | |
628 | struct dma_ops_domain *dma_dom; | |
629 | unsigned i, num_pte_pages; | |
630 | u64 *l2_pde; | |
631 | u64 address; | |
632 | ||
633 | /* | |
634 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
635 | */ | |
636 | if ((order < 25) || (order > 30)) | |
637 | return NULL; | |
638 | ||
639 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
640 | if (!dma_dom) | |
641 | return NULL; | |
642 | ||
643 | spin_lock_init(&dma_dom->domain.lock); | |
644 | ||
645 | dma_dom->domain.id = domain_id_alloc(); | |
646 | if (dma_dom->domain.id == 0) | |
647 | goto free_dma_dom; | |
648 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
649 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
650 | dma_dom->domain.priv = dma_dom; | |
651 | if (!dma_dom->domain.pt_root) | |
652 | goto free_dma_dom; | |
653 | dma_dom->aperture_size = (1ULL << order); | |
654 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
655 | GFP_KERNEL); | |
656 | if (!dma_dom->bitmap) | |
657 | goto free_dma_dom; | |
658 | /* | |
659 | * mark the first page as allocated so we never return 0 as | |
660 | * a valid dma-address. So we can use 0 as error value | |
661 | */ | |
662 | dma_dom->bitmap[0] = 1; | |
663 | dma_dom->next_bit = 0; | |
664 | ||
1c655773 JR |
665 | dma_dom->need_flush = false; |
666 | ||
431b2a20 | 667 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
668 | if (iommu->exclusion_start && |
669 | iommu->exclusion_start < dma_dom->aperture_size) { | |
670 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
a8132e5f JR |
671 | int pages = iommu_num_pages(iommu->exclusion_start, |
672 | iommu->exclusion_length); | |
ec487d1a JR |
673 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
674 | } | |
675 | ||
431b2a20 JR |
676 | /* |
677 | * At the last step, build the page tables so we don't need to | |
678 | * allocate page table pages in the dma_ops mapping/unmapping | |
679 | * path. | |
680 | */ | |
ec487d1a JR |
681 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
682 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
683 | GFP_KERNEL); | |
684 | if (!dma_dom->pte_pages) | |
685 | goto free_dma_dom; | |
686 | ||
687 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
688 | if (l2_pde == NULL) | |
689 | goto free_dma_dom; | |
690 | ||
691 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
692 | ||
693 | for (i = 0; i < num_pte_pages; ++i) { | |
694 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
695 | if (!dma_dom->pte_pages[i]) | |
696 | goto free_dma_dom; | |
697 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
698 | l2_pde[i] = IOMMU_L1_PDE(address); | |
699 | } | |
700 | ||
701 | return dma_dom; | |
702 | ||
703 | free_dma_dom: | |
704 | dma_ops_domain_free(dma_dom); | |
705 | ||
706 | return NULL; | |
707 | } | |
708 | ||
431b2a20 JR |
709 | /* |
710 | * Find out the protection domain structure for a given PCI device. This | |
711 | * will give us the pointer to the page table root for example. | |
712 | */ | |
b20ac0d4 JR |
713 | static struct protection_domain *domain_for_device(u16 devid) |
714 | { | |
715 | struct protection_domain *dom; | |
716 | unsigned long flags; | |
717 | ||
718 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
719 | dom = amd_iommu_pd_table[devid]; | |
720 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
721 | ||
722 | return dom; | |
723 | } | |
724 | ||
431b2a20 JR |
725 | /* |
726 | * If a device is not yet associated with a domain, this function does | |
727 | * assigns it visible for the hardware | |
728 | */ | |
b20ac0d4 JR |
729 | static void set_device_domain(struct amd_iommu *iommu, |
730 | struct protection_domain *domain, | |
731 | u16 devid) | |
732 | { | |
733 | unsigned long flags; | |
734 | ||
735 | u64 pte_root = virt_to_phys(domain->pt_root); | |
736 | ||
737 | pte_root |= (domain->mode & 0x07) << 9; | |
738 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | 2; | |
739 | ||
740 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
741 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
742 | amd_iommu_dev_table[devid].data[1] = pte_root >> 32; | |
743 | amd_iommu_dev_table[devid].data[2] = domain->id; | |
744 | ||
745 | amd_iommu_pd_table[devid] = domain; | |
746 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
747 | ||
748 | iommu_queue_inv_dev_entry(iommu, devid); | |
749 | ||
750 | iommu->need_sync = 1; | |
751 | } | |
752 | ||
431b2a20 JR |
753 | /***************************************************************************** |
754 | * | |
755 | * The next functions belong to the dma_ops mapping/unmapping code. | |
756 | * | |
757 | *****************************************************************************/ | |
758 | ||
dbcc112e JR |
759 | /* |
760 | * This function checks if the driver got a valid device from the caller to | |
761 | * avoid dereferencing invalid pointers. | |
762 | */ | |
763 | static bool check_device(struct device *dev) | |
764 | { | |
765 | if (!dev || !dev->dma_mask) | |
766 | return false; | |
767 | ||
768 | return true; | |
769 | } | |
770 | ||
431b2a20 JR |
771 | /* |
772 | * In the dma_ops path we only have the struct device. This function | |
773 | * finds the corresponding IOMMU, the protection domain and the | |
774 | * requestor id for a given device. | |
775 | * If the device is not yet associated with a domain this is also done | |
776 | * in this function. | |
777 | */ | |
b20ac0d4 JR |
778 | static int get_device_resources(struct device *dev, |
779 | struct amd_iommu **iommu, | |
780 | struct protection_domain **domain, | |
781 | u16 *bdf) | |
782 | { | |
783 | struct dma_ops_domain *dma_dom; | |
784 | struct pci_dev *pcidev; | |
785 | u16 _bdf; | |
786 | ||
dbcc112e JR |
787 | *iommu = NULL; |
788 | *domain = NULL; | |
789 | *bdf = 0xffff; | |
790 | ||
791 | if (dev->bus != &pci_bus_type) | |
792 | return 0; | |
b20ac0d4 JR |
793 | |
794 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 795 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 796 | |
431b2a20 | 797 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 798 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 799 | return 0; |
b20ac0d4 JR |
800 | |
801 | *bdf = amd_iommu_alias_table[_bdf]; | |
802 | ||
803 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
804 | if (*iommu == NULL) | |
805 | return 0; | |
806 | dma_dom = (*iommu)->default_dom; | |
807 | *domain = domain_for_device(*bdf); | |
808 | if (*domain == NULL) { | |
809 | *domain = &dma_dom->domain; | |
810 | set_device_domain(*iommu, *domain, *bdf); | |
811 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
812 | "device ", (*domain)->id); | |
813 | print_devid(_bdf, 1); | |
814 | } | |
815 | ||
816 | return 1; | |
817 | } | |
818 | ||
431b2a20 JR |
819 | /* |
820 | * This is the generic map function. It maps one 4kb page at paddr to | |
821 | * the given address in the DMA address space for the domain. | |
822 | */ | |
cb76c322 JR |
823 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
824 | struct dma_ops_domain *dom, | |
825 | unsigned long address, | |
826 | phys_addr_t paddr, | |
827 | int direction) | |
828 | { | |
829 | u64 *pte, __pte; | |
830 | ||
831 | WARN_ON(address > dom->aperture_size); | |
832 | ||
833 | paddr &= PAGE_MASK; | |
834 | ||
835 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
836 | pte += IOMMU_PTE_L0_INDEX(address); | |
837 | ||
838 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
839 | ||
840 | if (direction == DMA_TO_DEVICE) | |
841 | __pte |= IOMMU_PTE_IR; | |
842 | else if (direction == DMA_FROM_DEVICE) | |
843 | __pte |= IOMMU_PTE_IW; | |
844 | else if (direction == DMA_BIDIRECTIONAL) | |
845 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
846 | ||
847 | WARN_ON(*pte); | |
848 | ||
849 | *pte = __pte; | |
850 | ||
851 | return (dma_addr_t)address; | |
852 | } | |
853 | ||
431b2a20 JR |
854 | /* |
855 | * The generic unmapping function for on page in the DMA address space. | |
856 | */ | |
cb76c322 JR |
857 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
858 | struct dma_ops_domain *dom, | |
859 | unsigned long address) | |
860 | { | |
861 | u64 *pte; | |
862 | ||
863 | if (address >= dom->aperture_size) | |
864 | return; | |
865 | ||
866 | WARN_ON(address & 0xfffULL || address > dom->aperture_size); | |
867 | ||
868 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
869 | pte += IOMMU_PTE_L0_INDEX(address); | |
870 | ||
871 | WARN_ON(!*pte); | |
872 | ||
873 | *pte = 0ULL; | |
874 | } | |
875 | ||
431b2a20 JR |
876 | /* |
877 | * This function contains common code for mapping of a physically | |
878 | * contiguous memory region into DMA address space. It is uses by all | |
879 | * mapping functions provided by this IOMMU driver. | |
880 | * Must be called with the domain lock held. | |
881 | */ | |
cb76c322 JR |
882 | static dma_addr_t __map_single(struct device *dev, |
883 | struct amd_iommu *iommu, | |
884 | struct dma_ops_domain *dma_dom, | |
885 | phys_addr_t paddr, | |
886 | size_t size, | |
6d4f343f JR |
887 | int dir, |
888 | bool align) | |
cb76c322 JR |
889 | { |
890 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
891 | dma_addr_t address, start; | |
892 | unsigned int pages; | |
6d4f343f | 893 | unsigned long align_mask = 0; |
cb76c322 JR |
894 | int i; |
895 | ||
a8132e5f | 896 | pages = iommu_num_pages(paddr, size); |
cb76c322 JR |
897 | paddr &= PAGE_MASK; |
898 | ||
6d4f343f JR |
899 | if (align) |
900 | align_mask = (1UL << get_order(size)) - 1; | |
901 | ||
902 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask); | |
cb76c322 JR |
903 | if (unlikely(address == bad_dma_address)) |
904 | goto out; | |
905 | ||
906 | start = address; | |
907 | for (i = 0; i < pages; ++i) { | |
908 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
909 | paddr += PAGE_SIZE; | |
910 | start += PAGE_SIZE; | |
911 | } | |
912 | address += offset; | |
913 | ||
1c655773 JR |
914 | if (unlikely(dma_dom->need_flush && !iommu_fullflush)) { |
915 | iommu_flush_tlb(iommu, dma_dom->domain.id); | |
916 | dma_dom->need_flush = false; | |
917 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
918 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
919 | ||
cb76c322 JR |
920 | out: |
921 | return address; | |
922 | } | |
923 | ||
431b2a20 JR |
924 | /* |
925 | * Does the reverse of the __map_single function. Must be called with | |
926 | * the domain lock held too | |
927 | */ | |
cb76c322 JR |
928 | static void __unmap_single(struct amd_iommu *iommu, |
929 | struct dma_ops_domain *dma_dom, | |
930 | dma_addr_t dma_addr, | |
931 | size_t size, | |
932 | int dir) | |
933 | { | |
934 | dma_addr_t i, start; | |
935 | unsigned int pages; | |
936 | ||
937 | if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size)) | |
938 | return; | |
939 | ||
a8132e5f | 940 | pages = iommu_num_pages(dma_addr, size); |
cb76c322 JR |
941 | dma_addr &= PAGE_MASK; |
942 | start = dma_addr; | |
943 | ||
944 | for (i = 0; i < pages; ++i) { | |
945 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
946 | start += PAGE_SIZE; | |
947 | } | |
948 | ||
949 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
270cab24 | 950 | |
1c655773 JR |
951 | if (iommu_fullflush) |
952 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); | |
cb76c322 JR |
953 | } |
954 | ||
431b2a20 JR |
955 | /* |
956 | * The exported map_single function for dma_ops. | |
957 | */ | |
4da70b9e JR |
958 | static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, |
959 | size_t size, int dir) | |
960 | { | |
961 | unsigned long flags; | |
962 | struct amd_iommu *iommu; | |
963 | struct protection_domain *domain; | |
964 | u16 devid; | |
965 | dma_addr_t addr; | |
966 | ||
dbcc112e JR |
967 | if (!check_device(dev)) |
968 | return bad_dma_address; | |
969 | ||
4da70b9e JR |
970 | get_device_resources(dev, &iommu, &domain, &devid); |
971 | ||
972 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 973 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
974 | return (dma_addr_t)paddr; |
975 | ||
976 | spin_lock_irqsave(&domain->lock, flags); | |
6d4f343f | 977 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false); |
4da70b9e JR |
978 | if (addr == bad_dma_address) |
979 | goto out; | |
980 | ||
5507eef8 | 981 | if (unlikely(iommu->need_sync)) |
4da70b9e JR |
982 | iommu_completion_wait(iommu); |
983 | ||
984 | out: | |
985 | spin_unlock_irqrestore(&domain->lock, flags); | |
986 | ||
987 | return addr; | |
988 | } | |
989 | ||
431b2a20 JR |
990 | /* |
991 | * The exported unmap_single function for dma_ops. | |
992 | */ | |
4da70b9e JR |
993 | static void unmap_single(struct device *dev, dma_addr_t dma_addr, |
994 | size_t size, int dir) | |
995 | { | |
996 | unsigned long flags; | |
997 | struct amd_iommu *iommu; | |
998 | struct protection_domain *domain; | |
999 | u16 devid; | |
1000 | ||
dbcc112e JR |
1001 | if (!check_device(dev) || |
1002 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1003 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1004 | return; |
1005 | ||
1006 | spin_lock_irqsave(&domain->lock, flags); | |
1007 | ||
1008 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1009 | ||
5507eef8 | 1010 | if (unlikely(iommu->need_sync)) |
4da70b9e JR |
1011 | iommu_completion_wait(iommu); |
1012 | ||
1013 | spin_unlock_irqrestore(&domain->lock, flags); | |
1014 | } | |
1015 | ||
431b2a20 JR |
1016 | /* |
1017 | * This is a special map_sg function which is used if we should map a | |
1018 | * device which is not handled by an AMD IOMMU in the system. | |
1019 | */ | |
65b050ad JR |
1020 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1021 | int nelems, int dir) | |
1022 | { | |
1023 | struct scatterlist *s; | |
1024 | int i; | |
1025 | ||
1026 | for_each_sg(sglist, s, nelems, i) { | |
1027 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1028 | s->dma_length = s->length; | |
1029 | } | |
1030 | ||
1031 | return nelems; | |
1032 | } | |
1033 | ||
431b2a20 JR |
1034 | /* |
1035 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1036 | * lists). | |
1037 | */ | |
65b050ad JR |
1038 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
1039 | int nelems, int dir) | |
1040 | { | |
1041 | unsigned long flags; | |
1042 | struct amd_iommu *iommu; | |
1043 | struct protection_domain *domain; | |
1044 | u16 devid; | |
1045 | int i; | |
1046 | struct scatterlist *s; | |
1047 | phys_addr_t paddr; | |
1048 | int mapped_elems = 0; | |
1049 | ||
dbcc112e JR |
1050 | if (!check_device(dev)) |
1051 | return 0; | |
1052 | ||
65b050ad JR |
1053 | get_device_resources(dev, &iommu, &domain, &devid); |
1054 | ||
1055 | if (!iommu || !domain) | |
1056 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1057 | ||
1058 | spin_lock_irqsave(&domain->lock, flags); | |
1059 | ||
1060 | for_each_sg(sglist, s, nelems, i) { | |
1061 | paddr = sg_phys(s); | |
1062 | ||
1063 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
6d4f343f | 1064 | paddr, s->length, dir, false); |
65b050ad JR |
1065 | |
1066 | if (s->dma_address) { | |
1067 | s->dma_length = s->length; | |
1068 | mapped_elems++; | |
1069 | } else | |
1070 | goto unmap; | |
65b050ad JR |
1071 | } |
1072 | ||
5507eef8 | 1073 | if (unlikely(iommu->need_sync)) |
65b050ad JR |
1074 | iommu_completion_wait(iommu); |
1075 | ||
1076 | out: | |
1077 | spin_unlock_irqrestore(&domain->lock, flags); | |
1078 | ||
1079 | return mapped_elems; | |
1080 | unmap: | |
1081 | for_each_sg(sglist, s, mapped_elems, i) { | |
1082 | if (s->dma_address) | |
1083 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1084 | s->dma_length, dir); | |
1085 | s->dma_address = s->dma_length = 0; | |
1086 | } | |
1087 | ||
1088 | mapped_elems = 0; | |
1089 | ||
1090 | goto out; | |
1091 | } | |
1092 | ||
431b2a20 JR |
1093 | /* |
1094 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1095 | * lists). | |
1096 | */ | |
65b050ad JR |
1097 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
1098 | int nelems, int dir) | |
1099 | { | |
1100 | unsigned long flags; | |
1101 | struct amd_iommu *iommu; | |
1102 | struct protection_domain *domain; | |
1103 | struct scatterlist *s; | |
1104 | u16 devid; | |
1105 | int i; | |
1106 | ||
dbcc112e JR |
1107 | if (!check_device(dev) || |
1108 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1109 | return; |
1110 | ||
1111 | spin_lock_irqsave(&domain->lock, flags); | |
1112 | ||
1113 | for_each_sg(sglist, s, nelems, i) { | |
1114 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1115 | s->dma_length, dir); | |
65b050ad JR |
1116 | s->dma_address = s->dma_length = 0; |
1117 | } | |
1118 | ||
5507eef8 | 1119 | if (unlikely(iommu->need_sync)) |
65b050ad JR |
1120 | iommu_completion_wait(iommu); |
1121 | ||
1122 | spin_unlock_irqrestore(&domain->lock, flags); | |
1123 | } | |
1124 | ||
431b2a20 JR |
1125 | /* |
1126 | * The exported alloc_coherent function for dma_ops. | |
1127 | */ | |
5d8b53cf JR |
1128 | static void *alloc_coherent(struct device *dev, size_t size, |
1129 | dma_addr_t *dma_addr, gfp_t flag) | |
1130 | { | |
1131 | unsigned long flags; | |
1132 | void *virt_addr; | |
1133 | struct amd_iommu *iommu; | |
1134 | struct protection_domain *domain; | |
1135 | u16 devid; | |
1136 | phys_addr_t paddr; | |
1137 | ||
dbcc112e JR |
1138 | if (!check_device(dev)) |
1139 | return NULL; | |
1140 | ||
5d8b53cf JR |
1141 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1142 | if (!virt_addr) | |
1143 | return 0; | |
1144 | ||
1145 | memset(virt_addr, 0, size); | |
1146 | paddr = virt_to_phys(virt_addr); | |
1147 | ||
1148 | get_device_resources(dev, &iommu, &domain, &devid); | |
1149 | ||
1150 | if (!iommu || !domain) { | |
1151 | *dma_addr = (dma_addr_t)paddr; | |
1152 | return virt_addr; | |
1153 | } | |
1154 | ||
1155 | spin_lock_irqsave(&domain->lock, flags); | |
1156 | ||
1157 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
6d4f343f | 1158 | size, DMA_BIDIRECTIONAL, true); |
5d8b53cf JR |
1159 | |
1160 | if (*dma_addr == bad_dma_address) { | |
1161 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1162 | virt_addr = NULL; | |
1163 | goto out; | |
1164 | } | |
1165 | ||
5507eef8 | 1166 | if (unlikely(iommu->need_sync)) |
5d8b53cf JR |
1167 | iommu_completion_wait(iommu); |
1168 | ||
1169 | out: | |
1170 | spin_unlock_irqrestore(&domain->lock, flags); | |
1171 | ||
1172 | return virt_addr; | |
1173 | } | |
1174 | ||
431b2a20 JR |
1175 | /* |
1176 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1177 | */ |
5d8b53cf JR |
1178 | static void free_coherent(struct device *dev, size_t size, |
1179 | void *virt_addr, dma_addr_t dma_addr) | |
1180 | { | |
1181 | unsigned long flags; | |
1182 | struct amd_iommu *iommu; | |
1183 | struct protection_domain *domain; | |
1184 | u16 devid; | |
1185 | ||
dbcc112e JR |
1186 | if (!check_device(dev)) |
1187 | return; | |
1188 | ||
5d8b53cf JR |
1189 | get_device_resources(dev, &iommu, &domain, &devid); |
1190 | ||
1191 | if (!iommu || !domain) | |
1192 | goto free_mem; | |
1193 | ||
1194 | spin_lock_irqsave(&domain->lock, flags); | |
1195 | ||
1196 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1197 | |
5507eef8 | 1198 | if (unlikely(iommu->need_sync)) |
5d8b53cf JR |
1199 | iommu_completion_wait(iommu); |
1200 | ||
1201 | spin_unlock_irqrestore(&domain->lock, flags); | |
1202 | ||
1203 | free_mem: | |
1204 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1205 | } | |
1206 | ||
c432f3df | 1207 | /* |
431b2a20 JR |
1208 | * The function for pre-allocating protection domains. |
1209 | * | |
c432f3df JR |
1210 | * If the driver core informs the DMA layer if a driver grabs a device |
1211 | * we don't need to preallocate the protection domains anymore. | |
1212 | * For now we have to. | |
1213 | */ | |
1214 | void prealloc_protection_domains(void) | |
1215 | { | |
1216 | struct pci_dev *dev = NULL; | |
1217 | struct dma_ops_domain *dma_dom; | |
1218 | struct amd_iommu *iommu; | |
1219 | int order = amd_iommu_aperture_order; | |
1220 | u16 devid; | |
1221 | ||
1222 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1223 | devid = (dev->bus->number << 8) | dev->devfn; | |
3a61ec38 | 1224 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1225 | continue; |
1226 | devid = amd_iommu_alias_table[devid]; | |
1227 | if (domain_for_device(devid)) | |
1228 | continue; | |
1229 | iommu = amd_iommu_rlookup_table[devid]; | |
1230 | if (!iommu) | |
1231 | continue; | |
1232 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1233 | if (!dma_dom) | |
1234 | continue; | |
1235 | init_unity_mappings_for_device(dma_dom, devid); | |
1236 | set_device_domain(iommu, &dma_dom->domain, devid); | |
1237 | printk(KERN_INFO "AMD IOMMU: Allocated domain %d for device ", | |
1238 | dma_dom->domain.id); | |
1239 | print_devid(devid, 1); | |
1240 | } | |
1241 | } | |
1242 | ||
6631ee9d JR |
1243 | static struct dma_mapping_ops amd_iommu_dma_ops = { |
1244 | .alloc_coherent = alloc_coherent, | |
1245 | .free_coherent = free_coherent, | |
1246 | .map_single = map_single, | |
1247 | .unmap_single = unmap_single, | |
1248 | .map_sg = map_sg, | |
1249 | .unmap_sg = unmap_sg, | |
1250 | }; | |
1251 | ||
431b2a20 JR |
1252 | /* |
1253 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1254 | */ | |
6631ee9d JR |
1255 | int __init amd_iommu_init_dma_ops(void) |
1256 | { | |
1257 | struct amd_iommu *iommu; | |
1258 | int order = amd_iommu_aperture_order; | |
1259 | int ret; | |
1260 | ||
431b2a20 JR |
1261 | /* |
1262 | * first allocate a default protection domain for every IOMMU we | |
1263 | * found in the system. Devices not assigned to any other | |
1264 | * protection domain will be assigned to the default one. | |
1265 | */ | |
6631ee9d JR |
1266 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1267 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1268 | if (iommu->default_dom == NULL) | |
1269 | return -ENOMEM; | |
1270 | ret = iommu_init_unity_mappings(iommu); | |
1271 | if (ret) | |
1272 | goto free_domains; | |
1273 | } | |
1274 | ||
431b2a20 JR |
1275 | /* |
1276 | * If device isolation is enabled, pre-allocate the protection | |
1277 | * domains for each device. | |
1278 | */ | |
6631ee9d JR |
1279 | if (amd_iommu_isolate) |
1280 | prealloc_protection_domains(); | |
1281 | ||
1282 | iommu_detected = 1; | |
1283 | force_iommu = 1; | |
1284 | bad_dma_address = 0; | |
92af4e29 | 1285 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1286 | gart_iommu_aperture_disabled = 1; |
1287 | gart_iommu_aperture = 0; | |
92af4e29 | 1288 | #endif |
6631ee9d | 1289 | |
431b2a20 | 1290 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1291 | dma_ops = &amd_iommu_dma_ops; |
1292 | ||
1293 | return 0; | |
1294 | ||
1295 | free_domains: | |
1296 | ||
1297 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1298 | if (iommu->default_dom) | |
1299 | dma_ops_domain_free(iommu->default_dom); | |
1300 | } | |
1301 | ||
1302 | return ret; | |
1303 | } |