Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
26961efe JR |
44 | #ifdef CONFIG_IOMMU_API |
45 | static struct iommu_ops amd_iommu_ops; | |
46 | #endif | |
47 | ||
431b2a20 JR |
48 | /* |
49 | * general struct to manage commands send to an IOMMU | |
50 | */ | |
d6449536 | 51 | struct iommu_cmd { |
b6c02715 JR |
52 | u32 data[4]; |
53 | }; | |
54 | ||
bd0e5211 JR |
55 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
56 | struct unity_map_entry *e); | |
e275a2a0 | 57 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bda3092 JR |
58 | static u64* alloc_pte(struct protection_domain *dom, |
59 | unsigned long address, u64 | |
60 | **pte_page, gfp_t gfp); | |
00cd122a JR |
61 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
62 | unsigned long start_page, | |
63 | unsigned int pages); | |
a345b23b | 64 | static void reset_iommu_command_buffer(struct amd_iommu *iommu); |
bd0e5211 | 65 | |
c1eee67b CW |
66 | #ifndef BUS_NOTIFY_UNBOUND_DRIVER |
67 | #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005 | |
68 | #endif | |
69 | ||
7f26508b JR |
70 | #ifdef CONFIG_AMD_IOMMU_STATS |
71 | ||
72 | /* | |
73 | * Initialization code for statistics collection | |
74 | */ | |
75 | ||
da49f6df | 76 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 77 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 78 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 79 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 80 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 81 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 82 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 83 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 84 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 85 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 86 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 87 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 88 | |
7f26508b JR |
89 | static struct dentry *stats_dir; |
90 | static struct dentry *de_isolate; | |
91 | static struct dentry *de_fflush; | |
92 | ||
93 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
94 | { | |
95 | if (stats_dir == NULL) | |
96 | return; | |
97 | ||
98 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
99 | &cnt->value); | |
100 | } | |
101 | ||
102 | static void amd_iommu_stats_init(void) | |
103 | { | |
104 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
105 | if (stats_dir == NULL) | |
106 | return; | |
107 | ||
108 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
109 | (u32 *)&amd_iommu_isolate); | |
110 | ||
111 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
112 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
113 | |
114 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 115 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 116 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 117 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 118 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 119 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 120 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 121 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 122 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 123 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 124 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 125 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
126 | } |
127 | ||
128 | #endif | |
129 | ||
431b2a20 | 130 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
131 | static int iommu_has_npcache(struct amd_iommu *iommu) |
132 | { | |
ae9b9403 | 133 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
134 | } |
135 | ||
a80dc3e0 JR |
136 | /**************************************************************************** |
137 | * | |
138 | * Interrupt handling functions | |
139 | * | |
140 | ****************************************************************************/ | |
141 | ||
e3e59876 JR |
142 | static void dump_dte_entry(u16 devid) |
143 | { | |
144 | int i; | |
145 | ||
146 | for (i = 0; i < 8; ++i) | |
147 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
148 | amd_iommu_dev_table[devid].data[i]); | |
149 | } | |
150 | ||
945b4ac4 JR |
151 | static void dump_command(unsigned long phys_addr) |
152 | { | |
153 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
154 | int i; | |
155 | ||
156 | for (i = 0; i < 4; ++i) | |
157 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
158 | } | |
159 | ||
a345b23b | 160 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
161 | { |
162 | u32 *event = __evt; | |
163 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
164 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
165 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
166 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
167 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
168 | ||
169 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
170 | ||
171 | switch (type) { | |
172 | case EVENT_TYPE_ILL_DEV: | |
173 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
174 | "address=0x%016llx flags=0x%04x]\n", | |
175 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
176 | address, flags); | |
e3e59876 | 177 | dump_dte_entry(devid); |
90008ee4 JR |
178 | break; |
179 | case EVENT_TYPE_IO_FAULT: | |
180 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
181 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
182 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
183 | domid, address, flags); | |
184 | break; | |
185 | case EVENT_TYPE_DEV_TAB_ERR: | |
186 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
187 | "address=0x%016llx flags=0x%04x]\n", | |
188 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
189 | address, flags); | |
190 | break; | |
191 | case EVENT_TYPE_PAGE_TAB_ERR: | |
192 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
193 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
194 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
195 | domid, address, flags); | |
196 | break; | |
197 | case EVENT_TYPE_ILL_CMD: | |
198 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
a345b23b | 199 | reset_iommu_command_buffer(iommu); |
945b4ac4 | 200 | dump_command(address); |
90008ee4 JR |
201 | break; |
202 | case EVENT_TYPE_CMD_HARD_ERR: | |
203 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
204 | "flags=0x%04x]\n", address, flags); | |
205 | break; | |
206 | case EVENT_TYPE_IOTLB_INV_TO: | |
207 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
208 | "address=0x%016llx]\n", | |
209 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
210 | address); | |
211 | break; | |
212 | case EVENT_TYPE_INV_DEV_REQ: | |
213 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
214 | "address=0x%016llx flags=0x%04x]\n", | |
215 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
216 | address, flags); | |
217 | break; | |
218 | default: | |
219 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
220 | } | |
221 | } | |
222 | ||
223 | static void iommu_poll_events(struct amd_iommu *iommu) | |
224 | { | |
225 | u32 head, tail; | |
226 | unsigned long flags; | |
227 | ||
228 | spin_lock_irqsave(&iommu->lock, flags); | |
229 | ||
230 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
231 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
232 | ||
233 | while (head != tail) { | |
a345b23b | 234 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
235 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
236 | } | |
237 | ||
238 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
239 | ||
240 | spin_unlock_irqrestore(&iommu->lock, flags); | |
241 | } | |
242 | ||
a80dc3e0 JR |
243 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
244 | { | |
90008ee4 JR |
245 | struct amd_iommu *iommu; |
246 | ||
3bd22172 | 247 | for_each_iommu(iommu) |
90008ee4 JR |
248 | iommu_poll_events(iommu); |
249 | ||
250 | return IRQ_HANDLED; | |
a80dc3e0 JR |
251 | } |
252 | ||
431b2a20 JR |
253 | /**************************************************************************** |
254 | * | |
255 | * IOMMU command queuing functions | |
256 | * | |
257 | ****************************************************************************/ | |
258 | ||
259 | /* | |
260 | * Writes the command to the IOMMUs command buffer and informs the | |
261 | * hardware about the new command. Must be called with iommu->lock held. | |
262 | */ | |
d6449536 | 263 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
264 | { |
265 | u32 tail, head; | |
266 | u8 *target; | |
267 | ||
268 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 269 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
270 | memcpy_toio(target, cmd, sizeof(*cmd)); |
271 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
272 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
273 | if (tail == head) | |
274 | return -ENOMEM; | |
275 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
431b2a20 JR |
280 | /* |
281 | * General queuing function for commands. Takes iommu->lock and calls | |
282 | * __iommu_queue_command(). | |
283 | */ | |
d6449536 | 284 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
285 | { |
286 | unsigned long flags; | |
287 | int ret; | |
288 | ||
289 | spin_lock_irqsave(&iommu->lock, flags); | |
290 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 291 | if (!ret) |
0cfd7aa9 | 292 | iommu->need_sync = true; |
a19ae1ec JR |
293 | spin_unlock_irqrestore(&iommu->lock, flags); |
294 | ||
295 | return ret; | |
296 | } | |
297 | ||
8d201968 JR |
298 | /* |
299 | * This function waits until an IOMMU has completed a completion | |
300 | * wait command | |
301 | */ | |
302 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
303 | { | |
304 | int ready = 0; | |
305 | unsigned status = 0; | |
306 | unsigned long i = 0; | |
307 | ||
da49f6df JR |
308 | INC_STATS_COUNTER(compl_wait); |
309 | ||
8d201968 JR |
310 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
311 | ++i; | |
312 | /* wait for the bit to become one */ | |
313 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
314 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
315 | } | |
316 | ||
317 | /* set bit back to zero */ | |
318 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
319 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
320 | ||
321 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
322 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
323 | } | |
324 | ||
325 | /* | |
326 | * This function queues a completion wait command into the command | |
327 | * buffer of an IOMMU | |
328 | */ | |
329 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
330 | { | |
331 | struct iommu_cmd cmd; | |
332 | ||
333 | memset(&cmd, 0, sizeof(cmd)); | |
334 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
335 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
336 | ||
337 | return __iommu_queue_command(iommu, &cmd); | |
338 | } | |
339 | ||
431b2a20 JR |
340 | /* |
341 | * This function is called whenever we need to ensure that the IOMMU has | |
342 | * completed execution of all commands we sent. It sends a | |
343 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
344 | * us about that by writing a value to a physical address we pass with | |
345 | * the command. | |
346 | */ | |
a19ae1ec JR |
347 | static int iommu_completion_wait(struct amd_iommu *iommu) |
348 | { | |
8d201968 JR |
349 | int ret = 0; |
350 | unsigned long flags; | |
a19ae1ec | 351 | |
7e4f88da JR |
352 | spin_lock_irqsave(&iommu->lock, flags); |
353 | ||
09ee17eb JR |
354 | if (!iommu->need_sync) |
355 | goto out; | |
356 | ||
8d201968 | 357 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 358 | |
0cfd7aa9 | 359 | iommu->need_sync = false; |
a19ae1ec JR |
360 | |
361 | if (ret) | |
7e4f88da | 362 | goto out; |
a19ae1ec | 363 | |
8d201968 | 364 | __iommu_wait_for_completion(iommu); |
84df8175 | 365 | |
7e4f88da JR |
366 | out: |
367 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
368 | |
369 | return 0; | |
370 | } | |
371 | ||
431b2a20 JR |
372 | /* |
373 | * Command send function for invalidating a device table entry | |
374 | */ | |
a19ae1ec JR |
375 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
376 | { | |
d6449536 | 377 | struct iommu_cmd cmd; |
ee2fa743 | 378 | int ret; |
a19ae1ec JR |
379 | |
380 | BUG_ON(iommu == NULL); | |
381 | ||
382 | memset(&cmd, 0, sizeof(cmd)); | |
383 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
384 | cmd.data[0] = devid; | |
385 | ||
ee2fa743 JR |
386 | ret = iommu_queue_command(iommu, &cmd); |
387 | ||
ee2fa743 | 388 | return ret; |
a19ae1ec JR |
389 | } |
390 | ||
237b6f33 JR |
391 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
392 | u16 domid, int pde, int s) | |
393 | { | |
394 | memset(cmd, 0, sizeof(*cmd)); | |
395 | address &= PAGE_MASK; | |
396 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
397 | cmd->data[1] |= domid; | |
398 | cmd->data[2] = lower_32_bits(address); | |
399 | cmd->data[3] = upper_32_bits(address); | |
400 | if (s) /* size bit - we flush more than one 4kb page */ | |
401 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
402 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
403 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
404 | } | |
405 | ||
431b2a20 JR |
406 | /* |
407 | * Generic command send function for invalidaing TLB entries | |
408 | */ | |
a19ae1ec JR |
409 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
410 | u64 address, u16 domid, int pde, int s) | |
411 | { | |
d6449536 | 412 | struct iommu_cmd cmd; |
ee2fa743 | 413 | int ret; |
a19ae1ec | 414 | |
237b6f33 | 415 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 416 | |
ee2fa743 JR |
417 | ret = iommu_queue_command(iommu, &cmd); |
418 | ||
ee2fa743 | 419 | return ret; |
a19ae1ec JR |
420 | } |
421 | ||
431b2a20 JR |
422 | /* |
423 | * TLB invalidation function which is called from the mapping functions. | |
424 | * It invalidates a single PTE if the range to flush is within a single | |
425 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
426 | */ | |
a19ae1ec JR |
427 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
428 | u64 address, size_t size) | |
429 | { | |
999ba417 | 430 | int s = 0; |
e3c449f5 | 431 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
432 | |
433 | address &= PAGE_MASK; | |
434 | ||
999ba417 JR |
435 | if (pages > 1) { |
436 | /* | |
437 | * If we have to flush more than one page, flush all | |
438 | * TLB entries for this domain | |
439 | */ | |
440 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
441 | s = 1; | |
a19ae1ec JR |
442 | } |
443 | ||
999ba417 JR |
444 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
445 | ||
a19ae1ec JR |
446 | return 0; |
447 | } | |
b6c02715 | 448 | |
1c655773 JR |
449 | /* Flush the whole IO/TLB for a given protection domain */ |
450 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
451 | { | |
452 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
453 | ||
f57d98ae JR |
454 | INC_STATS_COUNTER(domain_flush_single); |
455 | ||
1c655773 JR |
456 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
457 | } | |
458 | ||
42a49f96 CW |
459 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
460 | static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid) | |
461 | { | |
462 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
463 | ||
464 | INC_STATS_COUNTER(domain_flush_single); | |
465 | ||
466 | iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1); | |
467 | } | |
468 | ||
43f49609 | 469 | /* |
e394d72a | 470 | * This function flushes one domain on one IOMMU |
43f49609 | 471 | */ |
e394d72a | 472 | static void flush_domain_on_iommu(struct amd_iommu *iommu, u16 domid) |
43f49609 | 473 | { |
43f49609 | 474 | struct iommu_cmd cmd; |
e394d72a | 475 | unsigned long flags; |
18811f55 | 476 | |
43f49609 JR |
477 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
478 | domid, 1, 1); | |
479 | ||
e394d72a JR |
480 | spin_lock_irqsave(&iommu->lock, flags); |
481 | __iommu_queue_command(iommu, &cmd); | |
482 | __iommu_completion_wait(iommu); | |
483 | __iommu_wait_for_completion(iommu); | |
484 | spin_unlock_irqrestore(&iommu->lock, flags); | |
43f49609 | 485 | } |
43f49609 | 486 | |
e394d72a | 487 | static void flush_all_domains_on_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
488 | { |
489 | int i; | |
490 | ||
491 | for (i = 1; i < MAX_DOMAIN_ID; ++i) { | |
492 | if (!test_bit(i, amd_iommu_pd_alloc_bitmap)) | |
493 | continue; | |
e394d72a | 494 | flush_domain_on_iommu(iommu, i); |
bfd1be18 | 495 | } |
e394d72a JR |
496 | |
497 | } | |
498 | ||
499 | /* | |
500 | * This function is used to flush the IO/TLB for a given protection domain | |
501 | * on every IOMMU in the system | |
502 | */ | |
503 | static void iommu_flush_domain(u16 domid) | |
504 | { | |
505 | struct amd_iommu *iommu; | |
506 | ||
507 | INC_STATS_COUNTER(domain_flush_all); | |
508 | ||
509 | for_each_iommu(iommu) | |
510 | flush_domain_on_iommu(iommu, domid); | |
511 | } | |
512 | ||
513 | void amd_iommu_flush_all_domains(void) | |
514 | { | |
515 | struct amd_iommu *iommu; | |
516 | ||
517 | for_each_iommu(iommu) | |
518 | flush_all_domains_on_iommu(iommu); | |
bfd1be18 JR |
519 | } |
520 | ||
d586d785 JR |
521 | static void flush_all_devices_for_iommu(struct amd_iommu *iommu) |
522 | { | |
523 | int i; | |
524 | ||
525 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
526 | if (iommu != amd_iommu_rlookup_table[i]) | |
527 | continue; | |
528 | ||
529 | iommu_queue_inv_dev_entry(iommu, i); | |
530 | iommu_completion_wait(iommu); | |
531 | } | |
532 | } | |
533 | ||
7d7a110c JR |
534 | void amd_iommu_flush_all_devices(void) |
535 | { | |
536 | struct amd_iommu *iommu; | |
537 | int i; | |
538 | ||
539 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
540 | if (amd_iommu_pd_table[i] == NULL) | |
541 | continue; | |
542 | ||
543 | iommu = amd_iommu_rlookup_table[i]; | |
544 | if (!iommu) | |
545 | continue; | |
546 | ||
547 | iommu_queue_inv_dev_entry(iommu, i); | |
548 | iommu_completion_wait(iommu); | |
549 | } | |
550 | } | |
551 | ||
a345b23b JR |
552 | static void reset_iommu_command_buffer(struct amd_iommu *iommu) |
553 | { | |
554 | pr_err("AMD-Vi: Resetting IOMMU command buffer\n"); | |
555 | ||
556 | amd_iommu_reset_cmd_buffer(iommu); | |
557 | flush_all_devices_for_iommu(iommu); | |
558 | flush_all_domains_on_iommu(iommu); | |
559 | } | |
560 | ||
431b2a20 JR |
561 | /**************************************************************************** |
562 | * | |
563 | * The functions below are used the create the page table mappings for | |
564 | * unity mapped regions. | |
565 | * | |
566 | ****************************************************************************/ | |
567 | ||
568 | /* | |
569 | * Generic mapping functions. It maps a physical address into a DMA | |
570 | * address space. It allocates the page table pages if necessary. | |
571 | * In the future it can be extended to a generic mapping function | |
572 | * supporting all features of AMD IOMMU page tables like level skipping | |
573 | * and full 64 bit address spaces. | |
574 | */ | |
38e817fe JR |
575 | static int iommu_map_page(struct protection_domain *dom, |
576 | unsigned long bus_addr, | |
577 | unsigned long phys_addr, | |
578 | int prot) | |
bd0e5211 | 579 | { |
8bda3092 | 580 | u64 __pte, *pte; |
bd0e5211 JR |
581 | |
582 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 583 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
584 | |
585 | /* only support 512GB address spaces for now */ | |
586 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
587 | return -EINVAL; | |
588 | ||
8bda3092 | 589 | pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL); |
bd0e5211 JR |
590 | |
591 | if (IOMMU_PTE_PRESENT(*pte)) | |
592 | return -EBUSY; | |
593 | ||
594 | __pte = phys_addr | IOMMU_PTE_P; | |
595 | if (prot & IOMMU_PROT_IR) | |
596 | __pte |= IOMMU_PTE_IR; | |
597 | if (prot & IOMMU_PROT_IW) | |
598 | __pte |= IOMMU_PTE_IW; | |
599 | ||
600 | *pte = __pte; | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
eb74ff6c JR |
605 | static void iommu_unmap_page(struct protection_domain *dom, |
606 | unsigned long bus_addr) | |
607 | { | |
608 | u64 *pte; | |
609 | ||
610 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
611 | ||
612 | if (!IOMMU_PTE_PRESENT(*pte)) | |
613 | return; | |
614 | ||
615 | pte = IOMMU_PTE_PAGE(*pte); | |
616 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
617 | ||
618 | if (!IOMMU_PTE_PRESENT(*pte)) | |
619 | return; | |
620 | ||
621 | pte = IOMMU_PTE_PAGE(*pte); | |
622 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
623 | ||
624 | *pte = 0; | |
625 | } | |
eb74ff6c | 626 | |
431b2a20 JR |
627 | /* |
628 | * This function checks if a specific unity mapping entry is needed for | |
629 | * this specific IOMMU. | |
630 | */ | |
bd0e5211 JR |
631 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
632 | struct unity_map_entry *entry) | |
633 | { | |
634 | u16 bdf, i; | |
635 | ||
636 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
637 | bdf = amd_iommu_alias_table[i]; | |
638 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
639 | return 1; | |
640 | } | |
641 | ||
642 | return 0; | |
643 | } | |
644 | ||
431b2a20 JR |
645 | /* |
646 | * Init the unity mappings for a specific IOMMU in the system | |
647 | * | |
648 | * Basically iterates over all unity mapping entries and applies them to | |
649 | * the default domain DMA of that IOMMU if necessary. | |
650 | */ | |
bd0e5211 JR |
651 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
652 | { | |
653 | struct unity_map_entry *entry; | |
654 | int ret; | |
655 | ||
656 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
657 | if (!iommu_for_unity_map(iommu, entry)) | |
658 | continue; | |
659 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
660 | if (ret) | |
661 | return ret; | |
662 | } | |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
431b2a20 JR |
667 | /* |
668 | * This function actually applies the mapping to the page table of the | |
669 | * dma_ops domain. | |
670 | */ | |
bd0e5211 JR |
671 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
672 | struct unity_map_entry *e) | |
673 | { | |
674 | u64 addr; | |
675 | int ret; | |
676 | ||
677 | for (addr = e->address_start; addr < e->address_end; | |
678 | addr += PAGE_SIZE) { | |
38e817fe | 679 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
680 | if (ret) |
681 | return ret; | |
682 | /* | |
683 | * if unity mapping is in aperture range mark the page | |
684 | * as allocated in the aperture | |
685 | */ | |
686 | if (addr < dma_dom->aperture_size) | |
c3239567 | 687 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 688 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
689 | } |
690 | ||
691 | return 0; | |
692 | } | |
693 | ||
431b2a20 JR |
694 | /* |
695 | * Inits the unity mappings required for a specific device | |
696 | */ | |
bd0e5211 JR |
697 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
698 | u16 devid) | |
699 | { | |
700 | struct unity_map_entry *e; | |
701 | int ret; | |
702 | ||
703 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
704 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
705 | continue; | |
706 | ret = dma_ops_unity_map(dma_dom, e); | |
707 | if (ret) | |
708 | return ret; | |
709 | } | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
431b2a20 JR |
714 | /**************************************************************************** |
715 | * | |
716 | * The next functions belong to the address allocator for the dma_ops | |
717 | * interface functions. They work like the allocators in the other IOMMU | |
718 | * drivers. Its basically a bitmap which marks the allocated pages in | |
719 | * the aperture. Maybe it could be enhanced in the future to a more | |
720 | * efficient allocator. | |
721 | * | |
722 | ****************************************************************************/ | |
d3086444 | 723 | |
431b2a20 | 724 | /* |
384de729 | 725 | * The address allocator core functions. |
431b2a20 JR |
726 | * |
727 | * called with domain->lock held | |
728 | */ | |
384de729 | 729 | |
00cd122a JR |
730 | /* |
731 | * This function checks if there is a PTE for a given dma address. If | |
732 | * there is one, it returns the pointer to it. | |
733 | */ | |
734 | static u64* fetch_pte(struct protection_domain *domain, | |
735 | unsigned long address) | |
736 | { | |
737 | u64 *pte; | |
738 | ||
739 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
740 | ||
741 | if (!IOMMU_PTE_PRESENT(*pte)) | |
742 | return NULL; | |
743 | ||
744 | pte = IOMMU_PTE_PAGE(*pte); | |
745 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
746 | ||
747 | if (!IOMMU_PTE_PRESENT(*pte)) | |
748 | return NULL; | |
749 | ||
750 | pte = IOMMU_PTE_PAGE(*pte); | |
751 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
752 | ||
753 | return pte; | |
754 | } | |
755 | ||
9cabe89b JR |
756 | /* |
757 | * This function is used to add a new aperture range to an existing | |
758 | * aperture in case of dma_ops domain allocation or address allocation | |
759 | * failure. | |
760 | */ | |
00cd122a JR |
761 | static int alloc_new_range(struct amd_iommu *iommu, |
762 | struct dma_ops_domain *dma_dom, | |
9cabe89b JR |
763 | bool populate, gfp_t gfp) |
764 | { | |
765 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
00cd122a | 766 | int i; |
9cabe89b | 767 | |
f5e9705c JR |
768 | #ifdef CONFIG_IOMMU_STRESS |
769 | populate = false; | |
770 | #endif | |
771 | ||
9cabe89b JR |
772 | if (index >= APERTURE_MAX_RANGES) |
773 | return -ENOMEM; | |
774 | ||
775 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
776 | if (!dma_dom->aperture[index]) | |
777 | return -ENOMEM; | |
778 | ||
779 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
780 | if (!dma_dom->aperture[index]->bitmap) | |
781 | goto out_free; | |
782 | ||
783 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
784 | ||
785 | if (populate) { | |
786 | unsigned long address = dma_dom->aperture_size; | |
787 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
788 | u64 *pte, *pte_page; | |
789 | ||
790 | for (i = 0; i < num_ptes; ++i) { | |
791 | pte = alloc_pte(&dma_dom->domain, address, | |
792 | &pte_page, gfp); | |
793 | if (!pte) | |
794 | goto out_free; | |
795 | ||
796 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
797 | ||
798 | address += APERTURE_RANGE_SIZE / 64; | |
799 | } | |
800 | } | |
801 | ||
802 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
803 | ||
00cd122a JR |
804 | /* Intialize the exclusion range if necessary */ |
805 | if (iommu->exclusion_start && | |
806 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
807 | iommu->exclusion_start < dma_dom->aperture_size) { | |
808 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
809 | int pages = iommu_num_pages(iommu->exclusion_start, | |
810 | iommu->exclusion_length, | |
811 | PAGE_SIZE); | |
812 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
813 | } | |
814 | ||
815 | /* | |
816 | * Check for areas already mapped as present in the new aperture | |
817 | * range and mark those pages as reserved in the allocator. Such | |
818 | * mappings may already exist as a result of requested unity | |
819 | * mappings for devices. | |
820 | */ | |
821 | for (i = dma_dom->aperture[index]->offset; | |
822 | i < dma_dom->aperture_size; | |
823 | i += PAGE_SIZE) { | |
824 | u64 *pte = fetch_pte(&dma_dom->domain, i); | |
825 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) | |
826 | continue; | |
827 | ||
828 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
829 | } | |
830 | ||
9cabe89b JR |
831 | return 0; |
832 | ||
833 | out_free: | |
834 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); | |
835 | ||
836 | kfree(dma_dom->aperture[index]); | |
837 | dma_dom->aperture[index] = NULL; | |
838 | ||
839 | return -ENOMEM; | |
840 | } | |
841 | ||
384de729 JR |
842 | static unsigned long dma_ops_area_alloc(struct device *dev, |
843 | struct dma_ops_domain *dom, | |
844 | unsigned int pages, | |
845 | unsigned long align_mask, | |
846 | u64 dma_mask, | |
847 | unsigned long start) | |
848 | { | |
803b8cb4 | 849 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
850 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
851 | int i = start >> APERTURE_RANGE_SHIFT; | |
852 | unsigned long boundary_size; | |
853 | unsigned long address = -1; | |
854 | unsigned long limit; | |
855 | ||
803b8cb4 JR |
856 | next_bit >>= PAGE_SHIFT; |
857 | ||
384de729 JR |
858 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
859 | PAGE_SIZE) >> PAGE_SHIFT; | |
860 | ||
861 | for (;i < max_index; ++i) { | |
862 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
863 | ||
864 | if (dom->aperture[i]->offset >= dma_mask) | |
865 | break; | |
866 | ||
867 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
868 | dma_mask >> PAGE_SHIFT); | |
869 | ||
870 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
871 | limit, next_bit, pages, 0, | |
872 | boundary_size, align_mask); | |
873 | if (address != -1) { | |
874 | address = dom->aperture[i]->offset + | |
875 | (address << PAGE_SHIFT); | |
803b8cb4 | 876 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
877 | break; |
878 | } | |
879 | ||
880 | next_bit = 0; | |
881 | } | |
882 | ||
883 | return address; | |
884 | } | |
885 | ||
d3086444 JR |
886 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
887 | struct dma_ops_domain *dom, | |
6d4f343f | 888 | unsigned int pages, |
832a90c3 JR |
889 | unsigned long align_mask, |
890 | u64 dma_mask) | |
d3086444 | 891 | { |
d3086444 | 892 | unsigned long address; |
d3086444 | 893 | |
fe16f088 JR |
894 | #ifdef CONFIG_IOMMU_STRESS |
895 | dom->next_address = 0; | |
896 | dom->need_flush = true; | |
897 | #endif | |
d3086444 | 898 | |
384de729 | 899 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 900 | dma_mask, dom->next_address); |
d3086444 | 901 | |
1c655773 | 902 | if (address == -1) { |
803b8cb4 | 903 | dom->next_address = 0; |
384de729 JR |
904 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
905 | dma_mask, 0); | |
1c655773 JR |
906 | dom->need_flush = true; |
907 | } | |
d3086444 | 908 | |
384de729 | 909 | if (unlikely(address == -1)) |
d3086444 JR |
910 | address = bad_dma_address; |
911 | ||
912 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
913 | ||
914 | return address; | |
915 | } | |
916 | ||
431b2a20 JR |
917 | /* |
918 | * The address free function. | |
919 | * | |
920 | * called with domain->lock held | |
921 | */ | |
d3086444 JR |
922 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
923 | unsigned long address, | |
924 | unsigned int pages) | |
925 | { | |
384de729 JR |
926 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
927 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 928 | |
384de729 JR |
929 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
930 | ||
47bccd6b JR |
931 | #ifdef CONFIG_IOMMU_STRESS |
932 | if (i < 4) | |
933 | return; | |
934 | #endif | |
80be308d | 935 | |
803b8cb4 | 936 | if (address >= dom->next_address) |
80be308d | 937 | dom->need_flush = true; |
384de729 JR |
938 | |
939 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 940 | |
384de729 JR |
941 | iommu_area_free(range->bitmap, address, pages); |
942 | ||
d3086444 JR |
943 | } |
944 | ||
431b2a20 JR |
945 | /**************************************************************************** |
946 | * | |
947 | * The next functions belong to the domain allocation. A domain is | |
948 | * allocated for every IOMMU as the default domain. If device isolation | |
949 | * is enabled, every device get its own domain. The most important thing | |
950 | * about domains is the page table mapping the DMA address space they | |
951 | * contain. | |
952 | * | |
953 | ****************************************************************************/ | |
954 | ||
ec487d1a JR |
955 | static u16 domain_id_alloc(void) |
956 | { | |
957 | unsigned long flags; | |
958 | int id; | |
959 | ||
960 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
961 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
962 | BUG_ON(id == 0); | |
963 | if (id > 0 && id < MAX_DOMAIN_ID) | |
964 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
965 | else | |
966 | id = 0; | |
967 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
968 | ||
969 | return id; | |
970 | } | |
971 | ||
a2acfb75 JR |
972 | static void domain_id_free(int id) |
973 | { | |
974 | unsigned long flags; | |
975 | ||
976 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
977 | if (id > 0 && id < MAX_DOMAIN_ID) | |
978 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
979 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
980 | } | |
a2acfb75 | 981 | |
431b2a20 JR |
982 | /* |
983 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
984 | * ranges. | |
985 | */ | |
ec487d1a JR |
986 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
987 | unsigned long start_page, | |
988 | unsigned int pages) | |
989 | { | |
384de729 | 990 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
991 | |
992 | if (start_page + pages > last_page) | |
993 | pages = last_page - start_page; | |
994 | ||
384de729 JR |
995 | for (i = start_page; i < start_page + pages; ++i) { |
996 | int index = i / APERTURE_RANGE_PAGES; | |
997 | int page = i % APERTURE_RANGE_PAGES; | |
998 | __set_bit(page, dom->aperture[index]->bitmap); | |
999 | } | |
ec487d1a JR |
1000 | } |
1001 | ||
86db2e5d | 1002 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1003 | { |
1004 | int i, j; | |
1005 | u64 *p1, *p2, *p3; | |
1006 | ||
86db2e5d | 1007 | p1 = domain->pt_root; |
ec487d1a JR |
1008 | |
1009 | if (!p1) | |
1010 | return; | |
1011 | ||
1012 | for (i = 0; i < 512; ++i) { | |
1013 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1014 | continue; | |
1015 | ||
1016 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1017 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1018 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1019 | continue; | |
1020 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1021 | free_page((unsigned long)p3); | |
1022 | } | |
1023 | ||
1024 | free_page((unsigned long)p2); | |
1025 | } | |
1026 | ||
1027 | free_page((unsigned long)p1); | |
86db2e5d JR |
1028 | |
1029 | domain->pt_root = NULL; | |
ec487d1a JR |
1030 | } |
1031 | ||
431b2a20 JR |
1032 | /* |
1033 | * Free a domain, only used if something went wrong in the | |
1034 | * allocation path and we need to free an already allocated page table | |
1035 | */ | |
ec487d1a JR |
1036 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1037 | { | |
384de729 JR |
1038 | int i; |
1039 | ||
ec487d1a JR |
1040 | if (!dom) |
1041 | return; | |
1042 | ||
86db2e5d | 1043 | free_pagetable(&dom->domain); |
ec487d1a | 1044 | |
384de729 JR |
1045 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1046 | if (!dom->aperture[i]) | |
1047 | continue; | |
1048 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1049 | kfree(dom->aperture[i]); | |
1050 | } | |
ec487d1a JR |
1051 | |
1052 | kfree(dom); | |
1053 | } | |
1054 | ||
431b2a20 JR |
1055 | /* |
1056 | * Allocates a new protection domain usable for the dma_ops functions. | |
1057 | * It also intializes the page table and the address allocator data | |
1058 | * structures required for the dma_ops interface | |
1059 | */ | |
d9cfed92 | 1060 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
1061 | { |
1062 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1063 | |
1064 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1065 | if (!dma_dom) | |
1066 | return NULL; | |
1067 | ||
1068 | spin_lock_init(&dma_dom->domain.lock); | |
1069 | ||
1070 | dma_dom->domain.id = domain_id_alloc(); | |
1071 | if (dma_dom->domain.id == 0) | |
1072 | goto free_dma_dom; | |
1073 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
1074 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 1075 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1076 | dma_dom->domain.priv = dma_dom; |
1077 | if (!dma_dom->domain.pt_root) | |
1078 | goto free_dma_dom; | |
ec487d1a | 1079 | |
1c655773 | 1080 | dma_dom->need_flush = false; |
bd60b735 | 1081 | dma_dom->target_dev = 0xffff; |
1c655773 | 1082 | |
00cd122a | 1083 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1084 | goto free_dma_dom; |
ec487d1a | 1085 | |
431b2a20 | 1086 | /* |
ec487d1a JR |
1087 | * mark the first page as allocated so we never return 0 as |
1088 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1089 | */ |
384de729 | 1090 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1091 | dma_dom->next_address = 0; |
ec487d1a | 1092 | |
ec487d1a JR |
1093 | |
1094 | return dma_dom; | |
1095 | ||
1096 | free_dma_dom: | |
1097 | dma_ops_domain_free(dma_dom); | |
1098 | ||
1099 | return NULL; | |
1100 | } | |
1101 | ||
5b28df6f JR |
1102 | /* |
1103 | * little helper function to check whether a given protection domain is a | |
1104 | * dma_ops domain | |
1105 | */ | |
1106 | static bool dma_ops_domain(struct protection_domain *domain) | |
1107 | { | |
1108 | return domain->flags & PD_DMA_OPS_MASK; | |
1109 | } | |
1110 | ||
431b2a20 JR |
1111 | /* |
1112 | * Find out the protection domain structure for a given PCI device. This | |
1113 | * will give us the pointer to the page table root for example. | |
1114 | */ | |
b20ac0d4 JR |
1115 | static struct protection_domain *domain_for_device(u16 devid) |
1116 | { | |
1117 | struct protection_domain *dom; | |
1118 | unsigned long flags; | |
1119 | ||
1120 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1121 | dom = amd_iommu_pd_table[devid]; | |
1122 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1123 | ||
1124 | return dom; | |
1125 | } | |
1126 | ||
431b2a20 JR |
1127 | /* |
1128 | * If a device is not yet associated with a domain, this function does | |
1129 | * assigns it visible for the hardware | |
1130 | */ | |
f1179dc0 JR |
1131 | static void attach_device(struct amd_iommu *iommu, |
1132 | struct protection_domain *domain, | |
1133 | u16 devid) | |
b20ac0d4 JR |
1134 | { |
1135 | unsigned long flags; | |
b20ac0d4 JR |
1136 | u64 pte_root = virt_to_phys(domain->pt_root); |
1137 | ||
863c74eb JR |
1138 | domain->dev_cnt += 1; |
1139 | ||
38ddf41b JR |
1140 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1141 | << DEV_ENTRY_MODE_SHIFT; | |
1142 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
1143 | |
1144 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
1145 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
1146 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
1147 | amd_iommu_dev_table[devid].data[2] = domain->id; |
1148 | ||
1149 | amd_iommu_pd_table[devid] = domain; | |
1150 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1151 | ||
42a49f96 CW |
1152 | /* |
1153 | * We might boot into a crash-kernel here. The crashed kernel | |
1154 | * left the caches in the IOMMU dirty. So we have to flush | |
1155 | * here to evict all dirty stuff. | |
1156 | */ | |
b20ac0d4 | 1157 | iommu_queue_inv_dev_entry(iommu, devid); |
42a49f96 | 1158 | iommu_flush_tlb_pde(iommu, domain->id); |
b20ac0d4 JR |
1159 | } |
1160 | ||
355bf553 JR |
1161 | /* |
1162 | * Removes a device from a protection domain (unlocked) | |
1163 | */ | |
1164 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1165 | { | |
1166 | ||
1167 | /* lock domain */ | |
1168 | spin_lock(&domain->lock); | |
1169 | ||
1170 | /* remove domain from the lookup table */ | |
1171 | amd_iommu_pd_table[devid] = NULL; | |
1172 | ||
1173 | /* remove entry from the device table seen by the hardware */ | |
1174 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1175 | amd_iommu_dev_table[devid].data[1] = 0; | |
1176 | amd_iommu_dev_table[devid].data[2] = 0; | |
1177 | ||
1178 | /* decrease reference counter */ | |
1179 | domain->dev_cnt -= 1; | |
1180 | ||
1181 | /* ready */ | |
1182 | spin_unlock(&domain->lock); | |
1183 | } | |
1184 | ||
1185 | /* | |
1186 | * Removes a device from a protection domain (with devtable_lock held) | |
1187 | */ | |
1188 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1189 | { | |
1190 | unsigned long flags; | |
1191 | ||
1192 | /* lock device table */ | |
1193 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1194 | __detach_device(domain, devid); | |
1195 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1196 | } | |
e275a2a0 JR |
1197 | |
1198 | static int device_change_notifier(struct notifier_block *nb, | |
1199 | unsigned long action, void *data) | |
1200 | { | |
1201 | struct device *dev = data; | |
1202 | struct pci_dev *pdev = to_pci_dev(dev); | |
1203 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1204 | struct protection_domain *domain; | |
1205 | struct dma_ops_domain *dma_domain; | |
1206 | struct amd_iommu *iommu; | |
1ac4cbbc | 1207 | unsigned long flags; |
e275a2a0 JR |
1208 | |
1209 | if (devid > amd_iommu_last_bdf) | |
1210 | goto out; | |
1211 | ||
1212 | devid = amd_iommu_alias_table[devid]; | |
1213 | ||
1214 | iommu = amd_iommu_rlookup_table[devid]; | |
1215 | if (iommu == NULL) | |
1216 | goto out; | |
1217 | ||
1218 | domain = domain_for_device(devid); | |
1219 | ||
1220 | if (domain && !dma_ops_domain(domain)) | |
1221 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1222 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1223 | ||
1224 | switch (action) { | |
c1eee67b | 1225 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1226 | if (!domain) |
1227 | goto out; | |
1228 | detach_device(domain, devid); | |
1ac4cbbc JR |
1229 | break; |
1230 | case BUS_NOTIFY_ADD_DEVICE: | |
1231 | /* allocate a protection domain if a device is added */ | |
1232 | dma_domain = find_protection_domain(devid); | |
1233 | if (dma_domain) | |
1234 | goto out; | |
d9cfed92 | 1235 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1236 | if (!dma_domain) |
1237 | goto out; | |
1238 | dma_domain->target_dev = devid; | |
1239 | ||
1240 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1241 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1242 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1243 | ||
e275a2a0 JR |
1244 | break; |
1245 | default: | |
1246 | goto out; | |
1247 | } | |
1248 | ||
1249 | iommu_queue_inv_dev_entry(iommu, devid); | |
1250 | iommu_completion_wait(iommu); | |
1251 | ||
1252 | out: | |
1253 | return 0; | |
1254 | } | |
1255 | ||
b25ae679 | 1256 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1257 | .notifier_call = device_change_notifier, |
1258 | }; | |
355bf553 | 1259 | |
431b2a20 JR |
1260 | /***************************************************************************** |
1261 | * | |
1262 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1263 | * | |
1264 | *****************************************************************************/ | |
1265 | ||
dbcc112e JR |
1266 | /* |
1267 | * This function checks if the driver got a valid device from the caller to | |
1268 | * avoid dereferencing invalid pointers. | |
1269 | */ | |
1270 | static bool check_device(struct device *dev) | |
1271 | { | |
1272 | if (!dev || !dev->dma_mask) | |
1273 | return false; | |
1274 | ||
1275 | return true; | |
1276 | } | |
1277 | ||
bd60b735 JR |
1278 | /* |
1279 | * In this function the list of preallocated protection domains is traversed to | |
1280 | * find the domain for a specific device | |
1281 | */ | |
1282 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1283 | { | |
1284 | struct dma_ops_domain *entry, *ret = NULL; | |
1285 | unsigned long flags; | |
1286 | ||
1287 | if (list_empty(&iommu_pd_list)) | |
1288 | return NULL; | |
1289 | ||
1290 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1291 | ||
1292 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1293 | if (entry->target_dev == devid) { | |
1294 | ret = entry; | |
bd60b735 JR |
1295 | break; |
1296 | } | |
1297 | } | |
1298 | ||
1299 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1300 | ||
1301 | return ret; | |
1302 | } | |
1303 | ||
431b2a20 JR |
1304 | /* |
1305 | * In the dma_ops path we only have the struct device. This function | |
1306 | * finds the corresponding IOMMU, the protection domain and the | |
1307 | * requestor id for a given device. | |
1308 | * If the device is not yet associated with a domain this is also done | |
1309 | * in this function. | |
1310 | */ | |
b20ac0d4 JR |
1311 | static int get_device_resources(struct device *dev, |
1312 | struct amd_iommu **iommu, | |
1313 | struct protection_domain **domain, | |
1314 | u16 *bdf) | |
1315 | { | |
1316 | struct dma_ops_domain *dma_dom; | |
1317 | struct pci_dev *pcidev; | |
1318 | u16 _bdf; | |
1319 | ||
dbcc112e JR |
1320 | *iommu = NULL; |
1321 | *domain = NULL; | |
1322 | *bdf = 0xffff; | |
1323 | ||
1324 | if (dev->bus != &pci_bus_type) | |
1325 | return 0; | |
b20ac0d4 JR |
1326 | |
1327 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1328 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1329 | |
431b2a20 | 1330 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1331 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1332 | return 0; |
b20ac0d4 JR |
1333 | |
1334 | *bdf = amd_iommu_alias_table[_bdf]; | |
1335 | ||
1336 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1337 | if (*iommu == NULL) | |
1338 | return 0; | |
b20ac0d4 JR |
1339 | *domain = domain_for_device(*bdf); |
1340 | if (*domain == NULL) { | |
bd60b735 JR |
1341 | dma_dom = find_protection_domain(*bdf); |
1342 | if (!dma_dom) | |
1343 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1344 | *domain = &dma_dom->domain; |
f1179dc0 | 1345 | attach_device(*iommu, *domain, *bdf); |
e9a22a13 JR |
1346 | DUMP_printk("Using protection domain %d for device %s\n", |
1347 | (*domain)->id, dev_name(dev)); | |
b20ac0d4 JR |
1348 | } |
1349 | ||
f91ba190 | 1350 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1351 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1352 | |
b20ac0d4 JR |
1353 | return 1; |
1354 | } | |
1355 | ||
8bda3092 JR |
1356 | /* |
1357 | * If the pte_page is not yet allocated this function is called | |
1358 | */ | |
1359 | static u64* alloc_pte(struct protection_domain *dom, | |
1360 | unsigned long address, u64 **pte_page, gfp_t gfp) | |
1361 | { | |
1362 | u64 *pte, *page; | |
1363 | ||
1364 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
1365 | ||
1366 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1367 | page = (u64 *)get_zeroed_page(gfp); | |
1368 | if (!page) | |
1369 | return NULL; | |
1370 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
1371 | } | |
1372 | ||
1373 | pte = IOMMU_PTE_PAGE(*pte); | |
1374 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
1375 | ||
1376 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1377 | page = (u64 *)get_zeroed_page(gfp); | |
1378 | if (!page) | |
1379 | return NULL; | |
1380 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
1381 | } | |
1382 | ||
1383 | pte = IOMMU_PTE_PAGE(*pte); | |
1384 | ||
1385 | if (pte_page) | |
1386 | *pte_page = pte; | |
1387 | ||
1388 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
1389 | ||
1390 | return pte; | |
1391 | } | |
1392 | ||
1393 | /* | |
1394 | * This function fetches the PTE for a given address in the aperture | |
1395 | */ | |
1396 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1397 | unsigned long address) | |
1398 | { | |
384de729 | 1399 | struct aperture_range *aperture; |
8bda3092 JR |
1400 | u64 *pte, *pte_page; |
1401 | ||
384de729 JR |
1402 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1403 | if (!aperture) | |
1404 | return NULL; | |
1405 | ||
1406 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 JR |
1407 | if (!pte) { |
1408 | pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC); | |
384de729 JR |
1409 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1410 | } else | |
1411 | pte += IOMMU_PTE_L0_INDEX(address); | |
8bda3092 JR |
1412 | |
1413 | return pte; | |
1414 | } | |
1415 | ||
431b2a20 JR |
1416 | /* |
1417 | * This is the generic map function. It maps one 4kb page at paddr to | |
1418 | * the given address in the DMA address space for the domain. | |
1419 | */ | |
cb76c322 JR |
1420 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1421 | struct dma_ops_domain *dom, | |
1422 | unsigned long address, | |
1423 | phys_addr_t paddr, | |
1424 | int direction) | |
1425 | { | |
1426 | u64 *pte, __pte; | |
1427 | ||
1428 | WARN_ON(address > dom->aperture_size); | |
1429 | ||
1430 | paddr &= PAGE_MASK; | |
1431 | ||
8bda3092 | 1432 | pte = dma_ops_get_pte(dom, address); |
53812c11 JR |
1433 | if (!pte) |
1434 | return bad_dma_address; | |
cb76c322 JR |
1435 | |
1436 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1437 | ||
1438 | if (direction == DMA_TO_DEVICE) | |
1439 | __pte |= IOMMU_PTE_IR; | |
1440 | else if (direction == DMA_FROM_DEVICE) | |
1441 | __pte |= IOMMU_PTE_IW; | |
1442 | else if (direction == DMA_BIDIRECTIONAL) | |
1443 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1444 | ||
1445 | WARN_ON(*pte); | |
1446 | ||
1447 | *pte = __pte; | |
1448 | ||
1449 | return (dma_addr_t)address; | |
1450 | } | |
1451 | ||
431b2a20 JR |
1452 | /* |
1453 | * The generic unmapping function for on page in the DMA address space. | |
1454 | */ | |
cb76c322 JR |
1455 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1456 | struct dma_ops_domain *dom, | |
1457 | unsigned long address) | |
1458 | { | |
384de729 | 1459 | struct aperture_range *aperture; |
cb76c322 JR |
1460 | u64 *pte; |
1461 | ||
1462 | if (address >= dom->aperture_size) | |
1463 | return; | |
1464 | ||
384de729 JR |
1465 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1466 | if (!aperture) | |
1467 | return; | |
1468 | ||
1469 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1470 | if (!pte) | |
1471 | return; | |
cb76c322 | 1472 | |
cb76c322 JR |
1473 | pte += IOMMU_PTE_L0_INDEX(address); |
1474 | ||
1475 | WARN_ON(!*pte); | |
1476 | ||
1477 | *pte = 0ULL; | |
1478 | } | |
1479 | ||
431b2a20 JR |
1480 | /* |
1481 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1482 | * contiguous memory region into DMA address space. It is used by all |
1483 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1484 | * Must be called with the domain lock held. |
1485 | */ | |
cb76c322 JR |
1486 | static dma_addr_t __map_single(struct device *dev, |
1487 | struct amd_iommu *iommu, | |
1488 | struct dma_ops_domain *dma_dom, | |
1489 | phys_addr_t paddr, | |
1490 | size_t size, | |
6d4f343f | 1491 | int dir, |
832a90c3 JR |
1492 | bool align, |
1493 | u64 dma_mask) | |
cb76c322 JR |
1494 | { |
1495 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1496 | dma_addr_t address, start, ret; |
cb76c322 | 1497 | unsigned int pages; |
6d4f343f | 1498 | unsigned long align_mask = 0; |
cb76c322 JR |
1499 | int i; |
1500 | ||
e3c449f5 | 1501 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1502 | paddr &= PAGE_MASK; |
1503 | ||
8ecaf8f1 JR |
1504 | INC_STATS_COUNTER(total_map_requests); |
1505 | ||
c1858976 JR |
1506 | if (pages > 1) |
1507 | INC_STATS_COUNTER(cross_page); | |
1508 | ||
6d4f343f JR |
1509 | if (align) |
1510 | align_mask = (1UL << get_order(size)) - 1; | |
1511 | ||
11b83888 | 1512 | retry: |
832a90c3 JR |
1513 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1514 | dma_mask); | |
11b83888 JR |
1515 | if (unlikely(address == bad_dma_address)) { |
1516 | /* | |
1517 | * setting next_address here will let the address | |
1518 | * allocator only scan the new allocated range in the | |
1519 | * first run. This is a small optimization. | |
1520 | */ | |
1521 | dma_dom->next_address = dma_dom->aperture_size; | |
1522 | ||
1523 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1524 | goto out; | |
1525 | ||
1526 | /* | |
1527 | * aperture was sucessfully enlarged by 128 MB, try | |
1528 | * allocation again | |
1529 | */ | |
1530 | goto retry; | |
1531 | } | |
cb76c322 JR |
1532 | |
1533 | start = address; | |
1534 | for (i = 0; i < pages; ++i) { | |
53812c11 JR |
1535 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
1536 | if (ret == bad_dma_address) | |
1537 | goto out_unmap; | |
1538 | ||
cb76c322 JR |
1539 | paddr += PAGE_SIZE; |
1540 | start += PAGE_SIZE; | |
1541 | } | |
1542 | address += offset; | |
1543 | ||
5774f7c5 JR |
1544 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1545 | ||
afa9fdc2 | 1546 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1547 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1548 | dma_dom->need_flush = false; | |
1549 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1550 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1551 | ||
cb76c322 JR |
1552 | out: |
1553 | return address; | |
53812c11 JR |
1554 | |
1555 | out_unmap: | |
1556 | ||
1557 | for (--i; i >= 0; --i) { | |
1558 | start -= PAGE_SIZE; | |
1559 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1560 | } | |
1561 | ||
1562 | dma_ops_free_addresses(dma_dom, address, pages); | |
1563 | ||
1564 | return bad_dma_address; | |
cb76c322 JR |
1565 | } |
1566 | ||
431b2a20 JR |
1567 | /* |
1568 | * Does the reverse of the __map_single function. Must be called with | |
1569 | * the domain lock held too | |
1570 | */ | |
cb76c322 JR |
1571 | static void __unmap_single(struct amd_iommu *iommu, |
1572 | struct dma_ops_domain *dma_dom, | |
1573 | dma_addr_t dma_addr, | |
1574 | size_t size, | |
1575 | int dir) | |
1576 | { | |
1577 | dma_addr_t i, start; | |
1578 | unsigned int pages; | |
1579 | ||
b8d9905d JR |
1580 | if ((dma_addr == bad_dma_address) || |
1581 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1582 | return; |
1583 | ||
e3c449f5 | 1584 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1585 | dma_addr &= PAGE_MASK; |
1586 | start = dma_addr; | |
1587 | ||
1588 | for (i = 0; i < pages; ++i) { | |
1589 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1590 | start += PAGE_SIZE; | |
1591 | } | |
1592 | ||
5774f7c5 JR |
1593 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1594 | ||
cb76c322 | 1595 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1596 | |
80be308d | 1597 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1598 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1599 | dma_dom->need_flush = false; |
1600 | } | |
cb76c322 JR |
1601 | } |
1602 | ||
431b2a20 JR |
1603 | /* |
1604 | * The exported map_single function for dma_ops. | |
1605 | */ | |
51491367 FT |
1606 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1607 | unsigned long offset, size_t size, | |
1608 | enum dma_data_direction dir, | |
1609 | struct dma_attrs *attrs) | |
4da70b9e JR |
1610 | { |
1611 | unsigned long flags; | |
1612 | struct amd_iommu *iommu; | |
1613 | struct protection_domain *domain; | |
1614 | u16 devid; | |
1615 | dma_addr_t addr; | |
832a90c3 | 1616 | u64 dma_mask; |
51491367 | 1617 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1618 | |
0f2a86f2 JR |
1619 | INC_STATS_COUNTER(cnt_map_single); |
1620 | ||
dbcc112e JR |
1621 | if (!check_device(dev)) |
1622 | return bad_dma_address; | |
1623 | ||
832a90c3 | 1624 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1625 | |
1626 | get_device_resources(dev, &iommu, &domain, &devid); | |
1627 | ||
1628 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1629 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1630 | return (dma_addr_t)paddr; |
1631 | ||
5b28df6f JR |
1632 | if (!dma_ops_domain(domain)) |
1633 | return bad_dma_address; | |
1634 | ||
4da70b9e | 1635 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1636 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1637 | dma_mask); | |
4da70b9e JR |
1638 | if (addr == bad_dma_address) |
1639 | goto out; | |
1640 | ||
09ee17eb | 1641 | iommu_completion_wait(iommu); |
4da70b9e JR |
1642 | |
1643 | out: | |
1644 | spin_unlock_irqrestore(&domain->lock, flags); | |
1645 | ||
1646 | return addr; | |
1647 | } | |
1648 | ||
431b2a20 JR |
1649 | /* |
1650 | * The exported unmap_single function for dma_ops. | |
1651 | */ | |
51491367 FT |
1652 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1653 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1654 | { |
1655 | unsigned long flags; | |
1656 | struct amd_iommu *iommu; | |
1657 | struct protection_domain *domain; | |
1658 | u16 devid; | |
1659 | ||
146a6917 JR |
1660 | INC_STATS_COUNTER(cnt_unmap_single); |
1661 | ||
dbcc112e JR |
1662 | if (!check_device(dev) || |
1663 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1664 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1665 | return; |
1666 | ||
5b28df6f JR |
1667 | if (!dma_ops_domain(domain)) |
1668 | return; | |
1669 | ||
4da70b9e JR |
1670 | spin_lock_irqsave(&domain->lock, flags); |
1671 | ||
1672 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1673 | ||
09ee17eb | 1674 | iommu_completion_wait(iommu); |
4da70b9e JR |
1675 | |
1676 | spin_unlock_irqrestore(&domain->lock, flags); | |
1677 | } | |
1678 | ||
431b2a20 JR |
1679 | /* |
1680 | * This is a special map_sg function which is used if we should map a | |
1681 | * device which is not handled by an AMD IOMMU in the system. | |
1682 | */ | |
65b050ad JR |
1683 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1684 | int nelems, int dir) | |
1685 | { | |
1686 | struct scatterlist *s; | |
1687 | int i; | |
1688 | ||
1689 | for_each_sg(sglist, s, nelems, i) { | |
1690 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1691 | s->dma_length = s->length; | |
1692 | } | |
1693 | ||
1694 | return nelems; | |
1695 | } | |
1696 | ||
431b2a20 JR |
1697 | /* |
1698 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1699 | * lists). | |
1700 | */ | |
65b050ad | 1701 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1702 | int nelems, enum dma_data_direction dir, |
1703 | struct dma_attrs *attrs) | |
65b050ad JR |
1704 | { |
1705 | unsigned long flags; | |
1706 | struct amd_iommu *iommu; | |
1707 | struct protection_domain *domain; | |
1708 | u16 devid; | |
1709 | int i; | |
1710 | struct scatterlist *s; | |
1711 | phys_addr_t paddr; | |
1712 | int mapped_elems = 0; | |
832a90c3 | 1713 | u64 dma_mask; |
65b050ad | 1714 | |
d03f067a JR |
1715 | INC_STATS_COUNTER(cnt_map_sg); |
1716 | ||
dbcc112e JR |
1717 | if (!check_device(dev)) |
1718 | return 0; | |
1719 | ||
832a90c3 | 1720 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1721 | |
1722 | get_device_resources(dev, &iommu, &domain, &devid); | |
1723 | ||
1724 | if (!iommu || !domain) | |
1725 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1726 | ||
5b28df6f JR |
1727 | if (!dma_ops_domain(domain)) |
1728 | return 0; | |
1729 | ||
65b050ad JR |
1730 | spin_lock_irqsave(&domain->lock, flags); |
1731 | ||
1732 | for_each_sg(sglist, s, nelems, i) { | |
1733 | paddr = sg_phys(s); | |
1734 | ||
1735 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1736 | paddr, s->length, dir, false, |
1737 | dma_mask); | |
65b050ad JR |
1738 | |
1739 | if (s->dma_address) { | |
1740 | s->dma_length = s->length; | |
1741 | mapped_elems++; | |
1742 | } else | |
1743 | goto unmap; | |
65b050ad JR |
1744 | } |
1745 | ||
09ee17eb | 1746 | iommu_completion_wait(iommu); |
65b050ad JR |
1747 | |
1748 | out: | |
1749 | spin_unlock_irqrestore(&domain->lock, flags); | |
1750 | ||
1751 | return mapped_elems; | |
1752 | unmap: | |
1753 | for_each_sg(sglist, s, mapped_elems, i) { | |
1754 | if (s->dma_address) | |
1755 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1756 | s->dma_length, dir); | |
1757 | s->dma_address = s->dma_length = 0; | |
1758 | } | |
1759 | ||
1760 | mapped_elems = 0; | |
1761 | ||
1762 | goto out; | |
1763 | } | |
1764 | ||
431b2a20 JR |
1765 | /* |
1766 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1767 | * lists). | |
1768 | */ | |
65b050ad | 1769 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1770 | int nelems, enum dma_data_direction dir, |
1771 | struct dma_attrs *attrs) | |
65b050ad JR |
1772 | { |
1773 | unsigned long flags; | |
1774 | struct amd_iommu *iommu; | |
1775 | struct protection_domain *domain; | |
1776 | struct scatterlist *s; | |
1777 | u16 devid; | |
1778 | int i; | |
1779 | ||
55877a6b JR |
1780 | INC_STATS_COUNTER(cnt_unmap_sg); |
1781 | ||
dbcc112e JR |
1782 | if (!check_device(dev) || |
1783 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1784 | return; |
1785 | ||
5b28df6f JR |
1786 | if (!dma_ops_domain(domain)) |
1787 | return; | |
1788 | ||
65b050ad JR |
1789 | spin_lock_irqsave(&domain->lock, flags); |
1790 | ||
1791 | for_each_sg(sglist, s, nelems, i) { | |
1792 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1793 | s->dma_length, dir); | |
65b050ad JR |
1794 | s->dma_address = s->dma_length = 0; |
1795 | } | |
1796 | ||
09ee17eb | 1797 | iommu_completion_wait(iommu); |
65b050ad JR |
1798 | |
1799 | spin_unlock_irqrestore(&domain->lock, flags); | |
1800 | } | |
1801 | ||
431b2a20 JR |
1802 | /* |
1803 | * The exported alloc_coherent function for dma_ops. | |
1804 | */ | |
5d8b53cf JR |
1805 | static void *alloc_coherent(struct device *dev, size_t size, |
1806 | dma_addr_t *dma_addr, gfp_t flag) | |
1807 | { | |
1808 | unsigned long flags; | |
1809 | void *virt_addr; | |
1810 | struct amd_iommu *iommu; | |
1811 | struct protection_domain *domain; | |
1812 | u16 devid; | |
1813 | phys_addr_t paddr; | |
832a90c3 | 1814 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1815 | |
c8f0fb36 JR |
1816 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1817 | ||
dbcc112e JR |
1818 | if (!check_device(dev)) |
1819 | return NULL; | |
5d8b53cf | 1820 | |
13d9fead FT |
1821 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1822 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1823 | |
c97ac535 | 1824 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1825 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1826 | if (!virt_addr) | |
b25ae679 | 1827 | return NULL; |
5d8b53cf | 1828 | |
5d8b53cf JR |
1829 | paddr = virt_to_phys(virt_addr); |
1830 | ||
5d8b53cf JR |
1831 | if (!iommu || !domain) { |
1832 | *dma_addr = (dma_addr_t)paddr; | |
1833 | return virt_addr; | |
1834 | } | |
1835 | ||
5b28df6f JR |
1836 | if (!dma_ops_domain(domain)) |
1837 | goto out_free; | |
1838 | ||
832a90c3 JR |
1839 | if (!dma_mask) |
1840 | dma_mask = *dev->dma_mask; | |
1841 | ||
5d8b53cf JR |
1842 | spin_lock_irqsave(&domain->lock, flags); |
1843 | ||
1844 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1845 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1846 | |
367d04c4 JS |
1847 | if (*dma_addr == bad_dma_address) { |
1848 | spin_unlock_irqrestore(&domain->lock, flags); | |
5b28df6f | 1849 | goto out_free; |
367d04c4 | 1850 | } |
5d8b53cf | 1851 | |
09ee17eb | 1852 | iommu_completion_wait(iommu); |
5d8b53cf | 1853 | |
5d8b53cf JR |
1854 | spin_unlock_irqrestore(&domain->lock, flags); |
1855 | ||
1856 | return virt_addr; | |
5b28df6f JR |
1857 | |
1858 | out_free: | |
1859 | ||
1860 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1861 | ||
1862 | return NULL; | |
5d8b53cf JR |
1863 | } |
1864 | ||
431b2a20 JR |
1865 | /* |
1866 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1867 | */ |
5d8b53cf JR |
1868 | static void free_coherent(struct device *dev, size_t size, |
1869 | void *virt_addr, dma_addr_t dma_addr) | |
1870 | { | |
1871 | unsigned long flags; | |
1872 | struct amd_iommu *iommu; | |
1873 | struct protection_domain *domain; | |
1874 | u16 devid; | |
1875 | ||
5d31ee7e JR |
1876 | INC_STATS_COUNTER(cnt_free_coherent); |
1877 | ||
dbcc112e JR |
1878 | if (!check_device(dev)) |
1879 | return; | |
1880 | ||
5d8b53cf JR |
1881 | get_device_resources(dev, &iommu, &domain, &devid); |
1882 | ||
1883 | if (!iommu || !domain) | |
1884 | goto free_mem; | |
1885 | ||
5b28df6f JR |
1886 | if (!dma_ops_domain(domain)) |
1887 | goto free_mem; | |
1888 | ||
5d8b53cf JR |
1889 | spin_lock_irqsave(&domain->lock, flags); |
1890 | ||
1891 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1892 | |
09ee17eb | 1893 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1894 | |
1895 | spin_unlock_irqrestore(&domain->lock, flags); | |
1896 | ||
1897 | free_mem: | |
1898 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1899 | } | |
1900 | ||
b39ba6ad JR |
1901 | /* |
1902 | * This function is called by the DMA layer to find out if we can handle a | |
1903 | * particular device. It is part of the dma_ops. | |
1904 | */ | |
1905 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1906 | { | |
1907 | u16 bdf; | |
1908 | struct pci_dev *pcidev; | |
1909 | ||
1910 | /* No device or no PCI device */ | |
1911 | if (!dev || dev->bus != &pci_bus_type) | |
1912 | return 0; | |
1913 | ||
1914 | pcidev = to_pci_dev(dev); | |
1915 | ||
1916 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1917 | ||
1918 | /* Out of our scope? */ | |
1919 | if (bdf > amd_iommu_last_bdf) | |
1920 | return 0; | |
1921 | ||
1922 | return 1; | |
1923 | } | |
1924 | ||
c432f3df | 1925 | /* |
431b2a20 JR |
1926 | * The function for pre-allocating protection domains. |
1927 | * | |
c432f3df JR |
1928 | * If the driver core informs the DMA layer if a driver grabs a device |
1929 | * we don't need to preallocate the protection domains anymore. | |
1930 | * For now we have to. | |
1931 | */ | |
0e93dd88 | 1932 | static void prealloc_protection_domains(void) |
c432f3df JR |
1933 | { |
1934 | struct pci_dev *dev = NULL; | |
1935 | struct dma_ops_domain *dma_dom; | |
1936 | struct amd_iommu *iommu; | |
c432f3df JR |
1937 | u16 devid; |
1938 | ||
1939 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1940 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1941 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1942 | continue; |
1943 | devid = amd_iommu_alias_table[devid]; | |
1944 | if (domain_for_device(devid)) | |
1945 | continue; | |
1946 | iommu = amd_iommu_rlookup_table[devid]; | |
1947 | if (!iommu) | |
1948 | continue; | |
d9cfed92 | 1949 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
1950 | if (!dma_dom) |
1951 | continue; | |
1952 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1953 | dma_dom->target_dev = devid; |
1954 | ||
1955 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1956 | } |
1957 | } | |
1958 | ||
160c1d8e | 1959 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
1960 | .alloc_coherent = alloc_coherent, |
1961 | .free_coherent = free_coherent, | |
51491367 FT |
1962 | .map_page = map_page, |
1963 | .unmap_page = unmap_page, | |
6631ee9d JR |
1964 | .map_sg = map_sg, |
1965 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1966 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1967 | }; |
1968 | ||
431b2a20 JR |
1969 | /* |
1970 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1971 | */ | |
6631ee9d JR |
1972 | int __init amd_iommu_init_dma_ops(void) |
1973 | { | |
1974 | struct amd_iommu *iommu; | |
6631ee9d JR |
1975 | int ret; |
1976 | ||
431b2a20 JR |
1977 | /* |
1978 | * first allocate a default protection domain for every IOMMU we | |
1979 | * found in the system. Devices not assigned to any other | |
1980 | * protection domain will be assigned to the default one. | |
1981 | */ | |
3bd22172 | 1982 | for_each_iommu(iommu) { |
d9cfed92 | 1983 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
1984 | if (iommu->default_dom == NULL) |
1985 | return -ENOMEM; | |
e2dc14a2 | 1986 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1987 | ret = iommu_init_unity_mappings(iommu); |
1988 | if (ret) | |
1989 | goto free_domains; | |
1990 | } | |
1991 | ||
431b2a20 JR |
1992 | /* |
1993 | * If device isolation is enabled, pre-allocate the protection | |
1994 | * domains for each device. | |
1995 | */ | |
6631ee9d JR |
1996 | if (amd_iommu_isolate) |
1997 | prealloc_protection_domains(); | |
1998 | ||
1999 | iommu_detected = 1; | |
2000 | force_iommu = 1; | |
2001 | bad_dma_address = 0; | |
92af4e29 | 2002 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
2003 | gart_iommu_aperture_disabled = 1; |
2004 | gart_iommu_aperture = 0; | |
92af4e29 | 2005 | #endif |
6631ee9d | 2006 | |
431b2a20 | 2007 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2008 | dma_ops = &amd_iommu_dma_ops; |
2009 | ||
26961efe | 2010 | register_iommu(&amd_iommu_ops); |
26961efe | 2011 | |
e275a2a0 JR |
2012 | bus_register_notifier(&pci_bus_type, &device_nb); |
2013 | ||
7f26508b JR |
2014 | amd_iommu_stats_init(); |
2015 | ||
6631ee9d JR |
2016 | return 0; |
2017 | ||
2018 | free_domains: | |
2019 | ||
3bd22172 | 2020 | for_each_iommu(iommu) { |
6631ee9d JR |
2021 | if (iommu->default_dom) |
2022 | dma_ops_domain_free(iommu->default_dom); | |
2023 | } | |
2024 | ||
2025 | return ret; | |
2026 | } | |
6d98cd80 JR |
2027 | |
2028 | /***************************************************************************** | |
2029 | * | |
2030 | * The following functions belong to the exported interface of AMD IOMMU | |
2031 | * | |
2032 | * This interface allows access to lower level functions of the IOMMU | |
2033 | * like protection domain handling and assignement of devices to domains | |
2034 | * which is not possible with the dma_ops interface. | |
2035 | * | |
2036 | *****************************************************************************/ | |
2037 | ||
6d98cd80 JR |
2038 | static void cleanup_domain(struct protection_domain *domain) |
2039 | { | |
2040 | unsigned long flags; | |
2041 | u16 devid; | |
2042 | ||
2043 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2044 | ||
2045 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
2046 | if (amd_iommu_pd_table[devid] == domain) | |
2047 | __detach_device(domain, devid); | |
2048 | ||
2049 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2050 | } | |
2051 | ||
c156e347 JR |
2052 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
2053 | { | |
2054 | struct protection_domain *domain; | |
2055 | ||
2056 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2057 | if (!domain) | |
2058 | return -ENOMEM; | |
2059 | ||
2060 | spin_lock_init(&domain->lock); | |
2061 | domain->mode = PAGE_MODE_3_LEVEL; | |
2062 | domain->id = domain_id_alloc(); | |
2063 | if (!domain->id) | |
2064 | goto out_free; | |
2065 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2066 | if (!domain->pt_root) | |
2067 | goto out_free; | |
2068 | ||
2069 | dom->priv = domain; | |
2070 | ||
2071 | return 0; | |
2072 | ||
2073 | out_free: | |
2074 | kfree(domain); | |
2075 | ||
2076 | return -ENOMEM; | |
2077 | } | |
2078 | ||
98383fc3 JR |
2079 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2080 | { | |
2081 | struct protection_domain *domain = dom->priv; | |
2082 | ||
2083 | if (!domain) | |
2084 | return; | |
2085 | ||
2086 | if (domain->dev_cnt > 0) | |
2087 | cleanup_domain(domain); | |
2088 | ||
2089 | BUG_ON(domain->dev_cnt != 0); | |
2090 | ||
2091 | free_pagetable(domain); | |
2092 | ||
2093 | domain_id_free(domain->id); | |
2094 | ||
2095 | kfree(domain); | |
2096 | ||
2097 | dom->priv = NULL; | |
2098 | } | |
2099 | ||
684f2888 JR |
2100 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2101 | struct device *dev) | |
2102 | { | |
2103 | struct protection_domain *domain = dom->priv; | |
2104 | struct amd_iommu *iommu; | |
2105 | struct pci_dev *pdev; | |
2106 | u16 devid; | |
2107 | ||
2108 | if (dev->bus != &pci_bus_type) | |
2109 | return; | |
2110 | ||
2111 | pdev = to_pci_dev(dev); | |
2112 | ||
2113 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2114 | ||
2115 | if (devid > 0) | |
2116 | detach_device(domain, devid); | |
2117 | ||
2118 | iommu = amd_iommu_rlookup_table[devid]; | |
2119 | if (!iommu) | |
2120 | return; | |
2121 | ||
2122 | iommu_queue_inv_dev_entry(iommu, devid); | |
2123 | iommu_completion_wait(iommu); | |
2124 | } | |
2125 | ||
01106066 JR |
2126 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2127 | struct device *dev) | |
2128 | { | |
2129 | struct protection_domain *domain = dom->priv; | |
2130 | struct protection_domain *old_domain; | |
2131 | struct amd_iommu *iommu; | |
2132 | struct pci_dev *pdev; | |
2133 | u16 devid; | |
2134 | ||
2135 | if (dev->bus != &pci_bus_type) | |
2136 | return -EINVAL; | |
2137 | ||
2138 | pdev = to_pci_dev(dev); | |
2139 | ||
2140 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2141 | ||
2142 | if (devid >= amd_iommu_last_bdf || | |
2143 | devid != amd_iommu_alias_table[devid]) | |
2144 | return -EINVAL; | |
2145 | ||
2146 | iommu = amd_iommu_rlookup_table[devid]; | |
2147 | if (!iommu) | |
2148 | return -EINVAL; | |
2149 | ||
2150 | old_domain = domain_for_device(devid); | |
2151 | if (old_domain) | |
71ff3bca | 2152 | detach_device(old_domain, devid); |
01106066 JR |
2153 | |
2154 | attach_device(iommu, domain, devid); | |
2155 | ||
2156 | iommu_completion_wait(iommu); | |
2157 | ||
2158 | return 0; | |
2159 | } | |
2160 | ||
c6229ca6 JR |
2161 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2162 | unsigned long iova, phys_addr_t paddr, | |
2163 | size_t size, int iommu_prot) | |
2164 | { | |
2165 | struct protection_domain *domain = dom->priv; | |
2166 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2167 | int prot = 0; | |
2168 | int ret; | |
2169 | ||
2170 | if (iommu_prot & IOMMU_READ) | |
2171 | prot |= IOMMU_PROT_IR; | |
2172 | if (iommu_prot & IOMMU_WRITE) | |
2173 | prot |= IOMMU_PROT_IW; | |
2174 | ||
2175 | iova &= PAGE_MASK; | |
2176 | paddr &= PAGE_MASK; | |
2177 | ||
2178 | for (i = 0; i < npages; ++i) { | |
2179 | ret = iommu_map_page(domain, iova, paddr, prot); | |
2180 | if (ret) | |
2181 | return ret; | |
2182 | ||
2183 | iova += PAGE_SIZE; | |
2184 | paddr += PAGE_SIZE; | |
2185 | } | |
2186 | ||
2187 | return 0; | |
2188 | } | |
2189 | ||
eb74ff6c JR |
2190 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2191 | unsigned long iova, size_t size) | |
2192 | { | |
2193 | ||
2194 | struct protection_domain *domain = dom->priv; | |
2195 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2196 | ||
2197 | iova &= PAGE_MASK; | |
2198 | ||
2199 | for (i = 0; i < npages; ++i) { | |
2200 | iommu_unmap_page(domain, iova); | |
2201 | iova += PAGE_SIZE; | |
2202 | } | |
2203 | ||
2204 | iommu_flush_domain(domain->id); | |
2205 | } | |
2206 | ||
645c4c8d JR |
2207 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2208 | unsigned long iova) | |
2209 | { | |
2210 | struct protection_domain *domain = dom->priv; | |
2211 | unsigned long offset = iova & ~PAGE_MASK; | |
2212 | phys_addr_t paddr; | |
2213 | u64 *pte; | |
2214 | ||
2215 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
2216 | ||
2217 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2218 | return 0; | |
2219 | ||
2220 | pte = IOMMU_PTE_PAGE(*pte); | |
2221 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
2222 | ||
2223 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2224 | return 0; | |
2225 | ||
2226 | pte = IOMMU_PTE_PAGE(*pte); | |
2227 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
2228 | ||
2229 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2230 | return 0; | |
2231 | ||
2232 | paddr = *pte & IOMMU_PAGE_MASK; | |
2233 | paddr |= offset; | |
2234 | ||
2235 | return paddr; | |
2236 | } | |
2237 | ||
dbb9fd86 SY |
2238 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2239 | unsigned long cap) | |
2240 | { | |
2241 | return 0; | |
2242 | } | |
2243 | ||
26961efe JR |
2244 | static struct iommu_ops amd_iommu_ops = { |
2245 | .domain_init = amd_iommu_domain_init, | |
2246 | .domain_destroy = amd_iommu_domain_destroy, | |
2247 | .attach_dev = amd_iommu_attach_device, | |
2248 | .detach_dev = amd_iommu_detach_device, | |
2249 | .map = amd_iommu_map_range, | |
2250 | .unmap = amd_iommu_unmap_range, | |
2251 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2252 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2253 | }; |
2254 |