Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
26961efe JR |
44 | #ifdef CONFIG_IOMMU_API |
45 | static struct iommu_ops amd_iommu_ops; | |
46 | #endif | |
47 | ||
431b2a20 JR |
48 | /* |
49 | * general struct to manage commands send to an IOMMU | |
50 | */ | |
d6449536 | 51 | struct iommu_cmd { |
b6c02715 JR |
52 | u32 data[4]; |
53 | }; | |
54 | ||
bd0e5211 JR |
55 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
56 | struct unity_map_entry *e); | |
e275a2a0 | 57 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bda3092 JR |
58 | static u64* alloc_pte(struct protection_domain *dom, |
59 | unsigned long address, u64 | |
60 | **pte_page, gfp_t gfp); | |
00cd122a JR |
61 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
62 | unsigned long start_page, | |
63 | unsigned int pages); | |
a345b23b | 64 | static void reset_iommu_command_buffer(struct amd_iommu *iommu); |
bd0e5211 | 65 | |
c1eee67b CW |
66 | #ifndef BUS_NOTIFY_UNBOUND_DRIVER |
67 | #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005 | |
68 | #endif | |
69 | ||
7f26508b JR |
70 | #ifdef CONFIG_AMD_IOMMU_STATS |
71 | ||
72 | /* | |
73 | * Initialization code for statistics collection | |
74 | */ | |
75 | ||
da49f6df | 76 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 77 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 78 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 79 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 80 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 81 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 82 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 83 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 84 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 85 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 86 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 87 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 88 | |
7f26508b JR |
89 | static struct dentry *stats_dir; |
90 | static struct dentry *de_isolate; | |
91 | static struct dentry *de_fflush; | |
92 | ||
93 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
94 | { | |
95 | if (stats_dir == NULL) | |
96 | return; | |
97 | ||
98 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
99 | &cnt->value); | |
100 | } | |
101 | ||
102 | static void amd_iommu_stats_init(void) | |
103 | { | |
104 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
105 | if (stats_dir == NULL) | |
106 | return; | |
107 | ||
108 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
109 | (u32 *)&amd_iommu_isolate); | |
110 | ||
111 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
112 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
113 | |
114 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 115 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 116 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 117 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 118 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 119 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 120 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 121 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 122 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 123 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 124 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 125 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
126 | } |
127 | ||
128 | #endif | |
129 | ||
431b2a20 | 130 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
131 | static int iommu_has_npcache(struct amd_iommu *iommu) |
132 | { | |
ae9b9403 | 133 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
134 | } |
135 | ||
a80dc3e0 JR |
136 | /**************************************************************************** |
137 | * | |
138 | * Interrupt handling functions | |
139 | * | |
140 | ****************************************************************************/ | |
141 | ||
e3e59876 JR |
142 | static void dump_dte_entry(u16 devid) |
143 | { | |
144 | int i; | |
145 | ||
146 | for (i = 0; i < 8; ++i) | |
147 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
148 | amd_iommu_dev_table[devid].data[i]); | |
149 | } | |
150 | ||
945b4ac4 JR |
151 | static void dump_command(unsigned long phys_addr) |
152 | { | |
153 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
154 | int i; | |
155 | ||
156 | for (i = 0; i < 4; ++i) | |
157 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
158 | } | |
159 | ||
a345b23b | 160 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
161 | { |
162 | u32 *event = __evt; | |
163 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
164 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
165 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
166 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
167 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
168 | ||
169 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
170 | ||
171 | switch (type) { | |
172 | case EVENT_TYPE_ILL_DEV: | |
173 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
174 | "address=0x%016llx flags=0x%04x]\n", | |
175 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
176 | address, flags); | |
e3e59876 | 177 | dump_dte_entry(devid); |
90008ee4 JR |
178 | break; |
179 | case EVENT_TYPE_IO_FAULT: | |
180 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
181 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
182 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
183 | domid, address, flags); | |
184 | break; | |
185 | case EVENT_TYPE_DEV_TAB_ERR: | |
186 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
187 | "address=0x%016llx flags=0x%04x]\n", | |
188 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
189 | address, flags); | |
190 | break; | |
191 | case EVENT_TYPE_PAGE_TAB_ERR: | |
192 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
193 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
194 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
195 | domid, address, flags); | |
196 | break; | |
197 | case EVENT_TYPE_ILL_CMD: | |
198 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
a345b23b | 199 | reset_iommu_command_buffer(iommu); |
945b4ac4 | 200 | dump_command(address); |
90008ee4 JR |
201 | break; |
202 | case EVENT_TYPE_CMD_HARD_ERR: | |
203 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
204 | "flags=0x%04x]\n", address, flags); | |
205 | break; | |
206 | case EVENT_TYPE_IOTLB_INV_TO: | |
207 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
208 | "address=0x%016llx]\n", | |
209 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
210 | address); | |
211 | break; | |
212 | case EVENT_TYPE_INV_DEV_REQ: | |
213 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
214 | "address=0x%016llx flags=0x%04x]\n", | |
215 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
216 | address, flags); | |
217 | break; | |
218 | default: | |
219 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
220 | } | |
221 | } | |
222 | ||
223 | static void iommu_poll_events(struct amd_iommu *iommu) | |
224 | { | |
225 | u32 head, tail; | |
226 | unsigned long flags; | |
227 | ||
228 | spin_lock_irqsave(&iommu->lock, flags); | |
229 | ||
230 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
231 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
232 | ||
233 | while (head != tail) { | |
a345b23b | 234 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
235 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
236 | } | |
237 | ||
238 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
239 | ||
240 | spin_unlock_irqrestore(&iommu->lock, flags); | |
241 | } | |
242 | ||
a80dc3e0 JR |
243 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
244 | { | |
90008ee4 JR |
245 | struct amd_iommu *iommu; |
246 | ||
3bd22172 | 247 | for_each_iommu(iommu) |
90008ee4 JR |
248 | iommu_poll_events(iommu); |
249 | ||
250 | return IRQ_HANDLED; | |
a80dc3e0 JR |
251 | } |
252 | ||
431b2a20 JR |
253 | /**************************************************************************** |
254 | * | |
255 | * IOMMU command queuing functions | |
256 | * | |
257 | ****************************************************************************/ | |
258 | ||
259 | /* | |
260 | * Writes the command to the IOMMUs command buffer and informs the | |
261 | * hardware about the new command. Must be called with iommu->lock held. | |
262 | */ | |
d6449536 | 263 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
264 | { |
265 | u32 tail, head; | |
266 | u8 *target; | |
267 | ||
268 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 269 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
270 | memcpy_toio(target, cmd, sizeof(*cmd)); |
271 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
272 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
273 | if (tail == head) | |
274 | return -ENOMEM; | |
275 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
431b2a20 JR |
280 | /* |
281 | * General queuing function for commands. Takes iommu->lock and calls | |
282 | * __iommu_queue_command(). | |
283 | */ | |
d6449536 | 284 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
285 | { |
286 | unsigned long flags; | |
287 | int ret; | |
288 | ||
289 | spin_lock_irqsave(&iommu->lock, flags); | |
290 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 291 | if (!ret) |
0cfd7aa9 | 292 | iommu->need_sync = true; |
a19ae1ec JR |
293 | spin_unlock_irqrestore(&iommu->lock, flags); |
294 | ||
295 | return ret; | |
296 | } | |
297 | ||
8d201968 JR |
298 | /* |
299 | * This function waits until an IOMMU has completed a completion | |
300 | * wait command | |
301 | */ | |
302 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
303 | { | |
304 | int ready = 0; | |
305 | unsigned status = 0; | |
306 | unsigned long i = 0; | |
307 | ||
da49f6df JR |
308 | INC_STATS_COUNTER(compl_wait); |
309 | ||
8d201968 JR |
310 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
311 | ++i; | |
312 | /* wait for the bit to become one */ | |
313 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
314 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
315 | } | |
316 | ||
317 | /* set bit back to zero */ | |
318 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
319 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
320 | ||
321 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
322 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
323 | } | |
324 | ||
325 | /* | |
326 | * This function queues a completion wait command into the command | |
327 | * buffer of an IOMMU | |
328 | */ | |
329 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
330 | { | |
331 | struct iommu_cmd cmd; | |
332 | ||
333 | memset(&cmd, 0, sizeof(cmd)); | |
334 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
335 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
336 | ||
337 | return __iommu_queue_command(iommu, &cmd); | |
338 | } | |
339 | ||
431b2a20 JR |
340 | /* |
341 | * This function is called whenever we need to ensure that the IOMMU has | |
342 | * completed execution of all commands we sent. It sends a | |
343 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
344 | * us about that by writing a value to a physical address we pass with | |
345 | * the command. | |
346 | */ | |
a19ae1ec JR |
347 | static int iommu_completion_wait(struct amd_iommu *iommu) |
348 | { | |
8d201968 JR |
349 | int ret = 0; |
350 | unsigned long flags; | |
a19ae1ec | 351 | |
7e4f88da JR |
352 | spin_lock_irqsave(&iommu->lock, flags); |
353 | ||
09ee17eb JR |
354 | if (!iommu->need_sync) |
355 | goto out; | |
356 | ||
8d201968 | 357 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 358 | |
0cfd7aa9 | 359 | iommu->need_sync = false; |
a19ae1ec JR |
360 | |
361 | if (ret) | |
7e4f88da | 362 | goto out; |
a19ae1ec | 363 | |
8d201968 | 364 | __iommu_wait_for_completion(iommu); |
84df8175 | 365 | |
7e4f88da JR |
366 | out: |
367 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
368 | |
369 | return 0; | |
370 | } | |
371 | ||
431b2a20 JR |
372 | /* |
373 | * Command send function for invalidating a device table entry | |
374 | */ | |
a19ae1ec JR |
375 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
376 | { | |
d6449536 | 377 | struct iommu_cmd cmd; |
ee2fa743 | 378 | int ret; |
a19ae1ec JR |
379 | |
380 | BUG_ON(iommu == NULL); | |
381 | ||
382 | memset(&cmd, 0, sizeof(cmd)); | |
383 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
384 | cmd.data[0] = devid; | |
385 | ||
ee2fa743 JR |
386 | ret = iommu_queue_command(iommu, &cmd); |
387 | ||
ee2fa743 | 388 | return ret; |
a19ae1ec JR |
389 | } |
390 | ||
237b6f33 JR |
391 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
392 | u16 domid, int pde, int s) | |
393 | { | |
394 | memset(cmd, 0, sizeof(*cmd)); | |
395 | address &= PAGE_MASK; | |
396 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
397 | cmd->data[1] |= domid; | |
398 | cmd->data[2] = lower_32_bits(address); | |
399 | cmd->data[3] = upper_32_bits(address); | |
400 | if (s) /* size bit - we flush more than one 4kb page */ | |
401 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
402 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
403 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
404 | } | |
405 | ||
431b2a20 JR |
406 | /* |
407 | * Generic command send function for invalidaing TLB entries | |
408 | */ | |
a19ae1ec JR |
409 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
410 | u64 address, u16 domid, int pde, int s) | |
411 | { | |
d6449536 | 412 | struct iommu_cmd cmd; |
ee2fa743 | 413 | int ret; |
a19ae1ec | 414 | |
237b6f33 | 415 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 416 | |
ee2fa743 JR |
417 | ret = iommu_queue_command(iommu, &cmd); |
418 | ||
ee2fa743 | 419 | return ret; |
a19ae1ec JR |
420 | } |
421 | ||
431b2a20 JR |
422 | /* |
423 | * TLB invalidation function which is called from the mapping functions. | |
424 | * It invalidates a single PTE if the range to flush is within a single | |
425 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
426 | */ | |
a19ae1ec JR |
427 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
428 | u64 address, size_t size) | |
429 | { | |
999ba417 | 430 | int s = 0; |
e3c449f5 | 431 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
432 | |
433 | address &= PAGE_MASK; | |
434 | ||
999ba417 JR |
435 | if (pages > 1) { |
436 | /* | |
437 | * If we have to flush more than one page, flush all | |
438 | * TLB entries for this domain | |
439 | */ | |
440 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
441 | s = 1; | |
a19ae1ec JR |
442 | } |
443 | ||
999ba417 JR |
444 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
445 | ||
a19ae1ec JR |
446 | return 0; |
447 | } | |
b6c02715 | 448 | |
1c655773 JR |
449 | /* Flush the whole IO/TLB for a given protection domain */ |
450 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
451 | { | |
452 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
453 | ||
f57d98ae JR |
454 | INC_STATS_COUNTER(domain_flush_single); |
455 | ||
1c655773 JR |
456 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
457 | } | |
458 | ||
42a49f96 CW |
459 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
460 | static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid) | |
461 | { | |
462 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
463 | ||
464 | INC_STATS_COUNTER(domain_flush_single); | |
465 | ||
466 | iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1); | |
467 | } | |
468 | ||
43f49609 | 469 | /* |
e394d72a | 470 | * This function flushes one domain on one IOMMU |
43f49609 | 471 | */ |
e394d72a | 472 | static void flush_domain_on_iommu(struct amd_iommu *iommu, u16 domid) |
43f49609 | 473 | { |
43f49609 | 474 | struct iommu_cmd cmd; |
e394d72a | 475 | unsigned long flags; |
18811f55 | 476 | |
43f49609 JR |
477 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
478 | domid, 1, 1); | |
479 | ||
e394d72a JR |
480 | spin_lock_irqsave(&iommu->lock, flags); |
481 | __iommu_queue_command(iommu, &cmd); | |
482 | __iommu_completion_wait(iommu); | |
483 | __iommu_wait_for_completion(iommu); | |
484 | spin_unlock_irqrestore(&iommu->lock, flags); | |
43f49609 | 485 | } |
43f49609 | 486 | |
e394d72a | 487 | static void flush_all_domains_on_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
488 | { |
489 | int i; | |
490 | ||
491 | for (i = 1; i < MAX_DOMAIN_ID; ++i) { | |
492 | if (!test_bit(i, amd_iommu_pd_alloc_bitmap)) | |
493 | continue; | |
e394d72a | 494 | flush_domain_on_iommu(iommu, i); |
bfd1be18 | 495 | } |
e394d72a JR |
496 | |
497 | } | |
498 | ||
499 | /* | |
500 | * This function is used to flush the IO/TLB for a given protection domain | |
501 | * on every IOMMU in the system | |
502 | */ | |
503 | static void iommu_flush_domain(u16 domid) | |
504 | { | |
505 | struct amd_iommu *iommu; | |
506 | ||
507 | INC_STATS_COUNTER(domain_flush_all); | |
508 | ||
509 | for_each_iommu(iommu) | |
510 | flush_domain_on_iommu(iommu, domid); | |
511 | } | |
512 | ||
513 | void amd_iommu_flush_all_domains(void) | |
514 | { | |
515 | struct amd_iommu *iommu; | |
516 | ||
517 | for_each_iommu(iommu) | |
518 | flush_all_domains_on_iommu(iommu); | |
bfd1be18 JR |
519 | } |
520 | ||
d586d785 JR |
521 | static void flush_all_devices_for_iommu(struct amd_iommu *iommu) |
522 | { | |
523 | int i; | |
524 | ||
525 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
526 | if (iommu != amd_iommu_rlookup_table[i]) | |
527 | continue; | |
528 | ||
529 | iommu_queue_inv_dev_entry(iommu, i); | |
530 | iommu_completion_wait(iommu); | |
531 | } | |
532 | } | |
533 | ||
7d7a110c JR |
534 | void amd_iommu_flush_all_devices(void) |
535 | { | |
536 | struct amd_iommu *iommu; | |
537 | int i; | |
538 | ||
539 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
540 | if (amd_iommu_pd_table[i] == NULL) | |
541 | continue; | |
542 | ||
543 | iommu = amd_iommu_rlookup_table[i]; | |
544 | if (!iommu) | |
545 | continue; | |
546 | ||
547 | iommu_queue_inv_dev_entry(iommu, i); | |
548 | iommu_completion_wait(iommu); | |
549 | } | |
550 | } | |
551 | ||
a345b23b JR |
552 | static void reset_iommu_command_buffer(struct amd_iommu *iommu) |
553 | { | |
554 | pr_err("AMD-Vi: Resetting IOMMU command buffer\n"); | |
555 | ||
b26e81b8 JR |
556 | if (iommu->reset_in_progress) |
557 | panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n"); | |
558 | ||
559 | iommu->reset_in_progress = true; | |
560 | ||
a345b23b JR |
561 | amd_iommu_reset_cmd_buffer(iommu); |
562 | flush_all_devices_for_iommu(iommu); | |
563 | flush_all_domains_on_iommu(iommu); | |
b26e81b8 JR |
564 | |
565 | iommu->reset_in_progress = false; | |
a345b23b JR |
566 | } |
567 | ||
431b2a20 JR |
568 | /**************************************************************************** |
569 | * | |
570 | * The functions below are used the create the page table mappings for | |
571 | * unity mapped regions. | |
572 | * | |
573 | ****************************************************************************/ | |
574 | ||
575 | /* | |
576 | * Generic mapping functions. It maps a physical address into a DMA | |
577 | * address space. It allocates the page table pages if necessary. | |
578 | * In the future it can be extended to a generic mapping function | |
579 | * supporting all features of AMD IOMMU page tables like level skipping | |
580 | * and full 64 bit address spaces. | |
581 | */ | |
38e817fe JR |
582 | static int iommu_map_page(struct protection_domain *dom, |
583 | unsigned long bus_addr, | |
584 | unsigned long phys_addr, | |
585 | int prot) | |
bd0e5211 | 586 | { |
8bda3092 | 587 | u64 __pte, *pte; |
bd0e5211 JR |
588 | |
589 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 590 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
591 | |
592 | /* only support 512GB address spaces for now */ | |
593 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
594 | return -EINVAL; | |
595 | ||
8bda3092 | 596 | pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL); |
bd0e5211 JR |
597 | |
598 | if (IOMMU_PTE_PRESENT(*pte)) | |
599 | return -EBUSY; | |
600 | ||
601 | __pte = phys_addr | IOMMU_PTE_P; | |
602 | if (prot & IOMMU_PROT_IR) | |
603 | __pte |= IOMMU_PTE_IR; | |
604 | if (prot & IOMMU_PROT_IW) | |
605 | __pte |= IOMMU_PTE_IW; | |
606 | ||
607 | *pte = __pte; | |
608 | ||
609 | return 0; | |
610 | } | |
611 | ||
eb74ff6c JR |
612 | static void iommu_unmap_page(struct protection_domain *dom, |
613 | unsigned long bus_addr) | |
614 | { | |
615 | u64 *pte; | |
616 | ||
617 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
618 | ||
619 | if (!IOMMU_PTE_PRESENT(*pte)) | |
620 | return; | |
621 | ||
622 | pte = IOMMU_PTE_PAGE(*pte); | |
623 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
624 | ||
625 | if (!IOMMU_PTE_PRESENT(*pte)) | |
626 | return; | |
627 | ||
628 | pte = IOMMU_PTE_PAGE(*pte); | |
629 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
630 | ||
631 | *pte = 0; | |
632 | } | |
eb74ff6c | 633 | |
431b2a20 JR |
634 | /* |
635 | * This function checks if a specific unity mapping entry is needed for | |
636 | * this specific IOMMU. | |
637 | */ | |
bd0e5211 JR |
638 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
639 | struct unity_map_entry *entry) | |
640 | { | |
641 | u16 bdf, i; | |
642 | ||
643 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
644 | bdf = amd_iommu_alias_table[i]; | |
645 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
646 | return 1; | |
647 | } | |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
431b2a20 JR |
652 | /* |
653 | * Init the unity mappings for a specific IOMMU in the system | |
654 | * | |
655 | * Basically iterates over all unity mapping entries and applies them to | |
656 | * the default domain DMA of that IOMMU if necessary. | |
657 | */ | |
bd0e5211 JR |
658 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
659 | { | |
660 | struct unity_map_entry *entry; | |
661 | int ret; | |
662 | ||
663 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
664 | if (!iommu_for_unity_map(iommu, entry)) | |
665 | continue; | |
666 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
667 | if (ret) | |
668 | return ret; | |
669 | } | |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
431b2a20 JR |
674 | /* |
675 | * This function actually applies the mapping to the page table of the | |
676 | * dma_ops domain. | |
677 | */ | |
bd0e5211 JR |
678 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
679 | struct unity_map_entry *e) | |
680 | { | |
681 | u64 addr; | |
682 | int ret; | |
683 | ||
684 | for (addr = e->address_start; addr < e->address_end; | |
685 | addr += PAGE_SIZE) { | |
38e817fe | 686 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
687 | if (ret) |
688 | return ret; | |
689 | /* | |
690 | * if unity mapping is in aperture range mark the page | |
691 | * as allocated in the aperture | |
692 | */ | |
693 | if (addr < dma_dom->aperture_size) | |
c3239567 | 694 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 695 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
696 | } |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
431b2a20 JR |
701 | /* |
702 | * Inits the unity mappings required for a specific device | |
703 | */ | |
bd0e5211 JR |
704 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
705 | u16 devid) | |
706 | { | |
707 | struct unity_map_entry *e; | |
708 | int ret; | |
709 | ||
710 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
711 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
712 | continue; | |
713 | ret = dma_ops_unity_map(dma_dom, e); | |
714 | if (ret) | |
715 | return ret; | |
716 | } | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
431b2a20 JR |
721 | /**************************************************************************** |
722 | * | |
723 | * The next functions belong to the address allocator for the dma_ops | |
724 | * interface functions. They work like the allocators in the other IOMMU | |
725 | * drivers. Its basically a bitmap which marks the allocated pages in | |
726 | * the aperture. Maybe it could be enhanced in the future to a more | |
727 | * efficient allocator. | |
728 | * | |
729 | ****************************************************************************/ | |
d3086444 | 730 | |
431b2a20 | 731 | /* |
384de729 | 732 | * The address allocator core functions. |
431b2a20 JR |
733 | * |
734 | * called with domain->lock held | |
735 | */ | |
384de729 | 736 | |
00cd122a JR |
737 | /* |
738 | * This function checks if there is a PTE for a given dma address. If | |
739 | * there is one, it returns the pointer to it. | |
740 | */ | |
741 | static u64* fetch_pte(struct protection_domain *domain, | |
742 | unsigned long address) | |
743 | { | |
744 | u64 *pte; | |
745 | ||
746 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
747 | ||
748 | if (!IOMMU_PTE_PRESENT(*pte)) | |
749 | return NULL; | |
750 | ||
751 | pte = IOMMU_PTE_PAGE(*pte); | |
752 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
753 | ||
754 | if (!IOMMU_PTE_PRESENT(*pte)) | |
755 | return NULL; | |
756 | ||
757 | pte = IOMMU_PTE_PAGE(*pte); | |
758 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
759 | ||
760 | return pte; | |
761 | } | |
762 | ||
9cabe89b JR |
763 | /* |
764 | * This function is used to add a new aperture range to an existing | |
765 | * aperture in case of dma_ops domain allocation or address allocation | |
766 | * failure. | |
767 | */ | |
00cd122a JR |
768 | static int alloc_new_range(struct amd_iommu *iommu, |
769 | struct dma_ops_domain *dma_dom, | |
9cabe89b JR |
770 | bool populate, gfp_t gfp) |
771 | { | |
772 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
00cd122a | 773 | int i; |
9cabe89b | 774 | |
f5e9705c JR |
775 | #ifdef CONFIG_IOMMU_STRESS |
776 | populate = false; | |
777 | #endif | |
778 | ||
9cabe89b JR |
779 | if (index >= APERTURE_MAX_RANGES) |
780 | return -ENOMEM; | |
781 | ||
782 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
783 | if (!dma_dom->aperture[index]) | |
784 | return -ENOMEM; | |
785 | ||
786 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
787 | if (!dma_dom->aperture[index]->bitmap) | |
788 | goto out_free; | |
789 | ||
790 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
791 | ||
792 | if (populate) { | |
793 | unsigned long address = dma_dom->aperture_size; | |
794 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
795 | u64 *pte, *pte_page; | |
796 | ||
797 | for (i = 0; i < num_ptes; ++i) { | |
798 | pte = alloc_pte(&dma_dom->domain, address, | |
799 | &pte_page, gfp); | |
800 | if (!pte) | |
801 | goto out_free; | |
802 | ||
803 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
804 | ||
805 | address += APERTURE_RANGE_SIZE / 64; | |
806 | } | |
807 | } | |
808 | ||
809 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
810 | ||
00cd122a JR |
811 | /* Intialize the exclusion range if necessary */ |
812 | if (iommu->exclusion_start && | |
813 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
814 | iommu->exclusion_start < dma_dom->aperture_size) { | |
815 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
816 | int pages = iommu_num_pages(iommu->exclusion_start, | |
817 | iommu->exclusion_length, | |
818 | PAGE_SIZE); | |
819 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
820 | } | |
821 | ||
822 | /* | |
823 | * Check for areas already mapped as present in the new aperture | |
824 | * range and mark those pages as reserved in the allocator. Such | |
825 | * mappings may already exist as a result of requested unity | |
826 | * mappings for devices. | |
827 | */ | |
828 | for (i = dma_dom->aperture[index]->offset; | |
829 | i < dma_dom->aperture_size; | |
830 | i += PAGE_SIZE) { | |
831 | u64 *pte = fetch_pte(&dma_dom->domain, i); | |
832 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) | |
833 | continue; | |
834 | ||
835 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
836 | } | |
837 | ||
9cabe89b JR |
838 | return 0; |
839 | ||
840 | out_free: | |
841 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); | |
842 | ||
843 | kfree(dma_dom->aperture[index]); | |
844 | dma_dom->aperture[index] = NULL; | |
845 | ||
846 | return -ENOMEM; | |
847 | } | |
848 | ||
384de729 JR |
849 | static unsigned long dma_ops_area_alloc(struct device *dev, |
850 | struct dma_ops_domain *dom, | |
851 | unsigned int pages, | |
852 | unsigned long align_mask, | |
853 | u64 dma_mask, | |
854 | unsigned long start) | |
855 | { | |
803b8cb4 | 856 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
857 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
858 | int i = start >> APERTURE_RANGE_SHIFT; | |
859 | unsigned long boundary_size; | |
860 | unsigned long address = -1; | |
861 | unsigned long limit; | |
862 | ||
803b8cb4 JR |
863 | next_bit >>= PAGE_SHIFT; |
864 | ||
384de729 JR |
865 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
866 | PAGE_SIZE) >> PAGE_SHIFT; | |
867 | ||
868 | for (;i < max_index; ++i) { | |
869 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
870 | ||
871 | if (dom->aperture[i]->offset >= dma_mask) | |
872 | break; | |
873 | ||
874 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
875 | dma_mask >> PAGE_SHIFT); | |
876 | ||
877 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
878 | limit, next_bit, pages, 0, | |
879 | boundary_size, align_mask); | |
880 | if (address != -1) { | |
881 | address = dom->aperture[i]->offset + | |
882 | (address << PAGE_SHIFT); | |
803b8cb4 | 883 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
884 | break; |
885 | } | |
886 | ||
887 | next_bit = 0; | |
888 | } | |
889 | ||
890 | return address; | |
891 | } | |
892 | ||
d3086444 JR |
893 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
894 | struct dma_ops_domain *dom, | |
6d4f343f | 895 | unsigned int pages, |
832a90c3 JR |
896 | unsigned long align_mask, |
897 | u64 dma_mask) | |
d3086444 | 898 | { |
d3086444 | 899 | unsigned long address; |
d3086444 | 900 | |
fe16f088 JR |
901 | #ifdef CONFIG_IOMMU_STRESS |
902 | dom->next_address = 0; | |
903 | dom->need_flush = true; | |
904 | #endif | |
d3086444 | 905 | |
384de729 | 906 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 907 | dma_mask, dom->next_address); |
d3086444 | 908 | |
1c655773 | 909 | if (address == -1) { |
803b8cb4 | 910 | dom->next_address = 0; |
384de729 JR |
911 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
912 | dma_mask, 0); | |
1c655773 JR |
913 | dom->need_flush = true; |
914 | } | |
d3086444 | 915 | |
384de729 | 916 | if (unlikely(address == -1)) |
d3086444 JR |
917 | address = bad_dma_address; |
918 | ||
919 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
920 | ||
921 | return address; | |
922 | } | |
923 | ||
431b2a20 JR |
924 | /* |
925 | * The address free function. | |
926 | * | |
927 | * called with domain->lock held | |
928 | */ | |
d3086444 JR |
929 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
930 | unsigned long address, | |
931 | unsigned int pages) | |
932 | { | |
384de729 JR |
933 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
934 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 935 | |
384de729 JR |
936 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
937 | ||
47bccd6b JR |
938 | #ifdef CONFIG_IOMMU_STRESS |
939 | if (i < 4) | |
940 | return; | |
941 | #endif | |
80be308d | 942 | |
803b8cb4 | 943 | if (address >= dom->next_address) |
80be308d | 944 | dom->need_flush = true; |
384de729 JR |
945 | |
946 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 947 | |
384de729 JR |
948 | iommu_area_free(range->bitmap, address, pages); |
949 | ||
d3086444 JR |
950 | } |
951 | ||
431b2a20 JR |
952 | /**************************************************************************** |
953 | * | |
954 | * The next functions belong to the domain allocation. A domain is | |
955 | * allocated for every IOMMU as the default domain. If device isolation | |
956 | * is enabled, every device get its own domain. The most important thing | |
957 | * about domains is the page table mapping the DMA address space they | |
958 | * contain. | |
959 | * | |
960 | ****************************************************************************/ | |
961 | ||
ec487d1a JR |
962 | static u16 domain_id_alloc(void) |
963 | { | |
964 | unsigned long flags; | |
965 | int id; | |
966 | ||
967 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
968 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
969 | BUG_ON(id == 0); | |
970 | if (id > 0 && id < MAX_DOMAIN_ID) | |
971 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
972 | else | |
973 | id = 0; | |
974 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
975 | ||
976 | return id; | |
977 | } | |
978 | ||
a2acfb75 JR |
979 | static void domain_id_free(int id) |
980 | { | |
981 | unsigned long flags; | |
982 | ||
983 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
984 | if (id > 0 && id < MAX_DOMAIN_ID) | |
985 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
986 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
987 | } | |
a2acfb75 | 988 | |
431b2a20 JR |
989 | /* |
990 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
991 | * ranges. | |
992 | */ | |
ec487d1a JR |
993 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
994 | unsigned long start_page, | |
995 | unsigned int pages) | |
996 | { | |
384de729 | 997 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
998 | |
999 | if (start_page + pages > last_page) | |
1000 | pages = last_page - start_page; | |
1001 | ||
384de729 JR |
1002 | for (i = start_page; i < start_page + pages; ++i) { |
1003 | int index = i / APERTURE_RANGE_PAGES; | |
1004 | int page = i % APERTURE_RANGE_PAGES; | |
1005 | __set_bit(page, dom->aperture[index]->bitmap); | |
1006 | } | |
ec487d1a JR |
1007 | } |
1008 | ||
86db2e5d | 1009 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1010 | { |
1011 | int i, j; | |
1012 | u64 *p1, *p2, *p3; | |
1013 | ||
86db2e5d | 1014 | p1 = domain->pt_root; |
ec487d1a JR |
1015 | |
1016 | if (!p1) | |
1017 | return; | |
1018 | ||
1019 | for (i = 0; i < 512; ++i) { | |
1020 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1021 | continue; | |
1022 | ||
1023 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1024 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1025 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1026 | continue; | |
1027 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1028 | free_page((unsigned long)p3); | |
1029 | } | |
1030 | ||
1031 | free_page((unsigned long)p2); | |
1032 | } | |
1033 | ||
1034 | free_page((unsigned long)p1); | |
86db2e5d JR |
1035 | |
1036 | domain->pt_root = NULL; | |
ec487d1a JR |
1037 | } |
1038 | ||
431b2a20 JR |
1039 | /* |
1040 | * Free a domain, only used if something went wrong in the | |
1041 | * allocation path and we need to free an already allocated page table | |
1042 | */ | |
ec487d1a JR |
1043 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1044 | { | |
384de729 JR |
1045 | int i; |
1046 | ||
ec487d1a JR |
1047 | if (!dom) |
1048 | return; | |
1049 | ||
86db2e5d | 1050 | free_pagetable(&dom->domain); |
ec487d1a | 1051 | |
384de729 JR |
1052 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1053 | if (!dom->aperture[i]) | |
1054 | continue; | |
1055 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1056 | kfree(dom->aperture[i]); | |
1057 | } | |
ec487d1a JR |
1058 | |
1059 | kfree(dom); | |
1060 | } | |
1061 | ||
431b2a20 JR |
1062 | /* |
1063 | * Allocates a new protection domain usable for the dma_ops functions. | |
1064 | * It also intializes the page table and the address allocator data | |
1065 | * structures required for the dma_ops interface | |
1066 | */ | |
d9cfed92 | 1067 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
1068 | { |
1069 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1070 | |
1071 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1072 | if (!dma_dom) | |
1073 | return NULL; | |
1074 | ||
1075 | spin_lock_init(&dma_dom->domain.lock); | |
1076 | ||
1077 | dma_dom->domain.id = domain_id_alloc(); | |
1078 | if (dma_dom->domain.id == 0) | |
1079 | goto free_dma_dom; | |
1080 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
1081 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 1082 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1083 | dma_dom->domain.priv = dma_dom; |
1084 | if (!dma_dom->domain.pt_root) | |
1085 | goto free_dma_dom; | |
ec487d1a | 1086 | |
1c655773 | 1087 | dma_dom->need_flush = false; |
bd60b735 | 1088 | dma_dom->target_dev = 0xffff; |
1c655773 | 1089 | |
00cd122a | 1090 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1091 | goto free_dma_dom; |
ec487d1a | 1092 | |
431b2a20 | 1093 | /* |
ec487d1a JR |
1094 | * mark the first page as allocated so we never return 0 as |
1095 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1096 | */ |
384de729 | 1097 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1098 | dma_dom->next_address = 0; |
ec487d1a | 1099 | |
ec487d1a JR |
1100 | |
1101 | return dma_dom; | |
1102 | ||
1103 | free_dma_dom: | |
1104 | dma_ops_domain_free(dma_dom); | |
1105 | ||
1106 | return NULL; | |
1107 | } | |
1108 | ||
5b28df6f JR |
1109 | /* |
1110 | * little helper function to check whether a given protection domain is a | |
1111 | * dma_ops domain | |
1112 | */ | |
1113 | static bool dma_ops_domain(struct protection_domain *domain) | |
1114 | { | |
1115 | return domain->flags & PD_DMA_OPS_MASK; | |
1116 | } | |
1117 | ||
431b2a20 JR |
1118 | /* |
1119 | * Find out the protection domain structure for a given PCI device. This | |
1120 | * will give us the pointer to the page table root for example. | |
1121 | */ | |
b20ac0d4 JR |
1122 | static struct protection_domain *domain_for_device(u16 devid) |
1123 | { | |
1124 | struct protection_domain *dom; | |
1125 | unsigned long flags; | |
1126 | ||
1127 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1128 | dom = amd_iommu_pd_table[devid]; | |
1129 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1130 | ||
1131 | return dom; | |
1132 | } | |
1133 | ||
431b2a20 JR |
1134 | /* |
1135 | * If a device is not yet associated with a domain, this function does | |
1136 | * assigns it visible for the hardware | |
1137 | */ | |
f1179dc0 JR |
1138 | static void attach_device(struct amd_iommu *iommu, |
1139 | struct protection_domain *domain, | |
1140 | u16 devid) | |
b20ac0d4 JR |
1141 | { |
1142 | unsigned long flags; | |
b20ac0d4 JR |
1143 | u64 pte_root = virt_to_phys(domain->pt_root); |
1144 | ||
863c74eb JR |
1145 | domain->dev_cnt += 1; |
1146 | ||
38ddf41b JR |
1147 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1148 | << DEV_ENTRY_MODE_SHIFT; | |
1149 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
1150 | |
1151 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
1152 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
1153 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
1154 | amd_iommu_dev_table[devid].data[2] = domain->id; |
1155 | ||
1156 | amd_iommu_pd_table[devid] = domain; | |
1157 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1158 | ||
42a49f96 CW |
1159 | /* |
1160 | * We might boot into a crash-kernel here. The crashed kernel | |
1161 | * left the caches in the IOMMU dirty. So we have to flush | |
1162 | * here to evict all dirty stuff. | |
1163 | */ | |
b20ac0d4 | 1164 | iommu_queue_inv_dev_entry(iommu, devid); |
42a49f96 | 1165 | iommu_flush_tlb_pde(iommu, domain->id); |
b20ac0d4 JR |
1166 | } |
1167 | ||
355bf553 JR |
1168 | /* |
1169 | * Removes a device from a protection domain (unlocked) | |
1170 | */ | |
1171 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1172 | { | |
1173 | ||
1174 | /* lock domain */ | |
1175 | spin_lock(&domain->lock); | |
1176 | ||
1177 | /* remove domain from the lookup table */ | |
1178 | amd_iommu_pd_table[devid] = NULL; | |
1179 | ||
1180 | /* remove entry from the device table seen by the hardware */ | |
1181 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1182 | amd_iommu_dev_table[devid].data[1] = 0; | |
1183 | amd_iommu_dev_table[devid].data[2] = 0; | |
1184 | ||
1185 | /* decrease reference counter */ | |
1186 | domain->dev_cnt -= 1; | |
1187 | ||
1188 | /* ready */ | |
1189 | spin_unlock(&domain->lock); | |
1190 | } | |
1191 | ||
1192 | /* | |
1193 | * Removes a device from a protection domain (with devtable_lock held) | |
1194 | */ | |
1195 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1196 | { | |
1197 | unsigned long flags; | |
1198 | ||
1199 | /* lock device table */ | |
1200 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1201 | __detach_device(domain, devid); | |
1202 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1203 | } | |
e275a2a0 JR |
1204 | |
1205 | static int device_change_notifier(struct notifier_block *nb, | |
1206 | unsigned long action, void *data) | |
1207 | { | |
1208 | struct device *dev = data; | |
1209 | struct pci_dev *pdev = to_pci_dev(dev); | |
1210 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1211 | struct protection_domain *domain; | |
1212 | struct dma_ops_domain *dma_domain; | |
1213 | struct amd_iommu *iommu; | |
1ac4cbbc | 1214 | unsigned long flags; |
e275a2a0 JR |
1215 | |
1216 | if (devid > amd_iommu_last_bdf) | |
1217 | goto out; | |
1218 | ||
1219 | devid = amd_iommu_alias_table[devid]; | |
1220 | ||
1221 | iommu = amd_iommu_rlookup_table[devid]; | |
1222 | if (iommu == NULL) | |
1223 | goto out; | |
1224 | ||
1225 | domain = domain_for_device(devid); | |
1226 | ||
1227 | if (domain && !dma_ops_domain(domain)) | |
1228 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1229 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1230 | ||
1231 | switch (action) { | |
c1eee67b | 1232 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1233 | if (!domain) |
1234 | goto out; | |
1235 | detach_device(domain, devid); | |
1ac4cbbc JR |
1236 | break; |
1237 | case BUS_NOTIFY_ADD_DEVICE: | |
1238 | /* allocate a protection domain if a device is added */ | |
1239 | dma_domain = find_protection_domain(devid); | |
1240 | if (dma_domain) | |
1241 | goto out; | |
d9cfed92 | 1242 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1243 | if (!dma_domain) |
1244 | goto out; | |
1245 | dma_domain->target_dev = devid; | |
1246 | ||
1247 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1248 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1249 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1250 | ||
e275a2a0 JR |
1251 | break; |
1252 | default: | |
1253 | goto out; | |
1254 | } | |
1255 | ||
1256 | iommu_queue_inv_dev_entry(iommu, devid); | |
1257 | iommu_completion_wait(iommu); | |
1258 | ||
1259 | out: | |
1260 | return 0; | |
1261 | } | |
1262 | ||
b25ae679 | 1263 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1264 | .notifier_call = device_change_notifier, |
1265 | }; | |
355bf553 | 1266 | |
431b2a20 JR |
1267 | /***************************************************************************** |
1268 | * | |
1269 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1270 | * | |
1271 | *****************************************************************************/ | |
1272 | ||
dbcc112e JR |
1273 | /* |
1274 | * This function checks if the driver got a valid device from the caller to | |
1275 | * avoid dereferencing invalid pointers. | |
1276 | */ | |
1277 | static bool check_device(struct device *dev) | |
1278 | { | |
1279 | if (!dev || !dev->dma_mask) | |
1280 | return false; | |
1281 | ||
1282 | return true; | |
1283 | } | |
1284 | ||
bd60b735 JR |
1285 | /* |
1286 | * In this function the list of preallocated protection domains is traversed to | |
1287 | * find the domain for a specific device | |
1288 | */ | |
1289 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1290 | { | |
1291 | struct dma_ops_domain *entry, *ret = NULL; | |
1292 | unsigned long flags; | |
1293 | ||
1294 | if (list_empty(&iommu_pd_list)) | |
1295 | return NULL; | |
1296 | ||
1297 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1298 | ||
1299 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1300 | if (entry->target_dev == devid) { | |
1301 | ret = entry; | |
bd60b735 JR |
1302 | break; |
1303 | } | |
1304 | } | |
1305 | ||
1306 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1307 | ||
1308 | return ret; | |
1309 | } | |
1310 | ||
431b2a20 JR |
1311 | /* |
1312 | * In the dma_ops path we only have the struct device. This function | |
1313 | * finds the corresponding IOMMU, the protection domain and the | |
1314 | * requestor id for a given device. | |
1315 | * If the device is not yet associated with a domain this is also done | |
1316 | * in this function. | |
1317 | */ | |
b20ac0d4 JR |
1318 | static int get_device_resources(struct device *dev, |
1319 | struct amd_iommu **iommu, | |
1320 | struct protection_domain **domain, | |
1321 | u16 *bdf) | |
1322 | { | |
1323 | struct dma_ops_domain *dma_dom; | |
1324 | struct pci_dev *pcidev; | |
1325 | u16 _bdf; | |
1326 | ||
dbcc112e JR |
1327 | *iommu = NULL; |
1328 | *domain = NULL; | |
1329 | *bdf = 0xffff; | |
1330 | ||
1331 | if (dev->bus != &pci_bus_type) | |
1332 | return 0; | |
b20ac0d4 JR |
1333 | |
1334 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1335 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1336 | |
431b2a20 | 1337 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1338 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1339 | return 0; |
b20ac0d4 JR |
1340 | |
1341 | *bdf = amd_iommu_alias_table[_bdf]; | |
1342 | ||
1343 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1344 | if (*iommu == NULL) | |
1345 | return 0; | |
b20ac0d4 JR |
1346 | *domain = domain_for_device(*bdf); |
1347 | if (*domain == NULL) { | |
bd60b735 JR |
1348 | dma_dom = find_protection_domain(*bdf); |
1349 | if (!dma_dom) | |
1350 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1351 | *domain = &dma_dom->domain; |
f1179dc0 | 1352 | attach_device(*iommu, *domain, *bdf); |
e9a22a13 JR |
1353 | DUMP_printk("Using protection domain %d for device %s\n", |
1354 | (*domain)->id, dev_name(dev)); | |
b20ac0d4 JR |
1355 | } |
1356 | ||
f91ba190 | 1357 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1358 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1359 | |
b20ac0d4 JR |
1360 | return 1; |
1361 | } | |
1362 | ||
8bda3092 JR |
1363 | /* |
1364 | * If the pte_page is not yet allocated this function is called | |
1365 | */ | |
1366 | static u64* alloc_pte(struct protection_domain *dom, | |
1367 | unsigned long address, u64 **pte_page, gfp_t gfp) | |
1368 | { | |
1369 | u64 *pte, *page; | |
1370 | ||
1371 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
1372 | ||
1373 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1374 | page = (u64 *)get_zeroed_page(gfp); | |
1375 | if (!page) | |
1376 | return NULL; | |
1377 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
1378 | } | |
1379 | ||
1380 | pte = IOMMU_PTE_PAGE(*pte); | |
1381 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
1382 | ||
1383 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1384 | page = (u64 *)get_zeroed_page(gfp); | |
1385 | if (!page) | |
1386 | return NULL; | |
1387 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
1388 | } | |
1389 | ||
1390 | pte = IOMMU_PTE_PAGE(*pte); | |
1391 | ||
1392 | if (pte_page) | |
1393 | *pte_page = pte; | |
1394 | ||
1395 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
1396 | ||
1397 | return pte; | |
1398 | } | |
1399 | ||
1400 | /* | |
1401 | * This function fetches the PTE for a given address in the aperture | |
1402 | */ | |
1403 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1404 | unsigned long address) | |
1405 | { | |
384de729 | 1406 | struct aperture_range *aperture; |
8bda3092 JR |
1407 | u64 *pte, *pte_page; |
1408 | ||
384de729 JR |
1409 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1410 | if (!aperture) | |
1411 | return NULL; | |
1412 | ||
1413 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 JR |
1414 | if (!pte) { |
1415 | pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC); | |
384de729 JR |
1416 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1417 | } else | |
1418 | pte += IOMMU_PTE_L0_INDEX(address); | |
8bda3092 JR |
1419 | |
1420 | return pte; | |
1421 | } | |
1422 | ||
431b2a20 JR |
1423 | /* |
1424 | * This is the generic map function. It maps one 4kb page at paddr to | |
1425 | * the given address in the DMA address space for the domain. | |
1426 | */ | |
cb76c322 JR |
1427 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1428 | struct dma_ops_domain *dom, | |
1429 | unsigned long address, | |
1430 | phys_addr_t paddr, | |
1431 | int direction) | |
1432 | { | |
1433 | u64 *pte, __pte; | |
1434 | ||
1435 | WARN_ON(address > dom->aperture_size); | |
1436 | ||
1437 | paddr &= PAGE_MASK; | |
1438 | ||
8bda3092 | 1439 | pte = dma_ops_get_pte(dom, address); |
53812c11 JR |
1440 | if (!pte) |
1441 | return bad_dma_address; | |
cb76c322 JR |
1442 | |
1443 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1444 | ||
1445 | if (direction == DMA_TO_DEVICE) | |
1446 | __pte |= IOMMU_PTE_IR; | |
1447 | else if (direction == DMA_FROM_DEVICE) | |
1448 | __pte |= IOMMU_PTE_IW; | |
1449 | else if (direction == DMA_BIDIRECTIONAL) | |
1450 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1451 | ||
1452 | WARN_ON(*pte); | |
1453 | ||
1454 | *pte = __pte; | |
1455 | ||
1456 | return (dma_addr_t)address; | |
1457 | } | |
1458 | ||
431b2a20 JR |
1459 | /* |
1460 | * The generic unmapping function for on page in the DMA address space. | |
1461 | */ | |
cb76c322 JR |
1462 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1463 | struct dma_ops_domain *dom, | |
1464 | unsigned long address) | |
1465 | { | |
384de729 | 1466 | struct aperture_range *aperture; |
cb76c322 JR |
1467 | u64 *pte; |
1468 | ||
1469 | if (address >= dom->aperture_size) | |
1470 | return; | |
1471 | ||
384de729 JR |
1472 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1473 | if (!aperture) | |
1474 | return; | |
1475 | ||
1476 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1477 | if (!pte) | |
1478 | return; | |
cb76c322 | 1479 | |
cb76c322 JR |
1480 | pte += IOMMU_PTE_L0_INDEX(address); |
1481 | ||
1482 | WARN_ON(!*pte); | |
1483 | ||
1484 | *pte = 0ULL; | |
1485 | } | |
1486 | ||
431b2a20 JR |
1487 | /* |
1488 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1489 | * contiguous memory region into DMA address space. It is used by all |
1490 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1491 | * Must be called with the domain lock held. |
1492 | */ | |
cb76c322 JR |
1493 | static dma_addr_t __map_single(struct device *dev, |
1494 | struct amd_iommu *iommu, | |
1495 | struct dma_ops_domain *dma_dom, | |
1496 | phys_addr_t paddr, | |
1497 | size_t size, | |
6d4f343f | 1498 | int dir, |
832a90c3 JR |
1499 | bool align, |
1500 | u64 dma_mask) | |
cb76c322 JR |
1501 | { |
1502 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1503 | dma_addr_t address, start, ret; |
cb76c322 | 1504 | unsigned int pages; |
6d4f343f | 1505 | unsigned long align_mask = 0; |
cb76c322 JR |
1506 | int i; |
1507 | ||
e3c449f5 | 1508 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1509 | paddr &= PAGE_MASK; |
1510 | ||
8ecaf8f1 JR |
1511 | INC_STATS_COUNTER(total_map_requests); |
1512 | ||
c1858976 JR |
1513 | if (pages > 1) |
1514 | INC_STATS_COUNTER(cross_page); | |
1515 | ||
6d4f343f JR |
1516 | if (align) |
1517 | align_mask = (1UL << get_order(size)) - 1; | |
1518 | ||
11b83888 | 1519 | retry: |
832a90c3 JR |
1520 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1521 | dma_mask); | |
11b83888 JR |
1522 | if (unlikely(address == bad_dma_address)) { |
1523 | /* | |
1524 | * setting next_address here will let the address | |
1525 | * allocator only scan the new allocated range in the | |
1526 | * first run. This is a small optimization. | |
1527 | */ | |
1528 | dma_dom->next_address = dma_dom->aperture_size; | |
1529 | ||
1530 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1531 | goto out; | |
1532 | ||
1533 | /* | |
1534 | * aperture was sucessfully enlarged by 128 MB, try | |
1535 | * allocation again | |
1536 | */ | |
1537 | goto retry; | |
1538 | } | |
cb76c322 JR |
1539 | |
1540 | start = address; | |
1541 | for (i = 0; i < pages; ++i) { | |
53812c11 JR |
1542 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
1543 | if (ret == bad_dma_address) | |
1544 | goto out_unmap; | |
1545 | ||
cb76c322 JR |
1546 | paddr += PAGE_SIZE; |
1547 | start += PAGE_SIZE; | |
1548 | } | |
1549 | address += offset; | |
1550 | ||
5774f7c5 JR |
1551 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1552 | ||
afa9fdc2 | 1553 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1554 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1555 | dma_dom->need_flush = false; | |
1556 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1557 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1558 | ||
cb76c322 JR |
1559 | out: |
1560 | return address; | |
53812c11 JR |
1561 | |
1562 | out_unmap: | |
1563 | ||
1564 | for (--i; i >= 0; --i) { | |
1565 | start -= PAGE_SIZE; | |
1566 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1567 | } | |
1568 | ||
1569 | dma_ops_free_addresses(dma_dom, address, pages); | |
1570 | ||
1571 | return bad_dma_address; | |
cb76c322 JR |
1572 | } |
1573 | ||
431b2a20 JR |
1574 | /* |
1575 | * Does the reverse of the __map_single function. Must be called with | |
1576 | * the domain lock held too | |
1577 | */ | |
cb76c322 JR |
1578 | static void __unmap_single(struct amd_iommu *iommu, |
1579 | struct dma_ops_domain *dma_dom, | |
1580 | dma_addr_t dma_addr, | |
1581 | size_t size, | |
1582 | int dir) | |
1583 | { | |
1584 | dma_addr_t i, start; | |
1585 | unsigned int pages; | |
1586 | ||
b8d9905d JR |
1587 | if ((dma_addr == bad_dma_address) || |
1588 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1589 | return; |
1590 | ||
e3c449f5 | 1591 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1592 | dma_addr &= PAGE_MASK; |
1593 | start = dma_addr; | |
1594 | ||
1595 | for (i = 0; i < pages; ++i) { | |
1596 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1597 | start += PAGE_SIZE; | |
1598 | } | |
1599 | ||
5774f7c5 JR |
1600 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1601 | ||
cb76c322 | 1602 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1603 | |
80be308d | 1604 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1605 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1606 | dma_dom->need_flush = false; |
1607 | } | |
cb76c322 JR |
1608 | } |
1609 | ||
431b2a20 JR |
1610 | /* |
1611 | * The exported map_single function for dma_ops. | |
1612 | */ | |
51491367 FT |
1613 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1614 | unsigned long offset, size_t size, | |
1615 | enum dma_data_direction dir, | |
1616 | struct dma_attrs *attrs) | |
4da70b9e JR |
1617 | { |
1618 | unsigned long flags; | |
1619 | struct amd_iommu *iommu; | |
1620 | struct protection_domain *domain; | |
1621 | u16 devid; | |
1622 | dma_addr_t addr; | |
832a90c3 | 1623 | u64 dma_mask; |
51491367 | 1624 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1625 | |
0f2a86f2 JR |
1626 | INC_STATS_COUNTER(cnt_map_single); |
1627 | ||
dbcc112e JR |
1628 | if (!check_device(dev)) |
1629 | return bad_dma_address; | |
1630 | ||
832a90c3 | 1631 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1632 | |
1633 | get_device_resources(dev, &iommu, &domain, &devid); | |
1634 | ||
1635 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1636 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1637 | return (dma_addr_t)paddr; |
1638 | ||
5b28df6f JR |
1639 | if (!dma_ops_domain(domain)) |
1640 | return bad_dma_address; | |
1641 | ||
4da70b9e | 1642 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1643 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1644 | dma_mask); | |
4da70b9e JR |
1645 | if (addr == bad_dma_address) |
1646 | goto out; | |
1647 | ||
09ee17eb | 1648 | iommu_completion_wait(iommu); |
4da70b9e JR |
1649 | |
1650 | out: | |
1651 | spin_unlock_irqrestore(&domain->lock, flags); | |
1652 | ||
1653 | return addr; | |
1654 | } | |
1655 | ||
431b2a20 JR |
1656 | /* |
1657 | * The exported unmap_single function for dma_ops. | |
1658 | */ | |
51491367 FT |
1659 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1660 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1661 | { |
1662 | unsigned long flags; | |
1663 | struct amd_iommu *iommu; | |
1664 | struct protection_domain *domain; | |
1665 | u16 devid; | |
1666 | ||
146a6917 JR |
1667 | INC_STATS_COUNTER(cnt_unmap_single); |
1668 | ||
dbcc112e JR |
1669 | if (!check_device(dev) || |
1670 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1671 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1672 | return; |
1673 | ||
5b28df6f JR |
1674 | if (!dma_ops_domain(domain)) |
1675 | return; | |
1676 | ||
4da70b9e JR |
1677 | spin_lock_irqsave(&domain->lock, flags); |
1678 | ||
1679 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1680 | ||
09ee17eb | 1681 | iommu_completion_wait(iommu); |
4da70b9e JR |
1682 | |
1683 | spin_unlock_irqrestore(&domain->lock, flags); | |
1684 | } | |
1685 | ||
431b2a20 JR |
1686 | /* |
1687 | * This is a special map_sg function which is used if we should map a | |
1688 | * device which is not handled by an AMD IOMMU in the system. | |
1689 | */ | |
65b050ad JR |
1690 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1691 | int nelems, int dir) | |
1692 | { | |
1693 | struct scatterlist *s; | |
1694 | int i; | |
1695 | ||
1696 | for_each_sg(sglist, s, nelems, i) { | |
1697 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1698 | s->dma_length = s->length; | |
1699 | } | |
1700 | ||
1701 | return nelems; | |
1702 | } | |
1703 | ||
431b2a20 JR |
1704 | /* |
1705 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1706 | * lists). | |
1707 | */ | |
65b050ad | 1708 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1709 | int nelems, enum dma_data_direction dir, |
1710 | struct dma_attrs *attrs) | |
65b050ad JR |
1711 | { |
1712 | unsigned long flags; | |
1713 | struct amd_iommu *iommu; | |
1714 | struct protection_domain *domain; | |
1715 | u16 devid; | |
1716 | int i; | |
1717 | struct scatterlist *s; | |
1718 | phys_addr_t paddr; | |
1719 | int mapped_elems = 0; | |
832a90c3 | 1720 | u64 dma_mask; |
65b050ad | 1721 | |
d03f067a JR |
1722 | INC_STATS_COUNTER(cnt_map_sg); |
1723 | ||
dbcc112e JR |
1724 | if (!check_device(dev)) |
1725 | return 0; | |
1726 | ||
832a90c3 | 1727 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1728 | |
1729 | get_device_resources(dev, &iommu, &domain, &devid); | |
1730 | ||
1731 | if (!iommu || !domain) | |
1732 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1733 | ||
5b28df6f JR |
1734 | if (!dma_ops_domain(domain)) |
1735 | return 0; | |
1736 | ||
65b050ad JR |
1737 | spin_lock_irqsave(&domain->lock, flags); |
1738 | ||
1739 | for_each_sg(sglist, s, nelems, i) { | |
1740 | paddr = sg_phys(s); | |
1741 | ||
1742 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1743 | paddr, s->length, dir, false, |
1744 | dma_mask); | |
65b050ad JR |
1745 | |
1746 | if (s->dma_address) { | |
1747 | s->dma_length = s->length; | |
1748 | mapped_elems++; | |
1749 | } else | |
1750 | goto unmap; | |
65b050ad JR |
1751 | } |
1752 | ||
09ee17eb | 1753 | iommu_completion_wait(iommu); |
65b050ad JR |
1754 | |
1755 | out: | |
1756 | spin_unlock_irqrestore(&domain->lock, flags); | |
1757 | ||
1758 | return mapped_elems; | |
1759 | unmap: | |
1760 | for_each_sg(sglist, s, mapped_elems, i) { | |
1761 | if (s->dma_address) | |
1762 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1763 | s->dma_length, dir); | |
1764 | s->dma_address = s->dma_length = 0; | |
1765 | } | |
1766 | ||
1767 | mapped_elems = 0; | |
1768 | ||
1769 | goto out; | |
1770 | } | |
1771 | ||
431b2a20 JR |
1772 | /* |
1773 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1774 | * lists). | |
1775 | */ | |
65b050ad | 1776 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1777 | int nelems, enum dma_data_direction dir, |
1778 | struct dma_attrs *attrs) | |
65b050ad JR |
1779 | { |
1780 | unsigned long flags; | |
1781 | struct amd_iommu *iommu; | |
1782 | struct protection_domain *domain; | |
1783 | struct scatterlist *s; | |
1784 | u16 devid; | |
1785 | int i; | |
1786 | ||
55877a6b JR |
1787 | INC_STATS_COUNTER(cnt_unmap_sg); |
1788 | ||
dbcc112e JR |
1789 | if (!check_device(dev) || |
1790 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1791 | return; |
1792 | ||
5b28df6f JR |
1793 | if (!dma_ops_domain(domain)) |
1794 | return; | |
1795 | ||
65b050ad JR |
1796 | spin_lock_irqsave(&domain->lock, flags); |
1797 | ||
1798 | for_each_sg(sglist, s, nelems, i) { | |
1799 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1800 | s->dma_length, dir); | |
65b050ad JR |
1801 | s->dma_address = s->dma_length = 0; |
1802 | } | |
1803 | ||
09ee17eb | 1804 | iommu_completion_wait(iommu); |
65b050ad JR |
1805 | |
1806 | spin_unlock_irqrestore(&domain->lock, flags); | |
1807 | } | |
1808 | ||
431b2a20 JR |
1809 | /* |
1810 | * The exported alloc_coherent function for dma_ops. | |
1811 | */ | |
5d8b53cf JR |
1812 | static void *alloc_coherent(struct device *dev, size_t size, |
1813 | dma_addr_t *dma_addr, gfp_t flag) | |
1814 | { | |
1815 | unsigned long flags; | |
1816 | void *virt_addr; | |
1817 | struct amd_iommu *iommu; | |
1818 | struct protection_domain *domain; | |
1819 | u16 devid; | |
1820 | phys_addr_t paddr; | |
832a90c3 | 1821 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1822 | |
c8f0fb36 JR |
1823 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1824 | ||
dbcc112e JR |
1825 | if (!check_device(dev)) |
1826 | return NULL; | |
5d8b53cf | 1827 | |
13d9fead FT |
1828 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1829 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1830 | |
c97ac535 | 1831 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1832 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1833 | if (!virt_addr) | |
b25ae679 | 1834 | return NULL; |
5d8b53cf | 1835 | |
5d8b53cf JR |
1836 | paddr = virt_to_phys(virt_addr); |
1837 | ||
5d8b53cf JR |
1838 | if (!iommu || !domain) { |
1839 | *dma_addr = (dma_addr_t)paddr; | |
1840 | return virt_addr; | |
1841 | } | |
1842 | ||
5b28df6f JR |
1843 | if (!dma_ops_domain(domain)) |
1844 | goto out_free; | |
1845 | ||
832a90c3 JR |
1846 | if (!dma_mask) |
1847 | dma_mask = *dev->dma_mask; | |
1848 | ||
5d8b53cf JR |
1849 | spin_lock_irqsave(&domain->lock, flags); |
1850 | ||
1851 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1852 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1853 | |
367d04c4 JS |
1854 | if (*dma_addr == bad_dma_address) { |
1855 | spin_unlock_irqrestore(&domain->lock, flags); | |
5b28df6f | 1856 | goto out_free; |
367d04c4 | 1857 | } |
5d8b53cf | 1858 | |
09ee17eb | 1859 | iommu_completion_wait(iommu); |
5d8b53cf | 1860 | |
5d8b53cf JR |
1861 | spin_unlock_irqrestore(&domain->lock, flags); |
1862 | ||
1863 | return virt_addr; | |
5b28df6f JR |
1864 | |
1865 | out_free: | |
1866 | ||
1867 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1868 | ||
1869 | return NULL; | |
5d8b53cf JR |
1870 | } |
1871 | ||
431b2a20 JR |
1872 | /* |
1873 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1874 | */ |
5d8b53cf JR |
1875 | static void free_coherent(struct device *dev, size_t size, |
1876 | void *virt_addr, dma_addr_t dma_addr) | |
1877 | { | |
1878 | unsigned long flags; | |
1879 | struct amd_iommu *iommu; | |
1880 | struct protection_domain *domain; | |
1881 | u16 devid; | |
1882 | ||
5d31ee7e JR |
1883 | INC_STATS_COUNTER(cnt_free_coherent); |
1884 | ||
dbcc112e JR |
1885 | if (!check_device(dev)) |
1886 | return; | |
1887 | ||
5d8b53cf JR |
1888 | get_device_resources(dev, &iommu, &domain, &devid); |
1889 | ||
1890 | if (!iommu || !domain) | |
1891 | goto free_mem; | |
1892 | ||
5b28df6f JR |
1893 | if (!dma_ops_domain(domain)) |
1894 | goto free_mem; | |
1895 | ||
5d8b53cf JR |
1896 | spin_lock_irqsave(&domain->lock, flags); |
1897 | ||
1898 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1899 | |
09ee17eb | 1900 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1901 | |
1902 | spin_unlock_irqrestore(&domain->lock, flags); | |
1903 | ||
1904 | free_mem: | |
1905 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1906 | } | |
1907 | ||
b39ba6ad JR |
1908 | /* |
1909 | * This function is called by the DMA layer to find out if we can handle a | |
1910 | * particular device. It is part of the dma_ops. | |
1911 | */ | |
1912 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1913 | { | |
1914 | u16 bdf; | |
1915 | struct pci_dev *pcidev; | |
1916 | ||
1917 | /* No device or no PCI device */ | |
1918 | if (!dev || dev->bus != &pci_bus_type) | |
1919 | return 0; | |
1920 | ||
1921 | pcidev = to_pci_dev(dev); | |
1922 | ||
1923 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1924 | ||
1925 | /* Out of our scope? */ | |
1926 | if (bdf > amd_iommu_last_bdf) | |
1927 | return 0; | |
1928 | ||
1929 | return 1; | |
1930 | } | |
1931 | ||
c432f3df | 1932 | /* |
431b2a20 JR |
1933 | * The function for pre-allocating protection domains. |
1934 | * | |
c432f3df JR |
1935 | * If the driver core informs the DMA layer if a driver grabs a device |
1936 | * we don't need to preallocate the protection domains anymore. | |
1937 | * For now we have to. | |
1938 | */ | |
0e93dd88 | 1939 | static void prealloc_protection_domains(void) |
c432f3df JR |
1940 | { |
1941 | struct pci_dev *dev = NULL; | |
1942 | struct dma_ops_domain *dma_dom; | |
1943 | struct amd_iommu *iommu; | |
c432f3df JR |
1944 | u16 devid; |
1945 | ||
1946 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1947 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1948 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1949 | continue; |
1950 | devid = amd_iommu_alias_table[devid]; | |
1951 | if (domain_for_device(devid)) | |
1952 | continue; | |
1953 | iommu = amd_iommu_rlookup_table[devid]; | |
1954 | if (!iommu) | |
1955 | continue; | |
d9cfed92 | 1956 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
1957 | if (!dma_dom) |
1958 | continue; | |
1959 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1960 | dma_dom->target_dev = devid; |
1961 | ||
1962 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1963 | } |
1964 | } | |
1965 | ||
160c1d8e | 1966 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
1967 | .alloc_coherent = alloc_coherent, |
1968 | .free_coherent = free_coherent, | |
51491367 FT |
1969 | .map_page = map_page, |
1970 | .unmap_page = unmap_page, | |
6631ee9d JR |
1971 | .map_sg = map_sg, |
1972 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1973 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1974 | }; |
1975 | ||
431b2a20 JR |
1976 | /* |
1977 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1978 | */ | |
6631ee9d JR |
1979 | int __init amd_iommu_init_dma_ops(void) |
1980 | { | |
1981 | struct amd_iommu *iommu; | |
6631ee9d JR |
1982 | int ret; |
1983 | ||
431b2a20 JR |
1984 | /* |
1985 | * first allocate a default protection domain for every IOMMU we | |
1986 | * found in the system. Devices not assigned to any other | |
1987 | * protection domain will be assigned to the default one. | |
1988 | */ | |
3bd22172 | 1989 | for_each_iommu(iommu) { |
d9cfed92 | 1990 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
1991 | if (iommu->default_dom == NULL) |
1992 | return -ENOMEM; | |
e2dc14a2 | 1993 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1994 | ret = iommu_init_unity_mappings(iommu); |
1995 | if (ret) | |
1996 | goto free_domains; | |
1997 | } | |
1998 | ||
431b2a20 JR |
1999 | /* |
2000 | * If device isolation is enabled, pre-allocate the protection | |
2001 | * domains for each device. | |
2002 | */ | |
6631ee9d JR |
2003 | if (amd_iommu_isolate) |
2004 | prealloc_protection_domains(); | |
2005 | ||
2006 | iommu_detected = 1; | |
2007 | force_iommu = 1; | |
2008 | bad_dma_address = 0; | |
92af4e29 | 2009 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
2010 | gart_iommu_aperture_disabled = 1; |
2011 | gart_iommu_aperture = 0; | |
92af4e29 | 2012 | #endif |
6631ee9d | 2013 | |
431b2a20 | 2014 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2015 | dma_ops = &amd_iommu_dma_ops; |
2016 | ||
26961efe | 2017 | register_iommu(&amd_iommu_ops); |
26961efe | 2018 | |
e275a2a0 JR |
2019 | bus_register_notifier(&pci_bus_type, &device_nb); |
2020 | ||
7f26508b JR |
2021 | amd_iommu_stats_init(); |
2022 | ||
6631ee9d JR |
2023 | return 0; |
2024 | ||
2025 | free_domains: | |
2026 | ||
3bd22172 | 2027 | for_each_iommu(iommu) { |
6631ee9d JR |
2028 | if (iommu->default_dom) |
2029 | dma_ops_domain_free(iommu->default_dom); | |
2030 | } | |
2031 | ||
2032 | return ret; | |
2033 | } | |
6d98cd80 JR |
2034 | |
2035 | /***************************************************************************** | |
2036 | * | |
2037 | * The following functions belong to the exported interface of AMD IOMMU | |
2038 | * | |
2039 | * This interface allows access to lower level functions of the IOMMU | |
2040 | * like protection domain handling and assignement of devices to domains | |
2041 | * which is not possible with the dma_ops interface. | |
2042 | * | |
2043 | *****************************************************************************/ | |
2044 | ||
6d98cd80 JR |
2045 | static void cleanup_domain(struct protection_domain *domain) |
2046 | { | |
2047 | unsigned long flags; | |
2048 | u16 devid; | |
2049 | ||
2050 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2051 | ||
2052 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
2053 | if (amd_iommu_pd_table[devid] == domain) | |
2054 | __detach_device(domain, devid); | |
2055 | ||
2056 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2057 | } | |
2058 | ||
c156e347 JR |
2059 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
2060 | { | |
2061 | struct protection_domain *domain; | |
2062 | ||
2063 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2064 | if (!domain) | |
2065 | return -ENOMEM; | |
2066 | ||
2067 | spin_lock_init(&domain->lock); | |
2068 | domain->mode = PAGE_MODE_3_LEVEL; | |
2069 | domain->id = domain_id_alloc(); | |
2070 | if (!domain->id) | |
2071 | goto out_free; | |
2072 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2073 | if (!domain->pt_root) | |
2074 | goto out_free; | |
2075 | ||
2076 | dom->priv = domain; | |
2077 | ||
2078 | return 0; | |
2079 | ||
2080 | out_free: | |
2081 | kfree(domain); | |
2082 | ||
2083 | return -ENOMEM; | |
2084 | } | |
2085 | ||
98383fc3 JR |
2086 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2087 | { | |
2088 | struct protection_domain *domain = dom->priv; | |
2089 | ||
2090 | if (!domain) | |
2091 | return; | |
2092 | ||
2093 | if (domain->dev_cnt > 0) | |
2094 | cleanup_domain(domain); | |
2095 | ||
2096 | BUG_ON(domain->dev_cnt != 0); | |
2097 | ||
2098 | free_pagetable(domain); | |
2099 | ||
2100 | domain_id_free(domain->id); | |
2101 | ||
2102 | kfree(domain); | |
2103 | ||
2104 | dom->priv = NULL; | |
2105 | } | |
2106 | ||
684f2888 JR |
2107 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2108 | struct device *dev) | |
2109 | { | |
2110 | struct protection_domain *domain = dom->priv; | |
2111 | struct amd_iommu *iommu; | |
2112 | struct pci_dev *pdev; | |
2113 | u16 devid; | |
2114 | ||
2115 | if (dev->bus != &pci_bus_type) | |
2116 | return; | |
2117 | ||
2118 | pdev = to_pci_dev(dev); | |
2119 | ||
2120 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2121 | ||
2122 | if (devid > 0) | |
2123 | detach_device(domain, devid); | |
2124 | ||
2125 | iommu = amd_iommu_rlookup_table[devid]; | |
2126 | if (!iommu) | |
2127 | return; | |
2128 | ||
2129 | iommu_queue_inv_dev_entry(iommu, devid); | |
2130 | iommu_completion_wait(iommu); | |
2131 | } | |
2132 | ||
01106066 JR |
2133 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2134 | struct device *dev) | |
2135 | { | |
2136 | struct protection_domain *domain = dom->priv; | |
2137 | struct protection_domain *old_domain; | |
2138 | struct amd_iommu *iommu; | |
2139 | struct pci_dev *pdev; | |
2140 | u16 devid; | |
2141 | ||
2142 | if (dev->bus != &pci_bus_type) | |
2143 | return -EINVAL; | |
2144 | ||
2145 | pdev = to_pci_dev(dev); | |
2146 | ||
2147 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2148 | ||
2149 | if (devid >= amd_iommu_last_bdf || | |
2150 | devid != amd_iommu_alias_table[devid]) | |
2151 | return -EINVAL; | |
2152 | ||
2153 | iommu = amd_iommu_rlookup_table[devid]; | |
2154 | if (!iommu) | |
2155 | return -EINVAL; | |
2156 | ||
2157 | old_domain = domain_for_device(devid); | |
2158 | if (old_domain) | |
71ff3bca | 2159 | detach_device(old_domain, devid); |
01106066 JR |
2160 | |
2161 | attach_device(iommu, domain, devid); | |
2162 | ||
2163 | iommu_completion_wait(iommu); | |
2164 | ||
2165 | return 0; | |
2166 | } | |
2167 | ||
c6229ca6 JR |
2168 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2169 | unsigned long iova, phys_addr_t paddr, | |
2170 | size_t size, int iommu_prot) | |
2171 | { | |
2172 | struct protection_domain *domain = dom->priv; | |
2173 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2174 | int prot = 0; | |
2175 | int ret; | |
2176 | ||
2177 | if (iommu_prot & IOMMU_READ) | |
2178 | prot |= IOMMU_PROT_IR; | |
2179 | if (iommu_prot & IOMMU_WRITE) | |
2180 | prot |= IOMMU_PROT_IW; | |
2181 | ||
2182 | iova &= PAGE_MASK; | |
2183 | paddr &= PAGE_MASK; | |
2184 | ||
2185 | for (i = 0; i < npages; ++i) { | |
2186 | ret = iommu_map_page(domain, iova, paddr, prot); | |
2187 | if (ret) | |
2188 | return ret; | |
2189 | ||
2190 | iova += PAGE_SIZE; | |
2191 | paddr += PAGE_SIZE; | |
2192 | } | |
2193 | ||
2194 | return 0; | |
2195 | } | |
2196 | ||
eb74ff6c JR |
2197 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2198 | unsigned long iova, size_t size) | |
2199 | { | |
2200 | ||
2201 | struct protection_domain *domain = dom->priv; | |
2202 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2203 | ||
2204 | iova &= PAGE_MASK; | |
2205 | ||
2206 | for (i = 0; i < npages; ++i) { | |
2207 | iommu_unmap_page(domain, iova); | |
2208 | iova += PAGE_SIZE; | |
2209 | } | |
2210 | ||
2211 | iommu_flush_domain(domain->id); | |
2212 | } | |
2213 | ||
645c4c8d JR |
2214 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2215 | unsigned long iova) | |
2216 | { | |
2217 | struct protection_domain *domain = dom->priv; | |
2218 | unsigned long offset = iova & ~PAGE_MASK; | |
2219 | phys_addr_t paddr; | |
2220 | u64 *pte; | |
2221 | ||
2222 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
2223 | ||
2224 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2225 | return 0; | |
2226 | ||
2227 | pte = IOMMU_PTE_PAGE(*pte); | |
2228 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
2229 | ||
2230 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2231 | return 0; | |
2232 | ||
2233 | pte = IOMMU_PTE_PAGE(*pte); | |
2234 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
2235 | ||
2236 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2237 | return 0; | |
2238 | ||
2239 | paddr = *pte & IOMMU_PAGE_MASK; | |
2240 | paddr |= offset; | |
2241 | ||
2242 | return paddr; | |
2243 | } | |
2244 | ||
dbb9fd86 SY |
2245 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2246 | unsigned long cap) | |
2247 | { | |
2248 | return 0; | |
2249 | } | |
2250 | ||
26961efe JR |
2251 | static struct iommu_ops amd_iommu_ops = { |
2252 | .domain_init = amd_iommu_domain_init, | |
2253 | .domain_destroy = amd_iommu_domain_destroy, | |
2254 | .attach_dev = amd_iommu_attach_device, | |
2255 | .detach_dev = amd_iommu_detach_device, | |
2256 | .map = amd_iommu_map_range, | |
2257 | .unmap = amd_iommu_unmap_range, | |
2258 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2259 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2260 | }; |
2261 |