Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
26961efe JR |
44 | #ifdef CONFIG_IOMMU_API |
45 | static struct iommu_ops amd_iommu_ops; | |
46 | #endif | |
47 | ||
431b2a20 JR |
48 | /* |
49 | * general struct to manage commands send to an IOMMU | |
50 | */ | |
d6449536 | 51 | struct iommu_cmd { |
b6c02715 JR |
52 | u32 data[4]; |
53 | }; | |
54 | ||
bd0e5211 JR |
55 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
56 | struct unity_map_entry *e); | |
e275a2a0 | 57 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bda3092 JR |
58 | static u64* alloc_pte(struct protection_domain *dom, |
59 | unsigned long address, u64 | |
60 | **pte_page, gfp_t gfp); | |
00cd122a JR |
61 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
62 | unsigned long start_page, | |
63 | unsigned int pages); | |
bd0e5211 | 64 | |
c1eee67b CW |
65 | #ifndef BUS_NOTIFY_UNBOUND_DRIVER |
66 | #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005 | |
67 | #endif | |
68 | ||
7f26508b JR |
69 | #ifdef CONFIG_AMD_IOMMU_STATS |
70 | ||
71 | /* | |
72 | * Initialization code for statistics collection | |
73 | */ | |
74 | ||
da49f6df | 75 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 76 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 77 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 78 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 79 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 80 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 81 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 82 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 83 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 84 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 85 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 86 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 87 | |
7f26508b JR |
88 | static struct dentry *stats_dir; |
89 | static struct dentry *de_isolate; | |
90 | static struct dentry *de_fflush; | |
91 | ||
92 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
93 | { | |
94 | if (stats_dir == NULL) | |
95 | return; | |
96 | ||
97 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
98 | &cnt->value); | |
99 | } | |
100 | ||
101 | static void amd_iommu_stats_init(void) | |
102 | { | |
103 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
104 | if (stats_dir == NULL) | |
105 | return; | |
106 | ||
107 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
108 | (u32 *)&amd_iommu_isolate); | |
109 | ||
110 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
111 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
112 | |
113 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 114 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 115 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 116 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 117 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 118 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 119 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 120 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 121 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 122 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 123 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 124 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
125 | } |
126 | ||
127 | #endif | |
128 | ||
431b2a20 | 129 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
130 | static int iommu_has_npcache(struct amd_iommu *iommu) |
131 | { | |
ae9b9403 | 132 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
133 | } |
134 | ||
a80dc3e0 JR |
135 | /**************************************************************************** |
136 | * | |
137 | * Interrupt handling functions | |
138 | * | |
139 | ****************************************************************************/ | |
140 | ||
e3e59876 JR |
141 | static void dump_dte_entry(u16 devid) |
142 | { | |
143 | int i; | |
144 | ||
145 | for (i = 0; i < 8; ++i) | |
146 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
147 | amd_iommu_dev_table[devid].data[i]); | |
148 | } | |
149 | ||
945b4ac4 JR |
150 | static void dump_command(unsigned long phys_addr) |
151 | { | |
152 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
153 | int i; | |
154 | ||
155 | for (i = 0; i < 4; ++i) | |
156 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
157 | } | |
158 | ||
90008ee4 JR |
159 | static void iommu_print_event(void *__evt) |
160 | { | |
161 | u32 *event = __evt; | |
162 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
163 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
164 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
165 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
166 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
167 | ||
168 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
169 | ||
170 | switch (type) { | |
171 | case EVENT_TYPE_ILL_DEV: | |
172 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
173 | "address=0x%016llx flags=0x%04x]\n", | |
174 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
175 | address, flags); | |
e3e59876 | 176 | dump_dte_entry(devid); |
90008ee4 JR |
177 | break; |
178 | case EVENT_TYPE_IO_FAULT: | |
179 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
180 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
181 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
182 | domid, address, flags); | |
183 | break; | |
184 | case EVENT_TYPE_DEV_TAB_ERR: | |
185 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
186 | "address=0x%016llx flags=0x%04x]\n", | |
187 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
188 | address, flags); | |
189 | break; | |
190 | case EVENT_TYPE_PAGE_TAB_ERR: | |
191 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
192 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
193 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
194 | domid, address, flags); | |
195 | break; | |
196 | case EVENT_TYPE_ILL_CMD: | |
197 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 198 | dump_command(address); |
90008ee4 JR |
199 | break; |
200 | case EVENT_TYPE_CMD_HARD_ERR: | |
201 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
202 | "flags=0x%04x]\n", address, flags); | |
203 | break; | |
204 | case EVENT_TYPE_IOTLB_INV_TO: | |
205 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
206 | "address=0x%016llx]\n", | |
207 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
208 | address); | |
209 | break; | |
210 | case EVENT_TYPE_INV_DEV_REQ: | |
211 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
212 | "address=0x%016llx flags=0x%04x]\n", | |
213 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
214 | address, flags); | |
215 | break; | |
216 | default: | |
217 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
218 | } | |
219 | } | |
220 | ||
221 | static void iommu_poll_events(struct amd_iommu *iommu) | |
222 | { | |
223 | u32 head, tail; | |
224 | unsigned long flags; | |
225 | ||
226 | spin_lock_irqsave(&iommu->lock, flags); | |
227 | ||
228 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
229 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
230 | ||
231 | while (head != tail) { | |
232 | iommu_print_event(iommu->evt_buf + head); | |
233 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
234 | } | |
235 | ||
236 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
237 | ||
238 | spin_unlock_irqrestore(&iommu->lock, flags); | |
239 | } | |
240 | ||
a80dc3e0 JR |
241 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
242 | { | |
90008ee4 JR |
243 | struct amd_iommu *iommu; |
244 | ||
3bd22172 | 245 | for_each_iommu(iommu) |
90008ee4 JR |
246 | iommu_poll_events(iommu); |
247 | ||
248 | return IRQ_HANDLED; | |
a80dc3e0 JR |
249 | } |
250 | ||
431b2a20 JR |
251 | /**************************************************************************** |
252 | * | |
253 | * IOMMU command queuing functions | |
254 | * | |
255 | ****************************************************************************/ | |
256 | ||
257 | /* | |
258 | * Writes the command to the IOMMUs command buffer and informs the | |
259 | * hardware about the new command. Must be called with iommu->lock held. | |
260 | */ | |
d6449536 | 261 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
262 | { |
263 | u32 tail, head; | |
264 | u8 *target; | |
265 | ||
266 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 267 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
268 | memcpy_toio(target, cmd, sizeof(*cmd)); |
269 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
270 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
271 | if (tail == head) | |
272 | return -ENOMEM; | |
273 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
431b2a20 JR |
278 | /* |
279 | * General queuing function for commands. Takes iommu->lock and calls | |
280 | * __iommu_queue_command(). | |
281 | */ | |
d6449536 | 282 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
283 | { |
284 | unsigned long flags; | |
285 | int ret; | |
286 | ||
287 | spin_lock_irqsave(&iommu->lock, flags); | |
288 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 289 | if (!ret) |
0cfd7aa9 | 290 | iommu->need_sync = true; |
a19ae1ec JR |
291 | spin_unlock_irqrestore(&iommu->lock, flags); |
292 | ||
293 | return ret; | |
294 | } | |
295 | ||
8d201968 JR |
296 | /* |
297 | * This function waits until an IOMMU has completed a completion | |
298 | * wait command | |
299 | */ | |
300 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
301 | { | |
302 | int ready = 0; | |
303 | unsigned status = 0; | |
304 | unsigned long i = 0; | |
305 | ||
da49f6df JR |
306 | INC_STATS_COUNTER(compl_wait); |
307 | ||
8d201968 JR |
308 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
309 | ++i; | |
310 | /* wait for the bit to become one */ | |
311 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
312 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
313 | } | |
314 | ||
315 | /* set bit back to zero */ | |
316 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
317 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
318 | ||
319 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
320 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
321 | } | |
322 | ||
323 | /* | |
324 | * This function queues a completion wait command into the command | |
325 | * buffer of an IOMMU | |
326 | */ | |
327 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
328 | { | |
329 | struct iommu_cmd cmd; | |
330 | ||
331 | memset(&cmd, 0, sizeof(cmd)); | |
332 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
333 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
334 | ||
335 | return __iommu_queue_command(iommu, &cmd); | |
336 | } | |
337 | ||
431b2a20 JR |
338 | /* |
339 | * This function is called whenever we need to ensure that the IOMMU has | |
340 | * completed execution of all commands we sent. It sends a | |
341 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
342 | * us about that by writing a value to a physical address we pass with | |
343 | * the command. | |
344 | */ | |
a19ae1ec JR |
345 | static int iommu_completion_wait(struct amd_iommu *iommu) |
346 | { | |
8d201968 JR |
347 | int ret = 0; |
348 | unsigned long flags; | |
a19ae1ec | 349 | |
7e4f88da JR |
350 | spin_lock_irqsave(&iommu->lock, flags); |
351 | ||
09ee17eb JR |
352 | if (!iommu->need_sync) |
353 | goto out; | |
354 | ||
8d201968 | 355 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 356 | |
0cfd7aa9 | 357 | iommu->need_sync = false; |
a19ae1ec JR |
358 | |
359 | if (ret) | |
7e4f88da | 360 | goto out; |
a19ae1ec | 361 | |
8d201968 | 362 | __iommu_wait_for_completion(iommu); |
84df8175 | 363 | |
7e4f88da JR |
364 | out: |
365 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
366 | |
367 | return 0; | |
368 | } | |
369 | ||
431b2a20 JR |
370 | /* |
371 | * Command send function for invalidating a device table entry | |
372 | */ | |
a19ae1ec JR |
373 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
374 | { | |
d6449536 | 375 | struct iommu_cmd cmd; |
ee2fa743 | 376 | int ret; |
a19ae1ec JR |
377 | |
378 | BUG_ON(iommu == NULL); | |
379 | ||
380 | memset(&cmd, 0, sizeof(cmd)); | |
381 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
382 | cmd.data[0] = devid; | |
383 | ||
ee2fa743 JR |
384 | ret = iommu_queue_command(iommu, &cmd); |
385 | ||
ee2fa743 | 386 | return ret; |
a19ae1ec JR |
387 | } |
388 | ||
237b6f33 JR |
389 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
390 | u16 domid, int pde, int s) | |
391 | { | |
392 | memset(cmd, 0, sizeof(*cmd)); | |
393 | address &= PAGE_MASK; | |
394 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
395 | cmd->data[1] |= domid; | |
396 | cmd->data[2] = lower_32_bits(address); | |
397 | cmd->data[3] = upper_32_bits(address); | |
398 | if (s) /* size bit - we flush more than one 4kb page */ | |
399 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
400 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
401 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
402 | } | |
403 | ||
431b2a20 JR |
404 | /* |
405 | * Generic command send function for invalidaing TLB entries | |
406 | */ | |
a19ae1ec JR |
407 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
408 | u64 address, u16 domid, int pde, int s) | |
409 | { | |
d6449536 | 410 | struct iommu_cmd cmd; |
ee2fa743 | 411 | int ret; |
a19ae1ec | 412 | |
237b6f33 | 413 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 414 | |
ee2fa743 JR |
415 | ret = iommu_queue_command(iommu, &cmd); |
416 | ||
ee2fa743 | 417 | return ret; |
a19ae1ec JR |
418 | } |
419 | ||
431b2a20 JR |
420 | /* |
421 | * TLB invalidation function which is called from the mapping functions. | |
422 | * It invalidates a single PTE if the range to flush is within a single | |
423 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
424 | */ | |
a19ae1ec JR |
425 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
426 | u64 address, size_t size) | |
427 | { | |
999ba417 | 428 | int s = 0; |
e3c449f5 | 429 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
430 | |
431 | address &= PAGE_MASK; | |
432 | ||
999ba417 JR |
433 | if (pages > 1) { |
434 | /* | |
435 | * If we have to flush more than one page, flush all | |
436 | * TLB entries for this domain | |
437 | */ | |
438 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
439 | s = 1; | |
a19ae1ec JR |
440 | } |
441 | ||
999ba417 JR |
442 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
443 | ||
a19ae1ec JR |
444 | return 0; |
445 | } | |
b6c02715 | 446 | |
1c655773 JR |
447 | /* Flush the whole IO/TLB for a given protection domain */ |
448 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
449 | { | |
450 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
451 | ||
f57d98ae JR |
452 | INC_STATS_COUNTER(domain_flush_single); |
453 | ||
1c655773 JR |
454 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
455 | } | |
456 | ||
42a49f96 CW |
457 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
458 | static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid) | |
459 | { | |
460 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
461 | ||
462 | INC_STATS_COUNTER(domain_flush_single); | |
463 | ||
464 | iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1); | |
465 | } | |
466 | ||
43f49609 | 467 | /* |
e394d72a | 468 | * This function flushes one domain on one IOMMU |
43f49609 | 469 | */ |
e394d72a | 470 | static void flush_domain_on_iommu(struct amd_iommu *iommu, u16 domid) |
43f49609 | 471 | { |
43f49609 | 472 | struct iommu_cmd cmd; |
e394d72a | 473 | unsigned long flags; |
18811f55 | 474 | |
43f49609 JR |
475 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
476 | domid, 1, 1); | |
477 | ||
e394d72a JR |
478 | spin_lock_irqsave(&iommu->lock, flags); |
479 | __iommu_queue_command(iommu, &cmd); | |
480 | __iommu_completion_wait(iommu); | |
481 | __iommu_wait_for_completion(iommu); | |
482 | spin_unlock_irqrestore(&iommu->lock, flags); | |
43f49609 | 483 | } |
43f49609 | 484 | |
e394d72a | 485 | static void flush_all_domains_on_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
486 | { |
487 | int i; | |
488 | ||
489 | for (i = 1; i < MAX_DOMAIN_ID; ++i) { | |
490 | if (!test_bit(i, amd_iommu_pd_alloc_bitmap)) | |
491 | continue; | |
e394d72a | 492 | flush_domain_on_iommu(iommu, i); |
bfd1be18 | 493 | } |
e394d72a JR |
494 | |
495 | } | |
496 | ||
497 | /* | |
498 | * This function is used to flush the IO/TLB for a given protection domain | |
499 | * on every IOMMU in the system | |
500 | */ | |
501 | static void iommu_flush_domain(u16 domid) | |
502 | { | |
503 | struct amd_iommu *iommu; | |
504 | ||
505 | INC_STATS_COUNTER(domain_flush_all); | |
506 | ||
507 | for_each_iommu(iommu) | |
508 | flush_domain_on_iommu(iommu, domid); | |
509 | } | |
510 | ||
511 | void amd_iommu_flush_all_domains(void) | |
512 | { | |
513 | struct amd_iommu *iommu; | |
514 | ||
515 | for_each_iommu(iommu) | |
516 | flush_all_domains_on_iommu(iommu); | |
bfd1be18 JR |
517 | } |
518 | ||
7d7a110c JR |
519 | void amd_iommu_flush_all_devices(void) |
520 | { | |
521 | struct amd_iommu *iommu; | |
522 | int i; | |
523 | ||
524 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
525 | if (amd_iommu_pd_table[i] == NULL) | |
526 | continue; | |
527 | ||
528 | iommu = amd_iommu_rlookup_table[i]; | |
529 | if (!iommu) | |
530 | continue; | |
531 | ||
532 | iommu_queue_inv_dev_entry(iommu, i); | |
533 | iommu_completion_wait(iommu); | |
534 | } | |
535 | } | |
536 | ||
431b2a20 JR |
537 | /**************************************************************************** |
538 | * | |
539 | * The functions below are used the create the page table mappings for | |
540 | * unity mapped regions. | |
541 | * | |
542 | ****************************************************************************/ | |
543 | ||
544 | /* | |
545 | * Generic mapping functions. It maps a physical address into a DMA | |
546 | * address space. It allocates the page table pages if necessary. | |
547 | * In the future it can be extended to a generic mapping function | |
548 | * supporting all features of AMD IOMMU page tables like level skipping | |
549 | * and full 64 bit address spaces. | |
550 | */ | |
38e817fe JR |
551 | static int iommu_map_page(struct protection_domain *dom, |
552 | unsigned long bus_addr, | |
553 | unsigned long phys_addr, | |
554 | int prot) | |
bd0e5211 | 555 | { |
8bda3092 | 556 | u64 __pte, *pte; |
bd0e5211 JR |
557 | |
558 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 559 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
560 | |
561 | /* only support 512GB address spaces for now */ | |
562 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
563 | return -EINVAL; | |
564 | ||
8bda3092 | 565 | pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL); |
bd0e5211 JR |
566 | |
567 | if (IOMMU_PTE_PRESENT(*pte)) | |
568 | return -EBUSY; | |
569 | ||
570 | __pte = phys_addr | IOMMU_PTE_P; | |
571 | if (prot & IOMMU_PROT_IR) | |
572 | __pte |= IOMMU_PTE_IR; | |
573 | if (prot & IOMMU_PROT_IW) | |
574 | __pte |= IOMMU_PTE_IW; | |
575 | ||
576 | *pte = __pte; | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
eb74ff6c JR |
581 | static void iommu_unmap_page(struct protection_domain *dom, |
582 | unsigned long bus_addr) | |
583 | { | |
584 | u64 *pte; | |
585 | ||
586 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
587 | ||
588 | if (!IOMMU_PTE_PRESENT(*pte)) | |
589 | return; | |
590 | ||
591 | pte = IOMMU_PTE_PAGE(*pte); | |
592 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
593 | ||
594 | if (!IOMMU_PTE_PRESENT(*pte)) | |
595 | return; | |
596 | ||
597 | pte = IOMMU_PTE_PAGE(*pte); | |
598 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
599 | ||
600 | *pte = 0; | |
601 | } | |
eb74ff6c | 602 | |
431b2a20 JR |
603 | /* |
604 | * This function checks if a specific unity mapping entry is needed for | |
605 | * this specific IOMMU. | |
606 | */ | |
bd0e5211 JR |
607 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
608 | struct unity_map_entry *entry) | |
609 | { | |
610 | u16 bdf, i; | |
611 | ||
612 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
613 | bdf = amd_iommu_alias_table[i]; | |
614 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
615 | return 1; | |
616 | } | |
617 | ||
618 | return 0; | |
619 | } | |
620 | ||
431b2a20 JR |
621 | /* |
622 | * Init the unity mappings for a specific IOMMU in the system | |
623 | * | |
624 | * Basically iterates over all unity mapping entries and applies them to | |
625 | * the default domain DMA of that IOMMU if necessary. | |
626 | */ | |
bd0e5211 JR |
627 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
628 | { | |
629 | struct unity_map_entry *entry; | |
630 | int ret; | |
631 | ||
632 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
633 | if (!iommu_for_unity_map(iommu, entry)) | |
634 | continue; | |
635 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
636 | if (ret) | |
637 | return ret; | |
638 | } | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
431b2a20 JR |
643 | /* |
644 | * This function actually applies the mapping to the page table of the | |
645 | * dma_ops domain. | |
646 | */ | |
bd0e5211 JR |
647 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
648 | struct unity_map_entry *e) | |
649 | { | |
650 | u64 addr; | |
651 | int ret; | |
652 | ||
653 | for (addr = e->address_start; addr < e->address_end; | |
654 | addr += PAGE_SIZE) { | |
38e817fe | 655 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
656 | if (ret) |
657 | return ret; | |
658 | /* | |
659 | * if unity mapping is in aperture range mark the page | |
660 | * as allocated in the aperture | |
661 | */ | |
662 | if (addr < dma_dom->aperture_size) | |
c3239567 | 663 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 664 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
665 | } |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
431b2a20 JR |
670 | /* |
671 | * Inits the unity mappings required for a specific device | |
672 | */ | |
bd0e5211 JR |
673 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
674 | u16 devid) | |
675 | { | |
676 | struct unity_map_entry *e; | |
677 | int ret; | |
678 | ||
679 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
680 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
681 | continue; | |
682 | ret = dma_ops_unity_map(dma_dom, e); | |
683 | if (ret) | |
684 | return ret; | |
685 | } | |
686 | ||
687 | return 0; | |
688 | } | |
689 | ||
431b2a20 JR |
690 | /**************************************************************************** |
691 | * | |
692 | * The next functions belong to the address allocator for the dma_ops | |
693 | * interface functions. They work like the allocators in the other IOMMU | |
694 | * drivers. Its basically a bitmap which marks the allocated pages in | |
695 | * the aperture. Maybe it could be enhanced in the future to a more | |
696 | * efficient allocator. | |
697 | * | |
698 | ****************************************************************************/ | |
d3086444 | 699 | |
431b2a20 | 700 | /* |
384de729 | 701 | * The address allocator core functions. |
431b2a20 JR |
702 | * |
703 | * called with domain->lock held | |
704 | */ | |
384de729 | 705 | |
00cd122a JR |
706 | /* |
707 | * This function checks if there is a PTE for a given dma address. If | |
708 | * there is one, it returns the pointer to it. | |
709 | */ | |
710 | static u64* fetch_pte(struct protection_domain *domain, | |
711 | unsigned long address) | |
712 | { | |
713 | u64 *pte; | |
714 | ||
715 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
716 | ||
717 | if (!IOMMU_PTE_PRESENT(*pte)) | |
718 | return NULL; | |
719 | ||
720 | pte = IOMMU_PTE_PAGE(*pte); | |
721 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
722 | ||
723 | if (!IOMMU_PTE_PRESENT(*pte)) | |
724 | return NULL; | |
725 | ||
726 | pte = IOMMU_PTE_PAGE(*pte); | |
727 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
728 | ||
729 | return pte; | |
730 | } | |
731 | ||
9cabe89b JR |
732 | /* |
733 | * This function is used to add a new aperture range to an existing | |
734 | * aperture in case of dma_ops domain allocation or address allocation | |
735 | * failure. | |
736 | */ | |
00cd122a JR |
737 | static int alloc_new_range(struct amd_iommu *iommu, |
738 | struct dma_ops_domain *dma_dom, | |
9cabe89b JR |
739 | bool populate, gfp_t gfp) |
740 | { | |
741 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
00cd122a | 742 | int i; |
9cabe89b | 743 | |
f5e9705c JR |
744 | #ifdef CONFIG_IOMMU_STRESS |
745 | populate = false; | |
746 | #endif | |
747 | ||
9cabe89b JR |
748 | if (index >= APERTURE_MAX_RANGES) |
749 | return -ENOMEM; | |
750 | ||
751 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
752 | if (!dma_dom->aperture[index]) | |
753 | return -ENOMEM; | |
754 | ||
755 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
756 | if (!dma_dom->aperture[index]->bitmap) | |
757 | goto out_free; | |
758 | ||
759 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
760 | ||
761 | if (populate) { | |
762 | unsigned long address = dma_dom->aperture_size; | |
763 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
764 | u64 *pte, *pte_page; | |
765 | ||
766 | for (i = 0; i < num_ptes; ++i) { | |
767 | pte = alloc_pte(&dma_dom->domain, address, | |
768 | &pte_page, gfp); | |
769 | if (!pte) | |
770 | goto out_free; | |
771 | ||
772 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
773 | ||
774 | address += APERTURE_RANGE_SIZE / 64; | |
775 | } | |
776 | } | |
777 | ||
778 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
779 | ||
00cd122a JR |
780 | /* Intialize the exclusion range if necessary */ |
781 | if (iommu->exclusion_start && | |
782 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
783 | iommu->exclusion_start < dma_dom->aperture_size) { | |
784 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
785 | int pages = iommu_num_pages(iommu->exclusion_start, | |
786 | iommu->exclusion_length, | |
787 | PAGE_SIZE); | |
788 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
789 | } | |
790 | ||
791 | /* | |
792 | * Check for areas already mapped as present in the new aperture | |
793 | * range and mark those pages as reserved in the allocator. Such | |
794 | * mappings may already exist as a result of requested unity | |
795 | * mappings for devices. | |
796 | */ | |
797 | for (i = dma_dom->aperture[index]->offset; | |
798 | i < dma_dom->aperture_size; | |
799 | i += PAGE_SIZE) { | |
800 | u64 *pte = fetch_pte(&dma_dom->domain, i); | |
801 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) | |
802 | continue; | |
803 | ||
804 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
805 | } | |
806 | ||
9cabe89b JR |
807 | return 0; |
808 | ||
809 | out_free: | |
810 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); | |
811 | ||
812 | kfree(dma_dom->aperture[index]); | |
813 | dma_dom->aperture[index] = NULL; | |
814 | ||
815 | return -ENOMEM; | |
816 | } | |
817 | ||
384de729 JR |
818 | static unsigned long dma_ops_area_alloc(struct device *dev, |
819 | struct dma_ops_domain *dom, | |
820 | unsigned int pages, | |
821 | unsigned long align_mask, | |
822 | u64 dma_mask, | |
823 | unsigned long start) | |
824 | { | |
803b8cb4 | 825 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
826 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
827 | int i = start >> APERTURE_RANGE_SHIFT; | |
828 | unsigned long boundary_size; | |
829 | unsigned long address = -1; | |
830 | unsigned long limit; | |
831 | ||
803b8cb4 JR |
832 | next_bit >>= PAGE_SHIFT; |
833 | ||
384de729 JR |
834 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
835 | PAGE_SIZE) >> PAGE_SHIFT; | |
836 | ||
837 | for (;i < max_index; ++i) { | |
838 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
839 | ||
840 | if (dom->aperture[i]->offset >= dma_mask) | |
841 | break; | |
842 | ||
843 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
844 | dma_mask >> PAGE_SHIFT); | |
845 | ||
846 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
847 | limit, next_bit, pages, 0, | |
848 | boundary_size, align_mask); | |
849 | if (address != -1) { | |
850 | address = dom->aperture[i]->offset + | |
851 | (address << PAGE_SHIFT); | |
803b8cb4 | 852 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
853 | break; |
854 | } | |
855 | ||
856 | next_bit = 0; | |
857 | } | |
858 | ||
859 | return address; | |
860 | } | |
861 | ||
d3086444 JR |
862 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
863 | struct dma_ops_domain *dom, | |
6d4f343f | 864 | unsigned int pages, |
832a90c3 JR |
865 | unsigned long align_mask, |
866 | u64 dma_mask) | |
d3086444 | 867 | { |
d3086444 | 868 | unsigned long address; |
d3086444 | 869 | |
fe16f088 JR |
870 | #ifdef CONFIG_IOMMU_STRESS |
871 | dom->next_address = 0; | |
872 | dom->need_flush = true; | |
873 | #endif | |
d3086444 | 874 | |
384de729 | 875 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 876 | dma_mask, dom->next_address); |
d3086444 | 877 | |
1c655773 | 878 | if (address == -1) { |
803b8cb4 | 879 | dom->next_address = 0; |
384de729 JR |
880 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
881 | dma_mask, 0); | |
1c655773 JR |
882 | dom->need_flush = true; |
883 | } | |
d3086444 | 884 | |
384de729 | 885 | if (unlikely(address == -1)) |
d3086444 JR |
886 | address = bad_dma_address; |
887 | ||
888 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
889 | ||
890 | return address; | |
891 | } | |
892 | ||
431b2a20 JR |
893 | /* |
894 | * The address free function. | |
895 | * | |
896 | * called with domain->lock held | |
897 | */ | |
d3086444 JR |
898 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
899 | unsigned long address, | |
900 | unsigned int pages) | |
901 | { | |
384de729 JR |
902 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
903 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 904 | |
384de729 JR |
905 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
906 | ||
47bccd6b JR |
907 | #ifdef CONFIG_IOMMU_STRESS |
908 | if (i < 4) | |
909 | return; | |
910 | #endif | |
80be308d | 911 | |
803b8cb4 | 912 | if (address >= dom->next_address) |
80be308d | 913 | dom->need_flush = true; |
384de729 JR |
914 | |
915 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 916 | |
384de729 JR |
917 | iommu_area_free(range->bitmap, address, pages); |
918 | ||
d3086444 JR |
919 | } |
920 | ||
431b2a20 JR |
921 | /**************************************************************************** |
922 | * | |
923 | * The next functions belong to the domain allocation. A domain is | |
924 | * allocated for every IOMMU as the default domain. If device isolation | |
925 | * is enabled, every device get its own domain. The most important thing | |
926 | * about domains is the page table mapping the DMA address space they | |
927 | * contain. | |
928 | * | |
929 | ****************************************************************************/ | |
930 | ||
ec487d1a JR |
931 | static u16 domain_id_alloc(void) |
932 | { | |
933 | unsigned long flags; | |
934 | int id; | |
935 | ||
936 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
937 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
938 | BUG_ON(id == 0); | |
939 | if (id > 0 && id < MAX_DOMAIN_ID) | |
940 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
941 | else | |
942 | id = 0; | |
943 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
944 | ||
945 | return id; | |
946 | } | |
947 | ||
a2acfb75 JR |
948 | static void domain_id_free(int id) |
949 | { | |
950 | unsigned long flags; | |
951 | ||
952 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
953 | if (id > 0 && id < MAX_DOMAIN_ID) | |
954 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
955 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
956 | } | |
a2acfb75 | 957 | |
431b2a20 JR |
958 | /* |
959 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
960 | * ranges. | |
961 | */ | |
ec487d1a JR |
962 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
963 | unsigned long start_page, | |
964 | unsigned int pages) | |
965 | { | |
384de729 | 966 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
967 | |
968 | if (start_page + pages > last_page) | |
969 | pages = last_page - start_page; | |
970 | ||
384de729 JR |
971 | for (i = start_page; i < start_page + pages; ++i) { |
972 | int index = i / APERTURE_RANGE_PAGES; | |
973 | int page = i % APERTURE_RANGE_PAGES; | |
974 | __set_bit(page, dom->aperture[index]->bitmap); | |
975 | } | |
ec487d1a JR |
976 | } |
977 | ||
86db2e5d | 978 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
979 | { |
980 | int i, j; | |
981 | u64 *p1, *p2, *p3; | |
982 | ||
86db2e5d | 983 | p1 = domain->pt_root; |
ec487d1a JR |
984 | |
985 | if (!p1) | |
986 | return; | |
987 | ||
988 | for (i = 0; i < 512; ++i) { | |
989 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
990 | continue; | |
991 | ||
992 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 993 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
994 | if (!IOMMU_PTE_PRESENT(p2[j])) |
995 | continue; | |
996 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
997 | free_page((unsigned long)p3); | |
998 | } | |
999 | ||
1000 | free_page((unsigned long)p2); | |
1001 | } | |
1002 | ||
1003 | free_page((unsigned long)p1); | |
86db2e5d JR |
1004 | |
1005 | domain->pt_root = NULL; | |
ec487d1a JR |
1006 | } |
1007 | ||
431b2a20 JR |
1008 | /* |
1009 | * Free a domain, only used if something went wrong in the | |
1010 | * allocation path and we need to free an already allocated page table | |
1011 | */ | |
ec487d1a JR |
1012 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1013 | { | |
384de729 JR |
1014 | int i; |
1015 | ||
ec487d1a JR |
1016 | if (!dom) |
1017 | return; | |
1018 | ||
86db2e5d | 1019 | free_pagetable(&dom->domain); |
ec487d1a | 1020 | |
384de729 JR |
1021 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1022 | if (!dom->aperture[i]) | |
1023 | continue; | |
1024 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1025 | kfree(dom->aperture[i]); | |
1026 | } | |
ec487d1a JR |
1027 | |
1028 | kfree(dom); | |
1029 | } | |
1030 | ||
431b2a20 JR |
1031 | /* |
1032 | * Allocates a new protection domain usable for the dma_ops functions. | |
1033 | * It also intializes the page table and the address allocator data | |
1034 | * structures required for the dma_ops interface | |
1035 | */ | |
d9cfed92 | 1036 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
1037 | { |
1038 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1039 | |
1040 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1041 | if (!dma_dom) | |
1042 | return NULL; | |
1043 | ||
1044 | spin_lock_init(&dma_dom->domain.lock); | |
1045 | ||
1046 | dma_dom->domain.id = domain_id_alloc(); | |
1047 | if (dma_dom->domain.id == 0) | |
1048 | goto free_dma_dom; | |
1049 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
1050 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 1051 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1052 | dma_dom->domain.priv = dma_dom; |
1053 | if (!dma_dom->domain.pt_root) | |
1054 | goto free_dma_dom; | |
ec487d1a | 1055 | |
1c655773 | 1056 | dma_dom->need_flush = false; |
bd60b735 | 1057 | dma_dom->target_dev = 0xffff; |
1c655773 | 1058 | |
00cd122a | 1059 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1060 | goto free_dma_dom; |
ec487d1a | 1061 | |
431b2a20 | 1062 | /* |
ec487d1a JR |
1063 | * mark the first page as allocated so we never return 0 as |
1064 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1065 | */ |
384de729 | 1066 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1067 | dma_dom->next_address = 0; |
ec487d1a | 1068 | |
ec487d1a JR |
1069 | |
1070 | return dma_dom; | |
1071 | ||
1072 | free_dma_dom: | |
1073 | dma_ops_domain_free(dma_dom); | |
1074 | ||
1075 | return NULL; | |
1076 | } | |
1077 | ||
5b28df6f JR |
1078 | /* |
1079 | * little helper function to check whether a given protection domain is a | |
1080 | * dma_ops domain | |
1081 | */ | |
1082 | static bool dma_ops_domain(struct protection_domain *domain) | |
1083 | { | |
1084 | return domain->flags & PD_DMA_OPS_MASK; | |
1085 | } | |
1086 | ||
431b2a20 JR |
1087 | /* |
1088 | * Find out the protection domain structure for a given PCI device. This | |
1089 | * will give us the pointer to the page table root for example. | |
1090 | */ | |
b20ac0d4 JR |
1091 | static struct protection_domain *domain_for_device(u16 devid) |
1092 | { | |
1093 | struct protection_domain *dom; | |
1094 | unsigned long flags; | |
1095 | ||
1096 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1097 | dom = amd_iommu_pd_table[devid]; | |
1098 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1099 | ||
1100 | return dom; | |
1101 | } | |
1102 | ||
431b2a20 JR |
1103 | /* |
1104 | * If a device is not yet associated with a domain, this function does | |
1105 | * assigns it visible for the hardware | |
1106 | */ | |
f1179dc0 JR |
1107 | static void attach_device(struct amd_iommu *iommu, |
1108 | struct protection_domain *domain, | |
1109 | u16 devid) | |
b20ac0d4 JR |
1110 | { |
1111 | unsigned long flags; | |
b20ac0d4 JR |
1112 | u64 pte_root = virt_to_phys(domain->pt_root); |
1113 | ||
863c74eb JR |
1114 | domain->dev_cnt += 1; |
1115 | ||
38ddf41b JR |
1116 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1117 | << DEV_ENTRY_MODE_SHIFT; | |
1118 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
1119 | |
1120 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
1121 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
1122 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
1123 | amd_iommu_dev_table[devid].data[2] = domain->id; |
1124 | ||
1125 | amd_iommu_pd_table[devid] = domain; | |
1126 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1127 | ||
42a49f96 CW |
1128 | /* |
1129 | * We might boot into a crash-kernel here. The crashed kernel | |
1130 | * left the caches in the IOMMU dirty. So we have to flush | |
1131 | * here to evict all dirty stuff. | |
1132 | */ | |
b20ac0d4 | 1133 | iommu_queue_inv_dev_entry(iommu, devid); |
42a49f96 | 1134 | iommu_flush_tlb_pde(iommu, domain->id); |
b20ac0d4 JR |
1135 | } |
1136 | ||
355bf553 JR |
1137 | /* |
1138 | * Removes a device from a protection domain (unlocked) | |
1139 | */ | |
1140 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1141 | { | |
1142 | ||
1143 | /* lock domain */ | |
1144 | spin_lock(&domain->lock); | |
1145 | ||
1146 | /* remove domain from the lookup table */ | |
1147 | amd_iommu_pd_table[devid] = NULL; | |
1148 | ||
1149 | /* remove entry from the device table seen by the hardware */ | |
1150 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1151 | amd_iommu_dev_table[devid].data[1] = 0; | |
1152 | amd_iommu_dev_table[devid].data[2] = 0; | |
1153 | ||
1154 | /* decrease reference counter */ | |
1155 | domain->dev_cnt -= 1; | |
1156 | ||
1157 | /* ready */ | |
1158 | spin_unlock(&domain->lock); | |
1159 | } | |
1160 | ||
1161 | /* | |
1162 | * Removes a device from a protection domain (with devtable_lock held) | |
1163 | */ | |
1164 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1165 | { | |
1166 | unsigned long flags; | |
1167 | ||
1168 | /* lock device table */ | |
1169 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1170 | __detach_device(domain, devid); | |
1171 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1172 | } | |
e275a2a0 JR |
1173 | |
1174 | static int device_change_notifier(struct notifier_block *nb, | |
1175 | unsigned long action, void *data) | |
1176 | { | |
1177 | struct device *dev = data; | |
1178 | struct pci_dev *pdev = to_pci_dev(dev); | |
1179 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1180 | struct protection_domain *domain; | |
1181 | struct dma_ops_domain *dma_domain; | |
1182 | struct amd_iommu *iommu; | |
1ac4cbbc | 1183 | unsigned long flags; |
e275a2a0 JR |
1184 | |
1185 | if (devid > amd_iommu_last_bdf) | |
1186 | goto out; | |
1187 | ||
1188 | devid = amd_iommu_alias_table[devid]; | |
1189 | ||
1190 | iommu = amd_iommu_rlookup_table[devid]; | |
1191 | if (iommu == NULL) | |
1192 | goto out; | |
1193 | ||
1194 | domain = domain_for_device(devid); | |
1195 | ||
1196 | if (domain && !dma_ops_domain(domain)) | |
1197 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1198 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1199 | ||
1200 | switch (action) { | |
c1eee67b | 1201 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1202 | if (!domain) |
1203 | goto out; | |
1204 | detach_device(domain, devid); | |
1ac4cbbc JR |
1205 | break; |
1206 | case BUS_NOTIFY_ADD_DEVICE: | |
1207 | /* allocate a protection domain if a device is added */ | |
1208 | dma_domain = find_protection_domain(devid); | |
1209 | if (dma_domain) | |
1210 | goto out; | |
d9cfed92 | 1211 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1212 | if (!dma_domain) |
1213 | goto out; | |
1214 | dma_domain->target_dev = devid; | |
1215 | ||
1216 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1217 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1218 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1219 | ||
e275a2a0 JR |
1220 | break; |
1221 | default: | |
1222 | goto out; | |
1223 | } | |
1224 | ||
1225 | iommu_queue_inv_dev_entry(iommu, devid); | |
1226 | iommu_completion_wait(iommu); | |
1227 | ||
1228 | out: | |
1229 | return 0; | |
1230 | } | |
1231 | ||
b25ae679 | 1232 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1233 | .notifier_call = device_change_notifier, |
1234 | }; | |
355bf553 | 1235 | |
431b2a20 JR |
1236 | /***************************************************************************** |
1237 | * | |
1238 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1239 | * | |
1240 | *****************************************************************************/ | |
1241 | ||
dbcc112e JR |
1242 | /* |
1243 | * This function checks if the driver got a valid device from the caller to | |
1244 | * avoid dereferencing invalid pointers. | |
1245 | */ | |
1246 | static bool check_device(struct device *dev) | |
1247 | { | |
1248 | if (!dev || !dev->dma_mask) | |
1249 | return false; | |
1250 | ||
1251 | return true; | |
1252 | } | |
1253 | ||
bd60b735 JR |
1254 | /* |
1255 | * In this function the list of preallocated protection domains is traversed to | |
1256 | * find the domain for a specific device | |
1257 | */ | |
1258 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1259 | { | |
1260 | struct dma_ops_domain *entry, *ret = NULL; | |
1261 | unsigned long flags; | |
1262 | ||
1263 | if (list_empty(&iommu_pd_list)) | |
1264 | return NULL; | |
1265 | ||
1266 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1267 | ||
1268 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1269 | if (entry->target_dev == devid) { | |
1270 | ret = entry; | |
bd60b735 JR |
1271 | break; |
1272 | } | |
1273 | } | |
1274 | ||
1275 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1276 | ||
1277 | return ret; | |
1278 | } | |
1279 | ||
431b2a20 JR |
1280 | /* |
1281 | * In the dma_ops path we only have the struct device. This function | |
1282 | * finds the corresponding IOMMU, the protection domain and the | |
1283 | * requestor id for a given device. | |
1284 | * If the device is not yet associated with a domain this is also done | |
1285 | * in this function. | |
1286 | */ | |
b20ac0d4 JR |
1287 | static int get_device_resources(struct device *dev, |
1288 | struct amd_iommu **iommu, | |
1289 | struct protection_domain **domain, | |
1290 | u16 *bdf) | |
1291 | { | |
1292 | struct dma_ops_domain *dma_dom; | |
1293 | struct pci_dev *pcidev; | |
1294 | u16 _bdf; | |
1295 | ||
dbcc112e JR |
1296 | *iommu = NULL; |
1297 | *domain = NULL; | |
1298 | *bdf = 0xffff; | |
1299 | ||
1300 | if (dev->bus != &pci_bus_type) | |
1301 | return 0; | |
b20ac0d4 JR |
1302 | |
1303 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1304 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1305 | |
431b2a20 | 1306 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1307 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1308 | return 0; |
b20ac0d4 JR |
1309 | |
1310 | *bdf = amd_iommu_alias_table[_bdf]; | |
1311 | ||
1312 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1313 | if (*iommu == NULL) | |
1314 | return 0; | |
b20ac0d4 JR |
1315 | *domain = domain_for_device(*bdf); |
1316 | if (*domain == NULL) { | |
bd60b735 JR |
1317 | dma_dom = find_protection_domain(*bdf); |
1318 | if (!dma_dom) | |
1319 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1320 | *domain = &dma_dom->domain; |
f1179dc0 | 1321 | attach_device(*iommu, *domain, *bdf); |
e9a22a13 JR |
1322 | DUMP_printk("Using protection domain %d for device %s\n", |
1323 | (*domain)->id, dev_name(dev)); | |
b20ac0d4 JR |
1324 | } |
1325 | ||
f91ba190 | 1326 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1327 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1328 | |
b20ac0d4 JR |
1329 | return 1; |
1330 | } | |
1331 | ||
8bda3092 JR |
1332 | /* |
1333 | * If the pte_page is not yet allocated this function is called | |
1334 | */ | |
1335 | static u64* alloc_pte(struct protection_domain *dom, | |
1336 | unsigned long address, u64 **pte_page, gfp_t gfp) | |
1337 | { | |
1338 | u64 *pte, *page; | |
1339 | ||
1340 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
1341 | ||
1342 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1343 | page = (u64 *)get_zeroed_page(gfp); | |
1344 | if (!page) | |
1345 | return NULL; | |
1346 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
1347 | } | |
1348 | ||
1349 | pte = IOMMU_PTE_PAGE(*pte); | |
1350 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
1351 | ||
1352 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1353 | page = (u64 *)get_zeroed_page(gfp); | |
1354 | if (!page) | |
1355 | return NULL; | |
1356 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
1357 | } | |
1358 | ||
1359 | pte = IOMMU_PTE_PAGE(*pte); | |
1360 | ||
1361 | if (pte_page) | |
1362 | *pte_page = pte; | |
1363 | ||
1364 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
1365 | ||
1366 | return pte; | |
1367 | } | |
1368 | ||
1369 | /* | |
1370 | * This function fetches the PTE for a given address in the aperture | |
1371 | */ | |
1372 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1373 | unsigned long address) | |
1374 | { | |
384de729 | 1375 | struct aperture_range *aperture; |
8bda3092 JR |
1376 | u64 *pte, *pte_page; |
1377 | ||
384de729 JR |
1378 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1379 | if (!aperture) | |
1380 | return NULL; | |
1381 | ||
1382 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 JR |
1383 | if (!pte) { |
1384 | pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC); | |
384de729 JR |
1385 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1386 | } else | |
1387 | pte += IOMMU_PTE_L0_INDEX(address); | |
8bda3092 JR |
1388 | |
1389 | return pte; | |
1390 | } | |
1391 | ||
431b2a20 JR |
1392 | /* |
1393 | * This is the generic map function. It maps one 4kb page at paddr to | |
1394 | * the given address in the DMA address space for the domain. | |
1395 | */ | |
cb76c322 JR |
1396 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1397 | struct dma_ops_domain *dom, | |
1398 | unsigned long address, | |
1399 | phys_addr_t paddr, | |
1400 | int direction) | |
1401 | { | |
1402 | u64 *pte, __pte; | |
1403 | ||
1404 | WARN_ON(address > dom->aperture_size); | |
1405 | ||
1406 | paddr &= PAGE_MASK; | |
1407 | ||
8bda3092 | 1408 | pte = dma_ops_get_pte(dom, address); |
53812c11 JR |
1409 | if (!pte) |
1410 | return bad_dma_address; | |
cb76c322 JR |
1411 | |
1412 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1413 | ||
1414 | if (direction == DMA_TO_DEVICE) | |
1415 | __pte |= IOMMU_PTE_IR; | |
1416 | else if (direction == DMA_FROM_DEVICE) | |
1417 | __pte |= IOMMU_PTE_IW; | |
1418 | else if (direction == DMA_BIDIRECTIONAL) | |
1419 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1420 | ||
1421 | WARN_ON(*pte); | |
1422 | ||
1423 | *pte = __pte; | |
1424 | ||
1425 | return (dma_addr_t)address; | |
1426 | } | |
1427 | ||
431b2a20 JR |
1428 | /* |
1429 | * The generic unmapping function for on page in the DMA address space. | |
1430 | */ | |
cb76c322 JR |
1431 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1432 | struct dma_ops_domain *dom, | |
1433 | unsigned long address) | |
1434 | { | |
384de729 | 1435 | struct aperture_range *aperture; |
cb76c322 JR |
1436 | u64 *pte; |
1437 | ||
1438 | if (address >= dom->aperture_size) | |
1439 | return; | |
1440 | ||
384de729 JR |
1441 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1442 | if (!aperture) | |
1443 | return; | |
1444 | ||
1445 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1446 | if (!pte) | |
1447 | return; | |
cb76c322 | 1448 | |
cb76c322 JR |
1449 | pte += IOMMU_PTE_L0_INDEX(address); |
1450 | ||
1451 | WARN_ON(!*pte); | |
1452 | ||
1453 | *pte = 0ULL; | |
1454 | } | |
1455 | ||
431b2a20 JR |
1456 | /* |
1457 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1458 | * contiguous memory region into DMA address space. It is used by all |
1459 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1460 | * Must be called with the domain lock held. |
1461 | */ | |
cb76c322 JR |
1462 | static dma_addr_t __map_single(struct device *dev, |
1463 | struct amd_iommu *iommu, | |
1464 | struct dma_ops_domain *dma_dom, | |
1465 | phys_addr_t paddr, | |
1466 | size_t size, | |
6d4f343f | 1467 | int dir, |
832a90c3 JR |
1468 | bool align, |
1469 | u64 dma_mask) | |
cb76c322 JR |
1470 | { |
1471 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1472 | dma_addr_t address, start, ret; |
cb76c322 | 1473 | unsigned int pages; |
6d4f343f | 1474 | unsigned long align_mask = 0; |
cb76c322 JR |
1475 | int i; |
1476 | ||
e3c449f5 | 1477 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1478 | paddr &= PAGE_MASK; |
1479 | ||
8ecaf8f1 JR |
1480 | INC_STATS_COUNTER(total_map_requests); |
1481 | ||
c1858976 JR |
1482 | if (pages > 1) |
1483 | INC_STATS_COUNTER(cross_page); | |
1484 | ||
6d4f343f JR |
1485 | if (align) |
1486 | align_mask = (1UL << get_order(size)) - 1; | |
1487 | ||
11b83888 | 1488 | retry: |
832a90c3 JR |
1489 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1490 | dma_mask); | |
11b83888 JR |
1491 | if (unlikely(address == bad_dma_address)) { |
1492 | /* | |
1493 | * setting next_address here will let the address | |
1494 | * allocator only scan the new allocated range in the | |
1495 | * first run. This is a small optimization. | |
1496 | */ | |
1497 | dma_dom->next_address = dma_dom->aperture_size; | |
1498 | ||
1499 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1500 | goto out; | |
1501 | ||
1502 | /* | |
1503 | * aperture was sucessfully enlarged by 128 MB, try | |
1504 | * allocation again | |
1505 | */ | |
1506 | goto retry; | |
1507 | } | |
cb76c322 JR |
1508 | |
1509 | start = address; | |
1510 | for (i = 0; i < pages; ++i) { | |
53812c11 JR |
1511 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
1512 | if (ret == bad_dma_address) | |
1513 | goto out_unmap; | |
1514 | ||
cb76c322 JR |
1515 | paddr += PAGE_SIZE; |
1516 | start += PAGE_SIZE; | |
1517 | } | |
1518 | address += offset; | |
1519 | ||
5774f7c5 JR |
1520 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1521 | ||
afa9fdc2 | 1522 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1523 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1524 | dma_dom->need_flush = false; | |
1525 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1526 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1527 | ||
cb76c322 JR |
1528 | out: |
1529 | return address; | |
53812c11 JR |
1530 | |
1531 | out_unmap: | |
1532 | ||
1533 | for (--i; i >= 0; --i) { | |
1534 | start -= PAGE_SIZE; | |
1535 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1536 | } | |
1537 | ||
1538 | dma_ops_free_addresses(dma_dom, address, pages); | |
1539 | ||
1540 | return bad_dma_address; | |
cb76c322 JR |
1541 | } |
1542 | ||
431b2a20 JR |
1543 | /* |
1544 | * Does the reverse of the __map_single function. Must be called with | |
1545 | * the domain lock held too | |
1546 | */ | |
cb76c322 JR |
1547 | static void __unmap_single(struct amd_iommu *iommu, |
1548 | struct dma_ops_domain *dma_dom, | |
1549 | dma_addr_t dma_addr, | |
1550 | size_t size, | |
1551 | int dir) | |
1552 | { | |
1553 | dma_addr_t i, start; | |
1554 | unsigned int pages; | |
1555 | ||
b8d9905d JR |
1556 | if ((dma_addr == bad_dma_address) || |
1557 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1558 | return; |
1559 | ||
e3c449f5 | 1560 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1561 | dma_addr &= PAGE_MASK; |
1562 | start = dma_addr; | |
1563 | ||
1564 | for (i = 0; i < pages; ++i) { | |
1565 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1566 | start += PAGE_SIZE; | |
1567 | } | |
1568 | ||
5774f7c5 JR |
1569 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1570 | ||
cb76c322 | 1571 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1572 | |
80be308d | 1573 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1574 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1575 | dma_dom->need_flush = false; |
1576 | } | |
cb76c322 JR |
1577 | } |
1578 | ||
431b2a20 JR |
1579 | /* |
1580 | * The exported map_single function for dma_ops. | |
1581 | */ | |
51491367 FT |
1582 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1583 | unsigned long offset, size_t size, | |
1584 | enum dma_data_direction dir, | |
1585 | struct dma_attrs *attrs) | |
4da70b9e JR |
1586 | { |
1587 | unsigned long flags; | |
1588 | struct amd_iommu *iommu; | |
1589 | struct protection_domain *domain; | |
1590 | u16 devid; | |
1591 | dma_addr_t addr; | |
832a90c3 | 1592 | u64 dma_mask; |
51491367 | 1593 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1594 | |
0f2a86f2 JR |
1595 | INC_STATS_COUNTER(cnt_map_single); |
1596 | ||
dbcc112e JR |
1597 | if (!check_device(dev)) |
1598 | return bad_dma_address; | |
1599 | ||
832a90c3 | 1600 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1601 | |
1602 | get_device_resources(dev, &iommu, &domain, &devid); | |
1603 | ||
1604 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1605 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1606 | return (dma_addr_t)paddr; |
1607 | ||
5b28df6f JR |
1608 | if (!dma_ops_domain(domain)) |
1609 | return bad_dma_address; | |
1610 | ||
4da70b9e | 1611 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1612 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1613 | dma_mask); | |
4da70b9e JR |
1614 | if (addr == bad_dma_address) |
1615 | goto out; | |
1616 | ||
09ee17eb | 1617 | iommu_completion_wait(iommu); |
4da70b9e JR |
1618 | |
1619 | out: | |
1620 | spin_unlock_irqrestore(&domain->lock, flags); | |
1621 | ||
1622 | return addr; | |
1623 | } | |
1624 | ||
431b2a20 JR |
1625 | /* |
1626 | * The exported unmap_single function for dma_ops. | |
1627 | */ | |
51491367 FT |
1628 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1629 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1630 | { |
1631 | unsigned long flags; | |
1632 | struct amd_iommu *iommu; | |
1633 | struct protection_domain *domain; | |
1634 | u16 devid; | |
1635 | ||
146a6917 JR |
1636 | INC_STATS_COUNTER(cnt_unmap_single); |
1637 | ||
dbcc112e JR |
1638 | if (!check_device(dev) || |
1639 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1640 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1641 | return; |
1642 | ||
5b28df6f JR |
1643 | if (!dma_ops_domain(domain)) |
1644 | return; | |
1645 | ||
4da70b9e JR |
1646 | spin_lock_irqsave(&domain->lock, flags); |
1647 | ||
1648 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1649 | ||
09ee17eb | 1650 | iommu_completion_wait(iommu); |
4da70b9e JR |
1651 | |
1652 | spin_unlock_irqrestore(&domain->lock, flags); | |
1653 | } | |
1654 | ||
431b2a20 JR |
1655 | /* |
1656 | * This is a special map_sg function which is used if we should map a | |
1657 | * device which is not handled by an AMD IOMMU in the system. | |
1658 | */ | |
65b050ad JR |
1659 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1660 | int nelems, int dir) | |
1661 | { | |
1662 | struct scatterlist *s; | |
1663 | int i; | |
1664 | ||
1665 | for_each_sg(sglist, s, nelems, i) { | |
1666 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1667 | s->dma_length = s->length; | |
1668 | } | |
1669 | ||
1670 | return nelems; | |
1671 | } | |
1672 | ||
431b2a20 JR |
1673 | /* |
1674 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1675 | * lists). | |
1676 | */ | |
65b050ad | 1677 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1678 | int nelems, enum dma_data_direction dir, |
1679 | struct dma_attrs *attrs) | |
65b050ad JR |
1680 | { |
1681 | unsigned long flags; | |
1682 | struct amd_iommu *iommu; | |
1683 | struct protection_domain *domain; | |
1684 | u16 devid; | |
1685 | int i; | |
1686 | struct scatterlist *s; | |
1687 | phys_addr_t paddr; | |
1688 | int mapped_elems = 0; | |
832a90c3 | 1689 | u64 dma_mask; |
65b050ad | 1690 | |
d03f067a JR |
1691 | INC_STATS_COUNTER(cnt_map_sg); |
1692 | ||
dbcc112e JR |
1693 | if (!check_device(dev)) |
1694 | return 0; | |
1695 | ||
832a90c3 | 1696 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1697 | |
1698 | get_device_resources(dev, &iommu, &domain, &devid); | |
1699 | ||
1700 | if (!iommu || !domain) | |
1701 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1702 | ||
5b28df6f JR |
1703 | if (!dma_ops_domain(domain)) |
1704 | return 0; | |
1705 | ||
65b050ad JR |
1706 | spin_lock_irqsave(&domain->lock, flags); |
1707 | ||
1708 | for_each_sg(sglist, s, nelems, i) { | |
1709 | paddr = sg_phys(s); | |
1710 | ||
1711 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1712 | paddr, s->length, dir, false, |
1713 | dma_mask); | |
65b050ad JR |
1714 | |
1715 | if (s->dma_address) { | |
1716 | s->dma_length = s->length; | |
1717 | mapped_elems++; | |
1718 | } else | |
1719 | goto unmap; | |
65b050ad JR |
1720 | } |
1721 | ||
09ee17eb | 1722 | iommu_completion_wait(iommu); |
65b050ad JR |
1723 | |
1724 | out: | |
1725 | spin_unlock_irqrestore(&domain->lock, flags); | |
1726 | ||
1727 | return mapped_elems; | |
1728 | unmap: | |
1729 | for_each_sg(sglist, s, mapped_elems, i) { | |
1730 | if (s->dma_address) | |
1731 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1732 | s->dma_length, dir); | |
1733 | s->dma_address = s->dma_length = 0; | |
1734 | } | |
1735 | ||
1736 | mapped_elems = 0; | |
1737 | ||
1738 | goto out; | |
1739 | } | |
1740 | ||
431b2a20 JR |
1741 | /* |
1742 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1743 | * lists). | |
1744 | */ | |
65b050ad | 1745 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1746 | int nelems, enum dma_data_direction dir, |
1747 | struct dma_attrs *attrs) | |
65b050ad JR |
1748 | { |
1749 | unsigned long flags; | |
1750 | struct amd_iommu *iommu; | |
1751 | struct protection_domain *domain; | |
1752 | struct scatterlist *s; | |
1753 | u16 devid; | |
1754 | int i; | |
1755 | ||
55877a6b JR |
1756 | INC_STATS_COUNTER(cnt_unmap_sg); |
1757 | ||
dbcc112e JR |
1758 | if (!check_device(dev) || |
1759 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1760 | return; |
1761 | ||
5b28df6f JR |
1762 | if (!dma_ops_domain(domain)) |
1763 | return; | |
1764 | ||
65b050ad JR |
1765 | spin_lock_irqsave(&domain->lock, flags); |
1766 | ||
1767 | for_each_sg(sglist, s, nelems, i) { | |
1768 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1769 | s->dma_length, dir); | |
65b050ad JR |
1770 | s->dma_address = s->dma_length = 0; |
1771 | } | |
1772 | ||
09ee17eb | 1773 | iommu_completion_wait(iommu); |
65b050ad JR |
1774 | |
1775 | spin_unlock_irqrestore(&domain->lock, flags); | |
1776 | } | |
1777 | ||
431b2a20 JR |
1778 | /* |
1779 | * The exported alloc_coherent function for dma_ops. | |
1780 | */ | |
5d8b53cf JR |
1781 | static void *alloc_coherent(struct device *dev, size_t size, |
1782 | dma_addr_t *dma_addr, gfp_t flag) | |
1783 | { | |
1784 | unsigned long flags; | |
1785 | void *virt_addr; | |
1786 | struct amd_iommu *iommu; | |
1787 | struct protection_domain *domain; | |
1788 | u16 devid; | |
1789 | phys_addr_t paddr; | |
832a90c3 | 1790 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1791 | |
c8f0fb36 JR |
1792 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1793 | ||
dbcc112e JR |
1794 | if (!check_device(dev)) |
1795 | return NULL; | |
5d8b53cf | 1796 | |
13d9fead FT |
1797 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1798 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1799 | |
c97ac535 | 1800 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1801 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1802 | if (!virt_addr) | |
b25ae679 | 1803 | return NULL; |
5d8b53cf | 1804 | |
5d8b53cf JR |
1805 | paddr = virt_to_phys(virt_addr); |
1806 | ||
5d8b53cf JR |
1807 | if (!iommu || !domain) { |
1808 | *dma_addr = (dma_addr_t)paddr; | |
1809 | return virt_addr; | |
1810 | } | |
1811 | ||
5b28df6f JR |
1812 | if (!dma_ops_domain(domain)) |
1813 | goto out_free; | |
1814 | ||
832a90c3 JR |
1815 | if (!dma_mask) |
1816 | dma_mask = *dev->dma_mask; | |
1817 | ||
5d8b53cf JR |
1818 | spin_lock_irqsave(&domain->lock, flags); |
1819 | ||
1820 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1821 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1822 | |
367d04c4 JS |
1823 | if (*dma_addr == bad_dma_address) { |
1824 | spin_unlock_irqrestore(&domain->lock, flags); | |
5b28df6f | 1825 | goto out_free; |
367d04c4 | 1826 | } |
5d8b53cf | 1827 | |
09ee17eb | 1828 | iommu_completion_wait(iommu); |
5d8b53cf | 1829 | |
5d8b53cf JR |
1830 | spin_unlock_irqrestore(&domain->lock, flags); |
1831 | ||
1832 | return virt_addr; | |
5b28df6f JR |
1833 | |
1834 | out_free: | |
1835 | ||
1836 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1837 | ||
1838 | return NULL; | |
5d8b53cf JR |
1839 | } |
1840 | ||
431b2a20 JR |
1841 | /* |
1842 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1843 | */ |
5d8b53cf JR |
1844 | static void free_coherent(struct device *dev, size_t size, |
1845 | void *virt_addr, dma_addr_t dma_addr) | |
1846 | { | |
1847 | unsigned long flags; | |
1848 | struct amd_iommu *iommu; | |
1849 | struct protection_domain *domain; | |
1850 | u16 devid; | |
1851 | ||
5d31ee7e JR |
1852 | INC_STATS_COUNTER(cnt_free_coherent); |
1853 | ||
dbcc112e JR |
1854 | if (!check_device(dev)) |
1855 | return; | |
1856 | ||
5d8b53cf JR |
1857 | get_device_resources(dev, &iommu, &domain, &devid); |
1858 | ||
1859 | if (!iommu || !domain) | |
1860 | goto free_mem; | |
1861 | ||
5b28df6f JR |
1862 | if (!dma_ops_domain(domain)) |
1863 | goto free_mem; | |
1864 | ||
5d8b53cf JR |
1865 | spin_lock_irqsave(&domain->lock, flags); |
1866 | ||
1867 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1868 | |
09ee17eb | 1869 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1870 | |
1871 | spin_unlock_irqrestore(&domain->lock, flags); | |
1872 | ||
1873 | free_mem: | |
1874 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1875 | } | |
1876 | ||
b39ba6ad JR |
1877 | /* |
1878 | * This function is called by the DMA layer to find out if we can handle a | |
1879 | * particular device. It is part of the dma_ops. | |
1880 | */ | |
1881 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1882 | { | |
1883 | u16 bdf; | |
1884 | struct pci_dev *pcidev; | |
1885 | ||
1886 | /* No device or no PCI device */ | |
1887 | if (!dev || dev->bus != &pci_bus_type) | |
1888 | return 0; | |
1889 | ||
1890 | pcidev = to_pci_dev(dev); | |
1891 | ||
1892 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1893 | ||
1894 | /* Out of our scope? */ | |
1895 | if (bdf > amd_iommu_last_bdf) | |
1896 | return 0; | |
1897 | ||
1898 | return 1; | |
1899 | } | |
1900 | ||
c432f3df | 1901 | /* |
431b2a20 JR |
1902 | * The function for pre-allocating protection domains. |
1903 | * | |
c432f3df JR |
1904 | * If the driver core informs the DMA layer if a driver grabs a device |
1905 | * we don't need to preallocate the protection domains anymore. | |
1906 | * For now we have to. | |
1907 | */ | |
0e93dd88 | 1908 | static void prealloc_protection_domains(void) |
c432f3df JR |
1909 | { |
1910 | struct pci_dev *dev = NULL; | |
1911 | struct dma_ops_domain *dma_dom; | |
1912 | struct amd_iommu *iommu; | |
c432f3df JR |
1913 | u16 devid; |
1914 | ||
1915 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1916 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1917 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1918 | continue; |
1919 | devid = amd_iommu_alias_table[devid]; | |
1920 | if (domain_for_device(devid)) | |
1921 | continue; | |
1922 | iommu = amd_iommu_rlookup_table[devid]; | |
1923 | if (!iommu) | |
1924 | continue; | |
d9cfed92 | 1925 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
1926 | if (!dma_dom) |
1927 | continue; | |
1928 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1929 | dma_dom->target_dev = devid; |
1930 | ||
1931 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1932 | } |
1933 | } | |
1934 | ||
160c1d8e | 1935 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
1936 | .alloc_coherent = alloc_coherent, |
1937 | .free_coherent = free_coherent, | |
51491367 FT |
1938 | .map_page = map_page, |
1939 | .unmap_page = unmap_page, | |
6631ee9d JR |
1940 | .map_sg = map_sg, |
1941 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1942 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1943 | }; |
1944 | ||
431b2a20 JR |
1945 | /* |
1946 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1947 | */ | |
6631ee9d JR |
1948 | int __init amd_iommu_init_dma_ops(void) |
1949 | { | |
1950 | struct amd_iommu *iommu; | |
6631ee9d JR |
1951 | int ret; |
1952 | ||
431b2a20 JR |
1953 | /* |
1954 | * first allocate a default protection domain for every IOMMU we | |
1955 | * found in the system. Devices not assigned to any other | |
1956 | * protection domain will be assigned to the default one. | |
1957 | */ | |
3bd22172 | 1958 | for_each_iommu(iommu) { |
d9cfed92 | 1959 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
1960 | if (iommu->default_dom == NULL) |
1961 | return -ENOMEM; | |
e2dc14a2 | 1962 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1963 | ret = iommu_init_unity_mappings(iommu); |
1964 | if (ret) | |
1965 | goto free_domains; | |
1966 | } | |
1967 | ||
431b2a20 JR |
1968 | /* |
1969 | * If device isolation is enabled, pre-allocate the protection | |
1970 | * domains for each device. | |
1971 | */ | |
6631ee9d JR |
1972 | if (amd_iommu_isolate) |
1973 | prealloc_protection_domains(); | |
1974 | ||
1975 | iommu_detected = 1; | |
1976 | force_iommu = 1; | |
1977 | bad_dma_address = 0; | |
92af4e29 | 1978 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1979 | gart_iommu_aperture_disabled = 1; |
1980 | gart_iommu_aperture = 0; | |
92af4e29 | 1981 | #endif |
6631ee9d | 1982 | |
431b2a20 | 1983 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1984 | dma_ops = &amd_iommu_dma_ops; |
1985 | ||
26961efe | 1986 | register_iommu(&amd_iommu_ops); |
26961efe | 1987 | |
e275a2a0 JR |
1988 | bus_register_notifier(&pci_bus_type, &device_nb); |
1989 | ||
7f26508b JR |
1990 | amd_iommu_stats_init(); |
1991 | ||
6631ee9d JR |
1992 | return 0; |
1993 | ||
1994 | free_domains: | |
1995 | ||
3bd22172 | 1996 | for_each_iommu(iommu) { |
6631ee9d JR |
1997 | if (iommu->default_dom) |
1998 | dma_ops_domain_free(iommu->default_dom); | |
1999 | } | |
2000 | ||
2001 | return ret; | |
2002 | } | |
6d98cd80 JR |
2003 | |
2004 | /***************************************************************************** | |
2005 | * | |
2006 | * The following functions belong to the exported interface of AMD IOMMU | |
2007 | * | |
2008 | * This interface allows access to lower level functions of the IOMMU | |
2009 | * like protection domain handling and assignement of devices to domains | |
2010 | * which is not possible with the dma_ops interface. | |
2011 | * | |
2012 | *****************************************************************************/ | |
2013 | ||
6d98cd80 JR |
2014 | static void cleanup_domain(struct protection_domain *domain) |
2015 | { | |
2016 | unsigned long flags; | |
2017 | u16 devid; | |
2018 | ||
2019 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2020 | ||
2021 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
2022 | if (amd_iommu_pd_table[devid] == domain) | |
2023 | __detach_device(domain, devid); | |
2024 | ||
2025 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2026 | } | |
2027 | ||
c156e347 JR |
2028 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
2029 | { | |
2030 | struct protection_domain *domain; | |
2031 | ||
2032 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2033 | if (!domain) | |
2034 | return -ENOMEM; | |
2035 | ||
2036 | spin_lock_init(&domain->lock); | |
2037 | domain->mode = PAGE_MODE_3_LEVEL; | |
2038 | domain->id = domain_id_alloc(); | |
2039 | if (!domain->id) | |
2040 | goto out_free; | |
2041 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2042 | if (!domain->pt_root) | |
2043 | goto out_free; | |
2044 | ||
2045 | dom->priv = domain; | |
2046 | ||
2047 | return 0; | |
2048 | ||
2049 | out_free: | |
2050 | kfree(domain); | |
2051 | ||
2052 | return -ENOMEM; | |
2053 | } | |
2054 | ||
98383fc3 JR |
2055 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2056 | { | |
2057 | struct protection_domain *domain = dom->priv; | |
2058 | ||
2059 | if (!domain) | |
2060 | return; | |
2061 | ||
2062 | if (domain->dev_cnt > 0) | |
2063 | cleanup_domain(domain); | |
2064 | ||
2065 | BUG_ON(domain->dev_cnt != 0); | |
2066 | ||
2067 | free_pagetable(domain); | |
2068 | ||
2069 | domain_id_free(domain->id); | |
2070 | ||
2071 | kfree(domain); | |
2072 | ||
2073 | dom->priv = NULL; | |
2074 | } | |
2075 | ||
684f2888 JR |
2076 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2077 | struct device *dev) | |
2078 | { | |
2079 | struct protection_domain *domain = dom->priv; | |
2080 | struct amd_iommu *iommu; | |
2081 | struct pci_dev *pdev; | |
2082 | u16 devid; | |
2083 | ||
2084 | if (dev->bus != &pci_bus_type) | |
2085 | return; | |
2086 | ||
2087 | pdev = to_pci_dev(dev); | |
2088 | ||
2089 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2090 | ||
2091 | if (devid > 0) | |
2092 | detach_device(domain, devid); | |
2093 | ||
2094 | iommu = amd_iommu_rlookup_table[devid]; | |
2095 | if (!iommu) | |
2096 | return; | |
2097 | ||
2098 | iommu_queue_inv_dev_entry(iommu, devid); | |
2099 | iommu_completion_wait(iommu); | |
2100 | } | |
2101 | ||
01106066 JR |
2102 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2103 | struct device *dev) | |
2104 | { | |
2105 | struct protection_domain *domain = dom->priv; | |
2106 | struct protection_domain *old_domain; | |
2107 | struct amd_iommu *iommu; | |
2108 | struct pci_dev *pdev; | |
2109 | u16 devid; | |
2110 | ||
2111 | if (dev->bus != &pci_bus_type) | |
2112 | return -EINVAL; | |
2113 | ||
2114 | pdev = to_pci_dev(dev); | |
2115 | ||
2116 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2117 | ||
2118 | if (devid >= amd_iommu_last_bdf || | |
2119 | devid != amd_iommu_alias_table[devid]) | |
2120 | return -EINVAL; | |
2121 | ||
2122 | iommu = amd_iommu_rlookup_table[devid]; | |
2123 | if (!iommu) | |
2124 | return -EINVAL; | |
2125 | ||
2126 | old_domain = domain_for_device(devid); | |
2127 | if (old_domain) | |
71ff3bca | 2128 | detach_device(old_domain, devid); |
01106066 JR |
2129 | |
2130 | attach_device(iommu, domain, devid); | |
2131 | ||
2132 | iommu_completion_wait(iommu); | |
2133 | ||
2134 | return 0; | |
2135 | } | |
2136 | ||
c6229ca6 JR |
2137 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2138 | unsigned long iova, phys_addr_t paddr, | |
2139 | size_t size, int iommu_prot) | |
2140 | { | |
2141 | struct protection_domain *domain = dom->priv; | |
2142 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2143 | int prot = 0; | |
2144 | int ret; | |
2145 | ||
2146 | if (iommu_prot & IOMMU_READ) | |
2147 | prot |= IOMMU_PROT_IR; | |
2148 | if (iommu_prot & IOMMU_WRITE) | |
2149 | prot |= IOMMU_PROT_IW; | |
2150 | ||
2151 | iova &= PAGE_MASK; | |
2152 | paddr &= PAGE_MASK; | |
2153 | ||
2154 | for (i = 0; i < npages; ++i) { | |
2155 | ret = iommu_map_page(domain, iova, paddr, prot); | |
2156 | if (ret) | |
2157 | return ret; | |
2158 | ||
2159 | iova += PAGE_SIZE; | |
2160 | paddr += PAGE_SIZE; | |
2161 | } | |
2162 | ||
2163 | return 0; | |
2164 | } | |
2165 | ||
eb74ff6c JR |
2166 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2167 | unsigned long iova, size_t size) | |
2168 | { | |
2169 | ||
2170 | struct protection_domain *domain = dom->priv; | |
2171 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2172 | ||
2173 | iova &= PAGE_MASK; | |
2174 | ||
2175 | for (i = 0; i < npages; ++i) { | |
2176 | iommu_unmap_page(domain, iova); | |
2177 | iova += PAGE_SIZE; | |
2178 | } | |
2179 | ||
2180 | iommu_flush_domain(domain->id); | |
2181 | } | |
2182 | ||
645c4c8d JR |
2183 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2184 | unsigned long iova) | |
2185 | { | |
2186 | struct protection_domain *domain = dom->priv; | |
2187 | unsigned long offset = iova & ~PAGE_MASK; | |
2188 | phys_addr_t paddr; | |
2189 | u64 *pte; | |
2190 | ||
2191 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
2192 | ||
2193 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2194 | return 0; | |
2195 | ||
2196 | pte = IOMMU_PTE_PAGE(*pte); | |
2197 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
2198 | ||
2199 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2200 | return 0; | |
2201 | ||
2202 | pte = IOMMU_PTE_PAGE(*pte); | |
2203 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
2204 | ||
2205 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2206 | return 0; | |
2207 | ||
2208 | paddr = *pte & IOMMU_PAGE_MASK; | |
2209 | paddr |= offset; | |
2210 | ||
2211 | return paddr; | |
2212 | } | |
2213 | ||
dbb9fd86 SY |
2214 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2215 | unsigned long cap) | |
2216 | { | |
2217 | return 0; | |
2218 | } | |
2219 | ||
26961efe JR |
2220 | static struct iommu_ops amd_iommu_ops = { |
2221 | .domain_init = amd_iommu_domain_init, | |
2222 | .domain_destroy = amd_iommu_domain_destroy, | |
2223 | .attach_dev = amd_iommu_attach_device, | |
2224 | .detach_dev = amd_iommu_detach_device, | |
2225 | .map = amd_iommu_map_range, | |
2226 | .unmap = amd_iommu_unmap_range, | |
2227 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2228 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2229 | }; |
2230 |