Commit | Line | Data |
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f6e2e6b6 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
22 | #include <linux/gfp.h> | |
23 | #include <linux/list.h> | |
7441e9cb | 24 | #include <linux/sysdev.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
f6e2e6b6 JR |
27 | #include <asm/pci-direct.h> |
28 | #include <asm/amd_iommu_types.h> | |
c6da992e | 29 | #include <asm/amd_iommu.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
f6e2e6b6 JR |
32 | |
33 | /* | |
34 | * definitions for the ACPI scanning code | |
35 | */ | |
f6e2e6b6 | 36 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
37 | |
38 | #define ACPI_IVHD_TYPE 0x10 | |
39 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
40 | #define ACPI_IVMD_TYPE 0x21 | |
41 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
42 | ||
43 | #define IVHD_DEV_ALL 0x01 | |
44 | #define IVHD_DEV_SELECT 0x02 | |
45 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
46 | #define IVHD_DEV_RANGE_END 0x04 | |
47 | #define IVHD_DEV_ALIAS 0x42 | |
48 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
49 | #define IVHD_DEV_EXT_SELECT 0x46 | |
50 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
51 | ||
6da7342f JR |
52 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 |
53 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | |
54 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | |
55 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | |
f6e2e6b6 JR |
56 | |
57 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
58 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
59 | ||
60 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
61 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
62 | #define ACPI_DEVFLAG_NMI 0x04 | |
63 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
64 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
65 | #define ACPI_DEVFLAG_LINT0 0x40 | |
66 | #define ACPI_DEVFLAG_LINT1 0x80 | |
67 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
68 | ||
b65233a9 JR |
69 | /* |
70 | * ACPI table definitions | |
71 | * | |
72 | * These data structures are laid over the table to parse the important values | |
73 | * out of it. | |
74 | */ | |
75 | ||
76 | /* | |
77 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
78 | * or more ivhd_entrys. | |
79 | */ | |
f6e2e6b6 JR |
80 | struct ivhd_header { |
81 | u8 type; | |
82 | u8 flags; | |
83 | u16 length; | |
84 | u16 devid; | |
85 | u16 cap_ptr; | |
86 | u64 mmio_phys; | |
87 | u16 pci_seg; | |
88 | u16 info; | |
89 | u32 reserved; | |
90 | } __attribute__((packed)); | |
91 | ||
b65233a9 JR |
92 | /* |
93 | * A device entry describing which devices a specific IOMMU translates and | |
94 | * which requestor ids they use. | |
95 | */ | |
f6e2e6b6 JR |
96 | struct ivhd_entry { |
97 | u8 type; | |
98 | u16 devid; | |
99 | u8 flags; | |
100 | u32 ext; | |
101 | } __attribute__((packed)); | |
102 | ||
b65233a9 JR |
103 | /* |
104 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
105 | * ranges for devices and regions that should be unity mapped. | |
106 | */ | |
f6e2e6b6 JR |
107 | struct ivmd_header { |
108 | u8 type; | |
109 | u8 flags; | |
110 | u16 length; | |
111 | u16 devid; | |
112 | u16 aux; | |
113 | u64 resv; | |
114 | u64 range_start; | |
115 | u64 range_length; | |
116 | } __attribute__((packed)); | |
117 | ||
fefda117 JR |
118 | bool amd_iommu_dump; |
119 | ||
c1cbebee JR |
120 | static int __initdata amd_iommu_detected; |
121 | ||
b65233a9 JR |
122 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
123 | to handle */ | |
2e22847f | 124 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 | 125 | we find in ACPI */ |
2e8b5696 JR |
126 | #ifdef CONFIG_IOMMU_STRESS |
127 | bool amd_iommu_isolate = false; | |
128 | #else | |
c226f853 JR |
129 | bool amd_iommu_isolate = true; /* if true, device isolation is |
130 | enabled */ | |
2e8b5696 JR |
131 | #endif |
132 | ||
afa9fdc2 | 133 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 134 | |
2e22847f | 135 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 136 | system */ |
928abd25 | 137 | |
b65233a9 JR |
138 | /* |
139 | * Pointer to the device table which is shared by all AMD IOMMUs | |
140 | * it is indexed by the PCI device id or the HT unit id and contains | |
141 | * information about the domain the device belongs to as well as the | |
142 | * page table root pointer. | |
143 | */ | |
928abd25 | 144 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
145 | |
146 | /* | |
147 | * The alias table is a driver specific data structure which contains the | |
148 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
149 | * More than one device can share the same requestor id. | |
150 | */ | |
928abd25 | 151 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
152 | |
153 | /* | |
154 | * The rlookup table is used to find the IOMMU which is responsible | |
155 | * for a specific device. It is also indexed by the PCI device id. | |
156 | */ | |
928abd25 | 157 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 JR |
158 | |
159 | /* | |
160 | * The pd table (protection domain table) is used to find the protection domain | |
161 | * data structure a device belongs to. Indexed with the PCI device id too. | |
162 | */ | |
928abd25 | 163 | struct protection_domain **amd_iommu_pd_table; |
b65233a9 JR |
164 | |
165 | /* | |
166 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
167 | * to know which ones are already in use. | |
168 | */ | |
928abd25 JR |
169 | unsigned long *amd_iommu_pd_alloc_bitmap; |
170 | ||
b65233a9 JR |
171 | static u32 dev_table_size; /* size of the device table */ |
172 | static u32 alias_table_size; /* size of the alias table */ | |
173 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 174 | |
208ec8c9 JR |
175 | static inline void update_last_devid(u16 devid) |
176 | { | |
177 | if (devid > amd_iommu_last_bdf) | |
178 | amd_iommu_last_bdf = devid; | |
179 | } | |
180 | ||
c571484e JR |
181 | static inline unsigned long tbl_size(int entry_size) |
182 | { | |
183 | unsigned shift = PAGE_SHIFT + | |
421f909c | 184 | get_order(((int)amd_iommu_last_bdf + 1) * entry_size); |
c571484e JR |
185 | |
186 | return 1UL << shift; | |
187 | } | |
188 | ||
b65233a9 JR |
189 | /**************************************************************************** |
190 | * | |
191 | * AMD IOMMU MMIO register space handling functions | |
192 | * | |
193 | * These functions are used to program the IOMMU device registers in | |
194 | * MMIO space required for that driver. | |
195 | * | |
196 | ****************************************************************************/ | |
3e8064ba | 197 | |
b65233a9 JR |
198 | /* |
199 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
200 | * exclusion range are passed through untranslated | |
201 | */ | |
05f92db9 | 202 | static void iommu_set_exclusion_range(struct amd_iommu *iommu) |
b2026aa2 JR |
203 | { |
204 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
205 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
206 | u64 entry; | |
207 | ||
208 | if (!iommu->exclusion_start) | |
209 | return; | |
210 | ||
211 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
212 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
213 | &entry, sizeof(entry)); | |
214 | ||
215 | entry = limit; | |
216 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
217 | &entry, sizeof(entry)); | |
218 | } | |
219 | ||
b65233a9 | 220 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
221 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
222 | { | |
f609891f | 223 | u64 entry; |
b2026aa2 JR |
224 | |
225 | BUG_ON(iommu->mmio_base == NULL); | |
226 | ||
227 | entry = virt_to_phys(amd_iommu_dev_table); | |
228 | entry |= (dev_table_size >> 12) - 1; | |
229 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
230 | &entry, sizeof(entry)); | |
231 | } | |
232 | ||
b65233a9 | 233 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
05f92db9 | 234 | static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
235 | { |
236 | u32 ctrl; | |
237 | ||
238 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
239 | ctrl |= (1 << bit); | |
240 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
241 | } | |
242 | ||
243 | static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit) | |
244 | { | |
245 | u32 ctrl; | |
246 | ||
199d0d50 | 247 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
248 | ctrl &= ~(1 << bit); |
249 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
250 | } | |
251 | ||
b65233a9 | 252 | /* Function to enable the hardware */ |
05f92db9 | 253 | static void iommu_enable(struct amd_iommu *iommu) |
b2026aa2 | 254 | { |
4c6f40d4 | 255 | printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n", |
a4e267c8 | 256 | dev_name(&iommu->dev->dev), iommu->cap_ptr); |
b2026aa2 JR |
257 | |
258 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); | |
b2026aa2 JR |
259 | } |
260 | ||
92ac4320 | 261 | static void iommu_disable(struct amd_iommu *iommu) |
126c52be | 262 | { |
a8c485bb CW |
263 | /* Disable command buffer */ |
264 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
265 | ||
266 | /* Disable event logging and event interrupts */ | |
267 | iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); | |
268 | iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); | |
269 | ||
270 | /* Disable IOMMU hardware itself */ | |
92ac4320 | 271 | iommu_feature_disable(iommu, CONTROL_IOMMU_EN); |
126c52be JR |
272 | } |
273 | ||
b65233a9 JR |
274 | /* |
275 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
276 | * the system has one. | |
277 | */ | |
6c56747b JR |
278 | static u8 * __init iommu_map_mmio_space(u64 address) |
279 | { | |
280 | u8 *ret; | |
281 | ||
282 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) | |
283 | return NULL; | |
284 | ||
285 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
286 | if (ret != NULL) | |
287 | return ret; | |
288 | ||
289 | release_mem_region(address, MMIO_REGION_LENGTH); | |
290 | ||
291 | return NULL; | |
292 | } | |
293 | ||
294 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
295 | { | |
296 | if (iommu->mmio_base) | |
297 | iounmap(iommu->mmio_base); | |
298 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
299 | } | |
300 | ||
b65233a9 JR |
301 | /**************************************************************************** |
302 | * | |
303 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
304 | * parsing. In this pass we try to find out the highest device id this | |
305 | * code has to handle. Upon this information the size of the shared data | |
306 | * structures is determined later. | |
307 | * | |
308 | ****************************************************************************/ | |
309 | ||
b514e555 JR |
310 | /* |
311 | * This function calculates the length of a given IVHD entry | |
312 | */ | |
313 | static inline int ivhd_entry_length(u8 *ivhd) | |
314 | { | |
315 | return 0x04 << (*ivhd >> 6); | |
316 | } | |
317 | ||
b65233a9 JR |
318 | /* |
319 | * This function reads the last device id the IOMMU has to handle from the PCI | |
320 | * capability header for this IOMMU | |
321 | */ | |
3e8064ba JR |
322 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
323 | { | |
324 | u32 cap; | |
325 | ||
326 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 327 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
328 | |
329 | return 0; | |
330 | } | |
331 | ||
b65233a9 JR |
332 | /* |
333 | * After reading the highest device id from the IOMMU PCI capability header | |
334 | * this function looks if there is a higher device id defined in the ACPI table | |
335 | */ | |
3e8064ba JR |
336 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
337 | { | |
338 | u8 *p = (void *)h, *end = (void *)h; | |
339 | struct ivhd_entry *dev; | |
340 | ||
341 | p += sizeof(*h); | |
342 | end += h->length; | |
343 | ||
344 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
345 | PCI_SLOT(h->devid), | |
346 | PCI_FUNC(h->devid), | |
347 | h->cap_ptr); | |
348 | ||
349 | while (p < end) { | |
350 | dev = (struct ivhd_entry *)p; | |
351 | switch (dev->type) { | |
352 | case IVHD_DEV_SELECT: | |
353 | case IVHD_DEV_RANGE_END: | |
354 | case IVHD_DEV_ALIAS: | |
355 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 356 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 357 | update_last_devid(dev->devid); |
3e8064ba JR |
358 | break; |
359 | default: | |
360 | break; | |
361 | } | |
b514e555 | 362 | p += ivhd_entry_length(p); |
3e8064ba JR |
363 | } |
364 | ||
365 | WARN_ON(p != end); | |
366 | ||
367 | return 0; | |
368 | } | |
369 | ||
b65233a9 JR |
370 | /* |
371 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
372 | * id which we need to handle. This is the first of three functions which parse | |
373 | * the ACPI table. So we check the checksum here. | |
374 | */ | |
3e8064ba JR |
375 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
376 | { | |
377 | int i; | |
378 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
379 | struct ivhd_header *h; | |
380 | ||
381 | /* | |
382 | * Validate checksum here so we don't need to do it when | |
383 | * we actually parse the table | |
384 | */ | |
385 | for (i = 0; i < table->length; ++i) | |
386 | checksum += p[i]; | |
387 | if (checksum != 0) | |
388 | /* ACPI table corrupt */ | |
389 | return -ENODEV; | |
390 | ||
391 | p += IVRS_HEADER_LENGTH; | |
392 | ||
393 | end += table->length; | |
394 | while (p < end) { | |
395 | h = (struct ivhd_header *)p; | |
396 | switch (h->type) { | |
397 | case ACPI_IVHD_TYPE: | |
398 | find_last_devid_from_ivhd(h); | |
399 | break; | |
400 | default: | |
401 | break; | |
402 | } | |
403 | p += h->length; | |
404 | } | |
405 | WARN_ON(p != end); | |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
b65233a9 JR |
410 | /**************************************************************************** |
411 | * | |
412 | * The following functions belong the the code path which parses the ACPI table | |
413 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
414 | * data structures, initialize the device/alias/rlookup table and also | |
415 | * basically initialize the hardware. | |
416 | * | |
417 | ****************************************************************************/ | |
418 | ||
419 | /* | |
420 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
421 | * write commands to that buffer later and the IOMMU will execute them | |
422 | * asynchronously | |
423 | */ | |
b36ca91e JR |
424 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
425 | { | |
d0312b21 | 426 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 427 | get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
428 | |
429 | if (cmd_buf == NULL) | |
430 | return NULL; | |
431 | ||
432 | iommu->cmd_buf_size = CMD_BUFFER_SIZE; | |
433 | ||
58492e12 JR |
434 | return cmd_buf; |
435 | } | |
436 | ||
93f1cc67 JR |
437 | /* |
438 | * This function resets the command buffer if the IOMMU stopped fetching | |
439 | * commands from it. | |
440 | */ | |
441 | void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) | |
442 | { | |
443 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
444 | ||
445 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
446 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
447 | ||
448 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
449 | } | |
450 | ||
58492e12 JR |
451 | /* |
452 | * This function writes the command buffer address to the hardware and | |
453 | * enables it. | |
454 | */ | |
455 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | |
456 | { | |
457 | u64 entry; | |
458 | ||
459 | BUG_ON(iommu->cmd_buf == NULL); | |
460 | ||
461 | entry = (u64)virt_to_phys(iommu->cmd_buf); | |
b36ca91e | 462 | entry |= MMIO_CMD_SIZE_512; |
58492e12 | 463 | |
b36ca91e | 464 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, |
58492e12 | 465 | &entry, sizeof(entry)); |
b36ca91e | 466 | |
93f1cc67 | 467 | amd_iommu_reset_cmd_buffer(iommu); |
b36ca91e JR |
468 | } |
469 | ||
470 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
471 | { | |
23c1713f JR |
472 | free_pages((unsigned long)iommu->cmd_buf, |
473 | get_order(iommu->cmd_buf_size)); | |
b36ca91e JR |
474 | } |
475 | ||
335503e5 JR |
476 | /* allocates the memory where the IOMMU will log its events to */ |
477 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
478 | { | |
335503e5 JR |
479 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
480 | get_order(EVT_BUFFER_SIZE)); | |
481 | ||
482 | if (iommu->evt_buf == NULL) | |
483 | return NULL; | |
484 | ||
1bc6f838 JR |
485 | iommu->evt_buf_size = EVT_BUFFER_SIZE; |
486 | ||
58492e12 JR |
487 | return iommu->evt_buf; |
488 | } | |
489 | ||
490 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | |
491 | { | |
492 | u64 entry; | |
493 | ||
494 | BUG_ON(iommu->evt_buf == NULL); | |
495 | ||
335503e5 | 496 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; |
58492e12 | 497 | |
335503e5 JR |
498 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, |
499 | &entry, sizeof(entry)); | |
500 | ||
09067207 JR |
501 | /* set head and tail to zero manually */ |
502 | writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
503 | writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
504 | ||
58492e12 | 505 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); |
335503e5 JR |
506 | } |
507 | ||
508 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
509 | { | |
510 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
511 | } | |
512 | ||
b65233a9 | 513 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
514 | static void set_dev_entry_bit(u16 devid, u8 bit) |
515 | { | |
516 | int i = (bit >> 5) & 0x07; | |
517 | int _bit = bit & 0x1f; | |
518 | ||
519 | amd_iommu_dev_table[devid].data[i] |= (1 << _bit); | |
520 | } | |
521 | ||
5ff4789d JR |
522 | /* Writes the specific IOMMU for a device into the rlookup table */ |
523 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
524 | { | |
525 | amd_iommu_rlookup_table[devid] = iommu; | |
526 | } | |
527 | ||
b65233a9 JR |
528 | /* |
529 | * This function takes the device specific flags read from the ACPI | |
530 | * table and sets up the device table entry with that information | |
531 | */ | |
5ff4789d JR |
532 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
533 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
534 | { |
535 | if (flags & ACPI_DEVFLAG_INITPASS) | |
536 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
537 | if (flags & ACPI_DEVFLAG_EXTINT) | |
538 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
539 | if (flags & ACPI_DEVFLAG_NMI) | |
540 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
541 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
542 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
543 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
544 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
545 | if (flags & ACPI_DEVFLAG_LINT0) | |
546 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
547 | if (flags & ACPI_DEVFLAG_LINT1) | |
548 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 549 | |
5ff4789d | 550 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
551 | } |
552 | ||
b65233a9 JR |
553 | /* |
554 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
555 | * it | |
556 | */ | |
3566b778 JR |
557 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
558 | { | |
559 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
560 | ||
561 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
562 | return; | |
563 | ||
564 | if (iommu) { | |
b65233a9 JR |
565 | /* |
566 | * We only can configure exclusion ranges per IOMMU, not | |
567 | * per device. But we can enable the exclusion range per | |
568 | * device. This is done here | |
569 | */ | |
3566b778 JR |
570 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
571 | iommu->exclusion_start = m->range_start; | |
572 | iommu->exclusion_length = m->range_length; | |
573 | } | |
574 | } | |
575 | ||
b65233a9 JR |
576 | /* |
577 | * This function reads some important data from the IOMMU PCI space and | |
578 | * initializes the driver data structure with it. It reads the hardware | |
579 | * capabilities and the first/last device entries | |
580 | */ | |
5d0c8e49 JR |
581 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
582 | { | |
5d0c8e49 | 583 | int cap_ptr = iommu->cap_ptr; |
a80dc3e0 | 584 | u32 range, misc; |
5d0c8e49 | 585 | |
3eaf28a1 JR |
586 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
587 | &iommu->cap); | |
588 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
589 | &range); | |
a80dc3e0 JR |
590 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
591 | &misc); | |
5d0c8e49 | 592 | |
d591b0a3 JR |
593 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
594 | MMIO_GET_FD(range)); | |
595 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
596 | MMIO_GET_LD(range)); | |
a80dc3e0 | 597 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
5d0c8e49 JR |
598 | } |
599 | ||
b65233a9 JR |
600 | /* |
601 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
602 | * initializes the hardware and our data structures with it. | |
603 | */ | |
5d0c8e49 JR |
604 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
605 | struct ivhd_header *h) | |
606 | { | |
607 | u8 *p = (u8 *)h; | |
608 | u8 *end = p, flags = 0; | |
609 | u16 dev_i, devid = 0, devid_start = 0, devid_to = 0; | |
610 | u32 ext_flags = 0; | |
58a3bee5 | 611 | bool alias = false; |
5d0c8e49 JR |
612 | struct ivhd_entry *e; |
613 | ||
614 | /* | |
615 | * First set the recommended feature enable bits from ACPI | |
616 | * into the IOMMU control registers | |
617 | */ | |
6da7342f | 618 | h->flags & IVHD_FLAG_HT_TUN_EN_MASK ? |
5d0c8e49 JR |
619 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : |
620 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
621 | ||
6da7342f | 622 | h->flags & IVHD_FLAG_PASSPW_EN_MASK ? |
5d0c8e49 JR |
623 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : |
624 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
625 | ||
6da7342f | 626 | h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ? |
5d0c8e49 JR |
627 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : |
628 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
629 | ||
6da7342f | 630 | h->flags & IVHD_FLAG_ISOC_EN_MASK ? |
5d0c8e49 JR |
631 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : |
632 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
633 | ||
634 | /* | |
635 | * make IOMMU memory accesses cache coherent | |
636 | */ | |
637 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
638 | ||
639 | /* | |
640 | * Done. Now parse the device entries | |
641 | */ | |
642 | p += sizeof(struct ivhd_header); | |
643 | end += h->length; | |
644 | ||
42a698f4 | 645 | |
5d0c8e49 JR |
646 | while (p < end) { |
647 | e = (struct ivhd_entry *)p; | |
648 | switch (e->type) { | |
649 | case IVHD_DEV_ALL: | |
42a698f4 JR |
650 | |
651 | DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x" | |
652 | " last device %02x:%02x.%x flags: %02x\n", | |
653 | PCI_BUS(iommu->first_device), | |
654 | PCI_SLOT(iommu->first_device), | |
655 | PCI_FUNC(iommu->first_device), | |
656 | PCI_BUS(iommu->last_device), | |
657 | PCI_SLOT(iommu->last_device), | |
658 | PCI_FUNC(iommu->last_device), | |
659 | e->flags); | |
660 | ||
5d0c8e49 JR |
661 | for (dev_i = iommu->first_device; |
662 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
663 | set_dev_entry_from_acpi(iommu, dev_i, |
664 | e->flags, 0); | |
5d0c8e49 JR |
665 | break; |
666 | case IVHD_DEV_SELECT: | |
42a698f4 JR |
667 | |
668 | DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " | |
669 | "flags: %02x\n", | |
670 | PCI_BUS(e->devid), | |
671 | PCI_SLOT(e->devid), | |
672 | PCI_FUNC(e->devid), | |
673 | e->flags); | |
674 | ||
5d0c8e49 | 675 | devid = e->devid; |
5ff4789d | 676 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
677 | break; |
678 | case IVHD_DEV_SELECT_RANGE_START: | |
42a698f4 JR |
679 | |
680 | DUMP_printk(" DEV_SELECT_RANGE_START\t " | |
681 | "devid: %02x:%02x.%x flags: %02x\n", | |
682 | PCI_BUS(e->devid), | |
683 | PCI_SLOT(e->devid), | |
684 | PCI_FUNC(e->devid), | |
685 | e->flags); | |
686 | ||
5d0c8e49 JR |
687 | devid_start = e->devid; |
688 | flags = e->flags; | |
689 | ext_flags = 0; | |
58a3bee5 | 690 | alias = false; |
5d0c8e49 JR |
691 | break; |
692 | case IVHD_DEV_ALIAS: | |
42a698f4 JR |
693 | |
694 | DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " | |
695 | "flags: %02x devid_to: %02x:%02x.%x\n", | |
696 | PCI_BUS(e->devid), | |
697 | PCI_SLOT(e->devid), | |
698 | PCI_FUNC(e->devid), | |
699 | e->flags, | |
700 | PCI_BUS(e->ext >> 8), | |
701 | PCI_SLOT(e->ext >> 8), | |
702 | PCI_FUNC(e->ext >> 8)); | |
703 | ||
5d0c8e49 JR |
704 | devid = e->devid; |
705 | devid_to = e->ext >> 8; | |
7a6a3a08 | 706 | set_dev_entry_from_acpi(iommu, devid , e->flags, 0); |
7455aab1 | 707 | set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); |
5d0c8e49 JR |
708 | amd_iommu_alias_table[devid] = devid_to; |
709 | break; | |
710 | case IVHD_DEV_ALIAS_RANGE: | |
42a698f4 JR |
711 | |
712 | DUMP_printk(" DEV_ALIAS_RANGE\t\t " | |
713 | "devid: %02x:%02x.%x flags: %02x " | |
714 | "devid_to: %02x:%02x.%x\n", | |
715 | PCI_BUS(e->devid), | |
716 | PCI_SLOT(e->devid), | |
717 | PCI_FUNC(e->devid), | |
718 | e->flags, | |
719 | PCI_BUS(e->ext >> 8), | |
720 | PCI_SLOT(e->ext >> 8), | |
721 | PCI_FUNC(e->ext >> 8)); | |
722 | ||
5d0c8e49 JR |
723 | devid_start = e->devid; |
724 | flags = e->flags; | |
725 | devid_to = e->ext >> 8; | |
726 | ext_flags = 0; | |
58a3bee5 | 727 | alias = true; |
5d0c8e49 JR |
728 | break; |
729 | case IVHD_DEV_EXT_SELECT: | |
42a698f4 JR |
730 | |
731 | DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " | |
732 | "flags: %02x ext: %08x\n", | |
733 | PCI_BUS(e->devid), | |
734 | PCI_SLOT(e->devid), | |
735 | PCI_FUNC(e->devid), | |
736 | e->flags, e->ext); | |
737 | ||
5d0c8e49 | 738 | devid = e->devid; |
5ff4789d JR |
739 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
740 | e->ext); | |
5d0c8e49 JR |
741 | break; |
742 | case IVHD_DEV_EXT_SELECT_RANGE: | |
42a698f4 JR |
743 | |
744 | DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " | |
745 | "%02x:%02x.%x flags: %02x ext: %08x\n", | |
746 | PCI_BUS(e->devid), | |
747 | PCI_SLOT(e->devid), | |
748 | PCI_FUNC(e->devid), | |
749 | e->flags, e->ext); | |
750 | ||
5d0c8e49 JR |
751 | devid_start = e->devid; |
752 | flags = e->flags; | |
753 | ext_flags = e->ext; | |
58a3bee5 | 754 | alias = false; |
5d0c8e49 JR |
755 | break; |
756 | case IVHD_DEV_RANGE_END: | |
42a698f4 JR |
757 | |
758 | DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", | |
759 | PCI_BUS(e->devid), | |
760 | PCI_SLOT(e->devid), | |
761 | PCI_FUNC(e->devid)); | |
762 | ||
5d0c8e49 JR |
763 | devid = e->devid; |
764 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
7a6a3a08 | 765 | if (alias) { |
5d0c8e49 | 766 | amd_iommu_alias_table[dev_i] = devid_to; |
7a6a3a08 JR |
767 | set_dev_entry_from_acpi(iommu, |
768 | devid_to, flags, ext_flags); | |
769 | } | |
770 | set_dev_entry_from_acpi(iommu, dev_i, | |
771 | flags, ext_flags); | |
5d0c8e49 JR |
772 | } |
773 | break; | |
774 | default: | |
775 | break; | |
776 | } | |
777 | ||
b514e555 | 778 | p += ivhd_entry_length(p); |
5d0c8e49 JR |
779 | } |
780 | } | |
781 | ||
b65233a9 | 782 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
783 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
784 | { | |
785 | u16 i; | |
786 | ||
787 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
788 | set_iommu_for_device(iommu, i); | |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
e47d402d JR |
793 | static void __init free_iommu_one(struct amd_iommu *iommu) |
794 | { | |
795 | free_command_buffer(iommu); | |
335503e5 | 796 | free_event_buffer(iommu); |
e47d402d JR |
797 | iommu_unmap_mmio_space(iommu); |
798 | } | |
799 | ||
800 | static void __init free_iommu_all(void) | |
801 | { | |
802 | struct amd_iommu *iommu, *next; | |
803 | ||
3bd22172 | 804 | for_each_iommu_safe(iommu, next) { |
e47d402d JR |
805 | list_del(&iommu->list); |
806 | free_iommu_one(iommu); | |
807 | kfree(iommu); | |
808 | } | |
809 | } | |
810 | ||
b65233a9 JR |
811 | /* |
812 | * This function clues the initialization function for one IOMMU | |
813 | * together and also allocates the command buffer and programs the | |
814 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
815 | */ | |
e47d402d JR |
816 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
817 | { | |
818 | spin_lock_init(&iommu->lock); | |
819 | list_add_tail(&iommu->list, &amd_iommu_list); | |
820 | ||
821 | /* | |
822 | * Copy data from ACPI table entry to the iommu struct | |
823 | */ | |
3eaf28a1 JR |
824 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
825 | if (!iommu->dev) | |
826 | return 1; | |
827 | ||
e47d402d | 828 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 829 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
830 | iommu->mmio_phys = h->mmio_phys; |
831 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
832 | if (!iommu->mmio_base) | |
833 | return -ENOMEM; | |
834 | ||
e47d402d JR |
835 | iommu->cmd_buf = alloc_command_buffer(iommu); |
836 | if (!iommu->cmd_buf) | |
837 | return -ENOMEM; | |
838 | ||
335503e5 JR |
839 | iommu->evt_buf = alloc_event_buffer(iommu); |
840 | if (!iommu->evt_buf) | |
841 | return -ENOMEM; | |
842 | ||
a80dc3e0 JR |
843 | iommu->int_enabled = false; |
844 | ||
e47d402d JR |
845 | init_iommu_from_pci(iommu); |
846 | init_iommu_from_acpi(iommu, h); | |
847 | init_iommu_devices(iommu); | |
848 | ||
8a66712b | 849 | return pci_enable_device(iommu->dev); |
e47d402d JR |
850 | } |
851 | ||
b65233a9 JR |
852 | /* |
853 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
854 | * IOMMU structure and initializes it with init_iommu_one() | |
855 | */ | |
e47d402d JR |
856 | static int __init init_iommu_all(struct acpi_table_header *table) |
857 | { | |
858 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
859 | struct ivhd_header *h; | |
860 | struct amd_iommu *iommu; | |
861 | int ret; | |
862 | ||
e47d402d JR |
863 | end += table->length; |
864 | p += IVRS_HEADER_LENGTH; | |
865 | ||
866 | while (p < end) { | |
867 | h = (struct ivhd_header *)p; | |
868 | switch (*p) { | |
869 | case ACPI_IVHD_TYPE: | |
9c72041f | 870 | |
ae908c22 | 871 | DUMP_printk("device: %02x:%02x.%01x cap: %04x " |
9c72041f JR |
872 | "seg: %d flags: %01x info %04x\n", |
873 | PCI_BUS(h->devid), PCI_SLOT(h->devid), | |
874 | PCI_FUNC(h->devid), h->cap_ptr, | |
875 | h->pci_seg, h->flags, h->info); | |
876 | DUMP_printk(" mmio-addr: %016llx\n", | |
877 | h->mmio_phys); | |
878 | ||
e47d402d JR |
879 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); |
880 | if (iommu == NULL) | |
881 | return -ENOMEM; | |
882 | ret = init_iommu_one(iommu, h); | |
883 | if (ret) | |
884 | return ret; | |
885 | break; | |
886 | default: | |
887 | break; | |
888 | } | |
889 | p += h->length; | |
890 | ||
891 | } | |
892 | WARN_ON(p != end); | |
893 | ||
894 | return 0; | |
895 | } | |
896 | ||
a80dc3e0 JR |
897 | /**************************************************************************** |
898 | * | |
899 | * The following functions initialize the MSI interrupts for all IOMMUs | |
900 | * in the system. Its a bit challenging because there could be multiple | |
901 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
902 | * pci_dev. | |
903 | * | |
904 | ****************************************************************************/ | |
905 | ||
a80dc3e0 JR |
906 | static int __init iommu_setup_msi(struct amd_iommu *iommu) |
907 | { | |
908 | int r; | |
a80dc3e0 JR |
909 | |
910 | if (pci_enable_msi(iommu->dev)) | |
911 | return 1; | |
912 | ||
913 | r = request_irq(iommu->dev->irq, amd_iommu_int_handler, | |
914 | IRQF_SAMPLE_RANDOM, | |
4c6f40d4 | 915 | "AMD-Vi", |
a80dc3e0 JR |
916 | NULL); |
917 | ||
918 | if (r) { | |
919 | pci_disable_msi(iommu->dev); | |
920 | return 1; | |
921 | } | |
922 | ||
fab6afa3 | 923 | iommu->int_enabled = true; |
58492e12 JR |
924 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); |
925 | ||
a80dc3e0 JR |
926 | return 0; |
927 | } | |
928 | ||
05f92db9 | 929 | static int iommu_init_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
930 | { |
931 | if (iommu->int_enabled) | |
932 | return 0; | |
933 | ||
d91cecdd | 934 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) |
a80dc3e0 JR |
935 | return iommu_setup_msi(iommu); |
936 | ||
937 | return 1; | |
938 | } | |
939 | ||
b65233a9 JR |
940 | /**************************************************************************** |
941 | * | |
942 | * The next functions belong to the third pass of parsing the ACPI | |
943 | * table. In this last pass the memory mapping requirements are | |
944 | * gathered (like exclusion and unity mapping reanges). | |
945 | * | |
946 | ****************************************************************************/ | |
947 | ||
be2a022c JR |
948 | static void __init free_unity_maps(void) |
949 | { | |
950 | struct unity_map_entry *entry, *next; | |
951 | ||
952 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
953 | list_del(&entry->list); | |
954 | kfree(entry); | |
955 | } | |
956 | } | |
957 | ||
b65233a9 | 958 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
959 | static int __init init_exclusion_range(struct ivmd_header *m) |
960 | { | |
961 | int i; | |
962 | ||
963 | switch (m->type) { | |
964 | case ACPI_IVMD_TYPE: | |
965 | set_device_exclusion_range(m->devid, m); | |
966 | break; | |
967 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 968 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
969 | set_device_exclusion_range(i, m); |
970 | break; | |
971 | case ACPI_IVMD_TYPE_RANGE: | |
972 | for (i = m->devid; i <= m->aux; ++i) | |
973 | set_device_exclusion_range(i, m); | |
974 | break; | |
975 | default: | |
976 | break; | |
977 | } | |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
b65233a9 | 982 | /* called for unity map ACPI definition */ |
be2a022c JR |
983 | static int __init init_unity_map_range(struct ivmd_header *m) |
984 | { | |
985 | struct unity_map_entry *e = 0; | |
02acc43a | 986 | char *s; |
be2a022c JR |
987 | |
988 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
989 | if (e == NULL) | |
990 | return -ENOMEM; | |
991 | ||
992 | switch (m->type) { | |
993 | default: | |
0bc252f4 JR |
994 | kfree(e); |
995 | return 0; | |
be2a022c | 996 | case ACPI_IVMD_TYPE: |
02acc43a | 997 | s = "IVMD_TYPEi\t\t\t"; |
be2a022c JR |
998 | e->devid_start = e->devid_end = m->devid; |
999 | break; | |
1000 | case ACPI_IVMD_TYPE_ALL: | |
02acc43a | 1001 | s = "IVMD_TYPE_ALL\t\t"; |
be2a022c JR |
1002 | e->devid_start = 0; |
1003 | e->devid_end = amd_iommu_last_bdf; | |
1004 | break; | |
1005 | case ACPI_IVMD_TYPE_RANGE: | |
02acc43a | 1006 | s = "IVMD_TYPE_RANGE\t\t"; |
be2a022c JR |
1007 | e->devid_start = m->devid; |
1008 | e->devid_end = m->aux; | |
1009 | break; | |
1010 | } | |
1011 | e->address_start = PAGE_ALIGN(m->range_start); | |
1012 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
1013 | e->prot = m->flags >> 1; | |
1014 | ||
02acc43a JR |
1015 | DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" |
1016 | " range_start: %016llx range_end: %016llx flags: %x\n", s, | |
1017 | PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start), | |
1018 | PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end), | |
1019 | PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), | |
1020 | e->address_start, e->address_end, m->flags); | |
1021 | ||
be2a022c JR |
1022 | list_add_tail(&e->list, &amd_iommu_unity_map); |
1023 | ||
1024 | return 0; | |
1025 | } | |
1026 | ||
b65233a9 | 1027 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
1028 | static int __init init_memory_definitions(struct acpi_table_header *table) |
1029 | { | |
1030 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1031 | struct ivmd_header *m; | |
1032 | ||
be2a022c JR |
1033 | end += table->length; |
1034 | p += IVRS_HEADER_LENGTH; | |
1035 | ||
1036 | while (p < end) { | |
1037 | m = (struct ivmd_header *)p; | |
1038 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
1039 | init_exclusion_range(m); | |
1040 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
1041 | init_unity_map_range(m); | |
1042 | ||
1043 | p += m->length; | |
1044 | } | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
9f5f5fb3 JR |
1049 | /* |
1050 | * Init the device table to not allow DMA access for devices and | |
1051 | * suppress all page faults | |
1052 | */ | |
1053 | static void init_device_table(void) | |
1054 | { | |
1055 | u16 devid; | |
1056 | ||
1057 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
1058 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
1059 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
1060 | } |
1061 | } | |
1062 | ||
b65233a9 JR |
1063 | /* |
1064 | * This function finally enables all IOMMUs found in the system after | |
1065 | * they have been initialized | |
1066 | */ | |
05f92db9 | 1067 | static void enable_iommus(void) |
8736197b JR |
1068 | { |
1069 | struct amd_iommu *iommu; | |
1070 | ||
3bd22172 | 1071 | for_each_iommu(iommu) { |
a8c485bb | 1072 | iommu_disable(iommu); |
58492e12 JR |
1073 | iommu_set_device_table(iommu); |
1074 | iommu_enable_command_buffer(iommu); | |
1075 | iommu_enable_event_buffer(iommu); | |
8736197b | 1076 | iommu_set_exclusion_range(iommu); |
a80dc3e0 | 1077 | iommu_init_msi(iommu); |
8736197b JR |
1078 | iommu_enable(iommu); |
1079 | } | |
1080 | } | |
1081 | ||
92ac4320 JR |
1082 | static void disable_iommus(void) |
1083 | { | |
1084 | struct amd_iommu *iommu; | |
1085 | ||
1086 | for_each_iommu(iommu) | |
1087 | iommu_disable(iommu); | |
1088 | } | |
1089 | ||
7441e9cb JR |
1090 | /* |
1091 | * Suspend/Resume support | |
1092 | * disable suspend until real resume implemented | |
1093 | */ | |
1094 | ||
1095 | static int amd_iommu_resume(struct sys_device *dev) | |
1096 | { | |
736501ee JR |
1097 | /* re-load the hardware */ |
1098 | enable_iommus(); | |
1099 | ||
1100 | /* | |
1101 | * we have to flush after the IOMMUs are enabled because a | |
1102 | * disabled IOMMU will never execute the commands we send | |
1103 | */ | |
736501ee | 1104 | amd_iommu_flush_all_devices(); |
6a047d8b | 1105 | amd_iommu_flush_all_domains(); |
736501ee | 1106 | |
7441e9cb JR |
1107 | return 0; |
1108 | } | |
1109 | ||
1110 | static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) | |
1111 | { | |
736501ee JR |
1112 | /* disable IOMMUs to go out of the way for BIOS */ |
1113 | disable_iommus(); | |
1114 | ||
1115 | return 0; | |
7441e9cb JR |
1116 | } |
1117 | ||
1118 | static struct sysdev_class amd_iommu_sysdev_class = { | |
1119 | .name = "amd_iommu", | |
1120 | .suspend = amd_iommu_suspend, | |
1121 | .resume = amd_iommu_resume, | |
1122 | }; | |
1123 | ||
1124 | static struct sys_device device_amd_iommu = { | |
1125 | .id = 0, | |
1126 | .cls = &amd_iommu_sysdev_class, | |
1127 | }; | |
1128 | ||
b65233a9 JR |
1129 | /* |
1130 | * This is the core init function for AMD IOMMU hardware in the system. | |
1131 | * This function is called from the generic x86 DMA layer initialization | |
1132 | * code. | |
1133 | * | |
1134 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1135 | * three times: | |
1136 | * | |
1137 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1138 | * Upon this information the size of the data structures is | |
1139 | * determined that needs to be allocated. | |
1140 | * | |
1141 | * 2 pass) Initialize the data structures just allocated with the | |
1142 | * information in the ACPI table about available AMD IOMMUs | |
1143 | * in the system. It also maps the PCI devices in the | |
1144 | * system to specific IOMMUs | |
1145 | * | |
1146 | * 3 pass) After the basic data structures are allocated and | |
1147 | * initialized we update them with information about memory | |
1148 | * remapping requirements parsed out of the ACPI table in | |
1149 | * this last pass. | |
1150 | * | |
1151 | * After that the hardware is initialized and ready to go. In the last | |
1152 | * step we do some Linux specific things like registering the driver in | |
1153 | * the dma_ops interface and initializing the suspend/resume support | |
1154 | * functions. Finally it prints some information about AMD IOMMUs and | |
1155 | * the driver state and enables the hardware. | |
1156 | */ | |
fe74c9cf JR |
1157 | int __init amd_iommu_init(void) |
1158 | { | |
1159 | int i, ret = 0; | |
1160 | ||
1161 | ||
8b14518f | 1162 | if (no_iommu) { |
4c6f40d4 | 1163 | printk(KERN_INFO "AMD-Vi disabled by kernel command line\n"); |
fe74c9cf JR |
1164 | return 0; |
1165 | } | |
1166 | ||
c1cbebee JR |
1167 | if (!amd_iommu_detected) |
1168 | return -ENODEV; | |
1169 | ||
fe74c9cf JR |
1170 | /* |
1171 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1172 | * we need to handle. Upon this information the shared data | |
1173 | * structures for the IOMMUs in the system will be allocated | |
1174 | */ | |
1175 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1176 | return -ENODEV; | |
1177 | ||
c571484e JR |
1178 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1179 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1180 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
1181 | |
1182 | ret = -ENOMEM; | |
1183 | ||
1184 | /* Device table - directly used by all IOMMUs */ | |
5dc8bff0 | 1185 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1186 | get_order(dev_table_size)); |
1187 | if (amd_iommu_dev_table == NULL) | |
1188 | goto out; | |
1189 | ||
1190 | /* | |
1191 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1192 | * IOMMU see for that device | |
1193 | */ | |
1194 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1195 | get_order(alias_table_size)); | |
1196 | if (amd_iommu_alias_table == NULL) | |
1197 | goto free; | |
1198 | ||
1199 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1200 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1201 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1202 | get_order(rlookup_table_size)); |
1203 | if (amd_iommu_rlookup_table == NULL) | |
1204 | goto free; | |
1205 | ||
1206 | /* | |
1207 | * Protection Domain table - maps devices to protection domains | |
1208 | * This table has the same size as the rlookup_table | |
1209 | */ | |
5dc8bff0 | 1210 | amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1211 | get_order(rlookup_table_size)); |
1212 | if (amd_iommu_pd_table == NULL) | |
1213 | goto free; | |
1214 | ||
5dc8bff0 JR |
1215 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1216 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1217 | get_order(MAX_DOMAIN_ID/8)); |
1218 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1219 | goto free; | |
1220 | ||
9f5f5fb3 JR |
1221 | /* init the device table */ |
1222 | init_device_table(); | |
1223 | ||
fe74c9cf | 1224 | /* |
5dc8bff0 | 1225 | * let all alias entries point to itself |
fe74c9cf | 1226 | */ |
3a61ec38 | 1227 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1228 | amd_iommu_alias_table[i] = i; |
1229 | ||
fe74c9cf JR |
1230 | /* |
1231 | * never allocate domain 0 because its used as the non-allocated and | |
1232 | * error value placeholder | |
1233 | */ | |
1234 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1235 | ||
1236 | /* | |
1237 | * now the data structures are allocated and basically initialized | |
1238 | * start the real acpi table scan | |
1239 | */ | |
1240 | ret = -ENODEV; | |
1241 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1242 | goto free; | |
1243 | ||
1244 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) | |
1245 | goto free; | |
1246 | ||
129d6aba | 1247 | ret = sysdev_class_register(&amd_iommu_sysdev_class); |
8736197b JR |
1248 | if (ret) |
1249 | goto free; | |
1250 | ||
129d6aba | 1251 | ret = sysdev_register(&device_amd_iommu); |
7441e9cb JR |
1252 | if (ret) |
1253 | goto free; | |
1254 | ||
4751a951 JR |
1255 | if (iommu_pass_through) |
1256 | ret = amd_iommu_init_passthrough(); | |
1257 | else | |
1258 | ret = amd_iommu_init_dma_ops(); | |
7441e9cb JR |
1259 | if (ret) |
1260 | goto free; | |
1261 | ||
8736197b JR |
1262 | enable_iommus(); |
1263 | ||
4751a951 JR |
1264 | if (iommu_pass_through) |
1265 | goto out; | |
1266 | ||
4c6f40d4 | 1267 | printk(KERN_INFO "AMD-Vi: device isolation "); |
fe74c9cf JR |
1268 | if (amd_iommu_isolate) |
1269 | printk("enabled\n"); | |
1270 | else | |
1271 | printk("disabled\n"); | |
1272 | ||
afa9fdc2 | 1273 | if (amd_iommu_unmap_flush) |
4c6f40d4 | 1274 | printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n"); |
1c655773 | 1275 | else |
4c6f40d4 | 1276 | printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n"); |
1c655773 | 1277 | |
fe74c9cf JR |
1278 | out: |
1279 | return ret; | |
1280 | ||
1281 | free: | |
d58befd3 JR |
1282 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, |
1283 | get_order(MAX_DOMAIN_ID/8)); | |
fe74c9cf | 1284 | |
9a836de0 JR |
1285 | free_pages((unsigned long)amd_iommu_pd_table, |
1286 | get_order(rlookup_table_size)); | |
fe74c9cf | 1287 | |
9a836de0 JR |
1288 | free_pages((unsigned long)amd_iommu_rlookup_table, |
1289 | get_order(rlookup_table_size)); | |
fe74c9cf | 1290 | |
9a836de0 JR |
1291 | free_pages((unsigned long)amd_iommu_alias_table, |
1292 | get_order(alias_table_size)); | |
fe74c9cf | 1293 | |
9a836de0 JR |
1294 | free_pages((unsigned long)amd_iommu_dev_table, |
1295 | get_order(dev_table_size)); | |
fe74c9cf JR |
1296 | |
1297 | free_iommu_all(); | |
1298 | ||
1299 | free_unity_maps(); | |
1300 | ||
1301 | goto out; | |
1302 | } | |
1303 | ||
09759042 JR |
1304 | void amd_iommu_shutdown(void) |
1305 | { | |
1306 | disable_iommus(); | |
1307 | } | |
1308 | ||
b65233a9 JR |
1309 | /**************************************************************************** |
1310 | * | |
1311 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1312 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1313 | * IOMMUs | |
1314 | * | |
1315 | ****************************************************************************/ | |
ae7877de JR |
1316 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1317 | { | |
1318 | return 0; | |
1319 | } | |
1320 | ||
1321 | void __init amd_iommu_detect(void) | |
1322 | { | |
299a140d | 1323 | if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture)) |
ae7877de JR |
1324 | return; |
1325 | ||
ae7877de JR |
1326 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1327 | iommu_detected = 1; | |
c1cbebee | 1328 | amd_iommu_detected = 1; |
92af4e29 | 1329 | #ifdef CONFIG_GART_IOMMU |
ae7877de JR |
1330 | gart_iommu_aperture_disabled = 1; |
1331 | gart_iommu_aperture = 0; | |
92af4e29 | 1332 | #endif |
ae7877de JR |
1333 | } |
1334 | } | |
1335 | ||
b65233a9 JR |
1336 | /**************************************************************************** |
1337 | * | |
1338 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1339 | * options. | |
1340 | * | |
1341 | ****************************************************************************/ | |
1342 | ||
fefda117 JR |
1343 | static int __init parse_amd_iommu_dump(char *str) |
1344 | { | |
1345 | amd_iommu_dump = true; | |
1346 | ||
1347 | return 1; | |
1348 | } | |
1349 | ||
918ad6c5 JR |
1350 | static int __init parse_amd_iommu_options(char *str) |
1351 | { | |
1352 | for (; *str; ++str) { | |
1c655773 | 1353 | if (strncmp(str, "isolate", 7) == 0) |
c226f853 | 1354 | amd_iommu_isolate = true; |
e5e1f606 | 1355 | if (strncmp(str, "share", 5) == 0) |
c226f853 | 1356 | amd_iommu_isolate = false; |
695b5676 | 1357 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 1358 | amd_iommu_unmap_flush = true; |
918ad6c5 JR |
1359 | } |
1360 | ||
1361 | return 1; | |
1362 | } | |
1363 | ||
fefda117 | 1364 | __setup("amd_iommu_dump", parse_amd_iommu_dump); |
918ad6c5 | 1365 | __setup("amd_iommu=", parse_amd_iommu_options); |