Commit | Line | Data |
---|---|---|
a32073bf AK |
1 | /* |
2 | * Shared support code for AMD K8 northbridges and derivates. | |
3 | * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2. | |
4 | */ | |
c767a54b JP |
5 | |
6 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
7 | ||
a32073bf | 8 | #include <linux/types.h> |
5a0e3ad6 | 9 | #include <linux/slab.h> |
a32073bf AK |
10 | #include <linux/init.h> |
11 | #include <linux/errno.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/spinlock.h> | |
23ac4ae8 | 14 | #include <asm/amd_nb.h> |
a32073bf | 15 | |
a32073bf AK |
16 | static u32 *flush_words; |
17 | ||
691269f0 | 18 | const struct pci_device_id amd_nb_misc_ids[] = { |
cf169702 JR |
19 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) }, |
20 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, | |
cb293250 | 21 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, |
24214449 | 22 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, |
7d64ac64 | 23 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, |
15895a72 | 24 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) }, |
94c1acf2 | 25 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, |
85a8885b | 26 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) }, |
a32073bf AK |
27 | {} |
28 | }; | |
9653a5c7 | 29 | EXPORT_SYMBOL(amd_nb_misc_ids); |
a32073bf | 30 | |
c391c788 | 31 | static const struct pci_device_id amd_nb_link_ids[] = { |
cb6c8520 | 32 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) }, |
7d64ac64 | 33 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) }, |
15895a72 | 34 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) }, |
94c1acf2 | 35 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) }, |
85a8885b | 36 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) }, |
41b2610c HR |
37 | {} |
38 | }; | |
39 | ||
24d9b70b JB |
40 | const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = { |
41 | { 0x00, 0x18, 0x20 }, | |
42 | { 0xff, 0x00, 0x20 }, | |
43 | { 0xfe, 0x00, 0x20 }, | |
44 | { } | |
45 | }; | |
46 | ||
eec1d4fa HR |
47 | struct amd_northbridge_info amd_northbridges; |
48 | EXPORT_SYMBOL(amd_northbridges); | |
a32073bf | 49 | |
9653a5c7 | 50 | static struct pci_dev *next_northbridge(struct pci_dev *dev, |
691269f0 | 51 | const struct pci_device_id *ids) |
a32073bf AK |
52 | { |
53 | do { | |
54 | dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); | |
55 | if (!dev) | |
56 | break; | |
9653a5c7 | 57 | } while (!pci_match_id(ids, dev)); |
a32073bf AK |
58 | return dev; |
59 | } | |
60 | ||
9653a5c7 | 61 | int amd_cache_northbridges(void) |
a32073bf | 62 | { |
84fd1d35 | 63 | u16 i = 0; |
9653a5c7 | 64 | struct amd_northbridge *nb; |
41b2610c | 65 | struct pci_dev *misc, *link; |
3c6df2a9 | 66 | |
9653a5c7 | 67 | if (amd_nb_num()) |
a32073bf AK |
68 | return 0; |
69 | ||
9653a5c7 HR |
70 | misc = NULL; |
71 | while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL) | |
72 | i++; | |
900f9ac9 | 73 | |
9653a5c7 HR |
74 | if (i == 0) |
75 | return 0; | |
a32073bf | 76 | |
9653a5c7 HR |
77 | nb = kzalloc(i * sizeof(struct amd_northbridge), GFP_KERNEL); |
78 | if (!nb) | |
a32073bf AK |
79 | return -ENOMEM; |
80 | ||
9653a5c7 HR |
81 | amd_northbridges.nb = nb; |
82 | amd_northbridges.num = i; | |
3c6df2a9 | 83 | |
41b2610c | 84 | link = misc = NULL; |
9653a5c7 HR |
85 | for (i = 0; i != amd_nb_num(); i++) { |
86 | node_to_amd_nb(i)->misc = misc = | |
87 | next_northbridge(misc, amd_nb_misc_ids); | |
41b2610c HR |
88 | node_to_amd_nb(i)->link = link = |
89 | next_northbridge(link, amd_nb_link_ids); | |
7d64ac64 | 90 | } |
9653a5c7 | 91 | |
1b457429 | 92 | if (amd_gart_present()) |
9653a5c7 | 93 | amd_northbridges.flags |= AMD_NB_GART; |
a32073bf | 94 | |
7d64ac64 AG |
95 | /* |
96 | * Check for L3 cache presence. | |
97 | */ | |
98 | if (!cpuid_edx(0x80000006)) | |
99 | return 0; | |
100 | ||
f658bcfb HR |
101 | /* |
102 | * Some CPU families support L3 Cache Index Disable. There are some | |
103 | * limitations because of E382 and E388 on family 0x10. | |
104 | */ | |
105 | if (boot_cpu_data.x86 == 0x10 && | |
106 | boot_cpu_data.x86_model >= 0x8 && | |
107 | (boot_cpu_data.x86_model > 0x9 || | |
108 | boot_cpu_data.x86_mask >= 0x1)) | |
109 | amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; | |
110 | ||
b453de02 HR |
111 | if (boot_cpu_data.x86 == 0x15) |
112 | amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; | |
113 | ||
cabb5bd7 HR |
114 | /* L3 cache partitioning is supported on family 0x15 */ |
115 | if (boot_cpu_data.x86 == 0x15) | |
116 | amd_northbridges.flags |= AMD_NB_L3_PARTITIONING; | |
117 | ||
a32073bf AK |
118 | return 0; |
119 | } | |
9653a5c7 | 120 | EXPORT_SYMBOL_GPL(amd_cache_northbridges); |
a32073bf | 121 | |
84fd1d35 BP |
122 | /* |
123 | * Ignores subdevice/subvendor but as far as I can figure out | |
124 | * they're useless anyways | |
125 | */ | |
126 | bool __init early_is_amd_nb(u32 device) | |
a32073bf | 127 | { |
691269f0 | 128 | const struct pci_device_id *id; |
a32073bf | 129 | u32 vendor = device & 0xffff; |
691269f0 | 130 | |
a32073bf | 131 | device >>= 16; |
9653a5c7 | 132 | for (id = amd_nb_misc_ids; id->vendor; id++) |
a32073bf | 133 | if (vendor == id->vendor && device == id->device) |
84fd1d35 BP |
134 | return true; |
135 | return false; | |
a32073bf AK |
136 | } |
137 | ||
24d25dbf BH |
138 | struct resource *amd_get_mmconfig_range(struct resource *res) |
139 | { | |
140 | u32 address; | |
141 | u64 base, msr; | |
142 | unsigned segn_busn_bits; | |
143 | ||
144 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) | |
145 | return NULL; | |
146 | ||
147 | /* assume all cpus from fam10h have mmconfig */ | |
148 | if (boot_cpu_data.x86 < 0x10) | |
149 | return NULL; | |
150 | ||
151 | address = MSR_FAM10H_MMIO_CONF_BASE; | |
152 | rdmsrl(address, msr); | |
153 | ||
154 | /* mmconfig is not enabled */ | |
155 | if (!(msr & FAM10H_MMIO_CONF_ENABLE)) | |
156 | return NULL; | |
157 | ||
158 | base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); | |
159 | ||
160 | segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & | |
161 | FAM10H_MMIO_CONF_BUSRANGE_MASK; | |
162 | ||
163 | res->flags = IORESOURCE_MEM; | |
164 | res->start = base; | |
165 | res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1; | |
166 | return res; | |
167 | } | |
168 | ||
cabb5bd7 HR |
169 | int amd_get_subcaches(int cpu) |
170 | { | |
171 | struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link; | |
172 | unsigned int mask; | |
cabb5bd7 HR |
173 | |
174 | if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) | |
175 | return 0; | |
176 | ||
177 | pci_read_config_dword(link, 0x1d4, &mask); | |
178 | ||
8196dab4 | 179 | return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf; |
cabb5bd7 HR |
180 | } |
181 | ||
2993ae33 | 182 | int amd_set_subcaches(int cpu, unsigned long mask) |
cabb5bd7 HR |
183 | { |
184 | static unsigned int reset, ban; | |
185 | struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
186 | unsigned int reg; | |
141168c3 | 187 | int cuid; |
cabb5bd7 HR |
188 | |
189 | if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf) | |
190 | return -EINVAL; | |
191 | ||
192 | /* if necessary, collect reset state of L3 partitioning and BAN mode */ | |
193 | if (reset == 0) { | |
194 | pci_read_config_dword(nb->link, 0x1d4, &reset); | |
195 | pci_read_config_dword(nb->misc, 0x1b8, &ban); | |
196 | ban &= 0x180000; | |
197 | } | |
198 | ||
199 | /* deactivate BAN mode if any subcaches are to be disabled */ | |
200 | if (mask != 0xf) { | |
201 | pci_read_config_dword(nb->misc, 0x1b8, ®); | |
202 | pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000); | |
203 | } | |
204 | ||
8196dab4 | 205 | cuid = cpu_data(cpu).cpu_core_id; |
cabb5bd7 HR |
206 | mask <<= 4 * cuid; |
207 | mask |= (0xf ^ (1 << cuid)) << 26; | |
208 | ||
209 | pci_write_config_dword(nb->link, 0x1d4, mask); | |
210 | ||
211 | /* reset BAN mode if L3 partitioning returned to reset state */ | |
212 | pci_read_config_dword(nb->link, 0x1d4, ®); | |
213 | if (reg == reset) { | |
214 | pci_read_config_dword(nb->misc, 0x1b8, ®); | |
215 | reg &= ~0x180000; | |
216 | pci_write_config_dword(nb->misc, 0x1b8, reg | ban); | |
217 | } | |
218 | ||
219 | return 0; | |
220 | } | |
221 | ||
84fd1d35 | 222 | static int amd_cache_gart(void) |
9653a5c7 | 223 | { |
84fd1d35 | 224 | u16 i; |
9653a5c7 HR |
225 | |
226 | if (!amd_nb_has_feature(AMD_NB_GART)) | |
227 | return 0; | |
228 | ||
229 | flush_words = kmalloc(amd_nb_num() * sizeof(u32), GFP_KERNEL); | |
230 | if (!flush_words) { | |
231 | amd_northbridges.flags &= ~AMD_NB_GART; | |
232 | return -ENOMEM; | |
233 | } | |
234 | ||
235 | for (i = 0; i != amd_nb_num(); i++) | |
236 | pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, | |
237 | &flush_words[i]); | |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
eec1d4fa | 242 | void amd_flush_garts(void) |
a32073bf AK |
243 | { |
244 | int flushed, i; | |
245 | unsigned long flags; | |
246 | static DEFINE_SPINLOCK(gart_lock); | |
247 | ||
9653a5c7 | 248 | if (!amd_nb_has_feature(AMD_NB_GART)) |
900f9ac9 AH |
249 | return; |
250 | ||
a32073bf AK |
251 | /* Avoid races between AGP and IOMMU. In theory it's not needed |
252 | but I'm not sure if the hardware won't lose flush requests | |
253 | when another is pending. This whole thing is so expensive anyways | |
254 | that it doesn't matter to serialize more. -AK */ | |
255 | spin_lock_irqsave(&gart_lock, flags); | |
256 | flushed = 0; | |
9653a5c7 HR |
257 | for (i = 0; i < amd_nb_num(); i++) { |
258 | pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c, | |
259 | flush_words[i] | 1); | |
a32073bf AK |
260 | flushed++; |
261 | } | |
9653a5c7 | 262 | for (i = 0; i < amd_nb_num(); i++) { |
a32073bf AK |
263 | u32 w; |
264 | /* Make sure the hardware actually executed the flush*/ | |
265 | for (;;) { | |
9653a5c7 | 266 | pci_read_config_dword(node_to_amd_nb(i)->misc, |
a32073bf AK |
267 | 0x9c, &w); |
268 | if (!(w & 1)) | |
269 | break; | |
270 | cpu_relax(); | |
271 | } | |
272 | } | |
273 | spin_unlock_irqrestore(&gart_lock, flags); | |
274 | if (!flushed) | |
c767a54b | 275 | pr_notice("nothing to flush?\n"); |
a32073bf | 276 | } |
eec1d4fa | 277 | EXPORT_SYMBOL_GPL(amd_flush_garts); |
a32073bf | 278 | |
eec1d4fa | 279 | static __init int init_amd_nbs(void) |
0e152cd7 BP |
280 | { |
281 | int err = 0; | |
282 | ||
9653a5c7 | 283 | err = amd_cache_northbridges(); |
0e152cd7 BP |
284 | |
285 | if (err < 0) | |
c767a54b | 286 | pr_notice("Cannot enumerate AMD northbridges\n"); |
0e152cd7 | 287 | |
9653a5c7 | 288 | if (amd_cache_gart() < 0) |
c767a54b | 289 | pr_notice("Cannot initialize GART flush words, GART support disabled\n"); |
9653a5c7 | 290 | |
0e152cd7 BP |
291 | return err; |
292 | } | |
293 | ||
294 | /* This has to go after the PCI subsystem */ | |
eec1d4fa | 295 | fs_initcall(init_amd_nbs); |