Commit | Line | Data |
---|---|---|
bb24c471 JP |
1 | /* |
2 | * apb_timer.c: Driver for Langwell APB timers | |
3 | * | |
4 | * (C) Copyright 2009 Intel Corporation | |
5 | * Author: Jacob Pan (jacob.jun.pan@intel.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | * | |
12 | * Note: | |
13 | * Langwell is the south complex of Intel Moorestown MID platform. There are | |
14 | * eight external timers in total that can be used by the operating system. | |
15 | * The timer information, such as frequency and addresses, is provided to the | |
16 | * OS via SFI tables. | |
17 | * Timer interrupts are routed via FW/HW emulated IOAPIC independently via | |
18 | * individual redirection table entries (RTE). | |
19 | * Unlike HPET, there is no master counter, therefore one of the timers are | |
20 | * used as clocksource. The overall allocation looks like: | |
21 | * - timer 0 - NR_CPUs for per cpu timer | |
22 | * - one timer for clocksource | |
23 | * - one timer for watchdog driver. | |
24 | * It is also worth notice that APB timer does not support true one-shot mode, | |
25 | * free-running mode will be used here to emulate one-shot mode. | |
26 | * APB timer can also be used as broadcast timer along with per cpu local APIC | |
27 | * timer, but by default APB timer has higher rating than local APIC timers. | |
28 | */ | |
29 | ||
30 | #include <linux/clocksource.h> | |
31 | #include <linux/clockchips.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/sysdev.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
bb24c471 JP |
37 | #include <linux/pm.h> |
38 | #include <linux/pci.h> | |
39 | #include <linux/sfi.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/cpu.h> | |
42 | #include <linux/irq.h> | |
43 | ||
44 | #include <asm/fixmap.h> | |
45 | #include <asm/apb_timer.h> | |
a875c019 | 46 | #include <asm/mrst.h> |
bb24c471 | 47 | |
c7bbf52a PA |
48 | #define APBT_MASK CLOCKSOURCE_MASK(32) |
49 | #define APBT_SHIFT 22 | |
a875c019 | 50 | #define APBT_CLOCKEVENT_RATING 110 |
c7bbf52a PA |
51 | #define APBT_CLOCKSOURCE_RATING 250 |
52 | #define APBT_MIN_DELTA_USEC 200 | |
bb24c471 JP |
53 | |
54 | #define EVT_TO_APBT_DEV(evt) container_of(evt, struct apbt_dev, evt) | |
55 | #define APBT_CLOCKEVENT0_NUM (0) | |
56 | #define APBT_CLOCKEVENT1_NUM (1) | |
57 | #define APBT_CLOCKSOURCE_NUM (2) | |
58 | ||
59 | static unsigned long apbt_address; | |
60 | static int apb_timer_block_enabled; | |
61 | static void __iomem *apbt_virt_address; | |
62 | static int phy_cs_timer_id; | |
63 | ||
64 | /* | |
65 | * Common DW APB timer info | |
66 | */ | |
67 | static uint64_t apbt_freq; | |
68 | ||
69 | static void apbt_set_mode(enum clock_event_mode mode, | |
c7bbf52a | 70 | struct clock_event_device *evt); |
bb24c471 | 71 | static int apbt_next_event(unsigned long delta, |
c7bbf52a | 72 | struct clock_event_device *evt); |
bb24c471 | 73 | static cycle_t apbt_read_clocksource(struct clocksource *cs); |
322aafa6 | 74 | static void apbt_restart_clocksource(struct clocksource *cs); |
bb24c471 JP |
75 | |
76 | struct apbt_dev { | |
c7bbf52a PA |
77 | struct clock_event_device evt; |
78 | unsigned int num; | |
79 | int cpu; | |
80 | unsigned int irq; | |
81 | unsigned int tick; | |
82 | unsigned int count; | |
83 | unsigned int flags; | |
84 | char name[10]; | |
bb24c471 JP |
85 | }; |
86 | ||
3010673e JP |
87 | static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev); |
88 | ||
bb24c471 JP |
89 | #ifdef CONFIG_SMP |
90 | static unsigned int apbt_num_timers_used; | |
bb24c471 JP |
91 | static struct apbt_dev *apbt_devs; |
92 | #endif | |
93 | ||
c7bbf52a | 94 | static inline unsigned long apbt_readl_reg(unsigned long a) |
bb24c471 | 95 | { |
c7bbf52a | 96 | return readl(apbt_virt_address + a); |
bb24c471 JP |
97 | } |
98 | ||
99 | static inline void apbt_writel_reg(unsigned long d, unsigned long a) | |
100 | { | |
c7bbf52a | 101 | writel(d, apbt_virt_address + a); |
bb24c471 JP |
102 | } |
103 | ||
104 | static inline unsigned long apbt_readl(int n, unsigned long a) | |
105 | { | |
c7bbf52a | 106 | return readl(apbt_virt_address + a + n * APBTMRS_REG_SIZE); |
bb24c471 JP |
107 | } |
108 | ||
109 | static inline void apbt_writel(int n, unsigned long d, unsigned long a) | |
110 | { | |
c7bbf52a | 111 | writel(d, apbt_virt_address + a + n * APBTMRS_REG_SIZE); |
bb24c471 JP |
112 | } |
113 | ||
114 | static inline void apbt_set_mapping(void) | |
115 | { | |
c7bbf52a PA |
116 | struct sfi_timer_table_entry *mtmr; |
117 | ||
118 | if (apbt_virt_address) { | |
119 | pr_debug("APBT base already mapped\n"); | |
120 | return; | |
121 | } | |
122 | mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM); | |
123 | if (mtmr == NULL) { | |
124 | printk(KERN_ERR "Failed to get MTMR %d from SFI\n", | |
125 | APBT_CLOCKEVENT0_NUM); | |
126 | return; | |
127 | } | |
128 | apbt_address = (unsigned long)mtmr->phys_addr; | |
129 | if (!apbt_address) { | |
130 | printk(KERN_WARNING "No timer base from SFI, use default\n"); | |
131 | apbt_address = APBT_DEFAULT_BASE; | |
132 | } | |
133 | apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE); | |
134 | if (apbt_virt_address) { | |
135 | pr_debug("Mapped APBT physical addr %p at virtual addr %p\n",\ | |
136 | (void *)apbt_address, (void *)apbt_virt_address); | |
137 | } else { | |
138 | pr_debug("Failed mapping APBT phy address at %p\n",\ | |
139 | (void *)apbt_address); | |
140 | goto panic_noapbt; | |
141 | } | |
142 | apbt_freq = mtmr->freq_hz / USEC_PER_SEC; | |
143 | sfi_free_mtmr(mtmr); | |
144 | ||
145 | /* Now figure out the physical timer id for clocksource device */ | |
146 | mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM); | |
147 | if (mtmr == NULL) | |
148 | goto panic_noapbt; | |
149 | ||
150 | /* Now figure out the physical timer id */ | |
151 | phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) | |
152 | / APBTMRS_REG_SIZE; | |
153 | pr_debug("Use timer %d for clocksource\n", phy_cs_timer_id); | |
154 | return; | |
bb24c471 JP |
155 | |
156 | panic_noapbt: | |
c7bbf52a | 157 | panic("Failed to setup APB system timer\n"); |
bb24c471 JP |
158 | |
159 | } | |
160 | ||
161 | static inline void apbt_clear_mapping(void) | |
162 | { | |
c7bbf52a PA |
163 | iounmap(apbt_virt_address); |
164 | apbt_virt_address = NULL; | |
bb24c471 JP |
165 | } |
166 | ||
167 | /* | |
168 | * APBT timer interrupt enable / disable | |
169 | */ | |
170 | static inline int is_apbt_capable(void) | |
171 | { | |
c7bbf52a | 172 | return apbt_virt_address ? 1 : 0; |
bb24c471 JP |
173 | } |
174 | ||
175 | static struct clocksource clocksource_apbt = { | |
c7bbf52a PA |
176 | .name = "apbt", |
177 | .rating = APBT_CLOCKSOURCE_RATING, | |
178 | .read = apbt_read_clocksource, | |
179 | .mask = APBT_MASK, | |
180 | .shift = APBT_SHIFT, | |
181 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
182 | .resume = apbt_restart_clocksource, | |
bb24c471 JP |
183 | }; |
184 | ||
185 | /* boot APB clock event device */ | |
186 | static struct clock_event_device apbt_clockevent = { | |
c7bbf52a PA |
187 | .name = "apbt0", |
188 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
189 | .set_mode = apbt_set_mode, | |
190 | .set_next_event = apbt_next_event, | |
191 | .shift = APBT_SHIFT, | |
192 | .irq = 0, | |
193 | .rating = APBT_CLOCKEVENT_RATING, | |
bb24c471 JP |
194 | }; |
195 | ||
bb24c471 JP |
196 | /* |
197 | * start count down from 0xffff_ffff. this is done by toggling the enable bit | |
198 | * then load initial load count to ~0. | |
199 | */ | |
200 | static void apbt_start_counter(int n) | |
201 | { | |
c7bbf52a PA |
202 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); |
203 | ||
204 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
205 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
206 | apbt_writel(n, ~0, APBTMR_N_LOAD_COUNT); | |
207 | /* enable, mask interrupt */ | |
208 | ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; | |
209 | ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT); | |
210 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
211 | /* read it once to get cached counter value initialized */ | |
212 | apbt_read_clocksource(&clocksource_apbt); | |
bb24c471 JP |
213 | } |
214 | ||
215 | static irqreturn_t apbt_interrupt_handler(int irq, void *data) | |
216 | { | |
c7bbf52a PA |
217 | struct apbt_dev *dev = (struct apbt_dev *)data; |
218 | struct clock_event_device *aevt = &dev->evt; | |
219 | ||
220 | if (!aevt->event_handler) { | |
221 | printk(KERN_INFO "Spurious APBT timer interrupt on %d\n", | |
222 | dev->num); | |
223 | return IRQ_NONE; | |
224 | } | |
225 | aevt->event_handler(aevt); | |
226 | return IRQ_HANDLED; | |
bb24c471 JP |
227 | } |
228 | ||
322aafa6 | 229 | static void apbt_restart_clocksource(struct clocksource *cs) |
bb24c471 | 230 | { |
c7bbf52a | 231 | apbt_start_counter(phy_cs_timer_id); |
bb24c471 JP |
232 | } |
233 | ||
bb24c471 JP |
234 | static void apbt_enable_int(int n) |
235 | { | |
c7bbf52a PA |
236 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); |
237 | /* clear pending intr */ | |
238 | apbt_readl(n, APBTMR_N_EOI); | |
239 | ctrl &= ~APBTMR_CONTROL_INT; | |
240 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
bb24c471 JP |
241 | } |
242 | ||
243 | static void apbt_disable_int(int n) | |
244 | { | |
c7bbf52a | 245 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); |
bb24c471 | 246 | |
c7bbf52a PA |
247 | ctrl |= APBTMR_CONTROL_INT; |
248 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
bb24c471 JP |
249 | } |
250 | ||
251 | ||
252 | static int __init apbt_clockevent_register(void) | |
253 | { | |
c7bbf52a PA |
254 | struct sfi_timer_table_entry *mtmr; |
255 | struct apbt_dev *adev = &__get_cpu_var(cpu_apbt_dev); | |
256 | ||
257 | mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM); | |
258 | if (mtmr == NULL) { | |
259 | printk(KERN_ERR "Failed to get MTMR %d from SFI\n", | |
260 | APBT_CLOCKEVENT0_NUM); | |
261 | return -ENODEV; | |
262 | } | |
263 | ||
264 | /* | |
265 | * We need to calculate the scaled math multiplication factor for | |
266 | * nanosecond to apbt tick conversion. | |
267 | * mult = (nsec/cycle)*2^APBT_SHIFT | |
268 | */ | |
269 | apbt_clockevent.mult = div_sc((unsigned long) mtmr->freq_hz | |
270 | , NSEC_PER_SEC, APBT_SHIFT); | |
271 | ||
272 | /* Calculate the min / max delta */ | |
273 | apbt_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
274 | &apbt_clockevent); | |
275 | apbt_clockevent.min_delta_ns = clockevent_delta2ns( | |
276 | APBT_MIN_DELTA_USEC*apbt_freq, | |
277 | &apbt_clockevent); | |
278 | /* | |
279 | * Start apbt with the boot cpu mask and make it | |
280 | * global if not used for per cpu timer. | |
281 | */ | |
282 | apbt_clockevent.cpumask = cpumask_of(smp_processor_id()); | |
283 | adev->num = smp_processor_id(); | |
284 | memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device)); | |
285 | ||
a875c019 | 286 | if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) { |
7b62dbec | 287 | adev->evt.rating = APBT_CLOCKEVENT_RATING - 100; |
3010673e | 288 | global_clock_event = &adev->evt; |
c7bbf52a PA |
289 | printk(KERN_DEBUG "%s clockevent registered as global\n", |
290 | global_clock_event->name); | |
291 | } | |
292 | ||
293 | if (request_irq(apbt_clockevent.irq, apbt_interrupt_handler, | |
294 | IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, | |
295 | apbt_clockevent.name, adev)) { | |
296 | printk(KERN_ERR "Failed request IRQ for APBT%d\n", | |
297 | apbt_clockevent.irq); | |
298 | } | |
299 | ||
300 | clockevents_register_device(&adev->evt); | |
301 | /* Start APBT 0 interrupts */ | |
302 | apbt_enable_int(APBT_CLOCKEVENT0_NUM); | |
303 | ||
304 | sfi_free_mtmr(mtmr); | |
305 | return 0; | |
bb24c471 JP |
306 | } |
307 | ||
308 | #ifdef CONFIG_SMP | |
a5ef2e70 TG |
309 | |
310 | static void apbt_setup_irq(struct apbt_dev *adev) | |
311 | { | |
312 | /* timer0 irq has been setup early */ | |
313 | if (adev->irq == 0) | |
314 | return; | |
315 | ||
6550904d JP |
316 | irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT); |
317 | irq_set_affinity(adev->irq, cpumask_of(adev->cpu)); | |
318 | /* APB timer irqs are set up as mp_irqs, timer is edge type */ | |
319 | __set_irq_handler(adev->irq, handle_edge_irq, 0, "edge"); | |
320 | ||
a5ef2e70 | 321 | if (system_state == SYSTEM_BOOTING) { |
a5ef2e70 | 322 | if (request_irq(adev->irq, apbt_interrupt_handler, |
6550904d JP |
323 | IRQF_TIMER | IRQF_DISABLED | |
324 | IRQF_NOBALANCING, | |
325 | adev->name, adev)) { | |
a5ef2e70 TG |
326 | printk(KERN_ERR "Failed request IRQ for APBT%d\n", |
327 | adev->num); | |
328 | } | |
329 | } else | |
330 | enable_irq(adev->irq); | |
331 | } | |
332 | ||
bb24c471 JP |
333 | /* Should be called with per cpu */ |
334 | void apbt_setup_secondary_clock(void) | |
335 | { | |
c7bbf52a PA |
336 | struct apbt_dev *adev; |
337 | struct clock_event_device *aevt; | |
338 | int cpu; | |
339 | ||
340 | /* Don't register boot CPU clockevent */ | |
341 | cpu = smp_processor_id(); | |
f6e9456c | 342 | if (!cpu) |
c7bbf52a PA |
343 | return; |
344 | /* | |
345 | * We need to calculate the scaled math multiplication factor for | |
346 | * nanosecond to apbt tick conversion. | |
347 | * mult = (nsec/cycle)*2^APBT_SHIFT | |
348 | */ | |
349 | printk(KERN_INFO "Init per CPU clockevent %d\n", cpu); | |
350 | adev = &per_cpu(cpu_apbt_dev, cpu); | |
351 | aevt = &adev->evt; | |
352 | ||
353 | memcpy(aevt, &apbt_clockevent, sizeof(*aevt)); | |
354 | aevt->cpumask = cpumask_of(cpu); | |
355 | aevt->name = adev->name; | |
356 | aevt->mode = CLOCK_EVT_MODE_UNUSED; | |
357 | ||
358 | printk(KERN_INFO "Registering CPU %d clockevent device %s, mask %08x\n", | |
359 | cpu, aevt->name, *(u32 *)aevt->cpumask); | |
360 | ||
361 | apbt_setup_irq(adev); | |
362 | ||
363 | clockevents_register_device(aevt); | |
364 | ||
365 | apbt_enable_int(cpu); | |
366 | ||
367 | return; | |
bb24c471 JP |
368 | } |
369 | ||
370 | /* | |
371 | * this notify handler process CPU hotplug events. in case of S0i3, nonboot | |
372 | * cpus are disabled/enabled frequently, for performance reasons, we keep the | |
373 | * per cpu timer irq registered so that we do need to do free_irq/request_irq. | |
374 | * | |
375 | * TODO: it might be more reliable to directly disable percpu clockevent device | |
376 | * without the notifier chain. currently, cpu 0 may get interrupts from other | |
377 | * cpu timers during the offline process due to the ordering of notification. | |
378 | * the extra interrupt is harmless. | |
379 | */ | |
380 | static int apbt_cpuhp_notify(struct notifier_block *n, | |
c7bbf52a | 381 | unsigned long action, void *hcpu) |
bb24c471 | 382 | { |
c7bbf52a PA |
383 | unsigned long cpu = (unsigned long)hcpu; |
384 | struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu); | |
385 | ||
386 | switch (action & 0xf) { | |
387 | case CPU_DEAD: | |
a5ef2e70 | 388 | disable_irq(adev->irq); |
c7bbf52a | 389 | apbt_disable_int(cpu); |
a5ef2e70 | 390 | if (system_state == SYSTEM_RUNNING) { |
c7bbf52a | 391 | pr_debug("skipping APBT CPU %lu offline\n", cpu); |
a5ef2e70 | 392 | } else if (adev) { |
c7bbf52a PA |
393 | pr_debug("APBT clockevent for cpu %lu offline\n", cpu); |
394 | free_irq(adev->irq, adev); | |
395 | } | |
396 | break; | |
397 | default: | |
d0ed0c32 | 398 | pr_debug("APBT notified %lu, no action\n", action); |
c7bbf52a PA |
399 | } |
400 | return NOTIFY_OK; | |
bb24c471 JP |
401 | } |
402 | ||
403 | static __init int apbt_late_init(void) | |
404 | { | |
a875c019 JP |
405 | if (mrst_timer_options == MRST_TIMER_LAPIC_APBT || |
406 | !apb_timer_block_enabled) | |
c7bbf52a PA |
407 | return 0; |
408 | /* This notifier should be called after workqueue is ready */ | |
409 | hotcpu_notifier(apbt_cpuhp_notify, -20); | |
410 | return 0; | |
bb24c471 JP |
411 | } |
412 | fs_initcall(apbt_late_init); | |
413 | #else | |
414 | ||
415 | void apbt_setup_secondary_clock(void) {} | |
416 | ||
417 | #endif /* CONFIG_SMP */ | |
418 | ||
419 | static void apbt_set_mode(enum clock_event_mode mode, | |
c7bbf52a | 420 | struct clock_event_device *evt) |
bb24c471 | 421 | { |
c7bbf52a PA |
422 | unsigned long ctrl; |
423 | uint64_t delta; | |
424 | int timer_num; | |
425 | struct apbt_dev *adev = EVT_TO_APBT_DEV(evt); | |
426 | ||
a875c019 JP |
427 | BUG_ON(!apbt_virt_address); |
428 | ||
c7bbf52a PA |
429 | timer_num = adev->num; |
430 | pr_debug("%s CPU %d timer %d mode=%d\n", | |
431 | __func__, first_cpu(*evt->cpumask), timer_num, mode); | |
432 | ||
433 | switch (mode) { | |
434 | case CLOCK_EVT_MODE_PERIODIC: | |
435 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * apbt_clockevent.mult; | |
436 | delta >>= apbt_clockevent.shift; | |
437 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
438 | ctrl |= APBTMR_CONTROL_MODE_PERIODIC; | |
439 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
440 | /* | |
441 | * DW APB p. 46, have to disable timer before load counter, | |
442 | * may cause sync problem. | |
443 | */ | |
444 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
445 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
446 | udelay(1); | |
447 | pr_debug("Setting clock period %d for HZ %d\n", (int)delta, HZ); | |
448 | apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT); | |
449 | ctrl |= APBTMR_CONTROL_ENABLE; | |
450 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
451 | break; | |
452 | /* APB timer does not have one-shot mode, use free running mode */ | |
453 | case CLOCK_EVT_MODE_ONESHOT: | |
454 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
455 | /* | |
456 | * set free running mode, this mode will let timer reload max | |
457 | * timeout which will give time (3min on 25MHz clock) to rearm | |
458 | * the next event, therefore emulate the one-shot mode. | |
459 | */ | |
460 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
461 | ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; | |
462 | ||
463 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
464 | /* write again to set free running mode */ | |
465 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
466 | ||
467 | /* | |
468 | * DW APB p. 46, load counter with all 1s before starting free | |
469 | * running mode. | |
470 | */ | |
471 | apbt_writel(timer_num, ~0, APBTMR_N_LOAD_COUNT); | |
472 | ctrl &= ~APBTMR_CONTROL_INT; | |
473 | ctrl |= APBTMR_CONTROL_ENABLE; | |
474 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
475 | break; | |
476 | ||
477 | case CLOCK_EVT_MODE_UNUSED: | |
478 | case CLOCK_EVT_MODE_SHUTDOWN: | |
479 | apbt_disable_int(timer_num); | |
480 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
481 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
482 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
483 | break; | |
484 | ||
485 | case CLOCK_EVT_MODE_RESUME: | |
486 | apbt_enable_int(timer_num); | |
487 | break; | |
488 | } | |
bb24c471 JP |
489 | } |
490 | ||
491 | static int apbt_next_event(unsigned long delta, | |
c7bbf52a | 492 | struct clock_event_device *evt) |
bb24c471 | 493 | { |
c7bbf52a PA |
494 | unsigned long ctrl; |
495 | int timer_num; | |
496 | ||
497 | struct apbt_dev *adev = EVT_TO_APBT_DEV(evt); | |
498 | ||
499 | timer_num = adev->num; | |
500 | /* Disable timer */ | |
501 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
502 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
503 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
504 | /* write new count */ | |
505 | apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT); | |
506 | ctrl |= APBTMR_CONTROL_ENABLE; | |
507 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
508 | return 0; | |
bb24c471 JP |
509 | } |
510 | ||
bb24c471 JP |
511 | static cycle_t apbt_read_clocksource(struct clocksource *cs) |
512 | { | |
5df91509 | 513 | unsigned long current_count; |
514 | ||
515 | current_count = apbt_readl(phy_cs_timer_id, APBTMR_N_CURRENT_VALUE); | |
516 | return (cycle_t)~current_count; | |
bb24c471 JP |
517 | } |
518 | ||
519 | static int apbt_clocksource_register(void) | |
520 | { | |
c7bbf52a PA |
521 | u64 start, now; |
522 | cycle_t t1; | |
523 | ||
524 | /* Start the counter, use timer 2 as source, timer 0/1 for event */ | |
525 | apbt_start_counter(phy_cs_timer_id); | |
526 | ||
527 | /* Verify whether apbt counter works */ | |
528 | t1 = apbt_read_clocksource(&clocksource_apbt); | |
529 | rdtscll(start); | |
530 | ||
531 | /* | |
532 | * We don't know the TSC frequency yet, but waiting for | |
533 | * 200000 TSC cycles is safe: | |
534 | * 4 GHz == 50us | |
535 | * 1 GHz == 200us | |
536 | */ | |
537 | do { | |
538 | rep_nop(); | |
539 | rdtscll(now); | |
540 | } while ((now - start) < 200000UL); | |
541 | ||
542 | /* APBT is the only always on clocksource, it has to work! */ | |
543 | if (t1 == apbt_read_clocksource(&clocksource_apbt)) | |
544 | panic("APBT counter not counting. APBT disabled\n"); | |
545 | ||
546 | /* | |
547 | * initialize and register APBT clocksource | |
548 | * convert that to ns/clock cycle | |
549 | * mult = (ns/c) * 2^APBT_SHIFT | |
550 | */ | |
551 | clocksource_apbt.mult = div_sc(MSEC_PER_SEC, | |
552 | (unsigned long) apbt_freq, APBT_SHIFT); | |
553 | clocksource_register(&clocksource_apbt); | |
554 | ||
555 | return 0; | |
bb24c471 JP |
556 | } |
557 | ||
558 | /* | |
559 | * Early setup the APBT timer, only use timer 0 for booting then switch to | |
560 | * per CPU timer if possible. | |
561 | * returns 1 if per cpu apbt is setup | |
562 | * returns 0 if no per cpu apbt is chosen | |
563 | * panic if set up failed, this is the only platform timer on Moorestown. | |
564 | */ | |
565 | void __init apbt_time_init(void) | |
566 | { | |
567 | #ifdef CONFIG_SMP | |
c7bbf52a PA |
568 | int i; |
569 | struct sfi_timer_table_entry *p_mtmr; | |
570 | unsigned int percpu_timer; | |
571 | struct apbt_dev *adev; | |
bb24c471 JP |
572 | #endif |
573 | ||
c7bbf52a PA |
574 | if (apb_timer_block_enabled) |
575 | return; | |
576 | apbt_set_mapping(); | |
577 | if (apbt_virt_address) { | |
578 | pr_debug("Found APBT version 0x%lx\n",\ | |
579 | apbt_readl_reg(APBTMRS_COMP_VERSION)); | |
580 | } else | |
581 | goto out_noapbt; | |
582 | /* | |
583 | * Read the frequency and check for a sane value, for ESL model | |
584 | * we extend the possible clock range to allow time scaling. | |
585 | */ | |
586 | ||
587 | if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) { | |
588 | pr_debug("APBT has invalid freq 0x%llx\n", apbt_freq); | |
589 | goto out_noapbt; | |
590 | } | |
591 | if (apbt_clocksource_register()) { | |
592 | pr_debug("APBT has failed to register clocksource\n"); | |
593 | goto out_noapbt; | |
594 | } | |
595 | if (!apbt_clockevent_register()) | |
596 | apb_timer_block_enabled = 1; | |
597 | else { | |
598 | pr_debug("APBT has failed to register clockevent\n"); | |
599 | goto out_noapbt; | |
600 | } | |
bb24c471 | 601 | #ifdef CONFIG_SMP |
c7bbf52a | 602 | /* kernel cmdline disable apb timer, so we will use lapic timers */ |
a875c019 | 603 | if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) { |
c7bbf52a PA |
604 | printk(KERN_INFO "apbt: disabled per cpu timer\n"); |
605 | return; | |
606 | } | |
607 | pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus()); | |
608 | if (num_possible_cpus() <= sfi_mtimer_num) { | |
609 | percpu_timer = 1; | |
610 | apbt_num_timers_used = num_possible_cpus(); | |
611 | } else { | |
612 | percpu_timer = 0; | |
613 | apbt_num_timers_used = 1; | |
614 | adev = &per_cpu(cpu_apbt_dev, 0); | |
615 | adev->flags &= ~APBT_DEV_USED; | |
616 | } | |
617 | pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used); | |
618 | ||
619 | /* here we set up per CPU timer data structure */ | |
620 | apbt_devs = kzalloc(sizeof(struct apbt_dev) * apbt_num_timers_used, | |
621 | GFP_KERNEL); | |
622 | if (!apbt_devs) { | |
623 | printk(KERN_ERR "Failed to allocate APB timer devices\n"); | |
624 | return; | |
625 | } | |
626 | for (i = 0; i < apbt_num_timers_used; i++) { | |
627 | adev = &per_cpu(cpu_apbt_dev, i); | |
628 | adev->num = i; | |
629 | adev->cpu = i; | |
630 | p_mtmr = sfi_get_mtmr(i); | |
631 | if (p_mtmr) { | |
632 | adev->tick = p_mtmr->freq_hz; | |
633 | adev->irq = p_mtmr->irq; | |
634 | } else | |
635 | printk(KERN_ERR "Failed to get timer for cpu %d\n", i); | |
636 | adev->count = 0; | |
637 | sprintf(adev->name, "apbt%d", i); | |
638 | } | |
bb24c471 JP |
639 | #endif |
640 | ||
c7bbf52a | 641 | return; |
bb24c471 JP |
642 | |
643 | out_noapbt: | |
c7bbf52a PA |
644 | apbt_clear_mapping(); |
645 | apb_timer_block_enabled = 0; | |
646 | panic("failed to enable APB timer\n"); | |
bb24c471 JP |
647 | } |
648 | ||
649 | static inline void apbt_disable(int n) | |
650 | { | |
c7bbf52a PA |
651 | if (is_apbt_capable()) { |
652 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); | |
653 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
654 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
655 | } | |
bb24c471 JP |
656 | } |
657 | ||
658 | /* called before apb_timer_enable, use early map */ | |
659 | unsigned long apbt_quick_calibrate() | |
660 | { | |
c7bbf52a PA |
661 | int i, scale; |
662 | u64 old, new; | |
663 | cycle_t t1, t2; | |
664 | unsigned long khz = 0; | |
665 | u32 loop, shift; | |
666 | ||
667 | apbt_set_mapping(); | |
668 | apbt_start_counter(phy_cs_timer_id); | |
669 | ||
670 | /* check if the timer can count down, otherwise return */ | |
671 | old = apbt_read_clocksource(&clocksource_apbt); | |
672 | i = 10000; | |
673 | while (--i) { | |
674 | if (old != apbt_read_clocksource(&clocksource_apbt)) | |
675 | break; | |
676 | } | |
677 | if (!i) | |
678 | goto failed; | |
679 | ||
680 | /* count 16 ms */ | |
681 | loop = (apbt_freq * 1000) << 4; | |
682 | ||
683 | /* restart the timer to ensure it won't get to 0 in the calibration */ | |
684 | apbt_start_counter(phy_cs_timer_id); | |
685 | ||
686 | old = apbt_read_clocksource(&clocksource_apbt); | |
687 | old += loop; | |
688 | ||
689 | t1 = __native_read_tsc(); | |
690 | ||
691 | do { | |
692 | new = apbt_read_clocksource(&clocksource_apbt); | |
693 | } while (new < old); | |
694 | ||
695 | t2 = __native_read_tsc(); | |
696 | ||
697 | shift = 5; | |
698 | if (unlikely(loop >> shift == 0)) { | |
699 | printk(KERN_INFO | |
700 | "APBT TSC calibration failed, not enough resolution\n"); | |
701 | return 0; | |
702 | } | |
703 | scale = (int)div_u64((t2 - t1), loop >> shift); | |
704 | khz = (scale * apbt_freq * 1000) >> shift; | |
705 | printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz); | |
706 | return khz; | |
bb24c471 | 707 | failed: |
c7bbf52a | 708 | return 0; |
bb24c471 | 709 | } |