Commit | Line | Data |
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bb24c471 JP |
1 | /* |
2 | * apb_timer.c: Driver for Langwell APB timers | |
3 | * | |
4 | * (C) Copyright 2009 Intel Corporation | |
5 | * Author: Jacob Pan (jacob.jun.pan@intel.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | * | |
12 | * Note: | |
13 | * Langwell is the south complex of Intel Moorestown MID platform. There are | |
14 | * eight external timers in total that can be used by the operating system. | |
15 | * The timer information, such as frequency and addresses, is provided to the | |
16 | * OS via SFI tables. | |
17 | * Timer interrupts are routed via FW/HW emulated IOAPIC independently via | |
18 | * individual redirection table entries (RTE). | |
19 | * Unlike HPET, there is no master counter, therefore one of the timers are | |
20 | * used as clocksource. The overall allocation looks like: | |
21 | * - timer 0 - NR_CPUs for per cpu timer | |
22 | * - one timer for clocksource | |
23 | * - one timer for watchdog driver. | |
24 | * It is also worth notice that APB timer does not support true one-shot mode, | |
25 | * free-running mode will be used here to emulate one-shot mode. | |
26 | * APB timer can also be used as broadcast timer along with per cpu local APIC | |
27 | * timer, but by default APB timer has higher rating than local APIC timers. | |
28 | */ | |
29 | ||
bb24c471 | 30 | #include <linux/delay.h> |
06c3df49 | 31 | #include <linux/dw_apb_timer.h> |
bb24c471 JP |
32 | #include <linux/errno.h> |
33 | #include <linux/init.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
bb24c471 | 35 | #include <linux/pm.h> |
bb24c471 JP |
36 | #include <linux/sfi.h> |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/cpu.h> | |
39 | #include <linux/irq.h> | |
40 | ||
41 | #include <asm/fixmap.h> | |
42 | #include <asm/apb_timer.h> | |
05454c26 | 43 | #include <asm/intel-mid.h> |
16f871bc | 44 | #include <asm/time.h> |
bb24c471 | 45 | |
a875c019 | 46 | #define APBT_CLOCKEVENT_RATING 110 |
c7bbf52a | 47 | #define APBT_CLOCKSOURCE_RATING 250 |
bb24c471 | 48 | |
bb24c471 | 49 | #define APBT_CLOCKEVENT0_NUM (0) |
bb24c471 JP |
50 | #define APBT_CLOCKSOURCE_NUM (2) |
51 | ||
06c3df49 | 52 | static phys_addr_t apbt_address; |
bb24c471 JP |
53 | static int apb_timer_block_enabled; |
54 | static void __iomem *apbt_virt_address; | |
bb24c471 JP |
55 | |
56 | /* | |
57 | * Common DW APB timer info | |
58 | */ | |
06c3df49 | 59 | static unsigned long apbt_freq; |
bb24c471 JP |
60 | |
61 | struct apbt_dev { | |
06c3df49 JI |
62 | struct dw_apb_clock_event_device *timer; |
63 | unsigned int num; | |
64 | int cpu; | |
65 | unsigned int irq; | |
66 | char name[10]; | |
bb24c471 JP |
67 | }; |
68 | ||
06c3df49 | 69 | static struct dw_apb_clocksource *clocksource_apbt; |
3010673e | 70 | |
06c3df49 | 71 | static inline void __iomem *adev_virt_addr(struct apbt_dev *adev) |
bb24c471 | 72 | { |
06c3df49 | 73 | return apbt_virt_address + adev->num * APBTMRS_REG_SIZE; |
bb24c471 JP |
74 | } |
75 | ||
06c3df49 | 76 | static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev); |
bb24c471 | 77 | |
06c3df49 JI |
78 | #ifdef CONFIG_SMP |
79 | static unsigned int apbt_num_timers_used; | |
80 | #endif | |
bb24c471 JP |
81 | |
82 | static inline void apbt_set_mapping(void) | |
83 | { | |
c7bbf52a | 84 | struct sfi_timer_table_entry *mtmr; |
06c3df49 | 85 | int phy_cs_timer_id = 0; |
c7bbf52a PA |
86 | |
87 | if (apbt_virt_address) { | |
88 | pr_debug("APBT base already mapped\n"); | |
89 | return; | |
90 | } | |
91 | mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM); | |
92 | if (mtmr == NULL) { | |
93 | printk(KERN_ERR "Failed to get MTMR %d from SFI\n", | |
94 | APBT_CLOCKEVENT0_NUM); | |
95 | return; | |
96 | } | |
06c3df49 | 97 | apbt_address = (phys_addr_t)mtmr->phys_addr; |
c7bbf52a PA |
98 | if (!apbt_address) { |
99 | printk(KERN_WARNING "No timer base from SFI, use default\n"); | |
100 | apbt_address = APBT_DEFAULT_BASE; | |
101 | } | |
102 | apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE); | |
06c3df49 JI |
103 | if (!apbt_virt_address) { |
104 | pr_debug("Failed mapping APBT phy address at %lu\n",\ | |
105 | (unsigned long)apbt_address); | |
c7bbf52a PA |
106 | goto panic_noapbt; |
107 | } | |
06c3df49 | 108 | apbt_freq = mtmr->freq_hz; |
c7bbf52a PA |
109 | sfi_free_mtmr(mtmr); |
110 | ||
111 | /* Now figure out the physical timer id for clocksource device */ | |
112 | mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM); | |
113 | if (mtmr == NULL) | |
114 | goto panic_noapbt; | |
115 | ||
116 | /* Now figure out the physical timer id */ | |
06c3df49 JI |
117 | pr_debug("Use timer %d for clocksource\n", |
118 | (int)(mtmr->phys_addr & 0xff) / APBTMRS_REG_SIZE); | |
119 | phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) / | |
120 | APBTMRS_REG_SIZE; | |
121 | ||
122 | clocksource_apbt = dw_apb_clocksource_init(APBT_CLOCKSOURCE_RATING, | |
123 | "apbt0", apbt_virt_address + phy_cs_timer_id * | |
124 | APBTMRS_REG_SIZE, apbt_freq); | |
c7bbf52a | 125 | return; |
bb24c471 JP |
126 | |
127 | panic_noapbt: | |
c7bbf52a | 128 | panic("Failed to setup APB system timer\n"); |
bb24c471 JP |
129 | |
130 | } | |
131 | ||
132 | static inline void apbt_clear_mapping(void) | |
133 | { | |
c7bbf52a PA |
134 | iounmap(apbt_virt_address); |
135 | apbt_virt_address = NULL; | |
bb24c471 JP |
136 | } |
137 | ||
bb24c471 JP |
138 | static int __init apbt_clockevent_register(void) |
139 | { | |
c7bbf52a | 140 | struct sfi_timer_table_entry *mtmr; |
89cbc767 | 141 | struct apbt_dev *adev = this_cpu_ptr(&cpu_apbt_dev); |
c7bbf52a PA |
142 | |
143 | mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM); | |
144 | if (mtmr == NULL) { | |
145 | printk(KERN_ERR "Failed to get MTMR %d from SFI\n", | |
146 | APBT_CLOCKEVENT0_NUM); | |
147 | return -ENODEV; | |
148 | } | |
149 | ||
c7bbf52a | 150 | adev->num = smp_processor_id(); |
06c3df49 | 151 | adev->timer = dw_apb_clockevent_init(smp_processor_id(), "apbt0", |
712b6aa8 | 152 | intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ? |
06c3df49 JI |
153 | APBT_CLOCKEVENT_RATING - 100 : APBT_CLOCKEVENT_RATING, |
154 | adev_virt_addr(adev), 0, apbt_freq); | |
155 | /* Firmware does EOI handling for us. */ | |
156 | adev->timer->eoi = NULL; | |
c7bbf52a | 157 | |
712b6aa8 | 158 | if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) { |
06c3df49 | 159 | global_clock_event = &adev->timer->ced; |
c7bbf52a PA |
160 | printk(KERN_DEBUG "%s clockevent registered as global\n", |
161 | global_clock_event->name); | |
162 | } | |
163 | ||
06c3df49 | 164 | dw_apb_clockevent_register(adev->timer); |
c7bbf52a PA |
165 | |
166 | sfi_free_mtmr(mtmr); | |
167 | return 0; | |
bb24c471 JP |
168 | } |
169 | ||
170 | #ifdef CONFIG_SMP | |
a5ef2e70 TG |
171 | |
172 | static void apbt_setup_irq(struct apbt_dev *adev) | |
173 | { | |
6550904d JP |
174 | irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT); |
175 | irq_set_affinity(adev->irq, cpumask_of(adev->cpu)); | |
a5ef2e70 TG |
176 | } |
177 | ||
bb24c471 JP |
178 | /* Should be called with per cpu */ |
179 | void apbt_setup_secondary_clock(void) | |
180 | { | |
c7bbf52a | 181 | struct apbt_dev *adev; |
c7bbf52a PA |
182 | int cpu; |
183 | ||
184 | /* Don't register boot CPU clockevent */ | |
185 | cpu = smp_processor_id(); | |
f6e9456c | 186 | if (!cpu) |
c7bbf52a | 187 | return; |
c7bbf52a | 188 | |
89cbc767 | 189 | adev = this_cpu_ptr(&cpu_apbt_dev); |
06c3df49 JI |
190 | if (!adev->timer) { |
191 | adev->timer = dw_apb_clockevent_init(cpu, adev->name, | |
192 | APBT_CLOCKEVENT_RATING, adev_virt_addr(adev), | |
193 | adev->irq, apbt_freq); | |
194 | adev->timer->eoi = NULL; | |
195 | } else { | |
196 | dw_apb_clockevent_resume(adev->timer); | |
197 | } | |
c7bbf52a | 198 | |
06c3df49 JI |
199 | printk(KERN_INFO "Registering CPU %d clockevent device %s, cpu %08x\n", |
200 | cpu, adev->name, adev->cpu); | |
c7bbf52a PA |
201 | |
202 | apbt_setup_irq(adev); | |
06c3df49 | 203 | dw_apb_clockevent_register(adev->timer); |
c7bbf52a PA |
204 | |
205 | return; | |
bb24c471 JP |
206 | } |
207 | ||
208 | /* | |
209 | * this notify handler process CPU hotplug events. in case of S0i3, nonboot | |
210 | * cpus are disabled/enabled frequently, for performance reasons, we keep the | |
211 | * per cpu timer irq registered so that we do need to do free_irq/request_irq. | |
212 | * | |
213 | * TODO: it might be more reliable to directly disable percpu clockevent device | |
214 | * without the notifier chain. currently, cpu 0 may get interrupts from other | |
215 | * cpu timers during the offline process due to the ordering of notification. | |
216 | * the extra interrupt is harmless. | |
217 | */ | |
148b9e2a | 218 | static int apbt_cpu_dead(unsigned int cpu) |
bb24c471 | 219 | { |
c7bbf52a PA |
220 | struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu); |
221 | ||
148b9e2a SAS |
222 | dw_apb_clockevent_pause(adev->timer); |
223 | if (system_state == SYSTEM_RUNNING) { | |
224 | pr_debug("skipping APBT CPU %u offline\n", cpu); | |
225 | } else { | |
226 | pr_debug("APBT clockevent for cpu %u offline\n", cpu); | |
227 | dw_apb_clockevent_stop(adev->timer); | |
c7bbf52a | 228 | } |
148b9e2a | 229 | return 0; |
bb24c471 JP |
230 | } |
231 | ||
232 | static __init int apbt_late_init(void) | |
233 | { | |
712b6aa8 | 234 | if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT || |
a875c019 | 235 | !apb_timer_block_enabled) |
c7bbf52a | 236 | return 0; |
148b9e2a SAS |
237 | return cpuhp_setup_state(CPUHP_X86_APB_DEAD, "X86_APB_DEAD", NULL, |
238 | apbt_cpu_dead); | |
bb24c471 JP |
239 | } |
240 | fs_initcall(apbt_late_init); | |
241 | #else | |
242 | ||
243 | void apbt_setup_secondary_clock(void) {} | |
244 | ||
245 | #endif /* CONFIG_SMP */ | |
246 | ||
bb24c471 JP |
247 | static int apbt_clocksource_register(void) |
248 | { | |
c7bbf52a PA |
249 | u64 start, now; |
250 | cycle_t t1; | |
251 | ||
252 | /* Start the counter, use timer 2 as source, timer 0/1 for event */ | |
06c3df49 | 253 | dw_apb_clocksource_start(clocksource_apbt); |
c7bbf52a PA |
254 | |
255 | /* Verify whether apbt counter works */ | |
06c3df49 | 256 | t1 = dw_apb_clocksource_read(clocksource_apbt); |
4ea1636b | 257 | start = rdtsc(); |
c7bbf52a PA |
258 | |
259 | /* | |
260 | * We don't know the TSC frequency yet, but waiting for | |
261 | * 200000 TSC cycles is safe: | |
262 | * 4 GHz == 50us | |
263 | * 1 GHz == 200us | |
264 | */ | |
265 | do { | |
266 | rep_nop(); | |
4ea1636b | 267 | now = rdtsc(); |
c7bbf52a PA |
268 | } while ((now - start) < 200000UL); |
269 | ||
270 | /* APBT is the only always on clocksource, it has to work! */ | |
06c3df49 | 271 | if (t1 == dw_apb_clocksource_read(clocksource_apbt)) |
c7bbf52a PA |
272 | panic("APBT counter not counting. APBT disabled\n"); |
273 | ||
06c3df49 | 274 | dw_apb_clocksource_register(clocksource_apbt); |
c7bbf52a PA |
275 | |
276 | return 0; | |
bb24c471 JP |
277 | } |
278 | ||
279 | /* | |
280 | * Early setup the APBT timer, only use timer 0 for booting then switch to | |
281 | * per CPU timer if possible. | |
282 | * returns 1 if per cpu apbt is setup | |
283 | * returns 0 if no per cpu apbt is chosen | |
284 | * panic if set up failed, this is the only platform timer on Moorestown. | |
285 | */ | |
286 | void __init apbt_time_init(void) | |
287 | { | |
288 | #ifdef CONFIG_SMP | |
c7bbf52a PA |
289 | int i; |
290 | struct sfi_timer_table_entry *p_mtmr; | |
c7bbf52a | 291 | struct apbt_dev *adev; |
bb24c471 JP |
292 | #endif |
293 | ||
c7bbf52a PA |
294 | if (apb_timer_block_enabled) |
295 | return; | |
296 | apbt_set_mapping(); | |
06c3df49 | 297 | if (!apbt_virt_address) |
c7bbf52a PA |
298 | goto out_noapbt; |
299 | /* | |
300 | * Read the frequency and check for a sane value, for ESL model | |
301 | * we extend the possible clock range to allow time scaling. | |
302 | */ | |
303 | ||
304 | if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) { | |
06c3df49 | 305 | pr_debug("APBT has invalid freq 0x%lx\n", apbt_freq); |
c7bbf52a PA |
306 | goto out_noapbt; |
307 | } | |
308 | if (apbt_clocksource_register()) { | |
309 | pr_debug("APBT has failed to register clocksource\n"); | |
310 | goto out_noapbt; | |
311 | } | |
312 | if (!apbt_clockevent_register()) | |
313 | apb_timer_block_enabled = 1; | |
314 | else { | |
315 | pr_debug("APBT has failed to register clockevent\n"); | |
316 | goto out_noapbt; | |
317 | } | |
bb24c471 | 318 | #ifdef CONFIG_SMP |
c7bbf52a | 319 | /* kernel cmdline disable apb timer, so we will use lapic timers */ |
712b6aa8 | 320 | if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) { |
c7bbf52a PA |
321 | printk(KERN_INFO "apbt: disabled per cpu timer\n"); |
322 | return; | |
323 | } | |
324 | pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus()); | |
8f170fae | 325 | if (num_possible_cpus() <= sfi_mtimer_num) |
c7bbf52a | 326 | apbt_num_timers_used = num_possible_cpus(); |
8f170fae | 327 | else |
c7bbf52a | 328 | apbt_num_timers_used = 1; |
c7bbf52a PA |
329 | pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used); |
330 | ||
331 | /* here we set up per CPU timer data structure */ | |
c7bbf52a PA |
332 | for (i = 0; i < apbt_num_timers_used; i++) { |
333 | adev = &per_cpu(cpu_apbt_dev, i); | |
334 | adev->num = i; | |
335 | adev->cpu = i; | |
336 | p_mtmr = sfi_get_mtmr(i); | |
06c3df49 | 337 | if (p_mtmr) |
c7bbf52a | 338 | adev->irq = p_mtmr->irq; |
06c3df49 | 339 | else |
c7bbf52a | 340 | printk(KERN_ERR "Failed to get timer for cpu %d\n", i); |
06c3df49 | 341 | snprintf(adev->name, sizeof(adev->name) - 1, "apbt%d", i); |
c7bbf52a | 342 | } |
bb24c471 JP |
343 | #endif |
344 | ||
c7bbf52a | 345 | return; |
bb24c471 JP |
346 | |
347 | out_noapbt: | |
c7bbf52a PA |
348 | apbt_clear_mapping(); |
349 | apb_timer_block_enabled = 0; | |
350 | panic("failed to enable APB timer\n"); | |
bb24c471 JP |
351 | } |
352 | ||
bb24c471 | 353 | /* called before apb_timer_enable, use early map */ |
06c3df49 | 354 | unsigned long apbt_quick_calibrate(void) |
bb24c471 | 355 | { |
c7bbf52a PA |
356 | int i, scale; |
357 | u64 old, new; | |
358 | cycle_t t1, t2; | |
359 | unsigned long khz = 0; | |
360 | u32 loop, shift; | |
361 | ||
362 | apbt_set_mapping(); | |
06c3df49 | 363 | dw_apb_clocksource_start(clocksource_apbt); |
c7bbf52a PA |
364 | |
365 | /* check if the timer can count down, otherwise return */ | |
06c3df49 | 366 | old = dw_apb_clocksource_read(clocksource_apbt); |
c7bbf52a PA |
367 | i = 10000; |
368 | while (--i) { | |
06c3df49 | 369 | if (old != dw_apb_clocksource_read(clocksource_apbt)) |
c7bbf52a PA |
370 | break; |
371 | } | |
372 | if (!i) | |
373 | goto failed; | |
374 | ||
375 | /* count 16 ms */ | |
06c3df49 | 376 | loop = (apbt_freq / 1000) << 4; |
c7bbf52a PA |
377 | |
378 | /* restart the timer to ensure it won't get to 0 in the calibration */ | |
06c3df49 | 379 | dw_apb_clocksource_start(clocksource_apbt); |
c7bbf52a | 380 | |
06c3df49 | 381 | old = dw_apb_clocksource_read(clocksource_apbt); |
c7bbf52a PA |
382 | old += loop; |
383 | ||
4ea1636b | 384 | t1 = rdtsc(); |
c7bbf52a PA |
385 | |
386 | do { | |
06c3df49 | 387 | new = dw_apb_clocksource_read(clocksource_apbt); |
c7bbf52a PA |
388 | } while (new < old); |
389 | ||
4ea1636b | 390 | t2 = rdtsc(); |
c7bbf52a PA |
391 | |
392 | shift = 5; | |
393 | if (unlikely(loop >> shift == 0)) { | |
394 | printk(KERN_INFO | |
395 | "APBT TSC calibration failed, not enough resolution\n"); | |
396 | return 0; | |
397 | } | |
398 | scale = (int)div_u64((t2 - t1), loop >> shift); | |
06c3df49 | 399 | khz = (scale * (apbt_freq / 1000)) >> shift; |
c7bbf52a PA |
400 | printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz); |
401 | return khz; | |
bb24c471 | 402 | failed: |
c7bbf52a | 403 | return 0; |
bb24c471 | 404 | } |