[deliverable/linux.git] / arch / x86 / kernel / aperture_64.c

/*
 * Firmware replacement code.
 *
 * Work around broken BIOSes that don't set an aperture or only set the
 * aperture in the AGP bridge.
 * If all fails map the aperture over some low memory.  This is cheaper than
 * doing bounce buffering. The memory is lost. This is done at early boot
 * because only the bootmem allocator can allocate 32+MB.
 *
 * Copyright 2002 Andi Kleen, SuSE Labs.
 */
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/mmzone.h>
#include <linux/pci_ids.h>
#include <linux/pci.h>
#include <linux/bitops.h>
#include <linux/ioport.h>
#include <asm/e820.h>
#include <asm/io.h>
#include <asm/gart.h>
#include <asm/pci-direct.h>
#include <asm/dma.h>
#include <asm/k8.h>

int gart_iommu_aperture;
int gart_iommu_aperture_disabled __initdata = 0;
int gart_iommu_aperture_allowed __initdata = 0;

int fallback_aper_order __initdata = 1; /* 64MB */
int fallback_aper_force __initdata = 0;

int fix_aperture __initdata = 1;

static struct resource gart_resource = {
	.name	= "GART",
	.flags	= IORESOURCE_MEM,
};

static void __init insert_aperture_resource(u32 aper_base, u32 aper_size)
{
	gart_resource.start = aper_base;
	gart_resource.end = aper_base + aper_size - 1;
	insert_resource(&iomem_resource, &gart_resource);
}

/* This code runs before the PCI subsystem is initialized, so just
   access the northbridge directly. */

static u32 __init allocate_aperture(void)
{
	u32 aper_size;
	void *p;

	if (fallback_aper_order > 7)
		fallback_aper_order = 7;
	aper_size = (32 * 1024 * 1024) << fallback_aper_order;

	/*
	 * Aperture has to be naturally aligned. This means a 2GB aperture
	 * won't have much chance of finding a place in the lower 4GB of
	 * memory. Unfortunately we cannot move it up because that would
	 * make the IOMMU useless.
	 */
	p = __alloc_bootmem_nopanic(aper_size, aper_size, 0);
	if (!p || __pa(p)+aper_size > 0xffffffff) {
		printk(KERN_ERR
			"Cannot allocate aperture memory hole (%p,%uK)\n",
				p, aper_size>>10);
		if (p)
			free_bootmem(__pa(p), aper_size);
		return 0;
	}
	printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n",
			aper_size >> 10, __pa(p));
	insert_aperture_resource((u32)__pa(p), aper_size);

	return (u32)__pa(p);
}

static int __init aperture_valid(u64 aper_base, u32 aper_size)
{
	if (!aper_base)
		return 0;

	if (aper_size < 64*1024*1024) {
		printk(KERN_ERR "Aperture too small (%d MB)\n", aper_size>>20);
		return 0;
	}
	if (aper_base + aper_size > 0x100000000UL) {
		printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
		return 0;
	}
	if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
		printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
		return 0;
	}

	return 1;
}

/* Find a PCI capability */
static __u32 __init find_cap(int num, int slot, int func, int cap)
{
	int bytes;
	u8 pos;

	if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
						PCI_STATUS_CAP_LIST))
		return 0;

	pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
	for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
		u8 id;

		pos &= ~3;
		id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
		if (id == 0xff)
			break;
		if (id == cap)
			return pos;
		pos = read_pci_config_byte(num, slot, func,
						pos+PCI_CAP_LIST_NEXT);
	}
	return 0;
}

/* Read a standard AGPv3 bridge header */
static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
{
	u32 apsize;
	u32 apsizereg;
	int nbits;
	u32 aper_low, aper_hi;
	u64 aper;

	printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", num, slot, func);
	apsizereg = read_pci_config_16(num, slot, func, cap + 0x14);
	if (apsizereg == 0xffffffff) {
		printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
		return 0;
	}

	apsize = apsizereg & 0xfff;
	/* Some BIOS use weird encodings not in the AGPv3 table. */
	if (apsize & 0xff)
		apsize |= 0xf00;
	nbits = hweight16(apsize);
	*order = 7 - nbits;
	if ((int)*order < 0) /* < 32MB */
		*order = 0;

	aper_low = read_pci_config(num, slot, func, 0x10);
	aper_hi = read_pci_config(num, slot, func, 0x14);
	aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);

	printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
			aper, 32 << *order, apsizereg);

	if (!aperture_valid(aper, (32*1024*1024) << *order))
		return 0;
	return (u32)aper;
}

/*
 * Look for an AGP bridge. Windows only expects the aperture in the
 * AGP bridge and some BIOS forget to initialize the Northbridge too.
 * Work around this here.
 *
 * Do an PCI bus scan by hand because we're running before the PCI
 * subsystem.
 *
 * All K8 AGP bridges are AGPv3 compliant, so we can do this scan
 * generically. It's probably overkill to always scan all slots because
 * the AGP bridges should be always an own bus on the HT hierarchy,
 * but do it here for future safety.
 */
static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
{
	int num, slot, func;

	/* Poor man's PCI discovery */
	for (num = 0; num < 256; num++) {
		for (slot = 0; slot < 32; slot++) {
			for (func = 0; func < 8; func++) {
				u32 class, cap;
				u8 type;
				class = read_pci_config(num, slot, func,
							PCI_CLASS_REVISION);
				if (class == 0xffffffff)
					break;

				switch (class >> 16) {
				case PCI_CLASS_BRIDGE_HOST:
				case PCI_CLASS_BRIDGE_OTHER: /* needed? */
					/* AGP bridge? */
					cap = find_cap(num, slot, func,
							PCI_CAP_ID_AGP);
					if (!cap)
						break;
					*valid_agp = 1;
					return read_agp(num, slot, func, cap,
							order);
				}

				/* No multi-function device? */
				type = read_pci_config_byte(num, slot, func,
							       PCI_HEADER_TYPE);
				if (!(type & 0x80))
					break;
			}
		}
	}
	printk(KERN_INFO "No AGP bridge found\n");

	return 0;
}

static int gart_fix_e820 __initdata = 1;

static int __init parse_gart_mem(char *p)
{
	if (!p)
		return -EINVAL;

	if (!strncmp(p, "off", 3))
		gart_fix_e820 = 0;
	else if (!strncmp(p, "on", 2))
		gart_fix_e820 = 1;

	return 0;
}
early_param("gart_fix_e820", parse_gart_mem);

void __init early_gart_iommu_check(void)
{
	/*
	 * in case it is enabled before, esp for kexec/kdump,
	 * previous kernel already enable that. memset called
	 * by allocate_aperture/__alloc_bootmem_nopanic cause restart.
	 * or second kernel have different position for GART hole. and new
	 * kernel could use hole as RAM that is still used by GART set by
	 * first kernel
	 * or BIOS forget to put that in reserved.
	 * try to update e820 to make that region as reserved.
	 */
	int fix, num;
	u32 ctl;
	u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
	u64 aper_base = 0, last_aper_base = 0;
	int aper_enabled = 0, last_aper_enabled = 0;

	if (!early_pci_allowed())
		return;

	fix = 0;
	for (num = 24; num < 32; num++) {
		if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
			continue;

		ctl = read_pci_config(0, num, 3, 0x90);
		aper_enabled = ctl & 1;
		aper_order = (ctl >> 1) & 7;
		aper_size = (32 * 1024 * 1024) << aper_order;
		aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
		aper_base <<= 25;

		if ((last_aper_order && aper_order != last_aper_order) ||
		    (last_aper_base && aper_base != last_aper_base) ||
		    (last_aper_enabled && aper_enabled != last_aper_enabled)) {
			fix = 1;
			break;
		}
		last_aper_order = aper_order;
		last_aper_base = aper_base;
		last_aper_enabled = aper_enabled;
	}

	if (!fix && !aper_enabled)
		return;

	if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
		fix = 1;

	if (gart_fix_e820 && !fix && aper_enabled) {
		if (e820_any_mapped(aper_base, aper_base + aper_size,
				    E820_RAM)) {
			/* reserved it, so we can resuse it in second kernel */
			printk(KERN_INFO "update e820 for GART\n");
			add_memory_region(aper_base, aper_size, E820_RESERVED);
			update_e820();
		}
		return;
	}

	/* different nodes have different setting, disable them all at first*/
	for (num = 24; num < 32; num++) {
		if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
			continue;

		ctl = read_pci_config(0, num, 3, 0x90);
		ctl &= ~1;
		write_pci_config(0, num, 3, 0x90, ctl);
	}

}

void __init gart_iommu_hole_init(void)
{
	u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
	u64 aper_base, last_aper_base = 0;
	int fix, num, valid_agp = 0;

	if (gart_iommu_aperture_disabled || !fix_aperture ||
	    !early_pci_allowed())
		return;

	printk(KERN_INFO  "Checking aperture...\n");

	fix = 0;
	for (num = 24; num < 32; num++) {
		if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
			continue;

		iommu_detected = 1;
		gart_iommu_aperture = 1;

		aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7;
		aper_size = (32 * 1024 * 1024) << aper_order;
		aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
		aper_base <<= 25;

		printk(KERN_INFO "CPU %d: aperture @ %Lx size %u MB\n",
				num-24, aper_base, aper_size>>20);

		if (!aperture_valid(aper_base, aper_size)) {
			fix = 1;
			break;
		}

		if ((last_aper_order && aper_order != last_aper_order) ||
		    (last_aper_base && aper_base != last_aper_base)) {
			fix = 1;
			break;
		}
		last_aper_order = aper_order;
		last_aper_base = aper_base;
	}

	if (!fix && !fallback_aper_force) {
		if (last_aper_base) {
			unsigned long n = (32 * 1024 * 1024) << last_aper_order;

			insert_aperture_resource((u32)last_aper_base, n);
		}
		return;
	}

	if (!fallback_aper_force)
		aper_alloc = search_agp_bridge(&aper_order, &valid_agp);

	if (aper_alloc) {
		/* Got the aperture from the AGP bridge */
	} else if (swiotlb && !valid_agp) {
		/* Do nothing */
	} else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) ||
		   force_iommu ||
		   valid_agp ||
		   fallback_aper_force) {
		printk(KERN_ERR
			"Your BIOS doesn't leave a aperture memory hole\n");
		printk(KERN_ERR
			"Please enable the IOMMU option in the BIOS setup\n");
		printk(KERN_ERR
			"This costs you %d MB of RAM\n",
				32 << fallback_aper_order);

		aper_order = fallback_aper_order;
		aper_alloc = allocate_aperture();
		if (!aper_alloc) {
			/*
			 * Could disable AGP and IOMMU here, but it's
			 * probably not worth it. But the later users
			 * cannot deal with bad apertures and turning
			 * on the aperture over memory causes very
			 * strange problems, so it's better to panic
			 * early.
			 */
			panic("Not enough memory for aperture");
		}
	} else {
		return;
	}

	/* Fix up the north bridges */
	for (num = 24; num < 32; num++) {
		if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
			continue;

		/*
		 * Don't enable translation yet. That is done later.
		 * Assume this BIOS didn't initialise the GART so
		 * just overwrite all previous bits
		 */
		write_pci_config(0, num, 3, 0x90, aper_order<<1);
		write_pci_config(0, num, 3, 0x94, aper_alloc>>25);
	}
}
Commit	Line	Data
c140df97	1	/*
1da177e4	2	* Firmware replacement code.
c140df97	3	*
1da177e4	4	* Work around broken BIOSes that don't set an aperture or only set the
c140df97 IM	5	* aperture in the AGP bridge.
	6	* If all fails map the aperture over some low memory. This is cheaper than
	7	* doing bounce buffering. The memory is lost. This is done at early boot
	8	* because only the bootmem allocator can allocate 32+MB.
	9	*
1da177e4	10	* Copyright 2002 Andi Kleen, SuSE Labs.
1da177e4	11	*/
1da177e4 LT	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/init.h>
	15	#include <linux/bootmem.h>
	16	#include <linux/mmzone.h>
	17	#include <linux/pci_ids.h>
	18	#include <linux/pci.h>
	19	#include <linux/bitops.h>
56dd669a	20	#include <linux/ioport.h>
1da177e4 LT	21	#include <asm/e820.h>
1da177e4 LT	22	#include <asm/io.h>
395624fc	23	#include <asm/gart.h>
1da177e4	24	#include <asm/pci-direct.h>
ca8642f6	25	#include <asm/dma.h>
a32073bf	26	#include <asm/k8.h>
1da177e4	27
0440d4c0 JR	28	int gart_iommu_aperture;
	29	int gart_iommu_aperture_disabled __initdata = 0;
	30	int gart_iommu_aperture_allowed __initdata = 0;
1da177e4 LT	31
1da177e4 LT	32	int fallback_aper_order __initdata = 1; /* 64MB */
c140df97	33	int fallback_aper_force __initdata = 0;
1da177e4 LT	34
	35	int fix_aperture __initdata = 1;
	36
56dd669a AD	37	static struct resource gart_resource = {
	38	.name = "GART",
	39	.flags = IORESOURCE_MEM,
	40	};
	41
	42	static void __init insert_aperture_resource(u32 aper_base, u32 aper_size)
	43	{
	44	gart_resource.start = aper_base;
	45	gart_resource.end = aper_base + aper_size - 1;
	46	insert_resource(&iomem_resource, &gart_resource);
	47	}
	48
42442ed5 AM	49	/* This code runs before the PCI subsystem is initialized, so just
42442ed5 AM	50	access the northbridge directly. */
1da177e4	51
c140df97	52	static u32 __init allocate_aperture(void)
1da177e4	53	{
1da177e4	54	u32 aper_size;
c140df97	55	void *p;
1da177e4	56
c140df97 IM	57	if (fallback_aper_order > 7)
	58	fallback_aper_order = 7;
	59	aper_size = (32 * 1024 * 1024) << fallback_aper_order;
1da177e4	60
c140df97 IM	61	/*
	62	* Aperture has to be naturally aligned. This means a 2GB aperture
	63	* won't have much chance of finding a place in the lower 4GB of
	64	* memory. Unfortunately we cannot move it up because that would
	65	* make the IOMMU useless.
1da177e4	66	*/
82d1bb72	67	p = __alloc_bootmem_nopanic(aper_size, aper_size, 0);
1da177e4	68	if (!p \|\| __pa(p)+aper_size > 0xffffffff) {
31183ba8 IM	69	printk(KERN_ERR
	70	"Cannot allocate aperture memory hole (%p,%uK)\n",
	71	p, aper_size>>10);
1da177e4	72	if (p)
82d1bb72	73	free_bootmem(__pa(p), aper_size);
1da177e4 LT	74	return 0;
1da177e4 LT	75	}
31183ba8 IM	76	printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n",
31183ba8 IM	77	aper_size >> 10, __pa(p));
56dd669a	78	insert_aperture_resource((u32)__pa(p), aper_size);
c140df97 IM	79
c140df97 IM	80	return (u32)__pa(p);
1da177e4 LT	81	}
1da177e4 LT	82
a32073bf	83	static int __init aperture_valid(u64 aper_base, u32 aper_size)
c140df97 IM	84	{
c140df97 IM	85	if (!aper_base)
1da177e4	86	return 0;
31183ba8	87
c140df97	88	if (aper_size < 6410241024) {
31183ba8	89	printk(KERN_ERR "Aperture too small (%d MB)\n", aper_size>>20);
1da177e4 LT	90	return 0;
1da177e4 LT	91	}
547c5355	92	if (aper_base + aper_size > 0x100000000UL) {
31183ba8	93	printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
c140df97	94	return 0;
1da177e4	95	}
eee5a9fa	96	if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
31183ba8	97	printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
c140df97 IM	98	return 0;
c140df97 IM	99	}
31183ba8	100
1da177e4	101	return 1;
c140df97	102	}
1da177e4	103
42442ed5	104	/* Find a PCI capability */
c140df97 IM	105	static __u32 __init find_cap(int num, int slot, int func, int cap)
c140df97 IM	106	{
1da177e4	107	int bytes;
c140df97 IM	108	u8 pos;
	109
	110	if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
	111	PCI_STATUS_CAP_LIST))
1da177e4	112	return 0;
c140df97 IM	113
	114	pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
	115	for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
1da177e4	116	u8 id;
c140df97 IM	117
	118	pos &= ~3;
	119	id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
1da177e4 LT	120	if (id == 0xff)
1da177e4 LT	121	break;
c140df97 IM	122	if (id == cap)
	123	return pos;
	124	pos = read_pci_config_byte(num, slot, func,
	125	pos+PCI_CAP_LIST_NEXT);
	126	}
1da177e4	127	return 0;
c140df97	128	}
1da177e4 LT	129
	130	/* Read a standard AGPv3 bridge header */
	131	static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
c140df97	132	{
1da177e4 LT	133	u32 apsize;
	134	u32 apsizereg;
	135	int nbits;
	136	u32 aper_low, aper_hi;
	137	u64 aper;
	138
31183ba8	139	printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", num, slot, func);
c140df97	140	apsizereg = read_pci_config_16(num, slot, func, cap + 0x14);
1da177e4	141	if (apsizereg == 0xffffffff) {
31183ba8	142	printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
1da177e4 LT	143	return 0;
	144	}
	145
	146	apsize = apsizereg & 0xfff;
	147	/* Some BIOS use weird encodings not in the AGPv3 table. */
c140df97 IM	148	if (apsize & 0xff)
c140df97 IM	149	apsize \|= 0xf00;
1da177e4 LT	150	nbits = hweight16(apsize);
	151	*order = 7 - nbits;
	152	if ((int)order < 0) / < 32MB */
	153	*order = 0;
c140df97 IM	154
	155	aper_low = read_pci_config(num, slot, func, 0x10);
	156	aper_hi = read_pci_config(num, slot, func, 0x14);
1da177e4 LT	157	aper = (aper_low & ~((1<<22)-1)) \| ((u64)aper_hi << 32);
1da177e4 LT	158
31183ba8 IM	159	printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
31183ba8 IM	160	aper, 32 << *order, apsizereg);
1da177e4	161
a32073bf	162	if (!aperture_valid(aper, (3210241024) << *order))
c140df97 IM	163	return 0;
	164	return (u32)aper;
	165	}
1da177e4	166
c140df97 IM	167	/*
	168	* Look for an AGP bridge. Windows only expects the aperture in the
	169	* AGP bridge and some BIOS forget to initialize the Northbridge too.
	170	* Work around this here.
	171	*
	172	* Do an PCI bus scan by hand because we're running before the PCI
	173	* subsystem.
	174	*
	175	* All K8 AGP bridges are AGPv3 compliant, so we can do this scan
	176	* generically. It's probably overkill to always scan all slots because
	177	* the AGP bridges should be always an own bus on the HT hierarchy,
	178	* but do it here for future safety.
	179	*/
1da177e4 LT	180	static __u32 __init search_agp_bridge(u32 order, int valid_agp)
	181	{
	182	int num, slot, func;
	183
	184	/* Poor man's PCI discovery */
c140df97 IM	185	for (num = 0; num < 256; num++) {
	186	for (slot = 0; slot < 32; slot++) {
	187	for (func = 0; func < 8; func++) {
1da177e4 LT	188	u32 class, cap;
1da177e4 LT	189	u8 type;
c140df97	190	class = read_pci_config(num, slot, func,
1da177e4 LT	191	PCI_CLASS_REVISION);
1da177e4 LT	192	if (class == 0xffffffff)
c140df97 IM	193	break;
	194
	195	switch (class >> 16) {
1da177e4 LT	196	case PCI_CLASS_BRIDGE_HOST:
	197	case PCI_CLASS_BRIDGE_OTHER: /* needed? */
	198	/* AGP bridge? */
c140df97 IM	199	cap = find_cap(num, slot, func,
c140df97 IM	200	PCI_CAP_ID_AGP);
1da177e4 LT	201	if (!cap)
1da177e4 LT	202	break;
c140df97 IM	203	*valid_agp = 1;
	204	return read_agp(num, slot, func, cap,
	205	order);
	206	}
	207
1da177e4	208	/* No multi-function device? */
c140df97	209	type = read_pci_config_byte(num, slot, func,
1da177e4 LT	210	PCI_HEADER_TYPE);
	211	if (!(type & 0x80))
	212	break;
c140df97 IM	213	}
c140df97 IM	214	}
1da177e4	215	}
31183ba8	216	printk(KERN_INFO "No AGP bridge found\n");
c140df97	217
1da177e4 LT	218	return 0;
	219	}
	220
aaf23042 YL	221	static int gart_fix_e820 __initdata = 1;
	222
	223	static int __init parse_gart_mem(char *p)
	224	{
	225	if (!p)
	226	return -EINVAL;
	227
	228	if (!strncmp(p, "off", 3))
	229	gart_fix_e820 = 0;
	230	else if (!strncmp(p, "on", 2))
	231	gart_fix_e820 = 1;
	232
	233	return 0;
	234	}
	235	early_param("gart_fix_e820", parse_gart_mem);
	236
	237	void __init early_gart_iommu_check(void)
	238	{
	239	/*
	240	* in case it is enabled before, esp for kexec/kdump,
	241	* previous kernel already enable that. memset called
	242	* by allocate_aperture/__alloc_bootmem_nopanic cause restart.
	243	* or second kernel have different position for GART hole. and new
	244	* kernel could use hole as RAM that is still used by GART set by
	245	* first kernel
	246	* or BIOS forget to put that in reserved.
	247	* try to update e820 to make that region as reserved.
	248	*/
	249	int fix, num;
	250	u32 ctl;
	251	u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
	252	u64 aper_base = 0, last_aper_base = 0;
	253	int aper_enabled = 0, last_aper_enabled = 0;
	254
	255	if (!early_pci_allowed())
	256	return;
	257
	258	fix = 0;
	259	for (num = 24; num < 32; num++) {
	260	if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
	261	continue;
	262
	263	ctl = read_pci_config(0, num, 3, 0x90);
	264	aper_enabled = ctl & 1;
	265	aper_order = (ctl >> 1) & 7;
	266	aper_size = (32 * 1024 * 1024) << aper_order;
	267	aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
	268	aper_base <<= 25;
	269
	270	if ((last_aper_order && aper_order != last_aper_order) \|\|
	271	(last_aper_base && aper_base != last_aper_base) \|\|
	272	(last_aper_enabled && aper_enabled != last_aper_enabled)) {
	273	fix = 1;
	274	break;
	275	}
	276	last_aper_order = aper_order;
	277	last_aper_base = aper_base;
	278	last_aper_enabled = aper_enabled;
	279	}
	280
	281	if (!fix && !aper_enabled)
	282	return;
	283
	284	if (!aper_base \|\| !aper_size \|\| aper_base + aper_size > 0x100000000UL)
285	fix = 1;
286
287	if (gart_fix_e820 && !fix && aper_enabled) {
288	if (e820_any_mapped(aper_base, aper_base + aper_size,
289	E820_RAM)) {
290	/* reserved it, so we can resuse it in second kernel */
291	printk(KERN_INFO "update e820 for GART\n");
292	add_memory_region(aper_base, aper_size, E820_RESERVED);
293	update_e820();
294	}
295	return;
296	}
297
298	/* different nodes have different setting, disable them all at first*/
299	for (num = 24; num < 32; num++) {
300	if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
301	continue;
302
303	ctl = read_pci_config(0, num, 3, 0x90);
304	ctl &= ~1;
305	write_pci_config(0, num, 3, 0x90, ctl);
306	}
307
308	}
309
0440d4c0	310	void __init gart_iommu_hole_init(void)
c140df97	311	{
50895c5d	312	u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
1da177e4	313	u64 aper_base, last_aper_base = 0;
c140df97	314	int fix, num, valid_agp = 0;
1da177e4	315
0440d4c0 JR	316	if (gart_iommu_aperture_disabled \|\| !fix_aperture \|\|
0440d4c0 JR	317	!early_pci_allowed())
1da177e4 LT	318	return;
1da177e4 LT	319
753811dc	320	printk(KERN_INFO "Checking aperture...\n");
1da177e4 LT	321
1da177e4 LT	322	fix = 0;
c140df97	323	for (num = 24; num < 32; num++) {
a32073bf AK	324	if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
a32073bf AK	325	continue;
1da177e4	326
8d4f6b93	327	iommu_detected = 1;
0440d4c0	328	gart_iommu_aperture = 1;
1da177e4	329
c140df97 IM	330	aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7;
c140df97 IM	331	aper_size = (32 * 1024 * 1024) << aper_order;
1da177e4	332	aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
c140df97	333	aper_base <<= 25;
1da177e4	334
31183ba8 IM	335	printk(KERN_INFO "CPU %d: aperture @ %Lx size %u MB\n",
31183ba8 IM	336	num-24, aper_base, aper_size>>20);
c140df97	337
a32073bf	338	if (!aperture_valid(aper_base, aper_size)) {
c140df97 IM	339	fix = 1;
c140df97 IM	340	break;
1da177e4 LT	341	}
	342
	343	if ((last_aper_order && aper_order != last_aper_order) \|\|
	344	(last_aper_base && aper_base != last_aper_base)) {
	345	fix = 1;
	346	break;
	347	}
	348	last_aper_order = aper_order;
	349	last_aper_base = aper_base;
c140df97	350	}
1da177e4	351
56dd669a AD	352	if (!fix && !fallback_aper_force) {
	353	if (last_aper_base) {
	354	unsigned long n = (32 * 1024 * 1024) << last_aper_order;
c140df97	355
56dd669a AD	356	insert_aperture_resource((u32)last_aper_base, n);
56dd669a AD	357	}
c140df97	358	return;
56dd669a	359	}
1da177e4 LT	360
1da177e4 LT	361	if (!fallback_aper_force)
c140df97 IM	362	aper_alloc = search_agp_bridge(&aper_order, &valid_agp);
	363
	364	if (aper_alloc) {
1da177e4	365	/* Got the aperture from the AGP bridge */
63f02fd7 AK	366	} else if (swiotlb && !valid_agp) {
63f02fd7 AK	367	/* Do nothing */
60b08c67	368	} else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) \|\|
1da177e4 LT	369	force_iommu \|\|
1da177e4 LT	370	valid_agp \|\|
c140df97	371	fallback_aper_force) {
31183ba8 IM	372	printk(KERN_ERR
	373	"Your BIOS doesn't leave a aperture memory hole\n");
	374	printk(KERN_ERR
	375	"Please enable the IOMMU option in the BIOS setup\n");
	376	printk(KERN_ERR
	377	"This costs you %d MB of RAM\n",
	378	32 << fallback_aper_order);
1da177e4 LT	379
	380	aper_order = fallback_aper_order;
	381	aper_alloc = allocate_aperture();
c140df97 IM	382	if (!aper_alloc) {
	383	/*
	384	* Could disable AGP and IOMMU here, but it's
	385	* probably not worth it. But the later users
	386	* cannot deal with bad apertures and turning
	387	* on the aperture over memory causes very
	388	* strange problems, so it's better to panic
	389	* early.
	390	*/
1da177e4 LT	391	panic("Not enough memory for aperture");
1da177e4 LT	392	}
c140df97 IM	393	} else {
	394	return;
	395	}
1da177e4 LT	396
1da177e4 LT	397	/* Fix up the north bridges */
c140df97	398	for (num = 24; num < 32; num++) {
a32073bf	399	if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
c140df97 IM	400	continue;
	401
	402	/*
	403	* Don't enable translation yet. That is done later.
	404	* Assume this BIOS didn't initialise the GART so
	405	* just overwrite all previous bits
	406	*/
	407	write_pci_config(0, num, 3, 0x90, aper_order<<1);
	408	write_pci_config(0, num, 3, 0x94, aper_alloc>>25);
	409	}
	410	}