Commit | Line | Data |
---|---|---|
c140df97 | 1 | /* |
1da177e4 | 2 | * Firmware replacement code. |
c140df97 | 3 | * |
1da177e4 | 4 | * Work around broken BIOSes that don't set an aperture or only set the |
c140df97 IM |
5 | * aperture in the AGP bridge. |
6 | * If all fails map the aperture over some low memory. This is cheaper than | |
7 | * doing bounce buffering. The memory is lost. This is done at early boot | |
8 | * because only the bootmem allocator can allocate 32+MB. | |
9 | * | |
1da177e4 | 10 | * Copyright 2002 Andi Kleen, SuSE Labs. |
1da177e4 | 11 | */ |
1da177e4 LT |
12 | #include <linux/kernel.h> |
13 | #include <linux/types.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/bootmem.h> | |
16 | #include <linux/mmzone.h> | |
17 | #include <linux/pci_ids.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/bitops.h> | |
56dd669a | 20 | #include <linux/ioport.h> |
2050d45d | 21 | #include <linux/suspend.h> |
1da177e4 LT |
22 | #include <asm/e820.h> |
23 | #include <asm/io.h> | |
395624fc | 24 | #include <asm/gart.h> |
1da177e4 | 25 | #include <asm/pci-direct.h> |
ca8642f6 | 26 | #include <asm/dma.h> |
a32073bf | 27 | #include <asm/k8.h> |
1da177e4 | 28 | |
0440d4c0 | 29 | int gart_iommu_aperture; |
7de6a4cd PM |
30 | int gart_iommu_aperture_disabled __initdata; |
31 | int gart_iommu_aperture_allowed __initdata; | |
1da177e4 LT |
32 | |
33 | int fallback_aper_order __initdata = 1; /* 64MB */ | |
7de6a4cd | 34 | int fallback_aper_force __initdata; |
1da177e4 LT |
35 | |
36 | int fix_aperture __initdata = 1; | |
37 | ||
55c0d721 YL |
38 | struct bus_dev_range { |
39 | int bus; | |
40 | int dev_base; | |
41 | int dev_limit; | |
42 | }; | |
43 | ||
44 | static struct bus_dev_range bus_dev_ranges[] __initdata = { | |
45 | { 0x00, 0x18, 0x20}, | |
46 | { 0xff, 0x00, 0x20}, | |
47 | { 0xfe, 0x00, 0x20} | |
48 | }; | |
49 | ||
56dd669a AD |
50 | static struct resource gart_resource = { |
51 | .name = "GART", | |
52 | .flags = IORESOURCE_MEM, | |
53 | }; | |
54 | ||
55 | static void __init insert_aperture_resource(u32 aper_base, u32 aper_size) | |
56 | { | |
57 | gart_resource.start = aper_base; | |
58 | gart_resource.end = aper_base + aper_size - 1; | |
59 | insert_resource(&iomem_resource, &gart_resource); | |
60 | } | |
61 | ||
42442ed5 AM |
62 | /* This code runs before the PCI subsystem is initialized, so just |
63 | access the northbridge directly. */ | |
1da177e4 | 64 | |
c140df97 | 65 | static u32 __init allocate_aperture(void) |
1da177e4 | 66 | { |
1da177e4 | 67 | u32 aper_size; |
c140df97 | 68 | void *p; |
1da177e4 | 69 | |
7677b2ef YL |
70 | /* aper_size should <= 1G */ |
71 | if (fallback_aper_order > 5) | |
72 | fallback_aper_order = 5; | |
c140df97 | 73 | aper_size = (32 * 1024 * 1024) << fallback_aper_order; |
1da177e4 | 74 | |
c140df97 IM |
75 | /* |
76 | * Aperture has to be naturally aligned. This means a 2GB aperture | |
77 | * won't have much chance of finding a place in the lower 4GB of | |
78 | * memory. Unfortunately we cannot move it up because that would | |
79 | * make the IOMMU useless. | |
1da177e4 | 80 | */ |
7677b2ef YL |
81 | /* |
82 | * using 512M as goal, in case kexec will load kernel_big | |
83 | * that will do the on position decompress, and could overlap with | |
84 | * that positon with gart that is used. | |
85 | * sequende: | |
86 | * kernel_small | |
87 | * ==> kexec (with kdump trigger path or previous doesn't shutdown gart) | |
88 | * ==> kernel_small(gart area become e820_reserved) | |
89 | * ==> kexec (with kdump trigger path or previous doesn't shutdown gart) | |
90 | * ==> kerne_big (uncompressed size will be big than 64M or 128M) | |
91 | * so don't use 512M below as gart iommu, leave the space for kernel | |
92 | * code for safe | |
93 | */ | |
94 | p = __alloc_bootmem_nopanic(aper_size, aper_size, 512ULL<<20); | |
1da177e4 | 95 | if (!p || __pa(p)+aper_size > 0xffffffff) { |
31183ba8 IM |
96 | printk(KERN_ERR |
97 | "Cannot allocate aperture memory hole (%p,%uK)\n", | |
98 | p, aper_size>>10); | |
1da177e4 | 99 | if (p) |
82d1bb72 | 100 | free_bootmem(__pa(p), aper_size); |
1da177e4 LT |
101 | return 0; |
102 | } | |
31183ba8 IM |
103 | printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n", |
104 | aper_size >> 10, __pa(p)); | |
56dd669a | 105 | insert_aperture_resource((u32)__pa(p), aper_size); |
2050d45d PM |
106 | register_nosave_region((u32)__pa(p) >> PAGE_SHIFT, |
107 | (u32)__pa(p+aper_size) >> PAGE_SHIFT); | |
c140df97 IM |
108 | |
109 | return (u32)__pa(p); | |
1da177e4 LT |
110 | } |
111 | ||
1da177e4 | 112 | |
42442ed5 | 113 | /* Find a PCI capability */ |
55c0d721 | 114 | static __u32 __init find_cap(int bus, int slot, int func, int cap) |
c140df97 | 115 | { |
1da177e4 | 116 | int bytes; |
c140df97 IM |
117 | u8 pos; |
118 | ||
55c0d721 | 119 | if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) & |
c140df97 | 120 | PCI_STATUS_CAP_LIST)) |
1da177e4 | 121 | return 0; |
c140df97 | 122 | |
55c0d721 | 123 | pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST); |
c140df97 | 124 | for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) { |
1da177e4 | 125 | u8 id; |
c140df97 IM |
126 | |
127 | pos &= ~3; | |
55c0d721 | 128 | id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID); |
1da177e4 LT |
129 | if (id == 0xff) |
130 | break; | |
c140df97 IM |
131 | if (id == cap) |
132 | return pos; | |
55c0d721 | 133 | pos = read_pci_config_byte(bus, slot, func, |
c140df97 IM |
134 | pos+PCI_CAP_LIST_NEXT); |
135 | } | |
1da177e4 | 136 | return 0; |
c140df97 | 137 | } |
1da177e4 LT |
138 | |
139 | /* Read a standard AGPv3 bridge header */ | |
55c0d721 | 140 | static __u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order) |
c140df97 | 141 | { |
1da177e4 LT |
142 | u32 apsize; |
143 | u32 apsizereg; | |
144 | int nbits; | |
145 | u32 aper_low, aper_hi; | |
146 | u64 aper; | |
1edc1ab3 | 147 | u32 old_order; |
1da177e4 | 148 | |
55c0d721 YL |
149 | printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", bus, slot, func); |
150 | apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14); | |
1da177e4 | 151 | if (apsizereg == 0xffffffff) { |
31183ba8 | 152 | printk(KERN_ERR "APSIZE in AGP bridge unreadable\n"); |
1da177e4 LT |
153 | return 0; |
154 | } | |
155 | ||
1edc1ab3 YL |
156 | /* old_order could be the value from NB gart setting */ |
157 | old_order = *order; | |
158 | ||
1da177e4 LT |
159 | apsize = apsizereg & 0xfff; |
160 | /* Some BIOS use weird encodings not in the AGPv3 table. */ | |
c140df97 IM |
161 | if (apsize & 0xff) |
162 | apsize |= 0xf00; | |
1da177e4 LT |
163 | nbits = hweight16(apsize); |
164 | *order = 7 - nbits; | |
165 | if ((int)*order < 0) /* < 32MB */ | |
166 | *order = 0; | |
c140df97 | 167 | |
55c0d721 YL |
168 | aper_low = read_pci_config(bus, slot, func, 0x10); |
169 | aper_hi = read_pci_config(bus, slot, func, 0x14); | |
1da177e4 LT |
170 | aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); |
171 | ||
1edc1ab3 YL |
172 | /* |
173 | * On some sick chips, APSIZE is 0. It means it wants 4G | |
174 | * so let double check that order, and lets trust AMD NB settings: | |
175 | */ | |
8c9fd91a YL |
176 | printk(KERN_INFO "Aperture from AGP @ %Lx old size %u MB\n", |
177 | aper, 32 << old_order); | |
178 | if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) { | |
1edc1ab3 YL |
179 | printk(KERN_INFO "Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n", |
180 | 32 << *order, apsizereg); | |
181 | *order = old_order; | |
182 | } | |
183 | ||
31183ba8 IM |
184 | printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n", |
185 | aper, 32 << *order, apsizereg); | |
1da177e4 | 186 | |
8c9fd91a | 187 | if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20)) |
c140df97 IM |
188 | return 0; |
189 | return (u32)aper; | |
190 | } | |
1da177e4 | 191 | |
c140df97 IM |
192 | /* |
193 | * Look for an AGP bridge. Windows only expects the aperture in the | |
194 | * AGP bridge and some BIOS forget to initialize the Northbridge too. | |
195 | * Work around this here. | |
196 | * | |
197 | * Do an PCI bus scan by hand because we're running before the PCI | |
198 | * subsystem. | |
199 | * | |
200 | * All K8 AGP bridges are AGPv3 compliant, so we can do this scan | |
201 | * generically. It's probably overkill to always scan all slots because | |
202 | * the AGP bridges should be always an own bus on the HT hierarchy, | |
203 | * but do it here for future safety. | |
204 | */ | |
1da177e4 LT |
205 | static __u32 __init search_agp_bridge(u32 *order, int *valid_agp) |
206 | { | |
55c0d721 | 207 | int bus, slot, func; |
1da177e4 LT |
208 | |
209 | /* Poor man's PCI discovery */ | |
55c0d721 | 210 | for (bus = 0; bus < 256; bus++) { |
c140df97 IM |
211 | for (slot = 0; slot < 32; slot++) { |
212 | for (func = 0; func < 8; func++) { | |
1da177e4 LT |
213 | u32 class, cap; |
214 | u8 type; | |
55c0d721 | 215 | class = read_pci_config(bus, slot, func, |
1da177e4 LT |
216 | PCI_CLASS_REVISION); |
217 | if (class == 0xffffffff) | |
c140df97 IM |
218 | break; |
219 | ||
220 | switch (class >> 16) { | |
1da177e4 LT |
221 | case PCI_CLASS_BRIDGE_HOST: |
222 | case PCI_CLASS_BRIDGE_OTHER: /* needed? */ | |
223 | /* AGP bridge? */ | |
55c0d721 | 224 | cap = find_cap(bus, slot, func, |
c140df97 | 225 | PCI_CAP_ID_AGP); |
1da177e4 LT |
226 | if (!cap) |
227 | break; | |
c140df97 | 228 | *valid_agp = 1; |
55c0d721 | 229 | return read_agp(bus, slot, func, cap, |
c140df97 IM |
230 | order); |
231 | } | |
232 | ||
1da177e4 | 233 | /* No multi-function device? */ |
55c0d721 | 234 | type = read_pci_config_byte(bus, slot, func, |
1da177e4 LT |
235 | PCI_HEADER_TYPE); |
236 | if (!(type & 0x80)) | |
237 | break; | |
c140df97 IM |
238 | } |
239 | } | |
1da177e4 | 240 | } |
31183ba8 | 241 | printk(KERN_INFO "No AGP bridge found\n"); |
c140df97 | 242 | |
1da177e4 LT |
243 | return 0; |
244 | } | |
245 | ||
aaf23042 YL |
246 | static int gart_fix_e820 __initdata = 1; |
247 | ||
248 | static int __init parse_gart_mem(char *p) | |
249 | { | |
250 | if (!p) | |
251 | return -EINVAL; | |
252 | ||
253 | if (!strncmp(p, "off", 3)) | |
254 | gart_fix_e820 = 0; | |
255 | else if (!strncmp(p, "on", 2)) | |
256 | gart_fix_e820 = 1; | |
257 | ||
258 | return 0; | |
259 | } | |
260 | early_param("gart_fix_e820", parse_gart_mem); | |
261 | ||
262 | void __init early_gart_iommu_check(void) | |
263 | { | |
264 | /* | |
265 | * in case it is enabled before, esp for kexec/kdump, | |
266 | * previous kernel already enable that. memset called | |
267 | * by allocate_aperture/__alloc_bootmem_nopanic cause restart. | |
268 | * or second kernel have different position for GART hole. and new | |
269 | * kernel could use hole as RAM that is still used by GART set by | |
270 | * first kernel | |
271 | * or BIOS forget to put that in reserved. | |
272 | * try to update e820 to make that region as reserved. | |
273 | */ | |
55c0d721 | 274 | int fix, slot; |
aaf23042 YL |
275 | u32 ctl; |
276 | u32 aper_size = 0, aper_order = 0, last_aper_order = 0; | |
277 | u64 aper_base = 0, last_aper_base = 0; | |
278 | int aper_enabled = 0, last_aper_enabled = 0; | |
55c0d721 | 279 | int i; |
aaf23042 YL |
280 | |
281 | if (!early_pci_allowed()) | |
282 | return; | |
283 | ||
284 | fix = 0; | |
55c0d721 YL |
285 | for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { |
286 | int bus; | |
287 | int dev_base, dev_limit; | |
288 | ||
289 | bus = bus_dev_ranges[i].bus; | |
290 | dev_base = bus_dev_ranges[i].dev_base; | |
291 | dev_limit = bus_dev_ranges[i].dev_limit; | |
292 | ||
293 | for (slot = dev_base; slot < dev_limit; slot++) { | |
294 | if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00))) | |
295 | continue; | |
296 | ||
297 | ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); | |
298 | aper_enabled = ctl & AMD64_GARTEN; | |
299 | aper_order = (ctl >> 1) & 7; | |
300 | aper_size = (32 * 1024 * 1024) << aper_order; | |
301 | aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; | |
302 | aper_base <<= 25; | |
303 | ||
304 | if ((last_aper_order && aper_order != last_aper_order) || | |
305 | (last_aper_base && aper_base != last_aper_base) || | |
306 | (last_aper_enabled && aper_enabled != last_aper_enabled)) { | |
307 | fix = 1; | |
308 | goto out; | |
309 | } | |
310 | last_aper_order = aper_order; | |
311 | last_aper_base = aper_base; | |
312 | last_aper_enabled = aper_enabled; | |
aaf23042 | 313 | } |
aaf23042 YL |
314 | } |
315 | ||
55c0d721 | 316 | out: |
aaf23042 YL |
317 | if (!fix && !aper_enabled) |
318 | return; | |
319 | ||
320 | if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL) | |
321 | fix = 1; | |
322 | ||
323 | if (gart_fix_e820 && !fix && aper_enabled) { | |
8c9fd91a YL |
324 | if (!e820_all_mapped(aper_base, aper_base + aper_size, |
325 | E820_RESERVED)) { | |
0abbc78a | 326 | /* reserve it, so we can reuse it in second kernel */ |
aaf23042 YL |
327 | printk(KERN_INFO "update e820 for GART\n"); |
328 | add_memory_region(aper_base, aper_size, E820_RESERVED); | |
329 | update_e820(); | |
330 | } | |
331 | return; | |
332 | } | |
333 | ||
334 | /* different nodes have different setting, disable them all at first*/ | |
55c0d721 YL |
335 | for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { |
336 | int bus; | |
337 | int dev_base, dev_limit; | |
338 | ||
339 | bus = bus_dev_ranges[i].bus; | |
340 | dev_base = bus_dev_ranges[i].dev_base; | |
341 | dev_limit = bus_dev_ranges[i].dev_limit; | |
aaf23042 | 342 | |
55c0d721 YL |
343 | for (slot = dev_base; slot < dev_limit; slot++) { |
344 | if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00))) | |
345 | continue; | |
346 | ||
347 | ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); | |
348 | ctl &= ~AMD64_GARTEN; | |
349 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); | |
350 | } | |
aaf23042 YL |
351 | } |
352 | ||
353 | } | |
354 | ||
8c9fd91a YL |
355 | static int __initdata printed_gart_size_msg; |
356 | ||
0440d4c0 | 357 | void __init gart_iommu_hole_init(void) |
c140df97 | 358 | { |
8c9fd91a | 359 | u32 agp_aper_base = 0, agp_aper_order = 0; |
50895c5d | 360 | u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0; |
1da177e4 | 361 | u64 aper_base, last_aper_base = 0; |
55c0d721 YL |
362 | int fix, slot, valid_agp = 0; |
363 | int i, node; | |
1da177e4 | 364 | |
0440d4c0 JR |
365 | if (gart_iommu_aperture_disabled || !fix_aperture || |
366 | !early_pci_allowed()) | |
1da177e4 LT |
367 | return; |
368 | ||
753811dc | 369 | printk(KERN_INFO "Checking aperture...\n"); |
1da177e4 | 370 | |
8c9fd91a YL |
371 | if (!fallback_aper_force) |
372 | agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp); | |
373 | ||
1da177e4 | 374 | fix = 0; |
47db4c3e | 375 | node = 0; |
55c0d721 YL |
376 | for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { |
377 | int bus; | |
378 | int dev_base, dev_limit; | |
379 | ||
380 | bus = bus_dev_ranges[i].bus; | |
381 | dev_base = bus_dev_ranges[i].dev_base; | |
382 | dev_limit = bus_dev_ranges[i].dev_limit; | |
383 | ||
384 | for (slot = dev_base; slot < dev_limit; slot++) { | |
385 | if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00))) | |
386 | continue; | |
387 | ||
388 | iommu_detected = 1; | |
389 | gart_iommu_aperture = 1; | |
390 | ||
391 | aper_order = (read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL) >> 1) & 7; | |
392 | aper_size = (32 * 1024 * 1024) << aper_order; | |
393 | aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; | |
394 | aper_base <<= 25; | |
395 | ||
396 | printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n", | |
397 | node, aper_base, aper_size >> 20); | |
398 | node++; | |
399 | ||
400 | if (!aperture_valid(aper_base, aper_size, 64<<20)) { | |
401 | if (valid_agp && agp_aper_base && | |
402 | agp_aper_base == aper_base && | |
403 | agp_aper_order == aper_order) { | |
404 | /* the same between two setting from NB and agp */ | |
405 | if (!no_iommu && end_pfn > MAX_DMA32_PFN && !printed_gart_size_msg) { | |
406 | printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n"); | |
407 | printk(KERN_ERR "please increase GART size in your BIOS setup\n"); | |
408 | printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n"); | |
409 | printed_gart_size_msg = 1; | |
410 | } | |
411 | } else { | |
412 | fix = 1; | |
413 | goto out; | |
8c9fd91a | 414 | } |
8c9fd91a | 415 | } |
1da177e4 | 416 | |
55c0d721 YL |
417 | if ((last_aper_order && aper_order != last_aper_order) || |
418 | (last_aper_base && aper_base != last_aper_base)) { | |
419 | fix = 1; | |
420 | goto out; | |
421 | } | |
422 | last_aper_order = aper_order; | |
423 | last_aper_base = aper_base; | |
1da177e4 | 424 | } |
c140df97 | 425 | } |
1da177e4 | 426 | |
55c0d721 | 427 | out: |
56dd669a AD |
428 | if (!fix && !fallback_aper_force) { |
429 | if (last_aper_base) { | |
430 | unsigned long n = (32 * 1024 * 1024) << last_aper_order; | |
c140df97 | 431 | |
56dd669a AD |
432 | insert_aperture_resource((u32)last_aper_base, n); |
433 | } | |
c140df97 | 434 | return; |
56dd669a | 435 | } |
1da177e4 | 436 | |
8c9fd91a YL |
437 | if (!fallback_aper_force) { |
438 | aper_alloc = agp_aper_base; | |
439 | aper_order = agp_aper_order; | |
440 | } | |
c140df97 IM |
441 | |
442 | if (aper_alloc) { | |
1da177e4 | 443 | /* Got the aperture from the AGP bridge */ |
63f02fd7 AK |
444 | } else if (swiotlb && !valid_agp) { |
445 | /* Do nothing */ | |
60b08c67 | 446 | } else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) || |
1da177e4 LT |
447 | force_iommu || |
448 | valid_agp || | |
c140df97 | 449 | fallback_aper_force) { |
31183ba8 IM |
450 | printk(KERN_ERR |
451 | "Your BIOS doesn't leave a aperture memory hole\n"); | |
452 | printk(KERN_ERR | |
453 | "Please enable the IOMMU option in the BIOS setup\n"); | |
454 | printk(KERN_ERR | |
455 | "This costs you %d MB of RAM\n", | |
456 | 32 << fallback_aper_order); | |
1da177e4 LT |
457 | |
458 | aper_order = fallback_aper_order; | |
459 | aper_alloc = allocate_aperture(); | |
c140df97 IM |
460 | if (!aper_alloc) { |
461 | /* | |
462 | * Could disable AGP and IOMMU here, but it's | |
463 | * probably not worth it. But the later users | |
464 | * cannot deal with bad apertures and turning | |
465 | * on the aperture over memory causes very | |
466 | * strange problems, so it's better to panic | |
467 | * early. | |
468 | */ | |
1da177e4 LT |
469 | panic("Not enough memory for aperture"); |
470 | } | |
c140df97 IM |
471 | } else { |
472 | return; | |
473 | } | |
1da177e4 LT |
474 | |
475 | /* Fix up the north bridges */ | |
55c0d721 YL |
476 | for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { |
477 | int bus; | |
478 | int dev_base, dev_limit; | |
479 | ||
480 | bus = bus_dev_ranges[i].bus; | |
481 | dev_base = bus_dev_ranges[i].dev_base; | |
482 | dev_limit = bus_dev_ranges[i].dev_limit; | |
483 | for (slot = dev_base; slot < dev_limit; slot++) { | |
484 | if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00))) | |
485 | continue; | |
486 | ||
487 | /* Don't enable translation yet. That is done later. | |
488 | Assume this BIOS didn't initialise the GART so | |
489 | just overwrite all previous bits */ | |
490 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, aper_order << 1); | |
491 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25); | |
492 | } | |
c140df97 IM |
493 | } |
494 | } |