Commit | Line | Data |
---|---|---|
c140df97 | 1 | /* |
1da177e4 | 2 | * Firmware replacement code. |
c140df97 | 3 | * |
1da177e4 | 4 | * Work around broken BIOSes that don't set an aperture or only set the |
c140df97 IM |
5 | * aperture in the AGP bridge. |
6 | * If all fails map the aperture over some low memory. This is cheaper than | |
7 | * doing bounce buffering. The memory is lost. This is done at early boot | |
8 | * because only the bootmem allocator can allocate 32+MB. | |
9 | * | |
1da177e4 | 10 | * Copyright 2002 Andi Kleen, SuSE Labs. |
1da177e4 | 11 | */ |
1da177e4 LT |
12 | #include <linux/kernel.h> |
13 | #include <linux/types.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/bootmem.h> | |
16 | #include <linux/mmzone.h> | |
17 | #include <linux/pci_ids.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/bitops.h> | |
56dd669a | 20 | #include <linux/ioport.h> |
2050d45d | 21 | #include <linux/suspend.h> |
1da177e4 LT |
22 | #include <asm/e820.h> |
23 | #include <asm/io.h> | |
395624fc | 24 | #include <asm/gart.h> |
1da177e4 | 25 | #include <asm/pci-direct.h> |
ca8642f6 | 26 | #include <asm/dma.h> |
a32073bf | 27 | #include <asm/k8.h> |
1da177e4 | 28 | |
0440d4c0 | 29 | int gart_iommu_aperture; |
7de6a4cd PM |
30 | int gart_iommu_aperture_disabled __initdata; |
31 | int gart_iommu_aperture_allowed __initdata; | |
1da177e4 LT |
32 | |
33 | int fallback_aper_order __initdata = 1; /* 64MB */ | |
7de6a4cd | 34 | int fallback_aper_force __initdata; |
1da177e4 LT |
35 | |
36 | int fix_aperture __initdata = 1; | |
37 | ||
56dd669a AD |
38 | static struct resource gart_resource = { |
39 | .name = "GART", | |
40 | .flags = IORESOURCE_MEM, | |
41 | }; | |
42 | ||
43 | static void __init insert_aperture_resource(u32 aper_base, u32 aper_size) | |
44 | { | |
45 | gart_resource.start = aper_base; | |
46 | gart_resource.end = aper_base + aper_size - 1; | |
47 | insert_resource(&iomem_resource, &gart_resource); | |
48 | } | |
49 | ||
42442ed5 AM |
50 | /* This code runs before the PCI subsystem is initialized, so just |
51 | access the northbridge directly. */ | |
1da177e4 | 52 | |
c140df97 | 53 | static u32 __init allocate_aperture(void) |
1da177e4 | 54 | { |
1da177e4 | 55 | u32 aper_size; |
c140df97 | 56 | void *p; |
1da177e4 | 57 | |
c140df97 IM |
58 | if (fallback_aper_order > 7) |
59 | fallback_aper_order = 7; | |
60 | aper_size = (32 * 1024 * 1024) << fallback_aper_order; | |
1da177e4 | 61 | |
c140df97 IM |
62 | /* |
63 | * Aperture has to be naturally aligned. This means a 2GB aperture | |
64 | * won't have much chance of finding a place in the lower 4GB of | |
65 | * memory. Unfortunately we cannot move it up because that would | |
66 | * make the IOMMU useless. | |
1da177e4 | 67 | */ |
82d1bb72 | 68 | p = __alloc_bootmem_nopanic(aper_size, aper_size, 0); |
1da177e4 | 69 | if (!p || __pa(p)+aper_size > 0xffffffff) { |
31183ba8 IM |
70 | printk(KERN_ERR |
71 | "Cannot allocate aperture memory hole (%p,%uK)\n", | |
72 | p, aper_size>>10); | |
1da177e4 | 73 | if (p) |
82d1bb72 | 74 | free_bootmem(__pa(p), aper_size); |
1da177e4 LT |
75 | return 0; |
76 | } | |
31183ba8 IM |
77 | printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n", |
78 | aper_size >> 10, __pa(p)); | |
56dd669a | 79 | insert_aperture_resource((u32)__pa(p), aper_size); |
2050d45d PM |
80 | register_nosave_region((u32)__pa(p) >> PAGE_SHIFT, |
81 | (u32)__pa(p+aper_size) >> PAGE_SHIFT); | |
c140df97 IM |
82 | |
83 | return (u32)__pa(p); | |
1da177e4 LT |
84 | } |
85 | ||
a32073bf | 86 | static int __init aperture_valid(u64 aper_base, u32 aper_size) |
c140df97 IM |
87 | { |
88 | if (!aper_base) | |
1da177e4 | 89 | return 0; |
31183ba8 | 90 | |
547c5355 | 91 | if (aper_base + aper_size > 0x100000000UL) { |
31183ba8 | 92 | printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n"); |
c140df97 | 93 | return 0; |
1da177e4 | 94 | } |
eee5a9fa | 95 | if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) { |
31183ba8 | 96 | printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n"); |
c140df97 IM |
97 | return 0; |
98 | } | |
261a5ec3 YL |
99 | if (aper_size < 64*1024*1024) { |
100 | printk(KERN_ERR "Aperture too small (%d MB)\n", aper_size>>20); | |
101 | return 0; | |
102 | } | |
31183ba8 | 103 | |
1da177e4 | 104 | return 1; |
c140df97 | 105 | } |
1da177e4 | 106 | |
42442ed5 | 107 | /* Find a PCI capability */ |
c140df97 IM |
108 | static __u32 __init find_cap(int num, int slot, int func, int cap) |
109 | { | |
1da177e4 | 110 | int bytes; |
c140df97 IM |
111 | u8 pos; |
112 | ||
113 | if (!(read_pci_config_16(num, slot, func, PCI_STATUS) & | |
114 | PCI_STATUS_CAP_LIST)) | |
1da177e4 | 115 | return 0; |
c140df97 IM |
116 | |
117 | pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST); | |
118 | for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) { | |
1da177e4 | 119 | u8 id; |
c140df97 IM |
120 | |
121 | pos &= ~3; | |
122 | id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID); | |
1da177e4 LT |
123 | if (id == 0xff) |
124 | break; | |
c140df97 IM |
125 | if (id == cap) |
126 | return pos; | |
127 | pos = read_pci_config_byte(num, slot, func, | |
128 | pos+PCI_CAP_LIST_NEXT); | |
129 | } | |
1da177e4 | 130 | return 0; |
c140df97 | 131 | } |
1da177e4 LT |
132 | |
133 | /* Read a standard AGPv3 bridge header */ | |
134 | static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order) | |
c140df97 | 135 | { |
1da177e4 LT |
136 | u32 apsize; |
137 | u32 apsizereg; | |
138 | int nbits; | |
139 | u32 aper_low, aper_hi; | |
140 | u64 aper; | |
1edc1ab3 | 141 | u32 old_order; |
1da177e4 | 142 | |
31183ba8 | 143 | printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", num, slot, func); |
c140df97 | 144 | apsizereg = read_pci_config_16(num, slot, func, cap + 0x14); |
1da177e4 | 145 | if (apsizereg == 0xffffffff) { |
31183ba8 | 146 | printk(KERN_ERR "APSIZE in AGP bridge unreadable\n"); |
1da177e4 LT |
147 | return 0; |
148 | } | |
149 | ||
1edc1ab3 YL |
150 | /* old_order could be the value from NB gart setting */ |
151 | old_order = *order; | |
152 | ||
1da177e4 LT |
153 | apsize = apsizereg & 0xfff; |
154 | /* Some BIOS use weird encodings not in the AGPv3 table. */ | |
c140df97 IM |
155 | if (apsize & 0xff) |
156 | apsize |= 0xf00; | |
1da177e4 LT |
157 | nbits = hweight16(apsize); |
158 | *order = 7 - nbits; | |
159 | if ((int)*order < 0) /* < 32MB */ | |
160 | *order = 0; | |
c140df97 IM |
161 | |
162 | aper_low = read_pci_config(num, slot, func, 0x10); | |
163 | aper_hi = read_pci_config(num, slot, func, 0x14); | |
1da177e4 LT |
164 | aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); |
165 | ||
1edc1ab3 YL |
166 | /* |
167 | * On some sick chips, APSIZE is 0. It means it wants 4G | |
168 | * so let double check that order, and lets trust AMD NB settings: | |
169 | */ | |
170 | if (aper + (32UL<<(20 + *order)) > 0x100000000UL) { | |
171 | printk(KERN_INFO "Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n", | |
172 | 32 << *order, apsizereg); | |
173 | *order = old_order; | |
174 | } | |
175 | ||
31183ba8 IM |
176 | printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n", |
177 | aper, 32 << *order, apsizereg); | |
1da177e4 | 178 | |
a32073bf | 179 | if (!aperture_valid(aper, (32*1024*1024) << *order)) |
c140df97 IM |
180 | return 0; |
181 | return (u32)aper; | |
182 | } | |
1da177e4 | 183 | |
c140df97 IM |
184 | /* |
185 | * Look for an AGP bridge. Windows only expects the aperture in the | |
186 | * AGP bridge and some BIOS forget to initialize the Northbridge too. | |
187 | * Work around this here. | |
188 | * | |
189 | * Do an PCI bus scan by hand because we're running before the PCI | |
190 | * subsystem. | |
191 | * | |
192 | * All K8 AGP bridges are AGPv3 compliant, so we can do this scan | |
193 | * generically. It's probably overkill to always scan all slots because | |
194 | * the AGP bridges should be always an own bus on the HT hierarchy, | |
195 | * but do it here for future safety. | |
196 | */ | |
1da177e4 LT |
197 | static __u32 __init search_agp_bridge(u32 *order, int *valid_agp) |
198 | { | |
199 | int num, slot, func; | |
200 | ||
201 | /* Poor man's PCI discovery */ | |
c140df97 IM |
202 | for (num = 0; num < 256; num++) { |
203 | for (slot = 0; slot < 32; slot++) { | |
204 | for (func = 0; func < 8; func++) { | |
1da177e4 LT |
205 | u32 class, cap; |
206 | u8 type; | |
c140df97 | 207 | class = read_pci_config(num, slot, func, |
1da177e4 LT |
208 | PCI_CLASS_REVISION); |
209 | if (class == 0xffffffff) | |
c140df97 IM |
210 | break; |
211 | ||
212 | switch (class >> 16) { | |
1da177e4 LT |
213 | case PCI_CLASS_BRIDGE_HOST: |
214 | case PCI_CLASS_BRIDGE_OTHER: /* needed? */ | |
215 | /* AGP bridge? */ | |
c140df97 IM |
216 | cap = find_cap(num, slot, func, |
217 | PCI_CAP_ID_AGP); | |
1da177e4 LT |
218 | if (!cap) |
219 | break; | |
c140df97 IM |
220 | *valid_agp = 1; |
221 | return read_agp(num, slot, func, cap, | |
222 | order); | |
223 | } | |
224 | ||
1da177e4 | 225 | /* No multi-function device? */ |
c140df97 | 226 | type = read_pci_config_byte(num, slot, func, |
1da177e4 LT |
227 | PCI_HEADER_TYPE); |
228 | if (!(type & 0x80)) | |
229 | break; | |
c140df97 IM |
230 | } |
231 | } | |
1da177e4 | 232 | } |
31183ba8 | 233 | printk(KERN_INFO "No AGP bridge found\n"); |
c140df97 | 234 | |
1da177e4 LT |
235 | return 0; |
236 | } | |
237 | ||
aaf23042 YL |
238 | static int gart_fix_e820 __initdata = 1; |
239 | ||
240 | static int __init parse_gart_mem(char *p) | |
241 | { | |
242 | if (!p) | |
243 | return -EINVAL; | |
244 | ||
245 | if (!strncmp(p, "off", 3)) | |
246 | gart_fix_e820 = 0; | |
247 | else if (!strncmp(p, "on", 2)) | |
248 | gart_fix_e820 = 1; | |
249 | ||
250 | return 0; | |
251 | } | |
252 | early_param("gart_fix_e820", parse_gart_mem); | |
253 | ||
254 | void __init early_gart_iommu_check(void) | |
255 | { | |
256 | /* | |
257 | * in case it is enabled before, esp for kexec/kdump, | |
258 | * previous kernel already enable that. memset called | |
259 | * by allocate_aperture/__alloc_bootmem_nopanic cause restart. | |
260 | * or second kernel have different position for GART hole. and new | |
261 | * kernel could use hole as RAM that is still used by GART set by | |
262 | * first kernel | |
263 | * or BIOS forget to put that in reserved. | |
264 | * try to update e820 to make that region as reserved. | |
265 | */ | |
266 | int fix, num; | |
267 | u32 ctl; | |
268 | u32 aper_size = 0, aper_order = 0, last_aper_order = 0; | |
269 | u64 aper_base = 0, last_aper_base = 0; | |
270 | int aper_enabled = 0, last_aper_enabled = 0; | |
271 | ||
272 | if (!early_pci_allowed()) | |
273 | return; | |
274 | ||
275 | fix = 0; | |
276 | for (num = 24; num < 32; num++) { | |
277 | if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) | |
278 | continue; | |
279 | ||
280 | ctl = read_pci_config(0, num, 3, 0x90); | |
281 | aper_enabled = ctl & 1; | |
282 | aper_order = (ctl >> 1) & 7; | |
283 | aper_size = (32 * 1024 * 1024) << aper_order; | |
284 | aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff; | |
285 | aper_base <<= 25; | |
286 | ||
287 | if ((last_aper_order && aper_order != last_aper_order) || | |
288 | (last_aper_base && aper_base != last_aper_base) || | |
289 | (last_aper_enabled && aper_enabled != last_aper_enabled)) { | |
290 | fix = 1; | |
291 | break; | |
292 | } | |
293 | last_aper_order = aper_order; | |
294 | last_aper_base = aper_base; | |
295 | last_aper_enabled = aper_enabled; | |
296 | } | |
297 | ||
298 | if (!fix && !aper_enabled) | |
299 | return; | |
300 | ||
301 | if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL) | |
302 | fix = 1; | |
303 | ||
304 | if (gart_fix_e820 && !fix && aper_enabled) { | |
305 | if (e820_any_mapped(aper_base, aper_base + aper_size, | |
306 | E820_RAM)) { | |
307 | /* reserved it, so we can resuse it in second kernel */ | |
308 | printk(KERN_INFO "update e820 for GART\n"); | |
309 | add_memory_region(aper_base, aper_size, E820_RESERVED); | |
310 | update_e820(); | |
311 | } | |
312 | return; | |
313 | } | |
314 | ||
315 | /* different nodes have different setting, disable them all at first*/ | |
316 | for (num = 24; num < 32; num++) { | |
317 | if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) | |
318 | continue; | |
319 | ||
320 | ctl = read_pci_config(0, num, 3, 0x90); | |
321 | ctl &= ~1; | |
322 | write_pci_config(0, num, 3, 0x90, ctl); | |
323 | } | |
324 | ||
325 | } | |
326 | ||
0440d4c0 | 327 | void __init gart_iommu_hole_init(void) |
c140df97 | 328 | { |
50895c5d | 329 | u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0; |
1da177e4 | 330 | u64 aper_base, last_aper_base = 0; |
c140df97 | 331 | int fix, num, valid_agp = 0; |
47db4c3e | 332 | int node; |
1da177e4 | 333 | |
0440d4c0 JR |
334 | if (gart_iommu_aperture_disabled || !fix_aperture || |
335 | !early_pci_allowed()) | |
1da177e4 LT |
336 | return; |
337 | ||
753811dc | 338 | printk(KERN_INFO "Checking aperture...\n"); |
1da177e4 LT |
339 | |
340 | fix = 0; | |
47db4c3e | 341 | node = 0; |
c140df97 | 342 | for (num = 24; num < 32; num++) { |
a32073bf AK |
343 | if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) |
344 | continue; | |
1da177e4 | 345 | |
8d4f6b93 | 346 | iommu_detected = 1; |
0440d4c0 | 347 | gart_iommu_aperture = 1; |
1da177e4 | 348 | |
c140df97 IM |
349 | aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7; |
350 | aper_size = (32 * 1024 * 1024) << aper_order; | |
1da177e4 | 351 | aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff; |
c140df97 | 352 | aper_base <<= 25; |
1da177e4 | 353 | |
47db4c3e YL |
354 | printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n", |
355 | node, aper_base, aper_size >> 20); | |
356 | node++; | |
c140df97 | 357 | |
a32073bf | 358 | if (!aperture_valid(aper_base, aper_size)) { |
c140df97 IM |
359 | fix = 1; |
360 | break; | |
1da177e4 LT |
361 | } |
362 | ||
363 | if ((last_aper_order && aper_order != last_aper_order) || | |
364 | (last_aper_base && aper_base != last_aper_base)) { | |
365 | fix = 1; | |
366 | break; | |
367 | } | |
368 | last_aper_order = aper_order; | |
369 | last_aper_base = aper_base; | |
c140df97 | 370 | } |
1da177e4 | 371 | |
56dd669a AD |
372 | if (!fix && !fallback_aper_force) { |
373 | if (last_aper_base) { | |
374 | unsigned long n = (32 * 1024 * 1024) << last_aper_order; | |
c140df97 | 375 | |
56dd669a AD |
376 | insert_aperture_resource((u32)last_aper_base, n); |
377 | } | |
c140df97 | 378 | return; |
56dd669a | 379 | } |
1da177e4 LT |
380 | |
381 | if (!fallback_aper_force) | |
c140df97 IM |
382 | aper_alloc = search_agp_bridge(&aper_order, &valid_agp); |
383 | ||
384 | if (aper_alloc) { | |
1da177e4 | 385 | /* Got the aperture from the AGP bridge */ |
63f02fd7 AK |
386 | } else if (swiotlb && !valid_agp) { |
387 | /* Do nothing */ | |
60b08c67 | 388 | } else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) || |
1da177e4 LT |
389 | force_iommu || |
390 | valid_agp || | |
c140df97 | 391 | fallback_aper_force) { |
31183ba8 IM |
392 | printk(KERN_ERR |
393 | "Your BIOS doesn't leave a aperture memory hole\n"); | |
394 | printk(KERN_ERR | |
395 | "Please enable the IOMMU option in the BIOS setup\n"); | |
396 | printk(KERN_ERR | |
397 | "This costs you %d MB of RAM\n", | |
398 | 32 << fallback_aper_order); | |
1da177e4 LT |
399 | |
400 | aper_order = fallback_aper_order; | |
401 | aper_alloc = allocate_aperture(); | |
c140df97 IM |
402 | if (!aper_alloc) { |
403 | /* | |
404 | * Could disable AGP and IOMMU here, but it's | |
405 | * probably not worth it. But the later users | |
406 | * cannot deal with bad apertures and turning | |
407 | * on the aperture over memory causes very | |
408 | * strange problems, so it's better to panic | |
409 | * early. | |
410 | */ | |
1da177e4 LT |
411 | panic("Not enough memory for aperture"); |
412 | } | |
c140df97 IM |
413 | } else { |
414 | return; | |
415 | } | |
1da177e4 LT |
416 | |
417 | /* Fix up the north bridges */ | |
c140df97 | 418 | for (num = 24; num < 32; num++) { |
a32073bf | 419 | if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) |
c140df97 IM |
420 | continue; |
421 | ||
422 | /* | |
423 | * Don't enable translation yet. That is done later. | |
424 | * Assume this BIOS didn't initialise the GART so | |
425 | * just overwrite all previous bits | |
426 | */ | |
427 | write_pci_config(0, num, 3, 0x90, aper_order<<1); | |
428 | write_pci_config(0, num, 3, 0x94, aper_alloc>>25); | |
429 | } | |
430 | } |