[deliverable/linux.git] / arch / x86 / kernel / aperture_64.c

/*
 * Firmware replacement code.
 *
 * Work around broken BIOSes that don't set an aperture or only set the
 * aperture in the AGP bridge.
 * If all fails map the aperture over some low memory.  This is cheaper than
 * doing bounce buffering. The memory is lost. This is done at early boot
 * because only the bootmem allocator can allocate 32+MB.
 *
 * Copyright 2002 Andi Kleen, SuSE Labs.
 */
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/mmzone.h>
#include <linux/pci_ids.h>
#include <linux/pci.h>
#include <linux/bitops.h>
#include <linux/ioport.h>
#include <linux/suspend.h>
#include <asm/e820.h>
#include <asm/io.h>
#include <asm/gart.h>
#include <asm/pci-direct.h>
#include <asm/dma.h>
#include <asm/k8.h>

int gart_iommu_aperture;
int gart_iommu_aperture_disabled __initdata;
int gart_iommu_aperture_allowed __initdata;

int fallback_aper_order __initdata = 1; /* 64MB */
int fallback_aper_force __initdata;

int fix_aperture __initdata = 1;

static struct resource gart_resource = {
	.name	= "GART",
	.flags	= IORESOURCE_MEM,
};

static void __init insert_aperture_resource(u32 aper_base, u32 aper_size)
{
	gart_resource.start = aper_base;
	gart_resource.end = aper_base + aper_size - 1;
	insert_resource(&iomem_resource, &gart_resource);
}

/* This code runs before the PCI subsystem is initialized, so just
   access the northbridge directly. */

static u32 __init allocate_aperture(void)
{
	u32 aper_size;
	void *p;

	if (fallback_aper_order > 7)
		fallback_aper_order = 7;
	aper_size = (32 * 1024 * 1024) << fallback_aper_order;

	/*
	 * Aperture has to be naturally aligned. This means a 2GB aperture
	 * won't have much chance of finding a place in the lower 4GB of
	 * memory. Unfortunately we cannot move it up because that would
	 * make the IOMMU useless.
	 */
	p = __alloc_bootmem_nopanic(aper_size, aper_size, 0);
	if (!p || __pa(p)+aper_size > 0xffffffff) {
		printk(KERN_ERR
			"Cannot allocate aperture memory hole (%p,%uK)\n",
				p, aper_size>>10);
		if (p)
			free_bootmem(__pa(p), aper_size);
		return 0;
	}
	printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n",
			aper_size >> 10, __pa(p));
	insert_aperture_resource((u32)__pa(p), aper_size);
	register_nosave_region((u32)__pa(p) >> PAGE_SHIFT,
				(u32)__pa(p+aper_size) >> PAGE_SHIFT);

	return (u32)__pa(p);
}

static int __init aperture_valid(u64 aper_base, u32 aper_size)
{
	if (!aper_base)
		return 0;

	if (aper_base + aper_size > 0x100000000UL) {
		printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
		return 0;
	}
	if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
		printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
		return 0;
	}
	if (aper_size < 64*1024*1024) {
		printk(KERN_ERR "Aperture too small (%d MB)\n", aper_size>>20);
		return 0;
	}

	return 1;
}

/* Find a PCI capability */
static __u32 __init find_cap(int num, int slot, int func, int cap)
{
	int bytes;
	u8 pos;

	if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
						PCI_STATUS_CAP_LIST))
		return 0;

	pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
	for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
		u8 id;

		pos &= ~3;
		id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
		if (id == 0xff)
			break;
		if (id == cap)
			return pos;
		pos = read_pci_config_byte(num, slot, func,
						pos+PCI_CAP_LIST_NEXT);
	}
	return 0;
}

/* Read a standard AGPv3 bridge header */
static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
{
	u32 apsize;
	u32 apsizereg;
	int nbits;
	u32 aper_low, aper_hi;
	u64 aper;

	printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", num, slot, func);
	apsizereg = read_pci_config_16(num, slot, func, cap + 0x14);
	if (apsizereg == 0xffffffff) {
		printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
		return 0;
	}

	apsize = apsizereg & 0xfff;
	/* Some BIOS use weird encodings not in the AGPv3 table. */
	if (apsize & 0xff)
		apsize |= 0xf00;
	nbits = hweight16(apsize);
	*order = 7 - nbits;
	if ((int)*order < 0) /* < 32MB */
		*order = 0;

	aper_low = read_pci_config(num, slot, func, 0x10);
	aper_hi = read_pci_config(num, slot, func, 0x14);
	aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);

	printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
			aper, 32 << *order, apsizereg);

	if (!aperture_valid(aper, (32*1024*1024) << *order))
		return 0;
	return (u32)aper;
}

/*
 * Look for an AGP bridge. Windows only expects the aperture in the
 * AGP bridge and some BIOS forget to initialize the Northbridge too.
 * Work around this here.
 *
 * Do an PCI bus scan by hand because we're running before the PCI
 * subsystem.
 *
 * All K8 AGP bridges are AGPv3 compliant, so we can do this scan
 * generically. It's probably overkill to always scan all slots because
 * the AGP bridges should be always an own bus on the HT hierarchy,
 * but do it here for future safety.
 */
static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
{
	int num, slot, func;

	/* Poor man's PCI discovery */
	for (num = 0; num < 256; num++) {
		for (slot = 0; slot < 32; slot++) {
			for (func = 0; func < 8; func++) {
				u32 class, cap;
				u8 type;
				class = read_pci_config(num, slot, func,
							PCI_CLASS_REVISION);
				if (class == 0xffffffff)
					break;

				switch (class >> 16) {
				case PCI_CLASS_BRIDGE_HOST:
				case PCI_CLASS_BRIDGE_OTHER: /* needed? */
					/* AGP bridge? */
					cap = find_cap(num, slot, func,
							PCI_CAP_ID_AGP);
					if (!cap)
						break;
					*valid_agp = 1;
					return read_agp(num, slot, func, cap,
							order);
				}

				/* No multi-function device? */
				type = read_pci_config_byte(num, slot, func,
							       PCI_HEADER_TYPE);
				if (!(type & 0x80))
					break;
			}
		}
	}
	printk(KERN_INFO "No AGP bridge found\n");

	return 0;
}

static int gart_fix_e820 __initdata = 1;

static int __init parse_gart_mem(char *p)
{
	if (!p)
		return -EINVAL;

	if (!strncmp(p, "off", 3))
		gart_fix_e820 = 0;
	else if (!strncmp(p, "on", 2))
		gart_fix_e820 = 1;

	return 0;
}
early_param("gart_fix_e820", parse_gart_mem);

void __init early_gart_iommu_check(void)
{
	/*
	 * in case it is enabled before, esp for kexec/kdump,
	 * previous kernel already enable that. memset called
	 * by allocate_aperture/__alloc_bootmem_nopanic cause restart.
	 * or second kernel have different position for GART hole. and new
	 * kernel could use hole as RAM that is still used by GART set by
	 * first kernel
	 * or BIOS forget to put that in reserved.
	 * try to update e820 to make that region as reserved.
	 */
	int fix, num;
	u32 ctl;
	u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
	u64 aper_base = 0, last_aper_base = 0;
	int aper_enabled = 0, last_aper_enabled = 0;

	if (!early_pci_allowed())
		return;

	fix = 0;
	for (num = 24; num < 32; num++) {
		if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
			continue;

		ctl = read_pci_config(0, num, 3, 0x90);
		aper_enabled = ctl & 1;
		aper_order = (ctl >> 1) & 7;
		aper_size = (32 * 1024 * 1024) << aper_order;
		aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
		aper_base <<= 25;

		if ((last_aper_order && aper_order != last_aper_order) ||
		    (last_aper_base && aper_base != last_aper_base) ||
		    (last_aper_enabled && aper_enabled != last_aper_enabled)) {
			fix = 1;
			break;
		}
		last_aper_order = aper_order;
		last_aper_base = aper_base;
		last_aper_enabled = aper_enabled;
	}

	if (!fix && !aper_enabled)
		return;

	if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
		fix = 1;

	if (gart_fix_e820 && !fix && aper_enabled) {
		if (e820_any_mapped(aper_base, aper_base + aper_size,
				    E820_RAM)) {
			/* reserved it, so we can resuse it in second kernel */
			printk(KERN_INFO "update e820 for GART\n");
			add_memory_region(aper_base, aper_size, E820_RESERVED);
			update_e820();
		}
		return;
	}

	/* different nodes have different setting, disable them all at first*/
	for (num = 24; num < 32; num++) {
		if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
			continue;

		ctl = read_pci_config(0, num, 3, 0x90);
		ctl &= ~1;
		write_pci_config(0, num, 3, 0x90, ctl);
	}

}

void __init gart_iommu_hole_init(void)
{
	u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
	u64 aper_base, last_aper_base = 0;
	int fix, num, valid_agp = 0;
	int node;

	if (gart_iommu_aperture_disabled || !fix_aperture ||
	    !early_pci_allowed())
		return;

	printk(KERN_INFO  "Checking aperture...\n");

	fix = 0;
	node = 0;
	for (num = 24; num < 32; num++) {
		if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
			continue;

		iommu_detected = 1;
		gart_iommu_aperture = 1;

		aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7;
		aper_size = (32 * 1024 * 1024) << aper_order;
		aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
		aper_base <<= 25;

		printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
				node, aper_base, aper_size >> 20);
		node++;

		if (!aperture_valid(aper_base, aper_size)) {
			fix = 1;
			break;
		}

		if ((last_aper_order && aper_order != last_aper_order) ||
		    (last_aper_base && aper_base != last_aper_base)) {
			fix = 1;
			break;
		}
		last_aper_order = aper_order;
		last_aper_base = aper_base;
	}

	if (!fix && !fallback_aper_force) {
		if (last_aper_base) {
			unsigned long n = (32 * 1024 * 1024) << last_aper_order;

			insert_aperture_resource((u32)last_aper_base, n);
		}
		return;
	}

	if (!fallback_aper_force)
		aper_alloc = search_agp_bridge(&aper_order, &valid_agp);

	if (aper_alloc) {
		/* Got the aperture from the AGP bridge */
	} else if (swiotlb && !valid_agp) {
		/* Do nothing */
	} else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) ||
		   force_iommu ||
		   valid_agp ||
		   fallback_aper_force) {
		printk(KERN_ERR
			"Your BIOS doesn't leave a aperture memory hole\n");
		printk(KERN_ERR
			"Please enable the IOMMU option in the BIOS setup\n");
		printk(KERN_ERR
			"This costs you %d MB of RAM\n",
				32 << fallback_aper_order);

		aper_order = fallback_aper_order;
		aper_alloc = allocate_aperture();
		if (!aper_alloc) {
			/*
			 * Could disable AGP and IOMMU here, but it's
			 * probably not worth it. But the later users
			 * cannot deal with bad apertures and turning
			 * on the aperture over memory causes very
			 * strange problems, so it's better to panic
			 * early.
			 */
			panic("Not enough memory for aperture");
		}
	} else {
		return;
	}

	/* Fix up the north bridges */
	for (num = 24; num < 32; num++) {
		if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
			continue;

		/*
		 * Don't enable translation yet. That is done later.
		 * Assume this BIOS didn't initialise the GART so
		 * just overwrite all previous bits
		 */
		write_pci_config(0, num, 3, 0x90, aper_order<<1);
		write_pci_config(0, num, 3, 0x94, aper_alloc>>25);
	}
}
Commit	Line	Data
c140df97	1	/*
1da177e4	2	* Firmware replacement code.
c140df97	3	*
1da177e4	4	* Work around broken BIOSes that don't set an aperture or only set the
c140df97 IM	5	* aperture in the AGP bridge.
	6	* If all fails map the aperture over some low memory. This is cheaper than
	7	* doing bounce buffering. The memory is lost. This is done at early boot
	8	* because only the bootmem allocator can allocate 32+MB.
	9	*
1da177e4	10	* Copyright 2002 Andi Kleen, SuSE Labs.
1da177e4	11	*/
1da177e4 LT	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/init.h>
	15	#include <linux/bootmem.h>
	16	#include <linux/mmzone.h>
	17	#include <linux/pci_ids.h>
	18	#include <linux/pci.h>
	19	#include <linux/bitops.h>
56dd669a	20	#include <linux/ioport.h>
2050d45d	21	#include <linux/suspend.h>
1da177e4 LT	22	#include <asm/e820.h>
1da177e4 LT	23	#include <asm/io.h>
395624fc	24	#include <asm/gart.h>
1da177e4	25	#include <asm/pci-direct.h>
ca8642f6	26	#include <asm/dma.h>
a32073bf	27	#include <asm/k8.h>
1da177e4	28
0440d4c0	29	int gart_iommu_aperture;
7de6a4cd PM	30	int gart_iommu_aperture_disabled __initdata;
7de6a4cd PM	31	int gart_iommu_aperture_allowed __initdata;
1da177e4 LT	32
1da177e4 LT	33	int fallback_aper_order __initdata = 1; /* 64MB */
7de6a4cd	34	int fallback_aper_force __initdata;
1da177e4 LT	35
	36	int fix_aperture __initdata = 1;
	37
56dd669a AD	38	static struct resource gart_resource = {
	39	.name = "GART",
	40	.flags = IORESOURCE_MEM,
	41	};
	42
	43	static void __init insert_aperture_resource(u32 aper_base, u32 aper_size)
	44	{
	45	gart_resource.start = aper_base;
	46	gart_resource.end = aper_base + aper_size - 1;
	47	insert_resource(&iomem_resource, &gart_resource);
	48	}
	49
42442ed5 AM	50	/* This code runs before the PCI subsystem is initialized, so just
42442ed5 AM	51	access the northbridge directly. */
1da177e4	52
c140df97	53	static u32 __init allocate_aperture(void)
1da177e4	54	{
1da177e4	55	u32 aper_size;
c140df97	56	void *p;
1da177e4	57
c140df97 IM	58	if (fallback_aper_order > 7)
	59	fallback_aper_order = 7;
	60	aper_size = (32 * 1024 * 1024) << fallback_aper_order;
1da177e4	61
c140df97 IM	62	/*
	63	* Aperture has to be naturally aligned. This means a 2GB aperture
	64	* won't have much chance of finding a place in the lower 4GB of
	65	* memory. Unfortunately we cannot move it up because that would
	66	* make the IOMMU useless.
1da177e4	67	*/
82d1bb72	68	p = __alloc_bootmem_nopanic(aper_size, aper_size, 0);
1da177e4	69	if (!p \|\| __pa(p)+aper_size > 0xffffffff) {
31183ba8 IM	70	printk(KERN_ERR
	71	"Cannot allocate aperture memory hole (%p,%uK)\n",
	72	p, aper_size>>10);
1da177e4	73	if (p)
82d1bb72	74	free_bootmem(__pa(p), aper_size);
1da177e4 LT	75	return 0;
1da177e4 LT	76	}
31183ba8 IM	77	printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n",
31183ba8 IM	78	aper_size >> 10, __pa(p));
56dd669a	79	insert_aperture_resource((u32)__pa(p), aper_size);
2050d45d PM	80	register_nosave_region((u32)__pa(p) >> PAGE_SHIFT,
2050d45d PM	81	(u32)__pa(p+aper_size) >> PAGE_SHIFT);
c140df97 IM	82
c140df97 IM	83	return (u32)__pa(p);
1da177e4 LT	84	}
1da177e4 LT	85
a32073bf	86	static int __init aperture_valid(u64 aper_base, u32 aper_size)
c140df97 IM	87	{
c140df97 IM	88	if (!aper_base)
1da177e4	89	return 0;
31183ba8	90
547c5355	91	if (aper_base + aper_size > 0x100000000UL) {
31183ba8	92	printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
c140df97	93	return 0;
1da177e4	94	}
eee5a9fa	95	if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
31183ba8	96	printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
c140df97 IM	97	return 0;
c140df97 IM	98	}
261a5ec3 YL	99	if (aper_size < 6410241024) {
	100	printk(KERN_ERR "Aperture too small (%d MB)\n", aper_size>>20);
	101	return 0;
	102	}
31183ba8	103
1da177e4	104	return 1;
c140df97	105	}
1da177e4	106
42442ed5	107	/* Find a PCI capability */
c140df97 IM	108	static __u32 __init find_cap(int num, int slot, int func, int cap)
c140df97 IM	109	{
1da177e4	110	int bytes;
c140df97 IM	111	u8 pos;
	112
	113	if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
	114	PCI_STATUS_CAP_LIST))
1da177e4	115	return 0;
c140df97 IM	116
	117	pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
	118	for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
1da177e4	119	u8 id;
c140df97 IM	120
	121	pos &= ~3;
	122	id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
1da177e4 LT	123	if (id == 0xff)
1da177e4 LT	124	break;
c140df97 IM	125	if (id == cap)
	126	return pos;
	127	pos = read_pci_config_byte(num, slot, func,
	128	pos+PCI_CAP_LIST_NEXT);
	129	}
1da177e4	130	return 0;
c140df97	131	}
1da177e4 LT	132
	133	/* Read a standard AGPv3 bridge header */
	134	static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
c140df97	135	{
1da177e4 LT	136	u32 apsize;
	137	u32 apsizereg;
	138	int nbits;
	139	u32 aper_low, aper_hi;
	140	u64 aper;
	141
31183ba8	142	printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", num, slot, func);
c140df97	143	apsizereg = read_pci_config_16(num, slot, func, cap + 0x14);
1da177e4	144	if (apsizereg == 0xffffffff) {
31183ba8	145	printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
1da177e4 LT	146	return 0;
	147	}
	148
	149	apsize = apsizereg & 0xfff;
	150	/* Some BIOS use weird encodings not in the AGPv3 table. */
c140df97 IM	151	if (apsize & 0xff)
c140df97 IM	152	apsize \|= 0xf00;
1da177e4 LT	153	nbits = hweight16(apsize);
	154	*order = 7 - nbits;
	155	if ((int)order < 0) / < 32MB */
	156	*order = 0;
c140df97 IM	157
	158	aper_low = read_pci_config(num, slot, func, 0x10);
	159	aper_hi = read_pci_config(num, slot, func, 0x14);
1da177e4 LT	160	aper = (aper_low & ~((1<<22)-1)) \| ((u64)aper_hi << 32);
1da177e4 LT	161
31183ba8 IM	162	printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
31183ba8 IM	163	aper, 32 << *order, apsizereg);
1da177e4	164
a32073bf	165	if (!aperture_valid(aper, (3210241024) << *order))
c140df97 IM	166	return 0;
	167	return (u32)aper;
	168	}
1da177e4	169
c140df97 IM	170	/*
	171	* Look for an AGP bridge. Windows only expects the aperture in the
	172	* AGP bridge and some BIOS forget to initialize the Northbridge too.
	173	* Work around this here.
	174	*
	175	* Do an PCI bus scan by hand because we're running before the PCI
	176	* subsystem.
	177	*
	178	* All K8 AGP bridges are AGPv3 compliant, so we can do this scan
	179	* generically. It's probably overkill to always scan all slots because
	180	* the AGP bridges should be always an own bus on the HT hierarchy,
	181	* but do it here for future safety.
	182	*/
1da177e4 LT	183	static __u32 __init search_agp_bridge(u32 order, int valid_agp)
	184	{
	185	int num, slot, func;
	186
	187	/* Poor man's PCI discovery */
c140df97 IM	188	for (num = 0; num < 256; num++) {
	189	for (slot = 0; slot < 32; slot++) {
	190	for (func = 0; func < 8; func++) {
1da177e4 LT	191	u32 class, cap;
1da177e4 LT	192	u8 type;
c140df97	193	class = read_pci_config(num, slot, func,
1da177e4 LT	194	PCI_CLASS_REVISION);
1da177e4 LT	195	if (class == 0xffffffff)
c140df97 IM	196	break;
	197
	198	switch (class >> 16) {
1da177e4 LT	199	case PCI_CLASS_BRIDGE_HOST:
	200	case PCI_CLASS_BRIDGE_OTHER: /* needed? */
	201	/* AGP bridge? */
c140df97 IM	202	cap = find_cap(num, slot, func,
c140df97 IM	203	PCI_CAP_ID_AGP);
1da177e4 LT	204	if (!cap)
1da177e4 LT	205	break;
c140df97 IM	206	*valid_agp = 1;
	207	return read_agp(num, slot, func, cap,
	208	order);
	209	}
	210
1da177e4	211	/* No multi-function device? */
c140df97	212	type = read_pci_config_byte(num, slot, func,
1da177e4 LT	213	PCI_HEADER_TYPE);
	214	if (!(type & 0x80))
	215	break;
c140df97 IM	216	}
c140df97 IM	217	}
1da177e4	218	}
31183ba8	219	printk(KERN_INFO "No AGP bridge found\n");
c140df97	220
1da177e4 LT	221	return 0;
	222	}
	223
aaf23042 YL	224	static int gart_fix_e820 __initdata = 1;
	225
	226	static int __init parse_gart_mem(char *p)
	227	{
	228	if (!p)
	229	return -EINVAL;
	230
	231	if (!strncmp(p, "off", 3))
	232	gart_fix_e820 = 0;
	233	else if (!strncmp(p, "on", 2))
	234	gart_fix_e820 = 1;
	235
	236	return 0;
	237	}
	238	early_param("gart_fix_e820", parse_gart_mem);
	239
	240	void __init early_gart_iommu_check(void)
	241	{
	242	/*
	243	* in case it is enabled before, esp for kexec/kdump,
	244	* previous kernel already enable that. memset called
	245	* by allocate_aperture/__alloc_bootmem_nopanic cause restart.
	246	* or second kernel have different position for GART hole. and new
	247	* kernel could use hole as RAM that is still used by GART set by
	248	* first kernel
	249	* or BIOS forget to put that in reserved.
	250	* try to update e820 to make that region as reserved.
	251	*/
	252	int fix, num;
	253	u32 ctl;
	254	u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
	255	u64 aper_base = 0, last_aper_base = 0;
	256	int aper_enabled = 0, last_aper_enabled = 0;
	257
	258	if (!early_pci_allowed())
	259	return;
	260
	261	fix = 0;
	262	for (num = 24; num < 32; num++) {
	263	if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
	264	continue;
	265
	266	ctl = read_pci_config(0, num, 3, 0x90);
	267	aper_enabled = ctl & 1;
	268	aper_order = (ctl >> 1) & 7;
	269	aper_size = (32 * 1024 * 1024) << aper_order;
	270	aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
	271	aper_base <<= 25;
	272
	273	if ((last_aper_order && aper_order != last_aper_order) \|\|
	274	(last_aper_base && aper_base != last_aper_base) \|\|
	275	(last_aper_enabled && aper_enabled != last_aper_enabled)) {
	276	fix = 1;
	277	break;
	278	}
	279	last_aper_order = aper_order;
	280	last_aper_base = aper_base;
	281	last_aper_enabled = aper_enabled;
	282	}
	283
	284	if (!fix && !aper_enabled)
	285	return;
	286
	287	if (!aper_base \|\| !aper_size \|\| aper_base + aper_size > 0x100000000UL)
288	fix = 1;
289
290	if (gart_fix_e820 && !fix && aper_enabled) {
291	if (e820_any_mapped(aper_base, aper_base + aper_size,
292	E820_RAM)) {
293	/* reserved it, so we can resuse it in second kernel */
294	printk(KERN_INFO "update e820 for GART\n");
295	add_memory_region(aper_base, aper_size, E820_RESERVED);
296	update_e820();
297	}
298	return;
299	}
300
301	/* different nodes have different setting, disable them all at first*/
302	for (num = 24; num < 32; num++) {
303	if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
304	continue;
305
306	ctl = read_pci_config(0, num, 3, 0x90);
307	ctl &= ~1;
308	write_pci_config(0, num, 3, 0x90, ctl);
309	}
310
311	}
312
0440d4c0	313	void __init gart_iommu_hole_init(void)
c140df97	314	{
50895c5d	315	u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
1da177e4	316	u64 aper_base, last_aper_base = 0;
c140df97	317	int fix, num, valid_agp = 0;
47db4c3e	318	int node;
1da177e4	319
0440d4c0 JR	320	if (gart_iommu_aperture_disabled \|\| !fix_aperture \|\|
0440d4c0 JR	321	!early_pci_allowed())
1da177e4 LT	322	return;
1da177e4 LT	323
753811dc	324	printk(KERN_INFO "Checking aperture...\n");
1da177e4 LT	325
1da177e4 LT	326	fix = 0;
47db4c3e	327	node = 0;
c140df97	328	for (num = 24; num < 32; num++) {
a32073bf AK	329	if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
a32073bf AK	330	continue;
1da177e4	331
8d4f6b93	332	iommu_detected = 1;
0440d4c0	333	gart_iommu_aperture = 1;
1da177e4	334
c140df97 IM	335	aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7;
c140df97 IM	336	aper_size = (32 * 1024 * 1024) << aper_order;
1da177e4	337	aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
c140df97	338	aper_base <<= 25;
1da177e4	339
47db4c3e YL	340	printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
	341	node, aper_base, aper_size >> 20);
	342	node++;
c140df97	343
a32073bf	344	if (!aperture_valid(aper_base, aper_size)) {
c140df97 IM	345	fix = 1;
c140df97 IM	346	break;
1da177e4 LT	347	}
	348
	349	if ((last_aper_order && aper_order != last_aper_order) \|\|
	350	(last_aper_base && aper_base != last_aper_base)) {
	351	fix = 1;
	352	break;
	353	}
	354	last_aper_order = aper_order;
	355	last_aper_base = aper_base;
c140df97	356	}
1da177e4	357
56dd669a AD	358	if (!fix && !fallback_aper_force) {
	359	if (last_aper_base) {
	360	unsigned long n = (32 * 1024 * 1024) << last_aper_order;
c140df97	361
56dd669a AD	362	insert_aperture_resource((u32)last_aper_base, n);
56dd669a AD	363	}
c140df97	364	return;
56dd669a	365	}
1da177e4 LT	366
1da177e4 LT	367	if (!fallback_aper_force)
c140df97 IM	368	aper_alloc = search_agp_bridge(&aper_order, &valid_agp);
	369
	370	if (aper_alloc) {
1da177e4	371	/* Got the aperture from the AGP bridge */
63f02fd7 AK	372	} else if (swiotlb && !valid_agp) {
63f02fd7 AK	373	/* Do nothing */
60b08c67	374	} else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) \|\|
1da177e4 LT	375	force_iommu \|\|
1da177e4 LT	376	valid_agp \|\|
c140df97	377	fallback_aper_force) {
31183ba8 IM	378	printk(KERN_ERR
	379	"Your BIOS doesn't leave a aperture memory hole\n");
	380	printk(KERN_ERR
	381	"Please enable the IOMMU option in the BIOS setup\n");
	382	printk(KERN_ERR
	383	"This costs you %d MB of RAM\n",
	384	32 << fallback_aper_order);
1da177e4 LT	385
	386	aper_order = fallback_aper_order;
	387	aper_alloc = allocate_aperture();
c140df97 IM	388	if (!aper_alloc) {
	389	/*
	390	* Could disable AGP and IOMMU here, but it's
	391	* probably not worth it. But the later users
	392	* cannot deal with bad apertures and turning
	393	* on the aperture over memory causes very
	394	* strange problems, so it's better to panic
	395	* early.
	396	*/
1da177e4 LT	397	panic("Not enough memory for aperture");
1da177e4 LT	398	}
c140df97 IM	399	} else {
	400	return;
	401	}
1da177e4 LT	402
1da177e4 LT	403	/* Fix up the north bridges */
c140df97	404	for (num = 24; num < 32; num++) {
a32073bf	405	if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
c140df97 IM	406	continue;
	407
	408	/*
	409	* Don't enable translation yet. That is done later.
	410	* Assume this BIOS didn't initialise the GART so
	411	* just overwrite all previous bits
	412	*/
	413	write_pci_config(0, num, 3, 0x90, aper_order<<1);
	414	write_pci_config(0, num, 3, 0x94, aper_alloc>>25);
	415	}
	416	}