[deliverable/linux.git] / arch / x86 / kernel / apic / apic_numachip.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Numascale NumaConnect-Specific APIC Code
 *
 * Copyright (C) 2011 Numascale AS. All rights reserved.
 *
 * Send feedback to <support@numascale.com>
 *
 */

#include <linux/errno.h>
#include <linux/threads.h>
#include <linux/cpumask.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/hardirq.h>
#include <linux/delay.h>

#include <asm/numachip/numachip_csr.h>
#include <asm/smp.h>
#include <asm/apic.h>
#include <asm/ipi.h>
#include <asm/apic_flat_64.h>

static int numachip_system __read_mostly;

static struct apic apic_numachip __read_mostly;

static unsigned int get_apic_id(unsigned long x)
{
	unsigned long value;
	unsigned int id;

	rdmsrl(MSR_FAM10H_NODE_ID, value);
	id = ((x >> 24) & 0xffU) | ((value << 2) & 0x3f00U);

	return id;
}

static unsigned long set_apic_id(unsigned int id)
{
	unsigned long x;

	x = ((id & 0xffU) << 24);
	return x;
}

static unsigned int read_xapic_id(void)
{
	return get_apic_id(apic_read(APIC_ID));
}

static int numachip_apic_id_valid(int apicid)
{
	/* Trust what bootloader passes in MADT */
	return 1;
}

static int numachip_apic_id_registered(void)
{
	return physid_isset(read_xapic_id(), phys_cpu_present_map);
}

static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
{
	return initial_apic_id >> index_msb;
}

static void numachip_vector_allocation_domain(int cpu, struct cpumask *retmask)
{
	cpumask_clear(retmask);
	cpumask_set_cpu(cpu, retmask);
}

static int __cpuinit numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
{
	union numachip_csr_g3_ext_irq_gen int_gen;

	int_gen.s._destination_apic_id = phys_apicid;
	int_gen.s._vector = 0;
	int_gen.s._msgtype = APIC_DM_INIT >> 8;
	int_gen.s._index = 0;

	write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);

	int_gen.s._msgtype = APIC_DM_STARTUP >> 8;
	int_gen.s._vector = start_rip >> 12;

	write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);

	atomic_set(&init_deasserted, 1);
	return 0;
}

static void numachip_send_IPI_one(int cpu, int vector)
{
	union numachip_csr_g3_ext_irq_gen int_gen;
	int apicid = per_cpu(x86_cpu_to_apicid, cpu);

	int_gen.s._destination_apic_id = apicid;
	int_gen.s._vector = vector;
	int_gen.s._msgtype = (vector == NMI_VECTOR ? APIC_DM_NMI : APIC_DM_FIXED) >> 8;
	int_gen.s._index = 0;

	write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
}

static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
{
	unsigned int cpu;

	for_each_cpu(cpu, mask)
		numachip_send_IPI_one(cpu, vector);
}

static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
						int vector)
{
	unsigned int this_cpu = smp_processor_id();
	unsigned int cpu;

	for_each_cpu(cpu, mask) {
		if (cpu != this_cpu)
			numachip_send_IPI_one(cpu, vector);
	}
}

static void numachip_send_IPI_allbutself(int vector)
{
	unsigned int this_cpu = smp_processor_id();
	unsigned int cpu;

	for_each_online_cpu(cpu) {
		if (cpu != this_cpu)
			numachip_send_IPI_one(cpu, vector);
	}
}

static void numachip_send_IPI_all(int vector)
{
	numachip_send_IPI_mask(cpu_online_mask, vector);
}

static void numachip_send_IPI_self(int vector)
{
	__default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
}

static int __init numachip_probe(void)
{
	return apic == &apic_numachip;
}

static void __init map_csrs(void)
{
	printk(KERN_INFO "NumaChip: Mapping local CSR space (%016llx - %016llx)\n",
		NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_BASE + NUMACHIP_LCSR_SIZE - 1);
	init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);

	printk(KERN_INFO "NumaChip: Mapping global CSR space (%016llx - %016llx)\n",
		NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_BASE + NUMACHIP_GCSR_SIZE - 1);
	init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE);
}

static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
{

	if (c->phys_proc_id != node) {
		c->phys_proc_id = node;
		per_cpu(cpu_llc_id, smp_processor_id()) = node;
	}
}

static int __init numachip_system_init(void)
{
	unsigned int val;

	if (!numachip_system)
		return 0;

	x86_cpuinit.fixup_cpu_id = fixup_cpu_id;

	map_csrs();

	val = read_lcsr(CSR_G0_NODE_IDS);
	printk(KERN_INFO "NumaChip: Local NodeID = %08x\n", val);

	return 0;
}
early_initcall(numachip_system_init);

static int numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
	if (!strncmp(oem_id, "NUMASC", 6)) {
		numachip_system = 1;
		return 1;
	}

	return 0;
}

static struct apic apic_numachip __refconst = {

	.name				= "NumaConnect system",
	.probe				= numachip_probe,
	.acpi_madt_oem_check		= numachip_acpi_madt_oem_check,
	.apic_id_valid			= numachip_apic_id_valid,
	.apic_id_registered		= numachip_apic_id_registered,

	.irq_delivery_mode		= dest_Fixed,
	.irq_dest_mode			= 0, /* physical */

	.target_cpus			= online_target_cpus,
	.disable_esr			= 0,
	.dest_logical			= 0,
	.check_apicid_used		= NULL,
	.check_apicid_present		= NULL,

	.vector_allocation_domain	= numachip_vector_allocation_domain,
	.init_apic_ldr			= flat_init_apic_ldr,

	.ioapic_phys_id_map		= NULL,
	.setup_apic_routing		= NULL,
	.multi_timer_check		= NULL,
	.cpu_present_to_apicid		= default_cpu_present_to_apicid,
	.apicid_to_cpu_present		= NULL,
	.setup_portio_remap		= NULL,
	.check_phys_apicid_present	= default_check_phys_apicid_present,
	.enable_apic_mode		= NULL,
	.phys_pkg_id			= numachip_phys_pkg_id,
	.mps_oem_check			= NULL,

	.get_apic_id			= get_apic_id,
	.set_apic_id			= set_apic_id,
	.apic_id_mask			= 0xffU << 24,

	.cpu_mask_to_apicid		= default_cpu_mask_to_apicid,
	.cpu_mask_to_apicid_and		= default_cpu_mask_to_apicid_and,

	.send_IPI_mask			= numachip_send_IPI_mask,
	.send_IPI_mask_allbutself	= numachip_send_IPI_mask_allbutself,
	.send_IPI_allbutself		= numachip_send_IPI_allbutself,
	.send_IPI_all			= numachip_send_IPI_all,
	.send_IPI_self			= numachip_send_IPI_self,

	.wakeup_secondary_cpu		= numachip_wakeup_secondary,
	.trampoline_phys_low		= DEFAULT_TRAMPOLINE_PHYS_LOW,
	.trampoline_phys_high		= DEFAULT_TRAMPOLINE_PHYS_HIGH,
	.wait_for_init_deassert		= NULL,
	.smp_callin_clear_local_apic	= NULL,
	.inquire_remote_apic		= NULL, /* REMRD not supported */

	.read				= native_apic_mem_read,
	.write				= native_apic_mem_write,
	.eoi_write			= native_apic_mem_write,
	.icr_read			= native_apic_icr_read,
	.icr_write			= native_apic_icr_write,
	.wait_icr_idle			= native_apic_wait_icr_idle,
	.safe_wait_icr_idle		= native_safe_apic_wait_icr_idle,
};
apic_driver(apic_numachip);
Commit	Line	Data
44b111b5 SP	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Numascale NumaConnect-Specific APIC Code
	7	*
	8	* Copyright (C) 2011 Numascale AS. All rights reserved.
	9	*
	10	* Send feedback to <support@numascale.com>
	11	*
	12	*/
	13
	14	#include <linux/errno.h>
	15	#include <linux/threads.h>
	16	#include <linux/cpumask.h>
	17	#include <linux/string.h>
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
	20	#include <linux/ctype.h>
	21	#include <linux/init.h>
	22	#include <linux/hardirq.h>
	23	#include <linux/delay.h>
	24
	25	#include <asm/numachip/numachip_csr.h>
	26	#include <asm/smp.h>
	27	#include <asm/apic.h>
	28	#include <asm/ipi.h>
	29	#include <asm/apic_flat_64.h>
	30
	31	static int numachip_system __read_mostly;
	32
	33	static struct apic apic_numachip __read_mostly;
	34
	35	static unsigned int get_apic_id(unsigned long x)
	36	{
	37	unsigned long value;
	38	unsigned int id;
	39
	40	rdmsrl(MSR_FAM10H_NODE_ID, value);
	41	id = ((x >> 24) & 0xffU) \| ((value << 2) & 0x3f00U);
	42
	43	return id;
	44	}
	45
	46	static unsigned long set_apic_id(unsigned int id)
	47	{
	48	unsigned long x;
	49
	50	x = ((id & 0xffU) << 24);
	51	return x;
	52	}
	53
	54	static unsigned int read_xapic_id(void)
	55	{
	56	return get_apic_id(apic_read(APIC_ID));
	57	}
	58
fa63030e DB	59	static int numachip_apic_id_valid(int apicid)
	60	{
	61	/* Trust what bootloader passes in MADT */
	62	return 1;
	63	}
	64
44b111b5 SP	65	static int numachip_apic_id_registered(void)
	66	{
	67	return physid_isset(read_xapic_id(), phys_cpu_present_map);
	68	}
	69
	70	static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
	71	{
	72	return initial_apic_id >> index_msb;
	73	}
	74
44b111b5 SP	75	static void numachip_vector_allocation_domain(int cpu, struct cpumask *retmask)
	76	{
	77	cpumask_clear(retmask);
	78	cpumask_set_cpu(cpu, retmask);
	79	}
	80
	81	static int __cpuinit numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
	82	{
	83	union numachip_csr_g3_ext_irq_gen int_gen;
	84
	85	int_gen.s._destination_apic_id = phys_apicid;
	86	int_gen.s._vector = 0;
	87	int_gen.s._msgtype = APIC_DM_INIT >> 8;
	88	int_gen.s._index = 0;
	89
	90	write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
	91
	92	int_gen.s._msgtype = APIC_DM_STARTUP >> 8;
	93	int_gen.s._vector = start_rip >> 12;
	94
	95	write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
	96
	97	atomic_set(&init_deasserted, 1);
	98	return 0;
	99	}
	100
	101	static void numachip_send_IPI_one(int cpu, int vector)
	102	{
	103	union numachip_csr_g3_ext_irq_gen int_gen;
	104	int apicid = per_cpu(x86_cpu_to_apicid, cpu);
	105
	106	int_gen.s._destination_apic_id = apicid;
	107	int_gen.s._vector = vector;
	108	int_gen.s._msgtype = (vector == NMI_VECTOR ? APIC_DM_NMI : APIC_DM_FIXED) >> 8;
	109	int_gen.s._index = 0;
	110
	111	write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
	112	}
	113
	114	static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
	115	{
	116	unsigned int cpu;
	117
	118	for_each_cpu(cpu, mask)
	119	numachip_send_IPI_one(cpu, vector);
	120	}
	121
	122	static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
	123	int vector)
	124	{
	125	unsigned int this_cpu = smp_processor_id();
	126	unsigned int cpu;
	127
	128	for_each_cpu(cpu, mask) {
	129	if (cpu != this_cpu)
	130	numachip_send_IPI_one(cpu, vector);
	131	}
	132	}
	133
	134	static void numachip_send_IPI_allbutself(int vector)
	135	{
	136	unsigned int this_cpu = smp_processor_id();
	137	unsigned int cpu;
	138
139	for_each_online_cpu(cpu) {
140	if (cpu != this_cpu)
141	numachip_send_IPI_one(cpu, vector);
142	}
143	}
144
145	static void numachip_send_IPI_all(int vector)
146	{
147	numachip_send_IPI_mask(cpu_online_mask, vector);
148	}
149
150	static void numachip_send_IPI_self(int vector)
151	{
152	__default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
153	}
154
44b111b5 SP	155	static int __init numachip_probe(void)
	156	{
	157	return apic == &apic_numachip;
	158	}
	159
	160	static void __init map_csrs(void)
	161	{
	162	printk(KERN_INFO "NumaChip: Mapping local CSR space (%016llx - %016llx)\n",
	163	NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_BASE + NUMACHIP_LCSR_SIZE - 1);
	164	init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
	165
	166	printk(KERN_INFO "NumaChip: Mapping global CSR space (%016llx - %016llx)\n",
	167	NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_BASE + NUMACHIP_GCSR_SIZE - 1);
	168	init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE);
	169	}
	170
	171	static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
	172	{
68894632 AH	173
	174	if (c->phys_proc_id != node) {
	175	c->phys_proc_id = node;
	176	per_cpu(cpu_llc_id, smp_processor_id()) = node;
	177	}
44b111b5 SP	178	}
	179
	180	static int __init numachip_system_init(void)
	181	{
	182	unsigned int val;
	183
	184	if (!numachip_system)
	185	return 0;
	186
	187	x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
	188
	189	map_csrs();
	190
	191	val = read_lcsr(CSR_G0_NODE_IDS);
	192	printk(KERN_INFO "NumaChip: Local NodeID = %08x\n", val);
	193
	194	return 0;
	195	}
	196	early_initcall(numachip_system_init);
	197
b7157acf	198	static int numachip_acpi_madt_oem_check(char oem_id, char oem_table_id)
44b111b5 SP	199	{
	200	if (!strncmp(oem_id, "NUMASC", 6)) {
	201	numachip_system = 1;
	202	return 1;
	203	}
	204
	205	return 0;
	206	}
	207
	208	static struct apic apic_numachip __refconst = {
	209
	210	.name = "NumaConnect system",
	211	.probe = numachip_probe,
	212	.acpi_madt_oem_check = numachip_acpi_madt_oem_check,
fa63030e	213	.apic_id_valid = numachip_apic_id_valid,
44b111b5 SP	214	.apic_id_registered = numachip_apic_id_registered,
	215
	216	.irq_delivery_mode = dest_Fixed,
	217	.irq_dest_mode = 0, /* physical */
	218
bf721d3a	219	.target_cpus = online_target_cpus,
44b111b5 SP	220	.disable_esr = 0,
	221	.dest_logical = 0,
	222	.check_apicid_used = NULL,
	223	.check_apicid_present = NULL,
	224
	225	.vector_allocation_domain = numachip_vector_allocation_domain,
	226	.init_apic_ldr = flat_init_apic_ldr,
	227
	228	.ioapic_phys_id_map = NULL,
	229	.setup_apic_routing = NULL,
	230	.multi_timer_check = NULL,
	231	.cpu_present_to_apicid = default_cpu_present_to_apicid,
	232	.apicid_to_cpu_present = NULL,
	233	.setup_portio_remap = NULL,
	234	.check_phys_apicid_present = default_check_phys_apicid_present,
	235	.enable_apic_mode = NULL,
	236	.phys_pkg_id = numachip_phys_pkg_id,
	237	.mps_oem_check = NULL,
	238
	239	.get_apic_id = get_apic_id,
	240	.set_apic_id = set_apic_id,
	241	.apic_id_mask = 0xffU << 24,
	242
6398268d AG	243	.cpu_mask_to_apicid = default_cpu_mask_to_apicid,
6398268d AG	244	.cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and,
44b111b5 SP	245
	246	.send_IPI_mask = numachip_send_IPI_mask,
	247	.send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
	248	.send_IPI_allbutself = numachip_send_IPI_allbutself,
	249	.send_IPI_all = numachip_send_IPI_all,
	250	.send_IPI_self = numachip_send_IPI_self,
	251
	252	.wakeup_secondary_cpu = numachip_wakeup_secondary,
	253	.trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
	254	.trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
	255	.wait_for_init_deassert = NULL,
	256	.smp_callin_clear_local_apic = NULL,
	257	.inquire_remote_apic = NULL, /* REMRD not supported */
	258
	259	.read = native_apic_mem_read,
	260	.write = native_apic_mem_write,
2a43195d	261	.eoi_write = native_apic_mem_write,
44b111b5 SP	262	.icr_read = native_apic_icr_read,
	263	.icr_write = native_apic_icr_write,
	264	.wait_icr_idle = native_apic_wait_icr_idle,
	265	.safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
	266	};
	267	apic_driver(apic_numachip);
	268