Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
d7f3d478 | 34 | #include <linux/irqdomain.h> |
3b7d1921 | 35 | #include <linux/msi.h> |
95d77884 | 36 | #include <linux/htirq.h> |
7dfb7103 | 37 | #include <linux/freezer.h> |
f26d6a2b | 38 | #include <linux/kthread.h> |
54168ed7 | 39 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 40 | #include <linux/slab.h> |
d4057bdb YL |
41 | #include <linux/bootmem.h> |
42 | #include <linux/dmar.h> | |
58ac1e76 | 43 | #include <linux/hpet.h> |
54d5d424 | 44 | |
d4057bdb | 45 | #include <asm/idle.h> |
1da177e4 LT |
46 | #include <asm/io.h> |
47 | #include <asm/smp.h> | |
6d652ea1 | 48 | #include <asm/cpu.h> |
1da177e4 | 49 | #include <asm/desc.h> |
d4057bdb YL |
50 | #include <asm/proto.h> |
51 | #include <asm/acpi.h> | |
52 | #include <asm/dma.h> | |
1da177e4 | 53 | #include <asm/timer.h> |
306e440d | 54 | #include <asm/i8259.h> |
2d3fcc1c | 55 | #include <asm/msidef.h> |
8b955b0d | 56 | #include <asm/hypertransport.h> |
a4dbc34d | 57 | #include <asm/setup.h> |
8a8f422d | 58 | #include <asm/irq_remapping.h> |
58ac1e76 | 59 | #include <asm/hpet.h> |
2c1b284e | 60 | #include <asm/hw_irq.h> |
1da177e4 | 61 | |
7b6aa335 | 62 | #include <asm/apic.h> |
1da177e4 | 63 | |
32f71aff | 64 | #define __apicdebuginit(type) static type __init |
136d249e | 65 | |
f44d1692 JL |
66 | #define for_each_ioapic(idx) \ |
67 | for ((idx) = 0; (idx) < nr_ioapics; (idx)++) | |
68 | #define for_each_ioapic_reverse(idx) \ | |
69 | for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--) | |
70 | #define for_each_pin(idx, pin) \ | |
71 | for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++) | |
72 | #define for_each_ioapic_pin(idx, pin) \ | |
73 | for_each_ioapic((idx)) \ | |
74 | for_each_pin((idx), (pin)) | |
75 | ||
2977fb3f CG |
76 | #define for_each_irq_pin(entry, head) \ |
77 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 78 | |
1da177e4 | 79 | /* |
54168ed7 IM |
80 | * Is the SiS APIC rmw bug present ? |
81 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
82 | */ |
83 | int sis_apic_bug = -1; | |
84 | ||
dade7716 TG |
85 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
86 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
d7f3d478 | 87 | static DEFINE_MUTEX(ioapic_mutex); |
44767bfa | 88 | static unsigned int ioapic_dynirq_base; |
b81975ea | 89 | static int ioapic_initialized; |
efa2559f | 90 | |
15a3c7cc JL |
91 | struct mp_pin_info { |
92 | int trigger; | |
93 | int polarity; | |
94 | int node; | |
95 | int set; | |
96 | u32 count; | |
97 | }; | |
98 | ||
b69c6c3b SS |
99 | static struct ioapic { |
100 | /* | |
101 | * # of IRQ routing registers | |
102 | */ | |
103 | int nr_registers; | |
57a6f740 SS |
104 | /* |
105 | * Saved state during suspend/resume, or while enabling intr-remap. | |
106 | */ | |
107 | struct IO_APIC_route_entry *saved_registers; | |
d5371430 SS |
108 | /* I/O APIC config */ |
109 | struct mpc_ioapic mp_config; | |
c040aaeb SS |
110 | /* IO APIC gsi routing info */ |
111 | struct mp_ioapic_gsi gsi_config; | |
d7f3d478 JL |
112 | struct ioapic_domain_cfg irqdomain_cfg; |
113 | struct irq_domain *irqdomain; | |
15a3c7cc | 114 | struct mp_pin_info *pin_info; |
b69c6c3b | 115 | } ioapics[MAX_IO_APICS]; |
1da177e4 | 116 | |
6f50d45f | 117 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
d5371430 | 118 | |
6f50d45f | 119 | int mpc_ioapic_id(int ioapic_idx) |
d5371430 | 120 | { |
6f50d45f | 121 | return ioapics[ioapic_idx].mp_config.apicid; |
d5371430 SS |
122 | } |
123 | ||
6f50d45f | 124 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
d5371430 | 125 | { |
6f50d45f | 126 | return ioapics[ioapic_idx].mp_config.apicaddr; |
d5371430 SS |
127 | } |
128 | ||
6f50d45f | 129 | struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
c040aaeb | 130 | { |
6f50d45f | 131 | return &ioapics[ioapic_idx].gsi_config; |
c040aaeb | 132 | } |
9f640ccb | 133 | |
18e48551 JL |
134 | static inline int mp_ioapic_pin_count(int ioapic) |
135 | { | |
136 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
137 | ||
138 | return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; | |
139 | } | |
140 | ||
141 | u32 mp_pin_to_gsi(int ioapic, int pin) | |
142 | { | |
143 | return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; | |
144 | } | |
145 | ||
95d76acc JL |
146 | /* |
147 | * Initialize all legacy IRQs and all pins on the first IOAPIC | |
148 | * if we have legacy interrupt controller. Kernel boot option "pirq=" | |
149 | * may rely on non-legacy pins on the first IOAPIC. | |
150 | */ | |
18e48551 JL |
151 | static inline int mp_init_irq_at_boot(int ioapic, int irq) |
152 | { | |
95d76acc JL |
153 | if (!nr_legacy_irqs()) |
154 | return 0; | |
155 | ||
156 | return ioapic == 0 || (irq >= 0 && irq < nr_legacy_irqs()); | |
18e48551 JL |
157 | } |
158 | ||
15a3c7cc JL |
159 | static inline struct mp_pin_info *mp_pin_info(int ioapic_idx, int pin) |
160 | { | |
161 | return ioapics[ioapic_idx].pin_info + pin; | |
162 | } | |
163 | ||
d7f3d478 JL |
164 | static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic) |
165 | { | |
166 | return ioapics[ioapic].irqdomain; | |
167 | } | |
168 | ||
c040aaeb | 169 | int nr_ioapics; |
2a4ab640 | 170 | |
a4384df3 EB |
171 | /* The one past the highest gsi number used */ |
172 | u32 gsi_top; | |
5777372a | 173 | |
584f734d | 174 | /* MP IRQ source entries */ |
c2c21745 | 175 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
176 | |
177 | /* # of MP IRQ source entries */ | |
178 | int mp_irq_entries; | |
179 | ||
bb8187d3 | 180 | #ifdef CONFIG_EISA |
8732fc4b AS |
181 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
182 | #endif | |
183 | ||
184 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
185 | ||
efa2559f YL |
186 | int skip_ioapic_setup; |
187 | ||
7167d08e HK |
188 | /** |
189 | * disable_ioapic_support() - disables ioapic support at runtime | |
190 | */ | |
191 | void disable_ioapic_support(void) | |
65a4e574 IM |
192 | { |
193 | #ifdef CONFIG_PCI | |
194 | noioapicquirk = 1; | |
195 | noioapicreroute = -1; | |
196 | #endif | |
197 | skip_ioapic_setup = 1; | |
198 | } | |
199 | ||
54168ed7 | 200 | static int __init parse_noapic(char *str) |
efa2559f YL |
201 | { |
202 | /* disable IO-APIC */ | |
7167d08e | 203 | disable_ioapic_support(); |
efa2559f YL |
204 | return 0; |
205 | } | |
206 | early_param("noapic", parse_noapic); | |
66759a01 | 207 | |
4b92b4f7 | 208 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node); |
710dcda6 | 209 | |
2d8009ba FT |
210 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
211 | void mp_save_irq(struct mpc_intsrc *m) | |
212 | { | |
213 | int i; | |
214 | ||
215 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
216 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
217 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
218 | m->srcbusirq, m->dstapic, m->dstirq); | |
219 | ||
220 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 221 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
222 | return; |
223 | } | |
224 | ||
0e3fa13f | 225 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
226 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
227 | panic("Max # of irq sources exceeded!!\n"); | |
228 | } | |
229 | ||
0b8f1efa YL |
230 | struct irq_pin_list { |
231 | int apic, pin; | |
232 | struct irq_pin_list *next; | |
233 | }; | |
234 | ||
7e495529 | 235 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 236 | { |
2ee39065 | 237 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
0b8f1efa YL |
238 | } |
239 | ||
13a0c3c2 | 240 | int __init arch_early_irq_init(void) |
8f09cd20 | 241 | { |
0b8f1efa | 242 | struct irq_cfg *cfg; |
4b92b4f7 | 243 | int i, node = cpu_to_node(0); |
d6c88a50 | 244 | |
95d76acc | 245 | if (!nr_legacy_irqs()) |
1f91233c | 246 | io_apic_irqs = ~0UL; |
1f91233c | 247 | |
f44d1692 | 248 | for_each_ioapic(i) { |
57a6f740 | 249 | ioapics[i].saved_registers = |
4c79185c | 250 | kzalloc(sizeof(struct IO_APIC_route_entry) * |
b69c6c3b | 251 | ioapics[i].nr_registers, GFP_KERNEL); |
57a6f740 | 252 | if (!ioapics[i].saved_registers) |
4c79185c SS |
253 | pr_err("IOAPIC %d: suspend/resume impossible!\n", i); |
254 | } | |
255 | ||
4b92b4f7 JL |
256 | /* |
257 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
258 | * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's. | |
259 | */ | |
260 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
261 | cfg = alloc_irq_and_cfg_at(i, node); | |
262 | cfg->vector = IRQ0_VECTOR + i; | |
263 | cpumask_setall(cfg->domain); | |
0b8f1efa | 264 | } |
13a0c3c2 YL |
265 | |
266 | return 0; | |
0b8f1efa | 267 | } |
8f09cd20 | 268 | |
32f5ef5d | 269 | static inline struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 270 | { |
2c778651 | 271 | return irq_get_chip_data(irq); |
8f09cd20 | 272 | } |
d6c88a50 | 273 | |
f981a3dc | 274 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
8f09cd20 | 275 | { |
0b8f1efa | 276 | struct irq_cfg *cfg; |
0f978f45 | 277 | |
2ee39065 | 278 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); |
6e2fff50 TG |
279 | if (!cfg) |
280 | return NULL; | |
2ee39065 | 281 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) |
6e2fff50 | 282 | goto out_cfg; |
2ee39065 | 283 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) |
6e2fff50 | 284 | goto out_domain; |
0b8f1efa | 285 | return cfg; |
6e2fff50 TG |
286 | out_domain: |
287 | free_cpumask_var(cfg->domain); | |
288 | out_cfg: | |
289 | kfree(cfg); | |
290 | return NULL; | |
8f09cd20 YL |
291 | } |
292 | ||
f981a3dc | 293 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) |
08c33db6 | 294 | { |
fbc6bff0 TG |
295 | if (!cfg) |
296 | return; | |
2c778651 | 297 | irq_set_chip_data(at, NULL); |
08c33db6 TG |
298 | free_cpumask_var(cfg->domain); |
299 | free_cpumask_var(cfg->old_domain); | |
300 | kfree(cfg); | |
301 | } | |
302 | ||
08c33db6 TG |
303 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) |
304 | { | |
305 | int res = irq_alloc_desc_at(at, node); | |
306 | struct irq_cfg *cfg; | |
307 | ||
308 | if (res < 0) { | |
309 | if (res != -EEXIST) | |
310 | return NULL; | |
32f5ef5d | 311 | cfg = irq_cfg(at); |
08c33db6 TG |
312 | if (cfg) |
313 | return cfg; | |
314 | } | |
315 | ||
f981a3dc | 316 | cfg = alloc_irq_cfg(at, node); |
08c33db6 | 317 | if (cfg) |
2c778651 | 318 | irq_set_chip_data(at, cfg); |
08c33db6 TG |
319 | else |
320 | irq_free_desc(at); | |
321 | return cfg; | |
322 | } | |
323 | ||
130fe05d LT |
324 | struct io_apic { |
325 | unsigned int index; | |
326 | unsigned int unused[3]; | |
327 | unsigned int data; | |
0280f7c4 SS |
328 | unsigned int unused2[11]; |
329 | unsigned int eoi; | |
130fe05d LT |
330 | }; |
331 | ||
332 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
333 | { | |
334 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
d5371430 | 335 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
130fe05d LT |
336 | } |
337 | ||
da165322 | 338 | void io_apic_eoi(unsigned int apic, unsigned int vector) |
0280f7c4 SS |
339 | { |
340 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
341 | writel(vector, &io_apic->eoi); | |
342 | } | |
343 | ||
4a8e2a31 | 344 | unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) |
130fe05d LT |
345 | { |
346 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
347 | writel(reg, &io_apic->index); | |
348 | return readl(&io_apic->data); | |
349 | } | |
350 | ||
4a8e2a31 | 351 | void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d LT |
352 | { |
353 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
136d249e | 354 | |
130fe05d LT |
355 | writel(reg, &io_apic->index); |
356 | writel(value, &io_apic->data); | |
357 | } | |
358 | ||
359 | /* | |
360 | * Re-write a value: to be used for read-modify-write | |
361 | * cycles where the read already set up the index register. | |
362 | * | |
363 | * Older SiS APIC requires we rewrite the index register | |
364 | */ | |
4a8e2a31 | 365 | void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d | 366 | { |
54168ed7 | 367 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
368 | |
369 | if (sis_apic_bug) | |
370 | writel(reg, &io_apic->index); | |
130fe05d LT |
371 | writel(value, &io_apic->data); |
372 | } | |
373 | ||
cf4c6a2f AK |
374 | union entry_union { |
375 | struct { u32 w1, w2; }; | |
376 | struct IO_APIC_route_entry entry; | |
377 | }; | |
378 | ||
e57253a8 SS |
379 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
380 | { | |
381 | union entry_union eu; | |
382 | ||
383 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
384 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
136d249e | 385 | |
e57253a8 SS |
386 | return eu.entry; |
387 | } | |
388 | ||
cf4c6a2f AK |
389 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
390 | { | |
391 | union entry_union eu; | |
392 | unsigned long flags; | |
136d249e | 393 | |
dade7716 | 394 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
e57253a8 | 395 | eu.entry = __ioapic_read_entry(apic, pin); |
dade7716 | 396 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
136d249e | 397 | |
cf4c6a2f AK |
398 | return eu.entry; |
399 | } | |
400 | ||
f9dadfa7 LT |
401 | /* |
402 | * When we write a new IO APIC routing entry, we need to write the high | |
403 | * word first! If the mask bit in the low word is clear, we will enable | |
404 | * the interrupt, and we need to make sure the entry is fully populated | |
405 | * before that happens. | |
406 | */ | |
136d249e | 407 | static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
cf4c6a2f | 408 | { |
50a8d4d2 F |
409 | union entry_union eu = {{0, 0}}; |
410 | ||
cf4c6a2f | 411 | eu.entry = e; |
f9dadfa7 LT |
412 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
413 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
414 | } |
415 | ||
1a8ce7ff | 416 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
417 | { |
418 | unsigned long flags; | |
136d249e | 419 | |
dade7716 | 420 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 421 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 422 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
423 | } |
424 | ||
425 | /* | |
426 | * When we mask an IO APIC routing entry, we need to write the low | |
427 | * word first, in order to set the mask bit before we change the | |
428 | * high bits! | |
429 | */ | |
430 | static void ioapic_mask_entry(int apic, int pin) | |
431 | { | |
432 | unsigned long flags; | |
433 | union entry_union eu = { .entry.mask = 1 }; | |
434 | ||
dade7716 | 435 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
436 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
437 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 438 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
439 | } |
440 | ||
1da177e4 LT |
441 | /* |
442 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
443 | * shared ISA-space IRQs, so we have to support them. We are super | |
444 | * fast in the common case, and fast for shared ISA-space IRQs. | |
445 | */ | |
136d249e | 446 | static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 447 | { |
2977fb3f | 448 | struct irq_pin_list **last, *entry; |
0f978f45 | 449 | |
2977fb3f CG |
450 | /* don't allow duplicates */ |
451 | last = &cfg->irq_2_pin; | |
452 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 453 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 454 | return 0; |
2977fb3f | 455 | last = &entry->next; |
1da177e4 | 456 | } |
0f978f45 | 457 | |
7e495529 | 458 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 459 | if (!entry) { |
c767a54b JP |
460 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
461 | node, apic, pin); | |
f3d1915a | 462 | return -ENOMEM; |
a7428cd2 | 463 | } |
1da177e4 LT |
464 | entry->apic = apic; |
465 | entry->pin = pin; | |
875e68ec | 466 | |
2977fb3f | 467 | *last = entry; |
f3d1915a CG |
468 | return 0; |
469 | } | |
470 | ||
df334bea JL |
471 | static void __remove_pin_from_irq(struct irq_cfg *cfg, int apic, int pin) |
472 | { | |
473 | struct irq_pin_list **last, *entry; | |
474 | ||
475 | last = &cfg->irq_2_pin; | |
476 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
477 | if (entry->apic == apic && entry->pin == pin) { | |
478 | *last = entry->next; | |
479 | kfree(entry); | |
480 | return; | |
481 | } else { | |
482 | last = &entry->next; | |
483 | } | |
484 | } | |
485 | ||
f3d1915a CG |
486 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
487 | { | |
7e495529 | 488 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 489 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
490 | } |
491 | ||
492 | /* | |
493 | * Reroute an IRQ to a different pin. | |
494 | */ | |
85ac16d0 | 495 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
496 | int oldapic, int oldpin, |
497 | int newapic, int newpin) | |
1da177e4 | 498 | { |
535b6429 | 499 | struct irq_pin_list *entry; |
1da177e4 | 500 | |
2977fb3f | 501 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
502 | if (entry->apic == oldapic && entry->pin == oldpin) { |
503 | entry->apic = newapic; | |
504 | entry->pin = newpin; | |
0f978f45 | 505 | /* every one is different, right? */ |
4eea6fff | 506 | return; |
0f978f45 | 507 | } |
1da177e4 | 508 | } |
0f978f45 | 509 | |
4eea6fff JF |
510 | /* old apic/pin didn't exist, so just add new ones */ |
511 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
512 | } |
513 | ||
c29d9db3 SS |
514 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
515 | int mask_and, int mask_or, | |
516 | void (*final)(struct irq_pin_list *entry)) | |
517 | { | |
518 | unsigned int reg, pin; | |
519 | ||
520 | pin = entry->pin; | |
521 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
522 | reg &= mask_and; | |
523 | reg |= mask_or; | |
524 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
525 | if (final) | |
526 | final(entry); | |
527 | } | |
528 | ||
2f210deb JF |
529 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
530 | int mask_and, int mask_or, | |
531 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 532 | { |
87783be4 | 533 | struct irq_pin_list *entry; |
047c8fdb | 534 | |
c29d9db3 SS |
535 | for_each_irq_pin(entry, cfg->irq_2_pin) |
536 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
537 | } | |
538 | ||
7f3e632f | 539 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 540 | { |
87783be4 CG |
541 | /* |
542 | * Synchronize the IO-APIC and the CPU by doing | |
543 | * a dummy read from the IO-APIC | |
544 | */ | |
545 | struct io_apic __iomem *io_apic; | |
136d249e | 546 | |
87783be4 | 547 | io_apic = io_apic_base(entry->apic); |
4e738e2f | 548 | readl(&io_apic->data); |
1da177e4 LT |
549 | } |
550 | ||
dd5f15e5 | 551 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 552 | { |
dd5f15e5 TG |
553 | unsigned long flags; |
554 | ||
555 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 556 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 557 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 558 | } |
1da177e4 | 559 | |
90297c5f | 560 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 561 | { |
90297c5f | 562 | mask_ioapic(data->chip_data); |
dd5f15e5 | 563 | } |
3145e941 | 564 | |
dd5f15e5 TG |
565 | static void __unmask_ioapic(struct irq_cfg *cfg) |
566 | { | |
567 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
568 | } |
569 | ||
dd5f15e5 | 570 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
571 | { |
572 | unsigned long flags; | |
573 | ||
dade7716 | 574 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 575 | __unmask_ioapic(cfg); |
dade7716 | 576 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
577 | } |
578 | ||
90297c5f | 579 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 580 | { |
90297c5f | 581 | unmask_ioapic(data->chip_data); |
3145e941 YL |
582 | } |
583 | ||
c0205701 SS |
584 | /* |
585 | * IO-APIC versions below 0x20 don't support EOI register. | |
586 | * For the record, here is the information about various versions: | |
587 | * 0Xh 82489DX | |
588 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
589 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
590 | * 30h-FFh Reserved | |
591 | * | |
592 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
593 | * version as 0x2. This is an error with documentation and these ICH chips | |
594 | * use io-apic's of version 0x20. | |
595 | * | |
596 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
597 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
598 | * mode to edge and then back to level, with RTE being masked during this. | |
599 | */ | |
da165322 | 600 | void native_eoi_ioapic_pin(int apic, int pin, int vector) |
c0205701 SS |
601 | { |
602 | if (mpc_ioapic_ver(apic) >= 0x20) { | |
da165322 | 603 | io_apic_eoi(apic, vector); |
c0205701 SS |
604 | } else { |
605 | struct IO_APIC_route_entry entry, entry1; | |
606 | ||
607 | entry = entry1 = __ioapic_read_entry(apic, pin); | |
608 | ||
609 | /* | |
610 | * Mask the entry and change the trigger mode to edge. | |
611 | */ | |
612 | entry1.mask = 1; | |
613 | entry1.trigger = IOAPIC_EDGE; | |
614 | ||
615 | __ioapic_write_entry(apic, pin, entry1); | |
616 | ||
617 | /* | |
618 | * Restore the previous level triggered entry. | |
619 | */ | |
620 | __ioapic_write_entry(apic, pin, entry); | |
621 | } | |
622 | } | |
623 | ||
9b1b0e42 | 624 | void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
c0205701 SS |
625 | { |
626 | struct irq_pin_list *entry; | |
627 | unsigned long flags; | |
628 | ||
629 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
630 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
da165322 JR |
631 | x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin, |
632 | cfg->vector); | |
c0205701 SS |
633 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
634 | } | |
635 | ||
1da177e4 LT |
636 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
637 | { | |
638 | struct IO_APIC_route_entry entry; | |
36062448 | 639 | |
1da177e4 | 640 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 641 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
642 | if (entry.delivery_mode == dest_SMI) |
643 | return; | |
1e75b31d | 644 | |
1da177e4 | 645 | /* |
1e75b31d SS |
646 | * Make sure the entry is masked and re-read the contents to check |
647 | * if it is a level triggered pin and if the remote-IRR is set. | |
648 | */ | |
649 | if (!entry.mask) { | |
650 | entry.mask = 1; | |
651 | ioapic_write_entry(apic, pin, entry); | |
652 | entry = ioapic_read_entry(apic, pin); | |
653 | } | |
654 | ||
655 | if (entry.irr) { | |
c0205701 SS |
656 | unsigned long flags; |
657 | ||
1e75b31d SS |
658 | /* |
659 | * Make sure the trigger mode is set to level. Explicit EOI | |
660 | * doesn't clear the remote-IRR if the trigger mode is not | |
661 | * set to level. | |
662 | */ | |
663 | if (!entry.trigger) { | |
664 | entry.trigger = IOAPIC_LEVEL; | |
665 | ioapic_write_entry(apic, pin, entry); | |
666 | } | |
667 | ||
c0205701 | 668 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
da165322 | 669 | x86_io_apic_ops.eoi_ioapic_pin(apic, pin, entry.vector); |
c0205701 | 670 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1e75b31d SS |
671 | } |
672 | ||
673 | /* | |
674 | * Clear the rest of the bits in the IO-APIC RTE except for the mask | |
675 | * bit. | |
1da177e4 | 676 | */ |
f9dadfa7 | 677 | ioapic_mask_entry(apic, pin); |
1e75b31d SS |
678 | entry = ioapic_read_entry(apic, pin); |
679 | if (entry.irr) | |
c767a54b | 680 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
1e75b31d | 681 | mpc_ioapic_id(apic), pin); |
1da177e4 LT |
682 | } |
683 | ||
54168ed7 | 684 | static void clear_IO_APIC (void) |
1da177e4 LT |
685 | { |
686 | int apic, pin; | |
687 | ||
f44d1692 JL |
688 | for_each_ioapic_pin(apic, pin) |
689 | clear_IO_APIC_pin(apic, pin); | |
1da177e4 LT |
690 | } |
691 | ||
54168ed7 | 692 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
693 | /* |
694 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
695 | * specific CPU-side IRQs. | |
696 | */ | |
697 | ||
698 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
699 | static int pirq_entries[MAX_PIRQS] = { |
700 | [0 ... MAX_PIRQS - 1] = -1 | |
701 | }; | |
1da177e4 | 702 | |
1da177e4 LT |
703 | static int __init ioapic_pirq_setup(char *str) |
704 | { | |
705 | int i, max; | |
706 | int ints[MAX_PIRQS+1]; | |
707 | ||
708 | get_options(str, ARRAY_SIZE(ints), ints); | |
709 | ||
1da177e4 LT |
710 | apic_printk(APIC_VERBOSE, KERN_INFO |
711 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
712 | max = MAX_PIRQS; | |
713 | if (ints[0] < MAX_PIRQS) | |
714 | max = ints[0]; | |
715 | ||
716 | for (i = 0; i < max; i++) { | |
717 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
718 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
719 | /* | |
720 | * PIRQs are mapped upside down, usually. | |
721 | */ | |
722 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
723 | } | |
724 | return 1; | |
725 | } | |
726 | ||
727 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
728 | #endif /* CONFIG_X86_32 */ |
729 | ||
54168ed7 | 730 | /* |
05c3dc2c | 731 | * Saves all the IO-APIC RTE's |
54168ed7 | 732 | */ |
31dce14a | 733 | int save_ioapic_entries(void) |
54168ed7 | 734 | { |
54168ed7 | 735 | int apic, pin; |
31dce14a | 736 | int err = 0; |
54168ed7 | 737 | |
f44d1692 | 738 | for_each_ioapic(apic) { |
57a6f740 | 739 | if (!ioapics[apic].saved_registers) { |
31dce14a SS |
740 | err = -ENOMEM; |
741 | continue; | |
742 | } | |
54168ed7 | 743 | |
f44d1692 | 744 | for_each_pin(apic, pin) |
57a6f740 | 745 | ioapics[apic].saved_registers[pin] = |
54168ed7 | 746 | ioapic_read_entry(apic, pin); |
b24696bc | 747 | } |
5ffa4eb2 | 748 | |
31dce14a | 749 | return err; |
54168ed7 IM |
750 | } |
751 | ||
b24696bc FY |
752 | /* |
753 | * Mask all IO APIC entries. | |
754 | */ | |
31dce14a | 755 | void mask_ioapic_entries(void) |
05c3dc2c SS |
756 | { |
757 | int apic, pin; | |
758 | ||
f44d1692 | 759 | for_each_ioapic(apic) { |
2f344d2e | 760 | if (!ioapics[apic].saved_registers) |
31dce14a | 761 | continue; |
b24696bc | 762 | |
f44d1692 | 763 | for_each_pin(apic, pin) { |
05c3dc2c SS |
764 | struct IO_APIC_route_entry entry; |
765 | ||
57a6f740 | 766 | entry = ioapics[apic].saved_registers[pin]; |
05c3dc2c SS |
767 | if (!entry.mask) { |
768 | entry.mask = 1; | |
769 | ioapic_write_entry(apic, pin, entry); | |
770 | } | |
771 | } | |
772 | } | |
773 | } | |
774 | ||
b24696bc | 775 | /* |
57a6f740 | 776 | * Restore IO APIC entries which was saved in the ioapic structure. |
b24696bc | 777 | */ |
31dce14a | 778 | int restore_ioapic_entries(void) |
54168ed7 IM |
779 | { |
780 | int apic, pin; | |
781 | ||
f44d1692 | 782 | for_each_ioapic(apic) { |
2f344d2e | 783 | if (!ioapics[apic].saved_registers) |
31dce14a | 784 | continue; |
b24696bc | 785 | |
f44d1692 | 786 | for_each_pin(apic, pin) |
54168ed7 | 787 | ioapic_write_entry(apic, pin, |
57a6f740 | 788 | ioapics[apic].saved_registers[pin]); |
5ffa4eb2 | 789 | } |
b24696bc | 790 | return 0; |
54168ed7 IM |
791 | } |
792 | ||
1da177e4 LT |
793 | /* |
794 | * Find the IRQ entry number of a certain pin. | |
795 | */ | |
6f50d45f | 796 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
1da177e4 LT |
797 | { |
798 | int i; | |
799 | ||
800 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 | 801 | if (mp_irqs[i].irqtype == type && |
6f50d45f | 802 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
c2c21745 JSR |
803 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
804 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
805 | return i; |
806 | ||
807 | return -1; | |
808 | } | |
809 | ||
810 | /* | |
811 | * Find the pin to which IRQ[irq] (ISA) is connected | |
812 | */ | |
fcfd636a | 813 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
814 | { |
815 | int i; | |
816 | ||
817 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 818 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 819 | |
d27e2b8e | 820 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
821 | (mp_irqs[i].irqtype == type) && |
822 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 823 | |
c2c21745 | 824 | return mp_irqs[i].dstirq; |
1da177e4 LT |
825 | } |
826 | return -1; | |
827 | } | |
828 | ||
fcfd636a EB |
829 | static int __init find_isa_irq_apic(int irq, int type) |
830 | { | |
831 | int i; | |
832 | ||
833 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 834 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 835 | |
73b2961b | 836 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
837 | (mp_irqs[i].irqtype == type) && |
838 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
839 | break; |
840 | } | |
6f50d45f | 841 | |
fcfd636a | 842 | if (i < mp_irq_entries) { |
6f50d45f YL |
843 | int ioapic_idx; |
844 | ||
f44d1692 | 845 | for_each_ioapic(ioapic_idx) |
6f50d45f YL |
846 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) |
847 | return ioapic_idx; | |
fcfd636a EB |
848 | } |
849 | ||
850 | return -1; | |
851 | } | |
852 | ||
bb8187d3 | 853 | #ifdef CONFIG_EISA |
1da177e4 LT |
854 | /* |
855 | * EISA Edge/Level control register, ELCR | |
856 | */ | |
857 | static int EISA_ELCR(unsigned int irq) | |
858 | { | |
95d76acc | 859 | if (irq < nr_legacy_irqs()) { |
1da177e4 LT |
860 | unsigned int port = 0x4d0 + (irq >> 3); |
861 | return (inb(port) >> (irq & 7)) & 1; | |
862 | } | |
863 | apic_printk(APIC_VERBOSE, KERN_INFO | |
864 | "Broken MPtable reports ISA irq %d\n", irq); | |
865 | return 0; | |
866 | } | |
54168ed7 | 867 | |
c0a282c2 | 868 | #endif |
1da177e4 | 869 | |
6728801d AS |
870 | /* ISA interrupts are always polarity zero edge triggered, |
871 | * when listed as conforming in the MP table. */ | |
872 | ||
873 | #define default_ISA_trigger(idx) (0) | |
874 | #define default_ISA_polarity(idx) (0) | |
875 | ||
1da177e4 LT |
876 | /* EISA interrupts are always polarity zero and can be edge or level |
877 | * trigger depending on the ELCR value. If an interrupt is listed as | |
878 | * EISA conforming in the MP table, that means its trigger type must | |
879 | * be read in from the ELCR */ | |
880 | ||
c2c21745 | 881 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 882 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
883 | |
884 | /* PCI interrupts are always polarity one level triggered, | |
885 | * when listed as conforming in the MP table. */ | |
886 | ||
887 | #define default_PCI_trigger(idx) (1) | |
888 | #define default_PCI_polarity(idx) (1) | |
889 | ||
b77cf6a8 | 890 | static int irq_polarity(int idx) |
1da177e4 | 891 | { |
c2c21745 | 892 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
893 | int polarity; |
894 | ||
895 | /* | |
896 | * Determine IRQ line polarity (high active or low active): | |
897 | */ | |
c2c21745 | 898 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 899 | { |
54168ed7 IM |
900 | case 0: /* conforms, ie. bus-type dependent polarity */ |
901 | if (test_bit(bus, mp_bus_not_pci)) | |
902 | polarity = default_ISA_polarity(idx); | |
903 | else | |
904 | polarity = default_PCI_polarity(idx); | |
905 | break; | |
906 | case 1: /* high active */ | |
907 | { | |
908 | polarity = 0; | |
909 | break; | |
910 | } | |
911 | case 2: /* reserved */ | |
912 | { | |
c767a54b | 913 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
914 | polarity = 1; |
915 | break; | |
916 | } | |
917 | case 3: /* low active */ | |
918 | { | |
919 | polarity = 1; | |
920 | break; | |
921 | } | |
922 | default: /* invalid */ | |
923 | { | |
c767a54b | 924 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
925 | polarity = 1; |
926 | break; | |
927 | } | |
1da177e4 LT |
928 | } |
929 | return polarity; | |
930 | } | |
931 | ||
b77cf6a8 | 932 | static int irq_trigger(int idx) |
1da177e4 | 933 | { |
c2c21745 | 934 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
935 | int trigger; |
936 | ||
937 | /* | |
938 | * Determine IRQ trigger mode (edge or level sensitive): | |
939 | */ | |
c2c21745 | 940 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 941 | { |
54168ed7 IM |
942 | case 0: /* conforms, ie. bus-type dependent */ |
943 | if (test_bit(bus, mp_bus_not_pci)) | |
944 | trigger = default_ISA_trigger(idx); | |
945 | else | |
946 | trigger = default_PCI_trigger(idx); | |
bb8187d3 | 947 | #ifdef CONFIG_EISA |
54168ed7 IM |
948 | switch (mp_bus_id_to_type[bus]) { |
949 | case MP_BUS_ISA: /* ISA pin */ | |
950 | { | |
951 | /* set before the switch */ | |
952 | break; | |
953 | } | |
954 | case MP_BUS_EISA: /* EISA pin */ | |
955 | { | |
956 | trigger = default_EISA_trigger(idx); | |
957 | break; | |
958 | } | |
959 | case MP_BUS_PCI: /* PCI pin */ | |
960 | { | |
961 | /* set before the switch */ | |
962 | break; | |
963 | } | |
54168ed7 IM |
964 | default: |
965 | { | |
c767a54b | 966 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
967 | trigger = 1; |
968 | break; | |
969 | } | |
970 | } | |
971 | #endif | |
1da177e4 | 972 | break; |
54168ed7 | 973 | case 1: /* edge */ |
1da177e4 | 974 | { |
54168ed7 | 975 | trigger = 0; |
1da177e4 LT |
976 | break; |
977 | } | |
54168ed7 | 978 | case 2: /* reserved */ |
1da177e4 | 979 | { |
c767a54b | 980 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 981 | trigger = 1; |
1da177e4 LT |
982 | break; |
983 | } | |
54168ed7 | 984 | case 3: /* level */ |
1da177e4 | 985 | { |
54168ed7 | 986 | trigger = 1; |
1da177e4 LT |
987 | break; |
988 | } | |
54168ed7 | 989 | default: /* invalid */ |
1da177e4 | 990 | { |
c767a54b | 991 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 992 | trigger = 0; |
1da177e4 LT |
993 | break; |
994 | } | |
995 | } | |
996 | return trigger; | |
997 | } | |
998 | ||
d7f3d478 | 999 | static int alloc_irq_from_domain(struct irq_domain *domain, u32 gsi, int pin) |
6b9fb708 | 1000 | { |
d7f3d478 JL |
1001 | int irq = -1; |
1002 | int ioapic = (int)(long)domain->host_data; | |
1003 | int type = ioapics[ioapic].irqdomain_cfg.type; | |
1004 | ||
1005 | switch (type) { | |
1006 | case IOAPIC_DOMAIN_LEGACY: | |
1007 | /* | |
1008 | * Dynamically allocate IRQ number for non-ISA IRQs in the first 16 | |
1009 | * GSIs on some weird platforms. | |
1010 | */ | |
1011 | if (gsi < nr_legacy_irqs()) | |
1012 | irq = irq_create_mapping(domain, pin); | |
1013 | else if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0) | |
1014 | irq = gsi; | |
1015 | break; | |
1016 | case IOAPIC_DOMAIN_STRICT: | |
1017 | if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0) | |
1018 | irq = gsi; | |
1019 | break; | |
1020 | case IOAPIC_DOMAIN_DYNAMIC: | |
1021 | irq = irq_create_mapping(domain, pin); | |
1022 | break; | |
1023 | default: | |
1024 | WARN(1, "ioapic: unknown irqdomain type %d\n", type); | |
1025 | break; | |
1026 | } | |
1027 | ||
1028 | return irq > 0 ? irq : -1; | |
1029 | } | |
1030 | ||
1031 | static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, | |
1032 | unsigned int flags) | |
1033 | { | |
1034 | int irq; | |
1035 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); | |
15a3c7cc | 1036 | struct mp_pin_info *info = mp_pin_info(ioapic, pin); |
d7f3d478 | 1037 | |
b81975ea JL |
1038 | if (!domain) |
1039 | return -1; | |
16ee7b3d JL |
1040 | |
1041 | mutex_lock(&ioapic_mutex); | |
1042 | ||
6b9fb708 | 1043 | /* |
d7f3d478 JL |
1044 | * Don't use irqdomain to manage ISA IRQs because there may be |
1045 | * multiple IOAPIC pins sharing the same ISA IRQ number and | |
1046 | * irqdomain only supports 1:1 mapping between IOAPIC pin and | |
1047 | * IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are used | |
1048 | * for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H). | |
1049 | * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are | |
1050 | * available, and some BIOSes may use MP Interrupt Source records | |
1051 | * to override IRQ numbers for PIRQs instead of reprogramming | |
1052 | * the interrupt routing logic. Thus there may be multiple pins | |
1053 | * sharing the same legacy IRQ number when ACPI is disabled. | |
6b9fb708 | 1054 | */ |
16ee7b3d JL |
1055 | if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) { |
1056 | irq = mp_irqs[idx].srcbusirq; | |
1057 | if (flags & IOAPIC_MAP_ALLOC) { | |
1058 | if (info->count == 0 && | |
1059 | mp_irqdomain_map(domain, irq, pin) != 0) | |
1060 | irq = -1; | |
1061 | ||
1062 | /* special handling for timer IRQ0 */ | |
1063 | if (irq == 0) | |
1064 | info->count++; | |
1065 | } | |
1066 | } else { | |
1067 | irq = irq_find_mapping(domain, pin); | |
1068 | if (irq <= 0 && (flags & IOAPIC_MAP_ALLOC)) | |
1069 | irq = alloc_irq_from_domain(domain, gsi, pin); | |
d7f3d478 JL |
1070 | } |
1071 | ||
15a3c7cc | 1072 | if (flags & IOAPIC_MAP_ALLOC) { |
f395dcae JL |
1073 | /* special handling for legacy IRQs */ |
1074 | if (irq < nr_legacy_irqs() && info->count == 1 && | |
1075 | mp_irqdomain_map(domain, irq, pin) != 0) | |
1076 | irq = -1; | |
1077 | ||
15a3c7cc JL |
1078 | if (irq > 0) |
1079 | info->count++; | |
1080 | else if (info->count == 0) | |
1081 | info->set = 0; | |
1082 | } | |
16ee7b3d | 1083 | |
d7f3d478 JL |
1084 | mutex_unlock(&ioapic_mutex); |
1085 | ||
1086 | return irq > 0 ? irq : -1; | |
6b9fb708 JL |
1087 | } |
1088 | ||
d7f3d478 | 1089 | static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags) |
1da177e4 | 1090 | { |
d7f3d478 | 1091 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
1da177e4 LT |
1092 | |
1093 | /* | |
1094 | * Debugging check, we are in big trouble if this message pops up! | |
1095 | */ | |
c2c21745 | 1096 | if (mp_irqs[idx].dstirq != pin) |
c767a54b | 1097 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
1da177e4 | 1098 | |
54168ed7 | 1099 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1100 | /* |
1101 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1102 | */ | |
1103 | if ((pin >= 16) && (pin <= 23)) { | |
1104 | if (pirq_entries[pin-16] != -1) { | |
1105 | if (!pirq_entries[pin-16]) { | |
1106 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1107 | "disabling PIRQ%d\n", pin-16); | |
1108 | } else { | |
d7f3d478 | 1109 | int irq = pirq_entries[pin-16]; |
1da177e4 LT |
1110 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
1111 | "using PIRQ%d -> IRQ %d\n", | |
1112 | pin-16, irq); | |
6b9fb708 | 1113 | return irq; |
1da177e4 LT |
1114 | } |
1115 | } | |
1116 | } | |
54168ed7 IM |
1117 | #endif |
1118 | ||
d7f3d478 JL |
1119 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags); |
1120 | } | |
6b9fb708 | 1121 | |
d7f3d478 JL |
1122 | int mp_map_gsi_to_irq(u32 gsi, unsigned int flags) |
1123 | { | |
1124 | int ioapic, pin, idx; | |
1125 | ||
1126 | ioapic = mp_find_ioapic(gsi); | |
1127 | if (ioapic < 0) | |
1128 | return -1; | |
1129 | ||
1130 | pin = mp_find_ioapic_pin(ioapic, gsi); | |
1131 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1132 | if ((flags & IOAPIC_MAP_CHECK) && idx < 0) | |
1133 | return -1; | |
1134 | ||
1135 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags); | |
1da177e4 LT |
1136 | } |
1137 | ||
df334bea JL |
1138 | void mp_unmap_irq(int irq) |
1139 | { | |
1140 | struct irq_data *data = irq_get_irq_data(irq); | |
1141 | struct mp_pin_info *info; | |
1142 | int ioapic, pin; | |
1143 | ||
1144 | if (!data || !data->domain) | |
1145 | return; | |
1146 | ||
1147 | ioapic = (int)(long)data->domain->host_data; | |
1148 | pin = (int)data->hwirq; | |
1149 | info = mp_pin_info(ioapic, pin); | |
1150 | ||
1151 | mutex_lock(&ioapic_mutex); | |
1152 | if (--info->count == 0) { | |
1153 | info->set = 0; | |
1154 | if (irq < nr_legacy_irqs() && | |
1155 | ioapics[ioapic].irqdomain_cfg.type == IOAPIC_DOMAIN_LEGACY) | |
1156 | mp_irqdomain_unmap(data->domain, irq); | |
1157 | else | |
1158 | irq_dispose_mapping(irq); | |
1159 | } | |
1160 | mutex_unlock(&ioapic_mutex); | |
1161 | } | |
1162 | ||
e20c06fd YL |
1163 | /* |
1164 | * Find a specific PCI IRQ entry. | |
1165 | * Not an __init, possibly needed by modules | |
1166 | */ | |
1167 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1168 | struct io_apic_irq_attr *irq_attr) |
e20c06fd | 1169 | { |
d7f3d478 | 1170 | int irq, i, best_ioapic = -1, best_idx = -1; |
e20c06fd YL |
1171 | |
1172 | apic_printk(APIC_DEBUG, | |
1173 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1174 | bus, slot, pin); | |
1175 | if (test_bit(bus, mp_bus_not_pci)) { | |
1176 | apic_printk(APIC_VERBOSE, | |
1177 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1178 | return -1; | |
1179 | } | |
79598505 | 1180 | |
e20c06fd YL |
1181 | for (i = 0; i < mp_irq_entries; i++) { |
1182 | int lbus = mp_irqs[i].srcbus; | |
79598505 JL |
1183 | int ioapic_idx, found = 0; |
1184 | ||
1185 | if (bus != lbus || mp_irqs[i].irqtype != mp_INT || | |
1186 | slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f)) | |
1187 | continue; | |
e20c06fd | 1188 | |
f44d1692 | 1189 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1190 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || |
79598505 JL |
1191 | mp_irqs[i].dstapic == MP_APIC_ALL) { |
1192 | found = 1; | |
e20c06fd | 1193 | break; |
e20c06fd | 1194 | } |
79598505 JL |
1195 | if (!found) |
1196 | continue; | |
1197 | ||
1198 | /* Skip ISA IRQs */ | |
d7f3d478 JL |
1199 | irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0); |
1200 | if (irq > 0 && !IO_APIC_IRQ(irq)) | |
79598505 JL |
1201 | continue; |
1202 | ||
1203 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
d7f3d478 JL |
1204 | best_idx = i; |
1205 | best_ioapic = ioapic_idx; | |
1206 | goto out; | |
79598505 | 1207 | } |
d7f3d478 | 1208 | |
79598505 JL |
1209 | /* |
1210 | * Use the first all-but-pin matching entry as a | |
1211 | * best-guess fuzzy result for broken mptables. | |
1212 | */ | |
d7f3d478 JL |
1213 | if (best_idx < 0) { |
1214 | best_idx = i; | |
1215 | best_ioapic = ioapic_idx; | |
e20c06fd YL |
1216 | } |
1217 | } | |
d7f3d478 JL |
1218 | if (best_idx < 0) |
1219 | return -1; | |
1220 | ||
1221 | out: | |
1222 | irq = pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, | |
1223 | IOAPIC_MAP_ALLOC); | |
1224 | if (irq > 0) | |
1225 | set_io_apic_irq_attr(irq_attr, best_ioapic, | |
1226 | mp_irqs[best_idx].dstirq, | |
1227 | irq_trigger(best_idx), | |
1228 | irq_polarity(best_idx)); | |
1229 | return irq; | |
e20c06fd YL |
1230 | } |
1231 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1232 | ||
497c9a19 YL |
1233 | void lock_vector_lock(void) |
1234 | { | |
1235 | /* Used to the online set of cpus does not change | |
1236 | * during assign_irq_vector. | |
1237 | */ | |
dade7716 | 1238 | raw_spin_lock(&vector_lock); |
497c9a19 | 1239 | } |
1da177e4 | 1240 | |
497c9a19 | 1241 | void unlock_vector_lock(void) |
1da177e4 | 1242 | { |
dade7716 | 1243 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1244 | } |
1da177e4 | 1245 | |
e7986739 MT |
1246 | static int |
1247 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1248 | { |
047c8fdb YL |
1249 | /* |
1250 | * NOTE! The local APIC isn't very good at handling | |
1251 | * multiple interrupts at the same interrupt level. | |
1252 | * As the interrupt level is determined by taking the | |
1253 | * vector number and shifting that right by 4, we | |
1254 | * want to spread these out a bit so that they don't | |
1255 | * all fall in the same interrupt level. | |
1256 | * | |
1257 | * Also, we've got to be careful not to trash gate | |
1258 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1259 | */ | |
6579b474 | 1260 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
1bccd58b | 1261 | static int current_offset = VECTOR_OFFSET_START % 16; |
22f65d31 MT |
1262 | int cpu, err; |
1263 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1264 | |
23359a88 | 1265 | if (cfg->move_in_progress) |
54168ed7 | 1266 | return -EBUSY; |
0a1ad60d | 1267 | |
22f65d31 MT |
1268 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1269 | return -ENOMEM; | |
ace80ab7 | 1270 | |
e7986739 | 1271 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 | 1272 | err = -ENOSPC; |
b39f25a8 SS |
1273 | cpumask_clear(cfg->old_domain); |
1274 | cpu = cpumask_first_and(mask, cpu_online_mask); | |
1275 | while (cpu < nr_cpu_ids) { | |
1ac322d0 | 1276 | int new_cpu, vector, offset; |
497c9a19 | 1277 | |
1ac322d0 | 1278 | apic->vector_allocation_domain(cpu, tmp_mask, mask); |
497c9a19 | 1279 | |
332afa65 | 1280 | if (cpumask_subset(tmp_mask, cfg->domain)) { |
1ac322d0 SS |
1281 | err = 0; |
1282 | if (cpumask_equal(tmp_mask, cfg->domain)) | |
1283 | break; | |
1284 | /* | |
1285 | * New cpumask using the vector is a proper subset of | |
1286 | * the current in use mask. So cleanup the vector | |
1287 | * allocation for the members that are not used anymore. | |
1288 | */ | |
1289 | cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask); | |
29c574c0 SS |
1290 | cfg->move_in_progress = |
1291 | cpumask_intersects(cfg->old_domain, cpu_online_mask); | |
1ac322d0 SS |
1292 | cpumask_and(cfg->domain, cfg->domain, tmp_mask); |
1293 | break; | |
332afa65 | 1294 | } |
497c9a19 | 1295 | |
54168ed7 IM |
1296 | vector = current_vector; |
1297 | offset = current_offset; | |
497c9a19 | 1298 | next: |
1bccd58b | 1299 | vector += 16; |
54168ed7 | 1300 | if (vector >= first_system_vector) { |
1bccd58b | 1301 | offset = (offset + 1) % 16; |
6579b474 | 1302 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 | 1303 | } |
8637e38a AG |
1304 | |
1305 | if (unlikely(current_vector == vector)) { | |
b39f25a8 SS |
1306 | cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask); |
1307 | cpumask_andnot(tmp_mask, mask, cfg->old_domain); | |
1308 | cpu = cpumask_first_and(tmp_mask, cpu_online_mask); | |
54168ed7 | 1309 | continue; |
8637e38a | 1310 | } |
b77b881f YL |
1311 | |
1312 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1313 | goto next; |
b77b881f | 1314 | |
9345005f PB |
1315 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) { |
1316 | if (per_cpu(vector_irq, new_cpu)[vector] > VECTOR_UNDEFINED) | |
54168ed7 | 1317 | goto next; |
9345005f | 1318 | } |
54168ed7 IM |
1319 | /* Found one! */ |
1320 | current_vector = vector; | |
1321 | current_offset = offset; | |
1ac322d0 | 1322 | if (cfg->vector) { |
22f65d31 | 1323 | cpumask_copy(cfg->old_domain, cfg->domain); |
29c574c0 SS |
1324 | cfg->move_in_progress = |
1325 | cpumask_intersects(cfg->old_domain, cpu_online_mask); | |
7a959cff | 1326 | } |
22f65d31 | 1327 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1328 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1329 | cfg->vector = vector; | |
22f65d31 MT |
1330 | cpumask_copy(cfg->domain, tmp_mask); |
1331 | err = 0; | |
1332 | break; | |
54168ed7 | 1333 | } |
22f65d31 MT |
1334 | free_cpumask_var(tmp_mask); |
1335 | return err; | |
497c9a19 YL |
1336 | } |
1337 | ||
9338ad6f | 1338 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1339 | { |
1340 | int err; | |
ace80ab7 | 1341 | unsigned long flags; |
ace80ab7 | 1342 | |
dade7716 | 1343 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1344 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1345 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1346 | return err; |
1347 | } | |
1348 | ||
3145e941 | 1349 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1350 | { |
497c9a19 YL |
1351 | int cpu, vector; |
1352 | ||
497c9a19 YL |
1353 | BUG_ON(!cfg->vector); |
1354 | ||
1355 | vector = cfg->vector; | |
1d44b30f | 1356 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
9345005f | 1357 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
497c9a19 YL |
1358 | |
1359 | cfg->vector = 0; | |
22f65d31 | 1360 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1361 | |
1362 | if (likely(!cfg->move_in_progress)) | |
1363 | return; | |
1d44b30f | 1364 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
9345005f | 1365 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { |
0ca4b6b0 MW |
1366 | if (per_cpu(vector_irq, cpu)[vector] != irq) |
1367 | continue; | |
9345005f | 1368 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
0ca4b6b0 MW |
1369 | break; |
1370 | } | |
1371 | } | |
1372 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1373 | } |
1374 | ||
1375 | void __setup_vector_irq(int cpu) | |
1376 | { | |
1377 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1378 | int irq, vector; |
1379 | struct irq_cfg *cfg; | |
1380 | ||
9d133e5d SS |
1381 | /* |
1382 | * vector_lock will make sure that we don't run into irq vector | |
1383 | * assignments that might be happening on another cpu in parallel, | |
1384 | * while we setup our initial vector to irq mappings. | |
1385 | */ | |
dade7716 | 1386 | raw_spin_lock(&vector_lock); |
497c9a19 | 1387 | /* Mark the inuse vectors */ |
ad9f4334 | 1388 | for_each_active_irq(irq) { |
32f5ef5d | 1389 | cfg = irq_cfg(irq); |
ad9f4334 TG |
1390 | if (!cfg) |
1391 | continue; | |
36e9e1ea | 1392 | |
22f65d31 | 1393 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1394 | continue; |
1395 | vector = cfg->vector; | |
497c9a19 YL |
1396 | per_cpu(vector_irq, cpu)[vector] = irq; |
1397 | } | |
1398 | /* Mark the free vectors */ | |
1399 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1400 | irq = per_cpu(vector_irq, cpu)[vector]; | |
9345005f | 1401 | if (irq <= VECTOR_UNDEFINED) |
497c9a19 YL |
1402 | continue; |
1403 | ||
1404 | cfg = irq_cfg(irq); | |
22f65d31 | 1405 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
9345005f | 1406 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
54168ed7 | 1407 | } |
dade7716 | 1408 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1409 | } |
3fde6900 | 1410 | |
f5b9ed7a | 1411 | static struct irq_chip ioapic_chip; |
1da177e4 | 1412 | |
047c8fdb | 1413 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1414 | static inline int IO_APIC_irq_trigger(int irq) |
1415 | { | |
d6c88a50 | 1416 | int apic, idx, pin; |
1d025192 | 1417 | |
f44d1692 JL |
1418 | for_each_ioapic_pin(apic, pin) { |
1419 | idx = find_irq_entry(apic, pin, mp_INT); | |
d7f3d478 | 1420 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0))) |
f44d1692 | 1421 | return irq_trigger(idx); |
d6c88a50 TG |
1422 | } |
1423 | /* | |
54168ed7 IM |
1424 | * nonexistent IRQs are edge default |
1425 | */ | |
d6c88a50 | 1426 | return 0; |
1d025192 | 1427 | } |
047c8fdb YL |
1428 | #else |
1429 | static inline int IO_APIC_irq_trigger(int irq) | |
1430 | { | |
54168ed7 | 1431 | return 1; |
047c8fdb YL |
1432 | } |
1433 | #endif | |
1d025192 | 1434 | |
1a0e62a4 TG |
1435 | static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, |
1436 | unsigned long trigger) | |
1da177e4 | 1437 | { |
c60eaf25 TG |
1438 | struct irq_chip *chip = &ioapic_chip; |
1439 | irq_flow_handler_t hdl; | |
1440 | bool fasteoi; | |
199751d7 | 1441 | |
6ebcc00e | 1442 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
c60eaf25 | 1443 | trigger == IOAPIC_LEVEL) { |
60c69948 | 1444 | irq_set_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1445 | fasteoi = true; |
1446 | } else { | |
60c69948 | 1447 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1448 | fasteoi = false; |
1449 | } | |
047c8fdb | 1450 | |
2976fd84 | 1451 | if (setup_remapped_irq(irq, cfg, chip)) |
c60eaf25 | 1452 | fasteoi = trigger != 0; |
29b61be6 | 1453 | |
c60eaf25 TG |
1454 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
1455 | irq_set_chip_and_handler_name(irq, chip, hdl, | |
1456 | fasteoi ? "fasteoi" : "edge"); | |
1da177e4 LT |
1457 | } |
1458 | ||
a6a25dd3 JR |
1459 | int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
1460 | unsigned int destination, int vector, | |
1461 | struct io_apic_irq_attr *attr) | |
c5b4712c | 1462 | { |
c5b4712c YL |
1463 | memset(entry, 0, sizeof(*entry)); |
1464 | ||
1465 | entry->delivery_mode = apic->irq_delivery_mode; | |
1466 | entry->dest_mode = apic->irq_dest_mode; | |
1467 | entry->dest = destination; | |
1468 | entry->vector = vector; | |
1469 | entry->mask = 0; /* enable IRQ */ | |
1470 | entry->trigger = attr->trigger; | |
1471 | entry->polarity = attr->polarity; | |
1472 | ||
1473 | /* | |
1474 | * Mask level triggered irqs. | |
497c9a19 YL |
1475 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. |
1476 | */ | |
c5b4712c | 1477 | if (attr->trigger) |
497c9a19 | 1478 | entry->mask = 1; |
c5b4712c | 1479 | |
497c9a19 YL |
1480 | return 0; |
1481 | } | |
1482 | ||
e4aff811 YL |
1483 | static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg, |
1484 | struct io_apic_irq_attr *attr) | |
497c9a19 | 1485 | { |
1da177e4 | 1486 | struct IO_APIC_route_entry entry; |
22f65d31 | 1487 | unsigned int dest; |
497c9a19 YL |
1488 | |
1489 | if (!IO_APIC_IRQ(irq)) | |
1490 | return; | |
f1c63001 | 1491 | |
fe402e1f | 1492 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1493 | return; |
1494 | ||
ff164324 AG |
1495 | if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(), |
1496 | &dest)) { | |
1497 | pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n", | |
1498 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); | |
1499 | __clear_irq_vector(irq, cfg); | |
1500 | ||
1501 | return; | |
1502 | } | |
497c9a19 YL |
1503 | |
1504 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1505 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
7fece832 | 1506 | "IRQ %d Mode:%i Active:%i Dest:%d)\n", |
e4aff811 YL |
1507 | attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin, |
1508 | cfg->vector, irq, attr->trigger, attr->polarity, dest); | |
497c9a19 | 1509 | |
a6a25dd3 JR |
1510 | if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) { |
1511 | pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
c5b4712c | 1512 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); |
3145e941 | 1513 | __clear_irq_vector(irq, cfg); |
c5b4712c | 1514 | |
497c9a19 YL |
1515 | return; |
1516 | } | |
1517 | ||
e4aff811 | 1518 | ioapic_register_intr(irq, cfg, attr->trigger); |
95d76acc | 1519 | if (irq < nr_legacy_irqs()) |
4305df94 | 1520 | legacy_pic->mask(irq); |
497c9a19 | 1521 | |
e4aff811 | 1522 | ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry); |
497c9a19 YL |
1523 | } |
1524 | ||
ed972ccf TG |
1525 | static void __init setup_IO_APIC_irqs(void) |
1526 | { | |
16ee7b3d JL |
1527 | unsigned int ioapic, pin; |
1528 | int idx; | |
ed972ccf TG |
1529 | |
1530 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1531 | ||
16ee7b3d JL |
1532 | for_each_ioapic_pin(ioapic, pin) { |
1533 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1534 | if (idx < 0) | |
1535 | apic_printk(APIC_VERBOSE, | |
1536 | KERN_DEBUG " apic %d pin %d not connected\n", | |
1537 | mpc_ioapic_id(ioapic), pin); | |
1538 | else | |
1539 | pin_2_irq(idx, ioapic, pin, | |
1540 | ioapic ? 0 : IOAPIC_MAP_ALLOC); | |
1541 | } | |
ed972ccf TG |
1542 | } |
1543 | ||
1da177e4 | 1544 | /* |
f7633ce5 | 1545 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1546 | */ |
6f50d45f | 1547 | static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx, |
49d0c7a0 | 1548 | unsigned int pin, int vector) |
1da177e4 LT |
1549 | { |
1550 | struct IO_APIC_route_entry entry; | |
ff164324 | 1551 | unsigned int dest; |
1da177e4 | 1552 | |
36062448 | 1553 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1554 | |
1555 | /* | |
1556 | * We use logical delivery to get the timer IRQ | |
1557 | * to the first CPU. | |
1558 | */ | |
a5a39156 AG |
1559 | if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(), |
1560 | apic->target_cpus(), &dest))) | |
ff164324 AG |
1561 | dest = BAD_APICID; |
1562 | ||
9b5bc8dc | 1563 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1564 | entry.mask = 0; /* don't mask IRQ for edge */ |
ff164324 | 1565 | entry.dest = dest; |
9b5bc8dc | 1566 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1567 | entry.polarity = 0; |
1568 | entry.trigger = 0; | |
1569 | entry.vector = vector; | |
1570 | ||
1571 | /* | |
1572 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1573 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1574 | */ |
2c778651 TG |
1575 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
1576 | "edge"); | |
1da177e4 LT |
1577 | |
1578 | /* | |
1579 | * Add it to the IO-APIC irq-routing table: | |
1580 | */ | |
6f50d45f | 1581 | ioapic_write_entry(ioapic_idx, pin, entry); |
1da177e4 LT |
1582 | } |
1583 | ||
afcc8a40 JR |
1584 | void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries) |
1585 | { | |
1586 | int i; | |
1587 | ||
1588 | pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n"); | |
1589 | ||
1590 | for (i = 0; i <= nr_entries; i++) { | |
1591 | struct IO_APIC_route_entry entry; | |
1592 | ||
1593 | entry = ioapic_read_entry(apic, i); | |
1594 | ||
1595 | pr_debug(" %02x %02X ", i, entry.dest); | |
1596 | pr_cont("%1d %1d %1d %1d %1d " | |
1597 | "%1d %1d %02X\n", | |
1598 | entry.mask, | |
1599 | entry.trigger, | |
1600 | entry.irr, | |
1601 | entry.polarity, | |
1602 | entry.delivery_status, | |
1603 | entry.dest_mode, | |
1604 | entry.delivery_mode, | |
1605 | entry.vector); | |
1606 | } | |
1607 | } | |
1608 | ||
1609 | void intel_ir_io_apic_print_entries(unsigned int apic, | |
1610 | unsigned int nr_entries) | |
1da177e4 | 1611 | { |
cda417dd | 1612 | int i; |
afcc8a40 JR |
1613 | |
1614 | pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n"); | |
1615 | ||
1616 | for (i = 0; i <= nr_entries; i++) { | |
1617 | struct IR_IO_APIC_route_entry *ir_entry; | |
1618 | struct IO_APIC_route_entry entry; | |
1619 | ||
1620 | entry = ioapic_read_entry(apic, i); | |
1621 | ||
1622 | ir_entry = (struct IR_IO_APIC_route_entry *)&entry; | |
1623 | ||
1624 | pr_debug(" %02x %04X ", i, ir_entry->index); | |
1625 | pr_cont("%1d %1d %1d %1d %1d " | |
1626 | "%1d %1d %X %02X\n", | |
1627 | ir_entry->format, | |
1628 | ir_entry->mask, | |
1629 | ir_entry->trigger, | |
1630 | ir_entry->irr, | |
1631 | ir_entry->polarity, | |
1632 | ir_entry->delivery_status, | |
1633 | ir_entry->index2, | |
1634 | ir_entry->zero, | |
1635 | ir_entry->vector); | |
1636 | } | |
1637 | } | |
1638 | ||
17405453 YY |
1639 | void ioapic_zap_locks(void) |
1640 | { | |
1641 | raw_spin_lock_init(&ioapic_lock); | |
1642 | } | |
1643 | ||
afcc8a40 JR |
1644 | __apicdebuginit(void) print_IO_APIC(int ioapic_idx) |
1645 | { | |
1da177e4 LT |
1646 | union IO_APIC_reg_00 reg_00; |
1647 | union IO_APIC_reg_01 reg_01; | |
1648 | union IO_APIC_reg_02 reg_02; | |
1649 | union IO_APIC_reg_03 reg_03; | |
1650 | unsigned long flags; | |
1da177e4 | 1651 | |
dade7716 | 1652 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
1653 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
1654 | reg_01.raw = io_apic_read(ioapic_idx, 1); | |
1da177e4 | 1655 | if (reg_01.bits.version >= 0x10) |
6f50d45f | 1656 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
d6c88a50 | 1657 | if (reg_01.bits.version >= 0x20) |
6f50d45f | 1658 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
dade7716 | 1659 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1660 | |
6f50d45f | 1661 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1662 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1663 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1664 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1665 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1666 | |
54168ed7 | 1667 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
bd6a46e0 NC |
1668 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
1669 | reg_01.bits.entries); | |
1da177e4 LT |
1670 | |
1671 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
bd6a46e0 NC |
1672 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
1673 | reg_01.bits.version); | |
1da177e4 LT |
1674 | |
1675 | /* | |
1676 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1677 | * but the value of reg_02 is read as the previous read register | |
1678 | * value, so ignore it if reg_02 == reg_01. | |
1679 | */ | |
1680 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1681 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1682 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1683 | } |
1684 | ||
1685 | /* | |
1686 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1687 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1688 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1689 | */ | |
1690 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1691 | reg_03.raw != reg_01.raw) { | |
1692 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1693 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1694 | } |
1695 | ||
1696 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1697 | ||
afcc8a40 | 1698 | x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries); |
cda417dd YL |
1699 | } |
1700 | ||
1701 | __apicdebuginit(void) print_IO_APICs(void) | |
1702 | { | |
6f50d45f | 1703 | int ioapic_idx; |
cda417dd YL |
1704 | struct irq_cfg *cfg; |
1705 | unsigned int irq; | |
6fd36ba0 | 1706 | struct irq_chip *chip; |
cda417dd YL |
1707 | |
1708 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
f44d1692 | 1709 | for_each_ioapic(ioapic_idx) |
cda417dd | 1710 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
6f50d45f YL |
1711 | mpc_ioapic_id(ioapic_idx), |
1712 | ioapics[ioapic_idx].nr_registers); | |
cda417dd YL |
1713 | |
1714 | /* | |
1715 | * We are a bit conservative about what we expect. We have to | |
1716 | * know about every hardware change ASAP. | |
1717 | */ | |
1718 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1719 | ||
f44d1692 | 1720 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1721 | print_IO_APIC(ioapic_idx); |
42f0efc5 | 1722 | |
1da177e4 | 1723 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1724 | for_each_active_irq(irq) { |
0b8f1efa YL |
1725 | struct irq_pin_list *entry; |
1726 | ||
6fd36ba0 MN |
1727 | chip = irq_get_chip(irq); |
1728 | if (chip != &ioapic_chip) | |
1729 | continue; | |
1730 | ||
32f5ef5d | 1731 | cfg = irq_cfg(irq); |
05e40760 DK |
1732 | if (!cfg) |
1733 | continue; | |
0b8f1efa | 1734 | entry = cfg->irq_2_pin; |
0f978f45 | 1735 | if (!entry) |
1da177e4 | 1736 | continue; |
8f09cd20 | 1737 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1738 | for_each_irq_pin(entry, cfg->irq_2_pin) |
c767a54b JP |
1739 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
1740 | pr_cont("\n"); | |
1da177e4 LT |
1741 | } |
1742 | ||
1743 | printk(KERN_INFO ".................................... done.\n"); | |
1da177e4 LT |
1744 | } |
1745 | ||
251e1e44 | 1746 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1747 | { |
251e1e44 | 1748 | int i; |
1da177e4 | 1749 | |
251e1e44 IM |
1750 | printk(KERN_DEBUG); |
1751 | ||
1752 | for (i = 0; i < 8; i++) | |
c767a54b | 1753 | pr_cont("%08x", apic_read(base + i*0x10)); |
251e1e44 | 1754 | |
c767a54b | 1755 | pr_cont("\n"); |
1da177e4 LT |
1756 | } |
1757 | ||
32f71aff | 1758 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1759 | { |
97a52714 | 1760 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1761 | u64 icr; |
1da177e4 | 1762 | |
251e1e44 | 1763 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1764 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1765 | v = apic_read(APIC_ID); |
54168ed7 | 1766 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1767 | v = apic_read(APIC_LVR); |
1768 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1769 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1770 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1771 | |
1772 | v = apic_read(APIC_TASKPRI); | |
1773 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1774 | ||
54168ed7 | 1775 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1776 | if (!APIC_XAPIC(ver)) { |
1777 | v = apic_read(APIC_ARBPRI); | |
1778 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1779 | v & APIC_ARBPRI_MASK); | |
1780 | } | |
1da177e4 LT |
1781 | v = apic_read(APIC_PROCPRI); |
1782 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1783 | } | |
1784 | ||
a11b5abe YL |
1785 | /* |
1786 | * Remote read supported only in the 82489DX and local APIC for | |
1787 | * Pentium processors. | |
1788 | */ | |
1789 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1790 | v = apic_read(APIC_RRR); | |
1791 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1792 | } | |
1793 | ||
1da177e4 LT |
1794 | v = apic_read(APIC_LDR); |
1795 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1796 | if (!x2apic_enabled()) { |
1797 | v = apic_read(APIC_DFR); | |
1798 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1799 | } | |
1da177e4 LT |
1800 | v = apic_read(APIC_SPIV); |
1801 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1802 | ||
1803 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1804 | print_APIC_field(APIC_ISR); |
1da177e4 | 1805 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1806 | print_APIC_field(APIC_TMR); |
1da177e4 | 1807 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1808 | print_APIC_field(APIC_IRR); |
1da177e4 | 1809 | |
54168ed7 IM |
1810 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1811 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1812 | apic_write(APIC_ESR, 0); |
54168ed7 | 1813 | |
1da177e4 LT |
1814 | v = apic_read(APIC_ESR); |
1815 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1816 | } | |
1817 | ||
7ab6af7a | 1818 | icr = apic_icr_read(); |
0c425cec IM |
1819 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1820 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1821 | |
1822 | v = apic_read(APIC_LVTT); | |
1823 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1824 | ||
1825 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1826 | v = apic_read(APIC_LVTPC); | |
1827 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1828 | } | |
1829 | v = apic_read(APIC_LVT0); | |
1830 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1831 | v = apic_read(APIC_LVT1); | |
1832 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1833 | ||
1834 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1835 | v = apic_read(APIC_LVTERR); | |
1836 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1837 | } | |
1838 | ||
1839 | v = apic_read(APIC_TMICT); | |
1840 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1841 | v = apic_read(APIC_TMCCT); | |
1842 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1843 | v = apic_read(APIC_TDCR); | |
1844 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1845 | |
1846 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1847 | v = apic_read(APIC_EFEAT); | |
1848 | maxlvt = (v >> 16) & 0xff; | |
1849 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1850 | v = apic_read(APIC_ECTRL); | |
1851 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1852 | for (i = 0; i < maxlvt; i++) { | |
1853 | v = apic_read(APIC_EILVTn(i)); | |
1854 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1855 | } | |
1856 | } | |
c767a54b | 1857 | pr_cont("\n"); |
1da177e4 LT |
1858 | } |
1859 | ||
2626eb2b | 1860 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1861 | { |
ffd5aae7 YL |
1862 | int cpu; |
1863 | ||
2626eb2b CG |
1864 | if (!maxcpu) |
1865 | return; | |
1866 | ||
ffd5aae7 | 1867 | preempt_disable(); |
2626eb2b CG |
1868 | for_each_online_cpu(cpu) { |
1869 | if (cpu >= maxcpu) | |
1870 | break; | |
ffd5aae7 | 1871 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1872 | } |
ffd5aae7 | 1873 | preempt_enable(); |
1da177e4 LT |
1874 | } |
1875 | ||
32f71aff | 1876 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1877 | { |
1da177e4 LT |
1878 | unsigned int v; |
1879 | unsigned long flags; | |
1880 | ||
95d76acc | 1881 | if (!nr_legacy_irqs()) |
1da177e4 LT |
1882 | return; |
1883 | ||
1884 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1885 | ||
5619c280 | 1886 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1887 | |
1888 | v = inb(0xa1) << 8 | inb(0x21); | |
1889 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1890 | ||
1891 | v = inb(0xa0) << 8 | inb(0x20); | |
1892 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1893 | ||
54168ed7 IM |
1894 | outb(0x0b,0xa0); |
1895 | outb(0x0b,0x20); | |
1da177e4 | 1896 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1897 | outb(0x0a,0xa0); |
1898 | outb(0x0a,0x20); | |
1da177e4 | 1899 | |
5619c280 | 1900 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1901 | |
1902 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1903 | ||
1904 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1905 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1906 | } | |
1907 | ||
2626eb2b CG |
1908 | static int __initdata show_lapic = 1; |
1909 | static __init int setup_show_lapic(char *arg) | |
1910 | { | |
1911 | int num = -1; | |
1912 | ||
1913 | if (strcmp(arg, "all") == 0) { | |
1914 | show_lapic = CONFIG_NR_CPUS; | |
1915 | } else { | |
1916 | get_option(&arg, &num); | |
1917 | if (num >= 0) | |
1918 | show_lapic = num; | |
1919 | } | |
1920 | ||
1921 | return 1; | |
1922 | } | |
1923 | __setup("show_lapic=", setup_show_lapic); | |
1924 | ||
1925 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1926 | { |
2626eb2b CG |
1927 | if (apic_verbosity == APIC_QUIET) |
1928 | return 0; | |
1929 | ||
32f71aff | 1930 | print_PIC(); |
4797f6b0 YL |
1931 | |
1932 | /* don't print out if apic is not there */ | |
8312136f | 1933 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1934 | return 0; |
1935 | ||
2626eb2b | 1936 | print_local_APICs(show_lapic); |
cda417dd | 1937 | print_IO_APICs(); |
32f71aff MR |
1938 | |
1939 | return 0; | |
1940 | } | |
1941 | ||
ded1f6ab | 1942 | late_initcall(print_ICs); |
32f71aff | 1943 | |
1da177e4 | 1944 | |
efa2559f YL |
1945 | /* Where if anywhere is the i8259 connect in external int mode */ |
1946 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1947 | ||
54168ed7 | 1948 | void __init enable_IO_APIC(void) |
1da177e4 | 1949 | { |
fcfd636a | 1950 | int i8259_apic, i8259_pin; |
f44d1692 | 1951 | int apic, pin; |
bc07844a | 1952 | |
95d76acc | 1953 | if (!nr_legacy_irqs()) |
bc07844a TG |
1954 | return; |
1955 | ||
f44d1692 | 1956 | for_each_ioapic_pin(apic, pin) { |
fcfd636a | 1957 | /* See if any of the pins is in ExtINT mode */ |
f44d1692 | 1958 | struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1959 | |
f44d1692 JL |
1960 | /* If the interrupt line is enabled and in ExtInt mode |
1961 | * I have found the pin where the i8259 is connected. | |
1962 | */ | |
1963 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1964 | ioapic_i8259.apic = apic; | |
1965 | ioapic_i8259.pin = pin; | |
1966 | goto found_i8259; | |
fcfd636a EB |
1967 | } |
1968 | } | |
1969 | found_i8259: | |
1970 | /* Look to see what if the MP table has reported the ExtINT */ | |
1971 | /* If we could not find the appropriate pin by looking at the ioapic | |
1972 | * the i8259 probably is not connected the ioapic but give the | |
1973 | * mptable a chance anyway. | |
1974 | */ | |
1975 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1976 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1977 | /* Trust the MP table if nothing is setup in the hardware */ | |
1978 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1979 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1980 | ioapic_i8259.pin = i8259_pin; | |
1981 | ioapic_i8259.apic = i8259_apic; | |
1982 | } | |
1983 | /* Complain if the MP table and the hardware disagree */ | |
1984 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1985 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1986 | { | |
1987 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1988 | } |
1989 | ||
1990 | /* | |
1991 | * Do not trust the IO-APIC being empty at bootup | |
1992 | */ | |
1993 | clear_IO_APIC(); | |
1994 | } | |
1995 | ||
1c4248ca | 1996 | void native_disable_io_apic(void) |
1da177e4 | 1997 | { |
650927ef | 1998 | /* |
0b968d23 | 1999 | * If the i8259 is routed through an IOAPIC |
650927ef | 2000 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2001 | * so legacy interrupts can be delivered. |
650927ef | 2002 | */ |
1c4248ca | 2003 | if (ioapic_i8259.pin != -1) { |
650927ef | 2004 | struct IO_APIC_route_entry entry; |
650927ef EB |
2005 | |
2006 | memset(&entry, 0, sizeof(entry)); | |
2007 | entry.mask = 0; /* Enabled */ | |
2008 | entry.trigger = 0; /* Edge */ | |
2009 | entry.irr = 0; | |
2010 | entry.polarity = 0; /* High */ | |
2011 | entry.delivery_status = 0; | |
2012 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2013 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2014 | entry.vector = 0; |
54168ed7 | 2015 | entry.dest = read_apic_id(); |
650927ef EB |
2016 | |
2017 | /* | |
2018 | * Add it to the IO-APIC irq-routing table: | |
2019 | */ | |
cf4c6a2f | 2020 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2021 | } |
54168ed7 | 2022 | |
1c4248ca JR |
2023 | if (cpu_has_apic || apic_from_smp_config()) |
2024 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); | |
2025 | ||
2026 | } | |
2027 | ||
2028 | /* | |
2029 | * Not an __init, needed by the reboot code | |
2030 | */ | |
2031 | void disable_IO_APIC(void) | |
2032 | { | |
7c6d9f97 | 2033 | /* |
1c4248ca | 2034 | * Clear the IO-APIC before rebooting: |
7c6d9f97 | 2035 | */ |
1c4248ca JR |
2036 | clear_IO_APIC(); |
2037 | ||
95d76acc | 2038 | if (!nr_legacy_irqs()) |
1c4248ca JR |
2039 | return; |
2040 | ||
2041 | x86_io_apic_ops.disable(); | |
1da177e4 LT |
2042 | } |
2043 | ||
54168ed7 | 2044 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2045 | /* |
2046 | * function to set the IO-APIC physical IDs based on the | |
2047 | * values stored in the MPC table. | |
2048 | * | |
2049 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2050 | */ | |
a38c5380 | 2051 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
2052 | { |
2053 | union IO_APIC_reg_00 reg_00; | |
2054 | physid_mask_t phys_id_present_map; | |
6f50d45f | 2055 | int ioapic_idx; |
1da177e4 LT |
2056 | int i; |
2057 | unsigned char old_id; | |
2058 | unsigned long flags; | |
2059 | ||
2060 | /* | |
2061 | * This is broken; anything with a real cpu count has to | |
2062 | * circumvent this idiocy regardless. | |
2063 | */ | |
7abc0753 | 2064 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
2065 | |
2066 | /* | |
2067 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2068 | */ | |
f44d1692 | 2069 | for_each_ioapic(ioapic_idx) { |
1da177e4 | 2070 | /* Read the register 0 value */ |
dade7716 | 2071 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2072 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 2073 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2074 | |
6f50d45f | 2075 | old_id = mpc_ioapic_id(ioapic_idx); |
1da177e4 | 2076 | |
6f50d45f | 2077 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
1da177e4 | 2078 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
6f50d45f | 2079 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
2080 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2081 | reg_00.bits.ID); | |
6f50d45f | 2082 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
1da177e4 LT |
2083 | } |
2084 | ||
1da177e4 LT |
2085 | /* |
2086 | * Sanity check, is the ID really free? Every APIC in a | |
2087 | * system must have a unique ID or we get lots of nice | |
2088 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2089 | */ | |
7abc0753 | 2090 | if (apic->check_apicid_used(&phys_id_present_map, |
6f50d45f | 2091 | mpc_ioapic_id(ioapic_idx))) { |
1da177e4 | 2092 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
6f50d45f | 2093 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
2094 | for (i = 0; i < get_physical_broadcast(); i++) |
2095 | if (!physid_isset(i, phys_id_present_map)) | |
2096 | break; | |
2097 | if (i >= get_physical_broadcast()) | |
2098 | panic("Max APIC ID exceeded!\n"); | |
2099 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2100 | i); | |
2101 | physid_set(i, phys_id_present_map); | |
6f50d45f | 2102 | ioapics[ioapic_idx].mp_config.apicid = i; |
1da177e4 LT |
2103 | } else { |
2104 | physid_mask_t tmp; | |
6f50d45f | 2105 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
d5371430 | 2106 | &tmp); |
1da177e4 LT |
2107 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2108 | "phys_id_present_map\n", | |
6f50d45f | 2109 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
2110 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2111 | } | |
2112 | ||
1da177e4 LT |
2113 | /* |
2114 | * We need to adjust the IRQ routing table | |
2115 | * if the ID changed. | |
2116 | */ | |
6f50d45f | 2117 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
1da177e4 | 2118 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2119 | if (mp_irqs[i].dstapic == old_id) |
2120 | mp_irqs[i].dstapic | |
6f50d45f | 2121 | = mpc_ioapic_id(ioapic_idx); |
1da177e4 LT |
2122 | |
2123 | /* | |
60d79fd9 YL |
2124 | * Update the ID register according to the right value |
2125 | * from the MPC table if they are different. | |
36062448 | 2126 | */ |
6f50d45f | 2127 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
60d79fd9 YL |
2128 | continue; |
2129 | ||
1da177e4 LT |
2130 | apic_printk(APIC_VERBOSE, KERN_INFO |
2131 | "...changing IO-APIC physical APIC ID to %d ...", | |
6f50d45f | 2132 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 | 2133 | |
6f50d45f | 2134 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
dade7716 | 2135 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2136 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
dade7716 | 2137 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2138 | |
2139 | /* | |
2140 | * Sanity check | |
2141 | */ | |
dade7716 | 2142 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2143 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 2144 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
6f50d45f | 2145 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
c767a54b | 2146 | pr_cont("could not set ID!\n"); |
1da177e4 LT |
2147 | else |
2148 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2149 | } | |
2150 | } | |
a38c5380 SAS |
2151 | |
2152 | void __init setup_ioapic_ids_from_mpc(void) | |
2153 | { | |
2154 | ||
2155 | if (acpi_ioapic) | |
2156 | return; | |
2157 | /* | |
2158 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2159 | * no meaning without the serial APIC bus. | |
2160 | */ | |
2161 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2162 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
2163 | return; | |
2164 | setup_ioapic_ids_from_mpc_nocheck(); | |
2165 | } | |
54168ed7 | 2166 | #endif |
1da177e4 | 2167 | |
7ce0bcfd | 2168 | int no_timer_check __initdata; |
8542b200 ZA |
2169 | |
2170 | static int __init notimercheck(char *s) | |
2171 | { | |
2172 | no_timer_check = 1; | |
2173 | return 1; | |
2174 | } | |
2175 | __setup("no_timer_check", notimercheck); | |
2176 | ||
1da177e4 LT |
2177 | /* |
2178 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2179 | * about the timer IRQ. We do the following to work around the situation: | |
2180 | * | |
2181 | * - timer IRQ defaults to IO-APIC IRQ | |
2182 | * - if this function detects that timer IRQs are defunct, then we fall | |
2183 | * back to ISA timer IRQs | |
2184 | */ | |
f0a7a5c9 | 2185 | static int __init timer_irq_works(void) |
1da177e4 LT |
2186 | { |
2187 | unsigned long t1 = jiffies; | |
4aae0702 | 2188 | unsigned long flags; |
1da177e4 | 2189 | |
8542b200 ZA |
2190 | if (no_timer_check) |
2191 | return 1; | |
2192 | ||
4aae0702 | 2193 | local_save_flags(flags); |
1da177e4 LT |
2194 | local_irq_enable(); |
2195 | /* Let ten ticks pass... */ | |
2196 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2197 | local_irq_restore(flags); |
1da177e4 LT |
2198 | |
2199 | /* | |
2200 | * Expect a few ticks at least, to be sure some possible | |
2201 | * glue logic does not lock up after one or two first | |
2202 | * ticks in a non-ExtINT mode. Also the local APIC | |
2203 | * might have cached one ExtINT interrupt. Finally, at | |
2204 | * least one tick may be lost due to delays. | |
2205 | */ | |
54168ed7 IM |
2206 | |
2207 | /* jiffies wrap? */ | |
1d16b53e | 2208 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2209 | return 1; |
1da177e4 LT |
2210 | return 0; |
2211 | } | |
2212 | ||
2213 | /* | |
2214 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2215 | * number of pending IRQ events unhandled. These cases are very rare, | |
2216 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2217 | * better to do it this way as thus we do not have to be aware of | |
2218 | * 'pending' interrupts in the IRQ path, except at this point. | |
2219 | */ | |
2220 | /* | |
2221 | * Edge triggered needs to resend any interrupt | |
2222 | * that was delayed but this is now handled in the device | |
2223 | * independent code. | |
2224 | */ | |
2225 | ||
2226 | /* | |
2227 | * Starting up a edge-triggered IO-APIC interrupt is | |
2228 | * nasty - we need to make sure that we get the edge. | |
2229 | * If it is already asserted for some reason, we need | |
2230 | * return 1 to indicate that is was pending. | |
2231 | * | |
2232 | * This is not complete - we should be able to fake | |
2233 | * an edge even if it isn't on the 8259A... | |
2234 | */ | |
54168ed7 | 2235 | |
61a38ce3 | 2236 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 2237 | { |
61a38ce3 | 2238 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
2239 | unsigned long flags; |
2240 | ||
dade7716 | 2241 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
95d76acc | 2242 | if (irq < nr_legacy_irqs()) { |
4305df94 | 2243 | legacy_pic->mask(irq); |
b81bb373 | 2244 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2245 | was_pending = 1; |
2246 | } | |
61a38ce3 | 2247 | __unmask_ioapic(data->chip_data); |
dade7716 | 2248 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2249 | |
2250 | return was_pending; | |
2251 | } | |
2252 | ||
90297c5f | 2253 | static int ioapic_retrigger_irq(struct irq_data *data) |
1da177e4 | 2254 | { |
90297c5f | 2255 | struct irq_cfg *cfg = data->chip_data; |
54168ed7 | 2256 | unsigned long flags; |
8d966a04 | 2257 | int cpu; |
54168ed7 | 2258 | |
dade7716 | 2259 | raw_spin_lock_irqsave(&vector_lock, flags); |
8d966a04 FY |
2260 | cpu = cpumask_first_and(cfg->domain, cpu_online_mask); |
2261 | apic->send_IPI_mask(cpumask_of(cpu), cfg->vector); | |
dade7716 | 2262 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2263 | |
2264 | return 1; | |
2265 | } | |
497c9a19 | 2266 | |
54168ed7 IM |
2267 | /* |
2268 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2269 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2270 | * handled with the level-triggered descriptor, but that one has slightly | |
2271 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2272 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2273 | * races. | |
2274 | */ | |
497c9a19 | 2275 | |
54168ed7 | 2276 | #ifdef CONFIG_SMP |
9338ad6f | 2277 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2278 | { |
2279 | cpumask_var_t cleanup_mask; | |
2280 | ||
2281 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2282 | unsigned int i; | |
e85abf8f GH |
2283 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2284 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2285 | } else { | |
2286 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2287 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2288 | free_cpumask_var(cleanup_mask); | |
2289 | } | |
2290 | cfg->move_in_progress = 0; | |
2291 | } | |
2292 | ||
2605fc21 | 2293 | asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) |
54168ed7 IM |
2294 | { |
2295 | unsigned vector, me; | |
8f2466f4 | 2296 | |
54168ed7 | 2297 | ack_APIC_irq(); |
54168ed7 | 2298 | irq_enter(); |
98ad1cc1 | 2299 | exit_idle(); |
54168ed7 IM |
2300 | |
2301 | me = smp_processor_id(); | |
2302 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
c7a730fa | 2303 | int irq; |
68a8ca59 | 2304 | unsigned int irr; |
54168ed7 IM |
2305 | struct irq_desc *desc; |
2306 | struct irq_cfg *cfg; | |
0a3aee0d | 2307 | irq = __this_cpu_read(vector_irq[vector]); |
54168ed7 | 2308 | |
9345005f | 2309 | if (irq <= VECTOR_UNDEFINED) |
0b8f1efa YL |
2310 | continue; |
2311 | ||
54168ed7 IM |
2312 | desc = irq_to_desc(irq); |
2313 | if (!desc) | |
2314 | continue; | |
2315 | ||
2316 | cfg = irq_cfg(irq); | |
94777fc5 DS |
2317 | if (!cfg) |
2318 | continue; | |
2319 | ||
239007b8 | 2320 | raw_spin_lock(&desc->lock); |
54168ed7 | 2321 | |
7f41c2e1 SS |
2322 | /* |
2323 | * Check if the irq migration is in progress. If so, we | |
2324 | * haven't received the cleanup request yet for this irq. | |
2325 | */ | |
2326 | if (cfg->move_in_progress) | |
2327 | goto unlock; | |
2328 | ||
22f65d31 | 2329 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2330 | goto unlock; |
2331 | ||
68a8ca59 SS |
2332 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2333 | /* | |
2334 | * Check if the vector that needs to be cleanedup is | |
2335 | * registered at the cpu's IRR. If so, then this is not | |
2336 | * the best time to clean it up. Lets clean it up in the | |
2337 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2338 | * to myself. | |
2339 | */ | |
2340 | if (irr & (1 << (vector % 32))) { | |
2341 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2342 | goto unlock; | |
2343 | } | |
3eb2be5f | 2344 | __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED); |
54168ed7 | 2345 | unlock: |
239007b8 | 2346 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2347 | } |
2348 | ||
2349 | irq_exit(); | |
2350 | } | |
2351 | ||
dd5f15e5 | 2352 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2353 | { |
a5e74b84 | 2354 | unsigned me; |
54168ed7 | 2355 | |
fcef5911 | 2356 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2357 | return; |
2358 | ||
54168ed7 | 2359 | me = smp_processor_id(); |
10b888d6 | 2360 | |
fcef5911 | 2361 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2362 | send_cleanup_vector(cfg); |
497c9a19 | 2363 | } |
a5e74b84 | 2364 | |
dd5f15e5 | 2365 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2366 | { |
dd5f15e5 | 2367 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2368 | } |
2369 | ||
2370 | void irq_force_complete_move(int irq) | |
2371 | { | |
32f5ef5d | 2372 | struct irq_cfg *cfg = irq_cfg(irq); |
a5e74b84 | 2373 | |
bbd391a1 PB |
2374 | if (!cfg) |
2375 | return; | |
2376 | ||
dd5f15e5 | 2377 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2378 | } |
497c9a19 | 2379 | #else |
dd5f15e5 | 2380 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2381 | #endif |
3145e941 | 2382 | |
7eb9ae07 SS |
2383 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
2384 | { | |
2385 | int apic, pin; | |
2386 | struct irq_pin_list *entry; | |
2387 | u8 vector = cfg->vector; | |
2388 | ||
2389 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
2390 | unsigned int reg; | |
2391 | ||
2392 | apic = entry->apic; | |
2393 | pin = entry->pin; | |
9f9d39e4 JR |
2394 | |
2395 | io_apic_write(apic, 0x11 + pin*2, dest); | |
7eb9ae07 SS |
2396 | reg = io_apic_read(apic, 0x10 + pin*2); |
2397 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2398 | reg |= vector; | |
2399 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
2400 | } | |
2401 | } | |
2402 | ||
2403 | /* | |
2404 | * Either sets data->affinity to a valid value, and returns | |
2405 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and | |
2406 | * leaves data->affinity untouched. | |
2407 | */ | |
2408 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
2409 | unsigned int *dest_id) | |
2410 | { | |
2411 | struct irq_cfg *cfg = data->chip_data; | |
2412 | unsigned int irq = data->irq; | |
2413 | int err; | |
2414 | ||
2415 | if (!config_enabled(CONFIG_SMP)) | |
fb24da80 | 2416 | return -EPERM; |
7eb9ae07 SS |
2417 | |
2418 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
2419 | return -EINVAL; | |
2420 | ||
2421 | err = assign_irq_vector(irq, cfg, mask); | |
2422 | if (err) | |
2423 | return err; | |
2424 | ||
2425 | err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id); | |
2426 | if (err) { | |
2427 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
2428 | pr_err("Failed to recover vector for irq %d\n", irq); | |
2429 | return err; | |
2430 | } | |
2431 | ||
2432 | cpumask_copy(data->affinity, mask); | |
2433 | ||
2434 | return 0; | |
2435 | } | |
2436 | ||
373dd7a2 JR |
2437 | |
2438 | int native_ioapic_set_affinity(struct irq_data *data, | |
2439 | const struct cpumask *mask, | |
2440 | bool force) | |
7eb9ae07 SS |
2441 | { |
2442 | unsigned int dest, irq = data->irq; | |
2443 | unsigned long flags; | |
2444 | int ret; | |
2445 | ||
2446 | if (!config_enabled(CONFIG_SMP)) | |
fb24da80 | 2447 | return -EPERM; |
7eb9ae07 SS |
2448 | |
2449 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2450 | ret = __ioapic_set_affinity(data, mask, &dest); | |
2451 | if (!ret) { | |
2452 | /* Only the high 8 bits are valid. */ | |
2453 | dest = SET_APIC_LOGICAL_ID(dest); | |
2454 | __target_IO_APIC_irq(irq, dest, data->chip_data); | |
2455 | ret = IRQ_SET_MASK_OK_NOCOPY; | |
2456 | } | |
2457 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2458 | return ret; | |
2459 | } | |
2460 | ||
90297c5f | 2461 | static void ack_apic_edge(struct irq_data *data) |
1d025192 | 2462 | { |
90297c5f | 2463 | irq_complete_move(data->chip_data); |
08221110 | 2464 | irq_move_irq(data); |
1d025192 YL |
2465 | ack_APIC_irq(); |
2466 | } | |
2467 | ||
3eb2cce8 | 2468 | atomic_t irq_mis_count; |
3eb2cce8 | 2469 | |
047c8fdb | 2470 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
d1ecad6e MN |
2471 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
2472 | { | |
2473 | struct irq_pin_list *entry; | |
2474 | unsigned long flags; | |
2475 | ||
2476 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2477 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
2478 | unsigned int reg; | |
2479 | int pin; | |
2480 | ||
2481 | pin = entry->pin; | |
2482 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
2483 | /* Is the remote IRR bit set? */ | |
2484 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
2485 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2486 | return true; | |
2487 | } | |
2488 | } | |
2489 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2490 | ||
2491 | return false; | |
2492 | } | |
2493 | ||
4da7072a AG |
2494 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) |
2495 | { | |
54168ed7 | 2496 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 2497 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
dd5f15e5 | 2498 | mask_ioapic(cfg); |
4da7072a | 2499 | return true; |
54168ed7 | 2500 | } |
4da7072a AG |
2501 | return false; |
2502 | } | |
2503 | ||
2504 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
2505 | struct irq_cfg *cfg, bool masked) | |
2506 | { | |
2507 | if (unlikely(masked)) { | |
2508 | /* Only migrate the irq if the ack has been received. | |
2509 | * | |
2510 | * On rare occasions the broadcast level triggered ack gets | |
2511 | * delayed going to ioapics, and if we reprogram the | |
2512 | * vector while Remote IRR is still set the irq will never | |
2513 | * fire again. | |
2514 | * | |
2515 | * To prevent this scenario we read the Remote IRR bit | |
2516 | * of the ioapic. This has two effects. | |
2517 | * - On any sane system the read of the ioapic will | |
2518 | * flush writes (and acks) going to the ioapic from | |
2519 | * this cpu. | |
2520 | * - We get to see if the ACK has actually been delivered. | |
2521 | * | |
2522 | * Based on failed experiments of reprogramming the | |
2523 | * ioapic entry from outside of irq context starting | |
2524 | * with masking the ioapic entry and then polling until | |
2525 | * Remote IRR was clear before reprogramming the | |
2526 | * ioapic I don't trust the Remote IRR bit to be | |
2527 | * completey accurate. | |
2528 | * | |
2529 | * However there appears to be no other way to plug | |
2530 | * this race, so if the Remote IRR bit is not | |
2531 | * accurate and is causing problems then it is a hardware bug | |
2532 | * and you can go talk to the chipset vendor about it. | |
2533 | */ | |
2534 | if (!io_apic_level_ack_pending(cfg)) | |
2535 | irq_move_masked_irq(data); | |
2536 | unmask_ioapic(cfg); | |
2537 | } | |
2538 | } | |
2539 | #else | |
2540 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) | |
2541 | { | |
2542 | return false; | |
2543 | } | |
2544 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
2545 | struct irq_cfg *cfg, bool masked) | |
2546 | { | |
2547 | } | |
047c8fdb YL |
2548 | #endif |
2549 | ||
4da7072a AG |
2550 | static void ack_apic_level(struct irq_data *data) |
2551 | { | |
2552 | struct irq_cfg *cfg = data->chip_data; | |
2553 | int i, irq = data->irq; | |
2554 | unsigned long v; | |
2555 | bool masked; | |
2556 | ||
2557 | irq_complete_move(cfg); | |
2558 | masked = ioapic_irqd_mask(data, cfg); | |
2559 | ||
3eb2cce8 | 2560 | /* |
916a0fe7 JF |
2561 | * It appears there is an erratum which affects at least version 0x11 |
2562 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2563 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2564 | * erroneously delivered as edge-triggered one but the respective IRR | |
2565 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2566 | * message but it will never arrive and further interrupts are blocked | |
2567 | * from the source. The exact reason is so far unknown, but the | |
2568 | * phenomenon was observed when two consecutive interrupt requests | |
2569 | * from a given source get delivered to the same CPU and the source is | |
2570 | * temporarily disabled in between. | |
2571 | * | |
2572 | * A workaround is to simulate an EOI message manually. We achieve it | |
2573 | * by setting the trigger mode to edge and then to level when the edge | |
2574 | * trigger mode gets detected in the TMR of a local APIC for a | |
2575 | * level-triggered interrupt. We mask the source for the time of the | |
2576 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2577 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2578 | * |
2579 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2580 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2581 | * destination that is handling the corresponding interrupt. This | |
2582 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2583 | * level-triggered io-apic interrupt will be seen as an edge | |
2584 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2585 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2586 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2587 | * supporting EOI register, we do an explicit EOI to clear the | |
2588 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2589 | * we use the above logic (mask+edge followed by unmask+level) from | |
2590 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2591 | */ |
3145e941 | 2592 | i = cfg->vector; |
3eb2cce8 | 2593 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2594 | |
54168ed7 IM |
2595 | /* |
2596 | * We must acknowledge the irq before we move it or the acknowledge will | |
2597 | * not propagate properly. | |
2598 | */ | |
2599 | ack_APIC_irq(); | |
2600 | ||
1c83995b SS |
2601 | /* |
2602 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2603 | * message via io-apic EOI register write or simulating it using | |
2604 | * mask+edge followed by unnask+level logic) manually when the | |
2605 | * level triggered interrupt is seen as the edge triggered interrupt | |
2606 | * at the cpu. | |
2607 | */ | |
ca64c47c MR |
2608 | if (!(v & (1 << (i & 0x1f)))) { |
2609 | atomic_inc(&irq_mis_count); | |
2610 | ||
dd5f15e5 | 2611 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2612 | } |
2613 | ||
4da7072a | 2614 | ioapic_irqd_unmask(data, cfg, masked); |
3eb2cce8 | 2615 | } |
1d025192 | 2616 | |
f5b9ed7a | 2617 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2618 | .name = "IO-APIC", |
2619 | .irq_startup = startup_ioapic_irq, | |
2620 | .irq_mask = mask_ioapic_irq, | |
2621 | .irq_unmask = unmask_ioapic_irq, | |
2622 | .irq_ack = ack_apic_edge, | |
2623 | .irq_eoi = ack_apic_level, | |
373dd7a2 | 2624 | .irq_set_affinity = native_ioapic_set_affinity, |
f7e909ea | 2625 | .irq_retrigger = ioapic_retrigger_irq, |
5613570b | 2626 | .flags = IRQCHIP_SKIP_SET_WAKE, |
1da177e4 LT |
2627 | }; |
2628 | ||
1da177e4 LT |
2629 | static inline void init_IO_APIC_traps(void) |
2630 | { | |
da51a821 | 2631 | struct irq_cfg *cfg; |
ad9f4334 | 2632 | unsigned int irq; |
1da177e4 | 2633 | |
ad9f4334 | 2634 | for_each_active_irq(irq) { |
32f5ef5d | 2635 | cfg = irq_cfg(irq); |
0b8f1efa | 2636 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2637 | /* |
2638 | * Hmm.. We don't have an entry for this, | |
2639 | * so default to an old-fashioned 8259 | |
2640 | * interrupt if we can.. | |
2641 | */ | |
95d76acc | 2642 | if (irq < nr_legacy_irqs()) |
b81bb373 | 2643 | legacy_pic->make_irq(irq); |
0b8f1efa | 2644 | else |
1da177e4 | 2645 | /* Strange. Oh, well.. */ |
2c778651 | 2646 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
2647 | } |
2648 | } | |
2649 | } | |
2650 | ||
f5b9ed7a IM |
2651 | /* |
2652 | * The local APIC irq-chip implementation: | |
2653 | */ | |
1da177e4 | 2654 | |
90297c5f | 2655 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2656 | { |
2657 | unsigned long v; | |
2658 | ||
2659 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2660 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2661 | } |
2662 | ||
90297c5f | 2663 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2664 | { |
f5b9ed7a | 2665 | unsigned long v; |
1da177e4 | 2666 | |
f5b9ed7a | 2667 | v = apic_read(APIC_LVT0); |
593f4a78 | 2668 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2669 | } |
1da177e4 | 2670 | |
90297c5f | 2671 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2672 | { |
2673 | ack_APIC_irq(); | |
2674 | } | |
2675 | ||
f5b9ed7a | 2676 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2677 | .name = "local-APIC", |
90297c5f TG |
2678 | .irq_mask = mask_lapic_irq, |
2679 | .irq_unmask = unmask_lapic_irq, | |
2680 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2681 | }; |
2682 | ||
60c69948 | 2683 | static void lapic_register_intr(int irq) |
c88ac1df | 2684 | { |
60c69948 | 2685 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2686 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2687 | "edge"); |
c88ac1df MR |
2688 | } |
2689 | ||
1da177e4 LT |
2690 | /* |
2691 | * This looks a bit hackish but it's about the only one way of sending | |
2692 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2693 | * not support the ExtINT mode, unfortunately. We need to send these | |
2694 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2695 | * 8259A interrupt line asserted until INTA. --macro | |
2696 | */ | |
28acf285 | 2697 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2698 | { |
fcfd636a | 2699 | int apic, pin, i; |
1da177e4 LT |
2700 | struct IO_APIC_route_entry entry0, entry1; |
2701 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2702 | |
fcfd636a | 2703 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2704 | if (pin == -1) { |
2705 | WARN_ON_ONCE(1); | |
2706 | return; | |
2707 | } | |
fcfd636a | 2708 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2709 | if (apic == -1) { |
2710 | WARN_ON_ONCE(1); | |
1da177e4 | 2711 | return; |
956fb531 | 2712 | } |
1da177e4 | 2713 | |
cf4c6a2f | 2714 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2715 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2716 | |
2717 | memset(&entry1, 0, sizeof(entry1)); | |
2718 | ||
2719 | entry1.dest_mode = 0; /* physical delivery */ | |
2720 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2721 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2722 | entry1.delivery_mode = dest_ExtINT; |
2723 | entry1.polarity = entry0.polarity; | |
2724 | entry1.trigger = 0; | |
2725 | entry1.vector = 0; | |
2726 | ||
cf4c6a2f | 2727 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2728 | |
2729 | save_control = CMOS_READ(RTC_CONTROL); | |
2730 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2731 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2732 | RTC_FREQ_SELECT); | |
2733 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2734 | ||
2735 | i = 100; | |
2736 | while (i-- > 0) { | |
2737 | mdelay(10); | |
2738 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2739 | i -= 10; | |
2740 | } | |
2741 | ||
2742 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2743 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2744 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2745 | |
cf4c6a2f | 2746 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2747 | } |
2748 | ||
efa2559f | 2749 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2750 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2751 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2752 | { |
2753 | disable_timer_pin_1 = 1; | |
2754 | return 0; | |
2755 | } | |
54168ed7 | 2756 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f | 2757 | |
1da177e4 LT |
2758 | /* |
2759 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2760 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2761 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2762 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2763 | * |
2764 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2765 | */ |
8542b200 | 2766 | static inline void __init check_timer(void) |
1da177e4 | 2767 | { |
32f5ef5d | 2768 | struct irq_cfg *cfg = irq_cfg(0); |
f6e9456c | 2769 | int node = cpu_to_node(0); |
fcfd636a | 2770 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2771 | unsigned long flags; |
047c8fdb | 2772 | int no_pin1 = 0; |
4aae0702 IM |
2773 | |
2774 | local_irq_save(flags); | |
d4d25dec | 2775 | |
1da177e4 LT |
2776 | /* |
2777 | * get/set the timer IRQ vector: | |
2778 | */ | |
4305df94 | 2779 | legacy_pic->mask(0); |
fe402e1f | 2780 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2781 | |
2782 | /* | |
d11d5794 MR |
2783 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2784 | * wire has to be disabled in the local APIC. Also | |
2785 | * timer interrupts need to be acknowledged manually in | |
2786 | * the 8259A for the i82489DX when using the NMI | |
2787 | * watchdog as that APIC treats NMIs as level-triggered. | |
2788 | * The AEOI mode will finish them in the 8259A | |
2789 | * automatically. | |
1da177e4 | 2790 | */ |
593f4a78 | 2791 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2792 | legacy_pic->init(1); |
1da177e4 | 2793 | |
fcfd636a EB |
2794 | pin1 = find_isa_irq_pin(0, mp_INT); |
2795 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2796 | pin2 = ioapic_i8259.pin; | |
2797 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2798 | |
49a66a0b MR |
2799 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2800 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2801 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2802 | |
691874fa MR |
2803 | /* |
2804 | * Some BIOS writers are clueless and report the ExtINTA | |
2805 | * I/O APIC input from the cascaded 8259A as the timer | |
2806 | * interrupt input. So just in case, if only one pin | |
2807 | * was found above, try it both directly and through the | |
2808 | * 8259A. | |
2809 | */ | |
2810 | if (pin1 == -1) { | |
6a9f5de2 | 2811 | panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); |
691874fa MR |
2812 | pin1 = pin2; |
2813 | apic1 = apic2; | |
2814 | no_pin1 = 1; | |
2815 | } else if (pin2 == -1) { | |
2816 | pin2 = pin1; | |
2817 | apic2 = apic1; | |
2818 | } | |
2819 | ||
1da177e4 LT |
2820 | if (pin1 != -1) { |
2821 | /* | |
2822 | * Ok, does IRQ0 through the IOAPIC work? | |
2823 | */ | |
691874fa | 2824 | if (no_pin1) { |
85ac16d0 | 2825 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2826 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac | 2827 | } else { |
60c69948 | 2828 | /* for edge trigger, setup_ioapic_irq already |
f72dccac YL |
2829 | * leave it unmasked. |
2830 | * so only need to unmask if it is level-trigger | |
2831 | * do we really have level trigger timer? | |
2832 | */ | |
2833 | int idx; | |
2834 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2835 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2836 | unmask_ioapic(cfg); |
691874fa | 2837 | } |
1da177e4 | 2838 | if (timer_irq_works()) { |
66759a01 CE |
2839 | if (disable_timer_pin_1 > 0) |
2840 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2841 | goto out; |
1da177e4 | 2842 | } |
6a9f5de2 | 2843 | panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); |
f72dccac | 2844 | local_irq_disable(); |
fcfd636a | 2845 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2846 | if (!no_pin1) |
49a66a0b MR |
2847 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2848 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2849 | |
49a66a0b MR |
2850 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2851 | "(IRQ0) through the 8259A ...\n"); | |
2852 | apic_printk(APIC_QUIET, KERN_INFO | |
2853 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2854 | /* |
2855 | * legacy devices should be connected to IO APIC #0 | |
2856 | */ | |
85ac16d0 | 2857 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2858 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2859 | legacy_pic->unmask(0); |
1da177e4 | 2860 | if (timer_irq_works()) { |
49a66a0b | 2861 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
4aae0702 | 2862 | goto out; |
1da177e4 LT |
2863 | } |
2864 | /* | |
2865 | * Cleanup, just in case ... | |
2866 | */ | |
f72dccac | 2867 | local_irq_disable(); |
4305df94 | 2868 | legacy_pic->mask(0); |
fcfd636a | 2869 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2870 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2871 | } |
1da177e4 | 2872 | |
49a66a0b MR |
2873 | apic_printk(APIC_QUIET, KERN_INFO |
2874 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2875 | |
60c69948 | 2876 | lapic_register_intr(0); |
497c9a19 | 2877 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2878 | legacy_pic->unmask(0); |
1da177e4 LT |
2879 | |
2880 | if (timer_irq_works()) { | |
49a66a0b | 2881 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2882 | goto out; |
1da177e4 | 2883 | } |
f72dccac | 2884 | local_irq_disable(); |
4305df94 | 2885 | legacy_pic->mask(0); |
497c9a19 | 2886 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2887 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2888 | |
49a66a0b MR |
2889 | apic_printk(APIC_QUIET, KERN_INFO |
2890 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2891 | |
b81bb373 JP |
2892 | legacy_pic->init(0); |
2893 | legacy_pic->make_irq(0); | |
593f4a78 | 2894 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2895 | |
2896 | unlock_ExtINT_logic(); | |
2897 | ||
2898 | if (timer_irq_works()) { | |
49a66a0b | 2899 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2900 | goto out; |
1da177e4 | 2901 | } |
f72dccac | 2902 | local_irq_disable(); |
49a66a0b | 2903 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
fb209bd8 YL |
2904 | if (x2apic_preenabled) |
2905 | apic_printk(APIC_QUIET, KERN_INFO | |
2906 | "Perhaps problem with the pre-enabled x2apic mode\n" | |
2907 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); | |
1da177e4 | 2908 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2909 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2910 | out: |
2911 | local_irq_restore(flags); | |
1da177e4 LT |
2912 | } |
2913 | ||
2914 | /* | |
af174783 MR |
2915 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2916 | * to devices. However there may be an I/O APIC pin available for | |
2917 | * this interrupt regardless. The pin may be left unconnected, but | |
2918 | * typically it will be reused as an ExtINT cascade interrupt for | |
2919 | * the master 8259A. In the MPS case such a pin will normally be | |
2920 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2921 | * there is no provision for ExtINT interrupts, and in the absence | |
2922 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2923 | * interrupt, that is edge-triggered and unmasked by default. We | |
2924 | * used to do this, but it caused problems on some systems because | |
2925 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2926 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2927 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2928 | * the I/O APIC in all cases now. No actual device should request | |
2929 | * it anyway. --macro | |
1da177e4 | 2930 | */ |
bc07844a | 2931 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 | 2932 | |
44767bfa JL |
2933 | static int mp_irqdomain_create(int ioapic) |
2934 | { | |
15a3c7cc | 2935 | size_t size; |
44767bfa JL |
2936 | int hwirqs = mp_ioapic_pin_count(ioapic); |
2937 | struct ioapic *ip = &ioapics[ioapic]; | |
2938 | struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg; | |
2939 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2940 | ||
15a3c7cc JL |
2941 | size = sizeof(struct mp_pin_info) * mp_ioapic_pin_count(ioapic); |
2942 | ip->pin_info = kzalloc(size, GFP_KERNEL); | |
2943 | if (!ip->pin_info) | |
2944 | return -ENOMEM; | |
2945 | ||
44767bfa JL |
2946 | if (cfg->type == IOAPIC_DOMAIN_INVALID) |
2947 | return 0; | |
2948 | ||
2949 | ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops, | |
2950 | (void *)(long)ioapic); | |
15a3c7cc JL |
2951 | if(!ip->irqdomain) { |
2952 | kfree(ip->pin_info); | |
2953 | ip->pin_info = NULL; | |
44767bfa | 2954 | return -ENOMEM; |
15a3c7cc | 2955 | } |
44767bfa JL |
2956 | |
2957 | if (cfg->type == IOAPIC_DOMAIN_LEGACY || | |
2958 | cfg->type == IOAPIC_DOMAIN_STRICT) | |
2959 | ioapic_dynirq_base = max(ioapic_dynirq_base, | |
2960 | gsi_cfg->gsi_end + 1); | |
2961 | ||
2962 | if (gsi_cfg->gsi_base == 0) | |
2963 | irq_set_default_host(ip->irqdomain); | |
2964 | ||
2965 | return 0; | |
2966 | } | |
2967 | ||
1da177e4 LT |
2968 | void __init setup_IO_APIC(void) |
2969 | { | |
44767bfa | 2970 | int ioapic; |
54168ed7 | 2971 | |
54168ed7 IM |
2972 | /* |
2973 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2974 | */ | |
95d76acc | 2975 | io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2976 | |
54168ed7 | 2977 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
44767bfa JL |
2978 | for_each_ioapic(ioapic) |
2979 | BUG_ON(mp_irqdomain_create(ioapic)); | |
2980 | ||
d6c88a50 | 2981 | /* |
54168ed7 IM |
2982 | * Set up IO-APIC IRQ routing. |
2983 | */ | |
de934103 TG |
2984 | x86_init.mpparse.setup_ioapic_ids(); |
2985 | ||
1da177e4 LT |
2986 | sync_Arb_IDs(); |
2987 | setup_IO_APIC_irqs(); | |
2988 | init_IO_APIC_traps(); | |
95d76acc | 2989 | if (nr_legacy_irqs()) |
bc07844a | 2990 | check_timer(); |
b81975ea JL |
2991 | |
2992 | ioapic_initialized = 1; | |
1da177e4 LT |
2993 | } |
2994 | ||
2995 | /* | |
0d2eb44f | 2996 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2997 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2998 | */ |
36062448 | 2999 | |
1da177e4 LT |
3000 | static int __init io_apic_bug_finalize(void) |
3001 | { | |
d6c88a50 TG |
3002 | if (sis_apic_bug == -1) |
3003 | sis_apic_bug = 0; | |
3004 | return 0; | |
1da177e4 LT |
3005 | } |
3006 | ||
3007 | late_initcall(io_apic_bug_finalize); | |
3008 | ||
6f50d45f | 3009 | static void resume_ioapic_id(int ioapic_idx) |
1da177e4 | 3010 | { |
1da177e4 LT |
3011 | unsigned long flags; |
3012 | union IO_APIC_reg_00 reg_00; | |
36062448 | 3013 | |
dade7716 | 3014 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
3015 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
3016 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { | |
3017 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); | |
3018 | io_apic_write(ioapic_idx, 0, reg_00.raw); | |
1da177e4 | 3019 | } |
dade7716 | 3020 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 3021 | } |
1da177e4 | 3022 | |
f3c6ea1b RW |
3023 | static void ioapic_resume(void) |
3024 | { | |
6f50d45f | 3025 | int ioapic_idx; |
f3c6ea1b | 3026 | |
f44d1692 | 3027 | for_each_ioapic_reverse(ioapic_idx) |
6f50d45f | 3028 | resume_ioapic_id(ioapic_idx); |
15bac20b SS |
3029 | |
3030 | restore_ioapic_entries(); | |
1da177e4 LT |
3031 | } |
3032 | ||
f3c6ea1b | 3033 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 3034 | .suspend = save_ioapic_entries, |
1da177e4 LT |
3035 | .resume = ioapic_resume, |
3036 | }; | |
3037 | ||
f3c6ea1b | 3038 | static int __init ioapic_init_ops(void) |
1da177e4 | 3039 | { |
f3c6ea1b RW |
3040 | register_syscore_ops(&ioapic_syscore_ops); |
3041 | ||
1da177e4 LT |
3042 | return 0; |
3043 | } | |
3044 | ||
f3c6ea1b | 3045 | device_initcall(ioapic_init_ops); |
1da177e4 | 3046 | |
3fc471ed | 3047 | /* |
54859f59 | 3048 | * Dynamic irq allocate and deallocation. Should be replaced by irq domains! |
3fc471ed | 3049 | */ |
b1ee5441 TG |
3050 | int arch_setup_hwirq(unsigned int irq, int node) |
3051 | { | |
3052 | struct irq_cfg *cfg; | |
3053 | unsigned long flags; | |
3054 | int ret; | |
3055 | ||
3056 | cfg = alloc_irq_cfg(irq, node); | |
3057 | if (!cfg) | |
3058 | return -ENOMEM; | |
3059 | ||
3060 | raw_spin_lock_irqsave(&vector_lock, flags); | |
3061 | ret = __assign_irq_vector(irq, cfg, apic->target_cpus()); | |
3062 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
3063 | ||
3064 | if (!ret) | |
3065 | irq_set_chip_data(irq, cfg); | |
3066 | else | |
3067 | free_irq_cfg(irq, cfg); | |
3068 | return ret; | |
3069 | } | |
3070 | ||
3071 | void arch_teardown_hwirq(unsigned int irq) | |
3072 | { | |
32f5ef5d | 3073 | struct irq_cfg *cfg = irq_cfg(irq); |
b1ee5441 TG |
3074 | unsigned long flags; |
3075 | ||
3076 | free_remapped_irq(irq); | |
3077 | raw_spin_lock_irqsave(&vector_lock, flags); | |
3078 | __clear_irq_vector(irq, cfg); | |
3079 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
3080 | free_irq_cfg(irq, cfg); | |
3081 | } | |
3082 | ||
2d3fcc1c | 3083 | /* |
27b46d76 | 3084 | * MSI message composition |
2d3fcc1c | 3085 | */ |
7601384f JR |
3086 | void native_compose_msi_msg(struct pci_dev *pdev, |
3087 | unsigned int irq, unsigned int dest, | |
3088 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3089 | { |
7601384f | 3090 | struct irq_cfg *cfg = irq_cfg(irq); |
2d3fcc1c | 3091 | |
7601384f | 3092 | msg->address_hi = MSI_ADDR_BASE_HI; |
54168ed7 | 3093 | |
5e2b930b | 3094 | if (x2apic_enabled()) |
7601384f | 3095 | msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest); |
f007e99c | 3096 | |
5e2b930b JR |
3097 | msg->address_lo = |
3098 | MSI_ADDR_BASE_LO | | |
3099 | ((apic->irq_dest_mode == 0) ? | |
3100 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
3101 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
3102 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
3103 | MSI_ADDR_REDIRECTION_CPU: | |
3104 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3105 | MSI_ADDR_DEST_ID(dest); | |
3106 | ||
3107 | msg->data = | |
3108 | MSI_DATA_TRIGGER_EDGE | | |
3109 | MSI_DATA_LEVEL_ASSERT | | |
3110 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
3111 | MSI_DATA_DELIVERY_FIXED: | |
3112 | MSI_DATA_DELIVERY_LOWPRI) | | |
3113 | MSI_DATA_VECTOR(cfg->vector); | |
7601384f JR |
3114 | } |
3115 | ||
3116 | #ifdef CONFIG_PCI_MSI | |
3117 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, | |
3118 | struct msi_msg *msg, u8 hpet_id) | |
3119 | { | |
3120 | struct irq_cfg *cfg; | |
3121 | int err; | |
3122 | unsigned dest; | |
3123 | ||
3124 | if (disable_apic) | |
3125 | return -ENXIO; | |
3126 | ||
3127 | cfg = irq_cfg(irq); | |
3128 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); | |
3129 | if (err) | |
3130 | return err; | |
3131 | ||
3132 | err = apic->cpu_mask_to_apicid_and(cfg->domain, | |
3133 | apic->target_cpus(), &dest); | |
3134 | if (err) | |
3135 | return err; | |
3136 | ||
3137 | x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id); | |
54168ed7 | 3138 | |
51906e77 | 3139 | return 0; |
2d3fcc1c EB |
3140 | } |
3141 | ||
5346b2a7 TG |
3142 | static int |
3143 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
2d3fcc1c | 3144 | { |
5346b2a7 | 3145 | struct irq_cfg *cfg = data->chip_data; |
3b7d1921 EB |
3146 | struct msi_msg msg; |
3147 | unsigned int dest; | |
fb24da80 | 3148 | int ret; |
3b7d1921 | 3149 | |
fb24da80 PB |
3150 | ret = __ioapic_set_affinity(data, mask, &dest); |
3151 | if (ret) | |
3152 | return ret; | |
2d3fcc1c | 3153 | |
5346b2a7 | 3154 | __get_cached_msi_msg(data->msi_desc, &msg); |
3b7d1921 EB |
3155 | |
3156 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3157 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3158 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3159 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3160 | ||
83a18912 | 3161 | __pci_write_msi_msg(data->msi_desc, &msg); |
d5dedd45 | 3162 | |
f841d792 | 3163 | return IRQ_SET_MASK_OK_NOCOPY; |
2d3fcc1c EB |
3164 | } |
3165 | ||
3b7d1921 EB |
3166 | /* |
3167 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3168 | * which implement the MSI or MSI-X Capability Structure. | |
3169 | */ | |
3170 | static struct irq_chip msi_chip = { | |
5346b2a7 | 3171 | .name = "PCI-MSI", |
280510f1 TG |
3172 | .irq_unmask = pci_msi_unmask_irq, |
3173 | .irq_mask = pci_msi_mask_irq, | |
5346b2a7 | 3174 | .irq_ack = ack_apic_edge, |
5346b2a7 | 3175 | .irq_set_affinity = msi_set_affinity, |
5346b2a7 | 3176 | .irq_retrigger = ioapic_retrigger_irq, |
5613570b | 3177 | .flags = IRQCHIP_SKIP_SET_WAKE, |
2d3fcc1c EB |
3178 | }; |
3179 | ||
5afba62c JR |
3180 | int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
3181 | unsigned int irq_base, unsigned int irq_offset) | |
1d025192 | 3182 | { |
c60eaf25 | 3183 | struct irq_chip *chip = &msi_chip; |
1d025192 | 3184 | struct msi_msg msg; |
51906e77 | 3185 | unsigned int irq = irq_base + irq_offset; |
60c69948 | 3186 | int ret; |
1d025192 | 3187 | |
c8bc6f3c | 3188 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3189 | if (ret < 0) |
3190 | return ret; | |
3191 | ||
51906e77 AG |
3192 | irq_set_msi_desc_off(irq_base, irq_offset, msidesc); |
3193 | ||
3194 | /* | |
3195 | * MSI-X message is written per-IRQ, the offset is always 0. | |
3196 | * MSI message denotes a contiguous group of IRQs, written for 0th IRQ. | |
3197 | */ | |
3198 | if (!irq_offset) | |
83a18912 | 3199 | pci_write_msi_msg(irq, &msg); |
1d025192 | 3200 | |
32f5ef5d | 3201 | setup_remapped_irq(irq, irq_cfg(irq), chip); |
c60eaf25 TG |
3202 | |
3203 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); | |
1d025192 | 3204 | |
c81bba49 YL |
3205 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3206 | ||
1d025192 YL |
3207 | return 0; |
3208 | } | |
3209 | ||
5afba62c | 3210 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
047c8fdb | 3211 | { |
0b8f1efa | 3212 | struct msi_desc *msidesc; |
be47be6c | 3213 | unsigned int irq; |
5afba62c JR |
3214 | int node, ret; |
3215 | ||
3216 | /* Multiple MSI vectors only supported with interrupt remapping */ | |
3217 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3218 | return 1; | |
54168ed7 | 3219 | |
d047f53a | 3220 | node = dev_to_node(&dev->dev); |
be47be6c | 3221 | |
0b8f1efa | 3222 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
be47be6c TG |
3223 | irq = irq_alloc_hwirq(node); |
3224 | if (!irq) | |
51906e77 | 3225 | return -ENOSPC; |
5afba62c | 3226 | |
51906e77 | 3227 | ret = setup_msi_irq(dev, msidesc, irq, 0); |
be47be6c TG |
3228 | if (ret < 0) { |
3229 | irq_free_hwirq(irq); | |
3230 | return ret; | |
3231 | } | |
3232 | ||
54168ed7 IM |
3233 | } |
3234 | return 0; | |
047c8fdb YL |
3235 | } |
3236 | ||
294ee6f8 | 3237 | void native_teardown_msi_irq(unsigned int irq) |
3b7d1921 | 3238 | { |
be47be6c | 3239 | irq_free_hwirq(irq); |
3b7d1921 EB |
3240 | } |
3241 | ||
d3f13810 | 3242 | #ifdef CONFIG_DMAR_TABLE |
fe52b2d2 TG |
3243 | static int |
3244 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
3245 | bool force) | |
54168ed7 | 3246 | { |
fe52b2d2 TG |
3247 | struct irq_cfg *cfg = data->chip_data; |
3248 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3249 | struct msi_msg msg; |
fb24da80 | 3250 | int ret; |
54168ed7 | 3251 | |
fb24da80 PB |
3252 | ret = __ioapic_set_affinity(data, mask, &dest); |
3253 | if (ret) | |
3254 | return ret; | |
54168ed7 | 3255 | |
54168ed7 IM |
3256 | dmar_msi_read(irq, &msg); |
3257 | ||
3258 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3259 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3260 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3261 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
086e8ced | 3262 | msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); |
54168ed7 IM |
3263 | |
3264 | dmar_msi_write(irq, &msg); | |
d5dedd45 | 3265 | |
f841d792 | 3266 | return IRQ_SET_MASK_OK_NOCOPY; |
54168ed7 | 3267 | } |
3145e941 | 3268 | |
8f7007aa | 3269 | static struct irq_chip dmar_msi_type = { |
fe52b2d2 TG |
3270 | .name = "DMAR_MSI", |
3271 | .irq_unmask = dmar_msi_unmask, | |
3272 | .irq_mask = dmar_msi_mask, | |
3273 | .irq_ack = ack_apic_edge, | |
fe52b2d2 | 3274 | .irq_set_affinity = dmar_msi_set_affinity, |
fe52b2d2 | 3275 | .irq_retrigger = ioapic_retrigger_irq, |
5613570b | 3276 | .flags = IRQCHIP_SKIP_SET_WAKE, |
54168ed7 IM |
3277 | }; |
3278 | ||
3279 | int arch_setup_dmar_msi(unsigned int irq) | |
3280 | { | |
3281 | int ret; | |
3282 | struct msi_msg msg; | |
2d3fcc1c | 3283 | |
c8bc6f3c | 3284 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3285 | if (ret < 0) |
3286 | return ret; | |
3287 | dmar_msi_write(irq, &msg); | |
2c778651 TG |
3288 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, |
3289 | "edge"); | |
54168ed7 IM |
3290 | return 0; |
3291 | } | |
3292 | #endif | |
3293 | ||
58ac1e76 | 3294 | #ifdef CONFIG_HPET_TIMER |
3295 | ||
d0fbca8f TG |
3296 | static int hpet_msi_set_affinity(struct irq_data *data, |
3297 | const struct cpumask *mask, bool force) | |
58ac1e76 | 3298 | { |
d0fbca8f | 3299 | struct irq_cfg *cfg = data->chip_data; |
58ac1e76 | 3300 | struct msi_msg msg; |
3301 | unsigned int dest; | |
fb24da80 | 3302 | int ret; |
58ac1e76 | 3303 | |
fb24da80 PB |
3304 | ret = __ioapic_set_affinity(data, mask, &dest); |
3305 | if (ret) | |
3306 | return ret; | |
58ac1e76 | 3307 | |
d0fbca8f | 3308 | hpet_msi_read(data->handler_data, &msg); |
58ac1e76 | 3309 | |
3310 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3311 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3312 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3313 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3314 | ||
d0fbca8f | 3315 | hpet_msi_write(data->handler_data, &msg); |
d5dedd45 | 3316 | |
f841d792 | 3317 | return IRQ_SET_MASK_OK_NOCOPY; |
58ac1e76 | 3318 | } |
3145e941 | 3319 | |
1cc18521 | 3320 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3321 | .name = "HPET_MSI", |
d0fbca8f TG |
3322 | .irq_unmask = hpet_msi_unmask, |
3323 | .irq_mask = hpet_msi_mask, | |
90297c5f | 3324 | .irq_ack = ack_apic_edge, |
d0fbca8f | 3325 | .irq_set_affinity = hpet_msi_set_affinity, |
90297c5f | 3326 | .irq_retrigger = ioapic_retrigger_irq, |
5613570b | 3327 | .flags = IRQCHIP_SKIP_SET_WAKE, |
58ac1e76 | 3328 | }; |
3329 | ||
71054d88 | 3330 | int default_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3331 | { |
c60eaf25 | 3332 | struct irq_chip *chip = &hpet_msi_type; |
58ac1e76 | 3333 | struct msi_msg msg; |
d0fbca8f | 3334 | int ret; |
58ac1e76 | 3335 | |
c8bc6f3c | 3336 | ret = msi_compose_msg(NULL, irq, &msg, id); |
58ac1e76 | 3337 | if (ret < 0) |
3338 | return ret; | |
3339 | ||
2c778651 | 3340 | hpet_msi_write(irq_get_handler_data(irq), &msg); |
60c69948 | 3341 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
32f5ef5d | 3342 | setup_remapped_irq(irq, irq_cfg(irq), chip); |
c81bba49 | 3343 | |
c60eaf25 | 3344 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); |
58ac1e76 | 3345 | return 0; |
3346 | } | |
3347 | #endif | |
3348 | ||
54168ed7 | 3349 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3350 | /* |
3351 | * Hypertransport interrupt support | |
3352 | */ | |
3353 | #ifdef CONFIG_HT_IRQ | |
3354 | ||
497c9a19 | 3355 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3356 | { |
ec68307c EB |
3357 | struct ht_irq_msg msg; |
3358 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3359 | |
497c9a19 | 3360 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3361 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3362 | |
497c9a19 | 3363 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3364 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3365 | |
ec68307c | 3366 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3367 | } |
3368 | ||
be5b7bf7 TG |
3369 | static int |
3370 | ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
8b955b0d | 3371 | { |
be5b7bf7 | 3372 | struct irq_cfg *cfg = data->chip_data; |
8b955b0d | 3373 | unsigned int dest; |
fb24da80 | 3374 | int ret; |
8b955b0d | 3375 | |
fb24da80 PB |
3376 | ret = __ioapic_set_affinity(data, mask, &dest); |
3377 | if (ret) | |
3378 | return ret; | |
8b955b0d | 3379 | |
be5b7bf7 | 3380 | target_ht_irq(data->irq, dest, cfg->vector); |
f841d792 | 3381 | return IRQ_SET_MASK_OK_NOCOPY; |
8b955b0d | 3382 | } |
3145e941 | 3383 | |
c37e108d | 3384 | static struct irq_chip ht_irq_chip = { |
be5b7bf7 TG |
3385 | .name = "PCI-HT", |
3386 | .irq_mask = mask_ht_irq, | |
3387 | .irq_unmask = unmask_ht_irq, | |
3388 | .irq_ack = ack_apic_edge, | |
be5b7bf7 | 3389 | .irq_set_affinity = ht_set_affinity, |
be5b7bf7 | 3390 | .irq_retrigger = ioapic_retrigger_irq, |
5613570b | 3391 | .flags = IRQCHIP_SKIP_SET_WAKE, |
8b955b0d EB |
3392 | }; |
3393 | ||
3394 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3395 | { | |
497c9a19 | 3396 | struct irq_cfg *cfg; |
ff164324 AG |
3397 | struct ht_irq_msg msg; |
3398 | unsigned dest; | |
497c9a19 | 3399 | int err; |
8b955b0d | 3400 | |
f1182638 JB |
3401 | if (disable_apic) |
3402 | return -ENXIO; | |
3403 | ||
3145e941 | 3404 | cfg = irq_cfg(irq); |
fe402e1f | 3405 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
ff164324 AG |
3406 | if (err) |
3407 | return err; | |
8b955b0d | 3408 | |
ff164324 AG |
3409 | err = apic->cpu_mask_to_apicid_and(cfg->domain, |
3410 | apic->target_cpus(), &dest); | |
3411 | if (err) | |
3412 | return err; | |
8b955b0d | 3413 | |
ff164324 | 3414 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3415 | |
ff164324 AG |
3416 | msg.address_lo = |
3417 | HT_IRQ_LOW_BASE | | |
3418 | HT_IRQ_LOW_DEST_ID(dest) | | |
3419 | HT_IRQ_LOW_VECTOR(cfg->vector) | | |
3420 | ((apic->irq_dest_mode == 0) ? | |
3421 | HT_IRQ_LOW_DM_PHYSICAL : | |
3422 | HT_IRQ_LOW_DM_LOGICAL) | | |
3423 | HT_IRQ_LOW_RQEOI_EDGE | | |
3424 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
3425 | HT_IRQ_LOW_MT_FIXED : | |
3426 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3427 | HT_IRQ_LOW_IRQ_MASKED; | |
8b955b0d | 3428 | |
ff164324 | 3429 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3430 | |
ff164324 AG |
3431 | irq_set_chip_and_handler_name(irq, &ht_irq_chip, |
3432 | handle_edge_irq, "edge"); | |
8b955b0d | 3433 | |
ff164324 | 3434 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); |
c81bba49 | 3435 | |
ff164324 | 3436 | return 0; |
8b955b0d EB |
3437 | } |
3438 | #endif /* CONFIG_HT_IRQ */ | |
3439 | ||
20443598 | 3440 | static int |
ff973d04 TG |
3441 | io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) |
3442 | { | |
3443 | struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); | |
3444 | int ret; | |
3445 | ||
3446 | if (!cfg) | |
3447 | return -EINVAL; | |
3448 | ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); | |
3449 | if (!ret) | |
e4aff811 | 3450 | setup_ioapic_irq(irq, cfg, attr); |
ff973d04 TG |
3451 | return ret; |
3452 | } | |
3453 | ||
41098ffe | 3454 | static int __init io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
3455 | { |
3456 | union IO_APIC_reg_01 reg_01; | |
3457 | unsigned long flags; | |
3458 | ||
dade7716 | 3459 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3460 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3461 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3462 | |
4b6b19a1 EB |
3463 | /* The register returns the maximum index redir index |
3464 | * supported, which is one less than the total number of redir | |
3465 | * entries. | |
3466 | */ | |
3467 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3468 | } |
3469 | ||
62a08ae2 TG |
3470 | unsigned int arch_dynirq_lower_bound(unsigned int from) |
3471 | { | |
b81975ea JL |
3472 | /* |
3473 | * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use | |
3474 | * gsi_top if ioapic_dynirq_base hasn't been initialized yet. | |
3475 | */ | |
3476 | return ioapic_initialized ? ioapic_dynirq_base : gsi_top; | |
62a08ae2 TG |
3477 | } |
3478 | ||
4a046d17 YL |
3479 | int __init arch_probe_nr_irqs(void) |
3480 | { | |
3481 | int nr; | |
3482 | ||
f1ee5548 YL |
3483 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3484 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3485 | |
95d76acc | 3486 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; |
f1ee5548 YL |
3487 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) |
3488 | /* | |
3489 | * for MSI and HT dyn irq | |
3490 | */ | |
95d76acc | 3491 | nr += gsi_top * 16; |
f1ee5548 YL |
3492 | #endif |
3493 | if (nr < nr_irqs) | |
4a046d17 YL |
3494 | nr_irqs = nr; |
3495 | ||
4b92b4f7 | 3496 | return 0; |
4a046d17 | 3497 | } |
4a046d17 | 3498 | |
54168ed7 | 3499 | #ifdef CONFIG_X86_32 |
41098ffe | 3500 | static int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3501 | { |
3502 | union IO_APIC_reg_00 reg_00; | |
3503 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3504 | physid_mask_t tmp; | |
3505 | unsigned long flags; | |
3506 | int i = 0; | |
3507 | ||
3508 | /* | |
36062448 PC |
3509 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3510 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3511 | * supports up to 16 on one shared APIC bus. |
36062448 | 3512 | * |
1da177e4 LT |
3513 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3514 | * advantage of new APIC bus architecture. | |
3515 | */ | |
3516 | ||
3517 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3518 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3519 | |
dade7716 | 3520 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3521 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3522 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3523 | |
3524 | if (apic_id >= get_physical_broadcast()) { | |
3525 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3526 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3527 | apic_id = reg_00.bits.ID; | |
3528 | } | |
3529 | ||
3530 | /* | |
36062448 | 3531 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3532 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3533 | */ | |
7abc0753 | 3534 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3535 | |
3536 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3537 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3538 | break; |
3539 | } | |
3540 | ||
3541 | if (i == get_physical_broadcast()) | |
3542 | panic("Max apic_id exceeded!\n"); | |
3543 | ||
3544 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3545 | "trying %d\n", ioapic, apic_id, i); | |
3546 | ||
3547 | apic_id = i; | |
36062448 | 3548 | } |
1da177e4 | 3549 | |
7abc0753 | 3550 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3551 | physids_or(apic_id_map, apic_id_map, tmp); |
3552 | ||
3553 | if (reg_00.bits.ID != apic_id) { | |
3554 | reg_00.bits.ID = apic_id; | |
3555 | ||
dade7716 | 3556 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3557 | io_apic_write(ioapic, 0, reg_00.raw); |
3558 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3559 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3560 | |
3561 | /* Sanity check */ | |
6070f9ec | 3562 | if (reg_00.bits.ID != apic_id) { |
c767a54b JP |
3563 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
3564 | ioapic); | |
6070f9ec AD |
3565 | return -1; |
3566 | } | |
1da177e4 LT |
3567 | } |
3568 | ||
3569 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3570 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3571 | ||
3572 | return apic_id; | |
3573 | } | |
41098ffe TG |
3574 | |
3575 | static u8 __init io_apic_unique_id(u8 id) | |
3576 | { | |
3577 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3578 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3579 | return io_apic_get_unique_id(nr_ioapics, id); | |
3580 | else | |
3581 | return id; | |
3582 | } | |
3583 | #else | |
3584 | static u8 __init io_apic_unique_id(u8 id) | |
3585 | { | |
3586 | int i; | |
3587 | DECLARE_BITMAP(used, 256); | |
3588 | ||
3589 | bitmap_zero(used, 256); | |
f44d1692 | 3590 | for_each_ioapic(i) |
d5371430 | 3591 | __set_bit(mpc_ioapic_id(i), used); |
41098ffe TG |
3592 | if (!test_bit(id, used)) |
3593 | return id; | |
3594 | return find_first_zero_bit(used, 256); | |
3595 | } | |
58f892e0 | 3596 | #endif |
1da177e4 | 3597 | |
41098ffe | 3598 | static int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3599 | { |
3600 | union IO_APIC_reg_01 reg_01; | |
3601 | unsigned long flags; | |
3602 | ||
dade7716 | 3603 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3604 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3605 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3606 | |
3607 | return reg_01.bits.version; | |
3608 | } | |
3609 | ||
9a0a91bb | 3610 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 3611 | { |
9a0a91bb | 3612 | int ioapic, pin, idx; |
61fd47e0 SL |
3613 | |
3614 | if (skip_ioapic_setup) | |
3615 | return -1; | |
3616 | ||
9a0a91bb EB |
3617 | ioapic = mp_find_ioapic(gsi); |
3618 | if (ioapic < 0) | |
61fd47e0 SL |
3619 | return -1; |
3620 | ||
9a0a91bb EB |
3621 | pin = mp_find_ioapic_pin(ioapic, gsi); |
3622 | if (pin < 0) | |
3623 | return -1; | |
3624 | ||
3625 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
3626 | if (idx < 0) | |
61fd47e0 SL |
3627 | return -1; |
3628 | ||
9a0a91bb EB |
3629 | *trigger = irq_trigger(idx); |
3630 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
3631 | return 0; |
3632 | } | |
3633 | ||
497c9a19 YL |
3634 | /* |
3635 | * This function currently is only a helper for the i386 smp boot process where | |
3636 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 3637 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
3638 | */ |
3639 | #ifdef CONFIG_SMP | |
3640 | void __init setup_ioapic_dest(void) | |
3641 | { | |
fad53995 | 3642 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 3643 | const struct cpumask *mask; |
5451ddc5 | 3644 | struct irq_data *idata; |
497c9a19 YL |
3645 | |
3646 | if (skip_ioapic_setup == 1) | |
3647 | return; | |
3648 | ||
f44d1692 | 3649 | for_each_ioapic_pin(ioapic, pin) { |
b9c61b70 YL |
3650 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
3651 | if (irq_entry == -1) | |
3652 | continue; | |
6c2e9403 | 3653 | |
d7f3d478 JL |
3654 | irq = pin_2_irq(irq_entry, ioapic, pin, 0); |
3655 | if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq)) | |
fad53995 EB |
3656 | continue; |
3657 | ||
5451ddc5 | 3658 | idata = irq_get_irq_data(irq); |
6c2e9403 | 3659 | |
b9c61b70 YL |
3660 | /* |
3661 | * Honour affinities which have been set in early boot | |
3662 | */ | |
5451ddc5 TG |
3663 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
3664 | mask = idata->affinity; | |
b9c61b70 YL |
3665 | else |
3666 | mask = apic->target_cpus(); | |
497c9a19 | 3667 | |
373dd7a2 | 3668 | x86_io_apic_ops.set_affinity(idata, mask, false); |
497c9a19 | 3669 | } |
b9c61b70 | 3670 | |
497c9a19 YL |
3671 | } |
3672 | #endif | |
3673 | ||
54168ed7 IM |
3674 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3675 | ||
3676 | static struct resource *ioapic_resources; | |
3677 | ||
f44d1692 | 3678 | static struct resource * __init ioapic_setup_resources(void) |
54168ed7 IM |
3679 | { |
3680 | unsigned long n; | |
3681 | struct resource *res; | |
3682 | char *mem; | |
f44d1692 | 3683 | int i, num = 0; |
54168ed7 | 3684 | |
f44d1692 JL |
3685 | for_each_ioapic(i) |
3686 | num++; | |
3687 | if (num == 0) | |
54168ed7 IM |
3688 | return NULL; |
3689 | ||
3690 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
f44d1692 | 3691 | n *= num; |
54168ed7 IM |
3692 | |
3693 | mem = alloc_bootmem(n); | |
3694 | res = (void *)mem; | |
3695 | ||
f44d1692 | 3696 | mem += sizeof(struct resource) * num; |
54168ed7 | 3697 | |
f44d1692 JL |
3698 | num = 0; |
3699 | for_each_ioapic(i) { | |
3700 | res[num].name = mem; | |
3701 | res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 3702 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 3703 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
f44d1692 | 3704 | num++; |
54168ed7 IM |
3705 | } |
3706 | ||
3707 | ioapic_resources = res; | |
3708 | ||
3709 | return res; | |
3710 | } | |
54168ed7 | 3711 | |
4a8e2a31 | 3712 | void __init native_io_apic_init_mappings(void) |
f3294a33 YL |
3713 | { |
3714 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 3715 | struct resource *ioapic_res; |
d6c88a50 | 3716 | int i; |
f3294a33 | 3717 | |
f44d1692 JL |
3718 | ioapic_res = ioapic_setup_resources(); |
3719 | for_each_ioapic(i) { | |
f3294a33 | 3720 | if (smp_found_config) { |
d5371430 | 3721 | ioapic_phys = mpc_ioapic_addr(i); |
54168ed7 | 3722 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
3723 | if (!ioapic_phys) { |
3724 | printk(KERN_ERR | |
3725 | "WARNING: bogus zero IO-APIC " | |
3726 | "address found in MPTABLE, " | |
3727 | "disabling IO/APIC support!\n"); | |
3728 | smp_found_config = 0; | |
3729 | skip_ioapic_setup = 1; | |
3730 | goto fake_ioapic_page; | |
3731 | } | |
54168ed7 | 3732 | #endif |
f3294a33 | 3733 | } else { |
54168ed7 | 3734 | #ifdef CONFIG_X86_32 |
f3294a33 | 3735 | fake_ioapic_page: |
54168ed7 | 3736 | #endif |
e79c65a9 | 3737 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3738 | ioapic_phys = __pa(ioapic_phys); |
3739 | } | |
3740 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
3741 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
3742 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
3743 | ioapic_phys); | |
f3294a33 | 3744 | idx++; |
54168ed7 | 3745 | |
ffc43836 | 3746 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 3747 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 3748 | ioapic_res++; |
f3294a33 YL |
3749 | } |
3750 | } | |
3751 | ||
857fdc53 | 3752 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
3753 | { |
3754 | int i; | |
3755 | struct resource *r = ioapic_resources; | |
3756 | ||
3757 | if (!r) { | |
857fdc53 | 3758 | if (nr_ioapics > 0) |
04c93ce4 BZ |
3759 | printk(KERN_ERR |
3760 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 3761 | return; |
54168ed7 IM |
3762 | } |
3763 | ||
f44d1692 | 3764 | for_each_ioapic(i) { |
54168ed7 IM |
3765 | insert_resource(&iomem_resource, r); |
3766 | r++; | |
3767 | } | |
54168ed7 | 3768 | } |
2a4ab640 | 3769 | |
eddb0c55 | 3770 | int mp_find_ioapic(u32 gsi) |
2a4ab640 | 3771 | { |
f44d1692 | 3772 | int i; |
2a4ab640 | 3773 | |
678301ec PB |
3774 | if (nr_ioapics == 0) |
3775 | return -1; | |
3776 | ||
2a4ab640 | 3777 | /* Find the IOAPIC that manages this GSI. */ |
f44d1692 | 3778 | for_each_ioapic(i) { |
c040aaeb | 3779 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
f44d1692 | 3780 | if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) |
2a4ab640 FT |
3781 | return i; |
3782 | } | |
54168ed7 | 3783 | |
2a4ab640 FT |
3784 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
3785 | return -1; | |
3786 | } | |
3787 | ||
eddb0c55 | 3788 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 | 3789 | { |
c040aaeb SS |
3790 | struct mp_ioapic_gsi *gsi_cfg; |
3791 | ||
f44d1692 | 3792 | if (WARN_ON(ioapic < 0)) |
2a4ab640 | 3793 | return -1; |
c040aaeb SS |
3794 | |
3795 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
3796 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) | |
2a4ab640 FT |
3797 | return -1; |
3798 | ||
c040aaeb | 3799 | return gsi - gsi_cfg->gsi_base; |
2a4ab640 FT |
3800 | } |
3801 | ||
41098ffe | 3802 | static __init int bad_ioapic(unsigned long address) |
2a4ab640 FT |
3803 | { |
3804 | if (nr_ioapics >= MAX_IO_APICS) { | |
73d63d03 SS |
3805 | pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n", |
3806 | MAX_IO_APICS, nr_ioapics); | |
2a4ab640 FT |
3807 | return 1; |
3808 | } | |
3809 | if (!address) { | |
73d63d03 | 3810 | pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n"); |
2a4ab640 FT |
3811 | return 1; |
3812 | } | |
54168ed7 IM |
3813 | return 0; |
3814 | } | |
3815 | ||
73d63d03 SS |
3816 | static __init int bad_ioapic_register(int idx) |
3817 | { | |
3818 | union IO_APIC_reg_00 reg_00; | |
3819 | union IO_APIC_reg_01 reg_01; | |
3820 | union IO_APIC_reg_02 reg_02; | |
3821 | ||
3822 | reg_00.raw = io_apic_read(idx, 0); | |
3823 | reg_01.raw = io_apic_read(idx, 1); | |
3824 | reg_02.raw = io_apic_read(idx, 2); | |
3825 | ||
3826 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { | |
3827 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", | |
3828 | mpc_ioapic_addr(idx)); | |
3829 | return 1; | |
3830 | } | |
3831 | ||
3832 | return 0; | |
3833 | } | |
3834 | ||
44767bfa JL |
3835 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base, |
3836 | struct ioapic_domain_cfg *cfg) | |
2a4ab640 FT |
3837 | { |
3838 | int idx = 0; | |
7716a5c4 | 3839 | int entries; |
c040aaeb | 3840 | struct mp_ioapic_gsi *gsi_cfg; |
2a4ab640 FT |
3841 | |
3842 | if (bad_ioapic(address)) | |
3843 | return; | |
3844 | ||
3845 | idx = nr_ioapics; | |
3846 | ||
d5371430 SS |
3847 | ioapics[idx].mp_config.type = MP_IOAPIC; |
3848 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; | |
3849 | ioapics[idx].mp_config.apicaddr = address; | |
44767bfa | 3850 | ioapics[idx].irqdomain = NULL; |
b81975ea | 3851 | ioapics[idx].irqdomain_cfg = *cfg; |
2a4ab640 FT |
3852 | |
3853 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
73d63d03 SS |
3854 | |
3855 | if (bad_ioapic_register(idx)) { | |
3856 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
3857 | return; | |
3858 | } | |
3859 | ||
d5371430 SS |
3860 | ioapics[idx].mp_config.apicid = io_apic_unique_id(id); |
3861 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); | |
2a4ab640 FT |
3862 | |
3863 | /* | |
3864 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
3865 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
3866 | */ | |
7716a5c4 | 3867 | entries = io_apic_get_redir_entries(idx); |
c040aaeb SS |
3868 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
3869 | gsi_cfg->gsi_base = gsi_base; | |
3870 | gsi_cfg->gsi_end = gsi_base + entries - 1; | |
7716a5c4 EB |
3871 | |
3872 | /* | |
3873 | * The number of IO-APIC IRQ registers (== #pins): | |
3874 | */ | |
b69c6c3b | 3875 | ioapics[idx].nr_registers = entries; |
2a4ab640 | 3876 | |
c040aaeb SS |
3877 | if (gsi_cfg->gsi_end >= gsi_top) |
3878 | gsi_top = gsi_cfg->gsi_end + 1; | |
2a4ab640 | 3879 | |
73d63d03 SS |
3880 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
3881 | idx, mpc_ioapic_id(idx), | |
3882 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), | |
3883 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2a4ab640 FT |
3884 | |
3885 | nr_ioapics++; | |
3886 | } | |
05ddafb1 | 3887 | |
15a3c7cc JL |
3888 | int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq, |
3889 | irq_hw_number_t hwirq) | |
3890 | { | |
3891 | int ioapic = (int)(long)domain->host_data; | |
3892 | struct mp_pin_info *info = mp_pin_info(ioapic, hwirq); | |
3893 | struct io_apic_irq_attr attr; | |
3894 | ||
15a3c7cc JL |
3895 | /* Get default attribute if not set by caller yet */ |
3896 | if (!info->set) { | |
3897 | u32 gsi = mp_pin_to_gsi(ioapic, hwirq); | |
3898 | ||
3899 | if (acpi_get_override_irq(gsi, &info->trigger, | |
3900 | &info->polarity) < 0) { | |
3901 | /* | |
3902 | * PCI interrupts are always polarity one level | |
3903 | * triggered. | |
3904 | */ | |
3905 | info->trigger = 1; | |
3906 | info->polarity = 1; | |
3907 | } | |
3908 | info->node = NUMA_NO_NODE; | |
f395dcae JL |
3909 | |
3910 | /* | |
3911 | * setup_IO_APIC_irqs() programs all legacy IRQs with default | |
3912 | * trigger and polarity attributes. Don't set the flag for that | |
3913 | * case so the first legacy IRQ user could reprogram the pin | |
3914 | * with real trigger and polarity attributes. | |
3915 | */ | |
3916 | if (virq >= nr_legacy_irqs() || info->count) | |
3917 | info->set = 1; | |
15a3c7cc JL |
3918 | } |
3919 | set_io_apic_irq_attr(&attr, ioapic, hwirq, info->trigger, | |
3920 | info->polarity); | |
3921 | ||
3922 | return io_apic_setup_irq_pin(virq, info->node, &attr); | |
3923 | } | |
3924 | ||
df334bea JL |
3925 | void mp_irqdomain_unmap(struct irq_domain *domain, unsigned int virq) |
3926 | { | |
3927 | struct irq_data *data = irq_get_irq_data(virq); | |
3928 | struct irq_cfg *cfg = irq_cfg(virq); | |
3929 | int ioapic = (int)(long)domain->host_data; | |
3930 | int pin = (int)data->hwirq; | |
3931 | ||
df334bea JL |
3932 | ioapic_mask_entry(ioapic, pin); |
3933 | __remove_pin_from_irq(cfg, ioapic, pin); | |
3934 | WARN_ON(cfg->irq_2_pin != NULL); | |
3935 | arch_teardown_hwirq(virq); | |
3936 | } | |
3937 | ||
15a3c7cc JL |
3938 | int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node) |
3939 | { | |
3940 | int ret = 0; | |
3941 | int ioapic, pin; | |
3942 | struct mp_pin_info *info; | |
3943 | ||
3944 | ioapic = mp_find_ioapic(gsi); | |
3945 | if (ioapic < 0) | |
3946 | return -ENODEV; | |
3947 | ||
3948 | pin = mp_find_ioapic_pin(ioapic, gsi); | |
3949 | info = mp_pin_info(ioapic, pin); | |
3950 | trigger = trigger ? 1 : 0; | |
3951 | polarity = polarity ? 1 : 0; | |
3952 | ||
3953 | mutex_lock(&ioapic_mutex); | |
3954 | if (!info->set) { | |
3955 | info->trigger = trigger; | |
3956 | info->polarity = polarity; | |
3957 | info->node = node; | |
3958 | info->set = 1; | |
3959 | } else if (info->trigger != trigger || info->polarity != polarity) { | |
3960 | ret = -EBUSY; | |
3961 | } | |
3962 | mutex_unlock(&ioapic_mutex); | |
3963 | ||
3964 | return ret; | |
3965 | } | |
3966 | ||
9eabc99a JL |
3967 | bool mp_should_keep_irq(struct device *dev) |
3968 | { | |
3969 | if (dev->power.is_prepared) | |
3970 | return true; | |
3971 | #ifdef CONFIG_PM_RUNTIME | |
3972 | if (dev->power.runtime_status == RPM_SUSPENDING) | |
3973 | return true; | |
3974 | #endif | |
3975 | ||
3976 | return false; | |
3977 | } | |
3978 | ||
05ddafb1 JP |
3979 | /* Enable IOAPIC early just for system timer */ |
3980 | void __init pre_init_apic_IRQ0(void) | |
3981 | { | |
f880ec78 | 3982 | struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; |
05ddafb1 JP |
3983 | |
3984 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
3985 | #ifndef CONFIG_SMP | |
cb2ded37 YL |
3986 | physid_set_mask_of_physid(boot_cpu_physical_apicid, |
3987 | &phys_cpu_present_map); | |
05ddafb1 | 3988 | #endif |
05ddafb1 JP |
3989 | setup_local_APIC(); |
3990 | ||
f880ec78 | 3991 | io_apic_setup_irq_pin(0, 0, &attr); |
2c778651 TG |
3992 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
3993 | "edge"); | |
05ddafb1 | 3994 | } |