Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
4173a0e7 DN |
63 | #include <asm/uv/uv_hub.h> |
64 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 65 | |
7b6aa335 | 66 | #include <asm/apic.h> |
1da177e4 | 67 | |
32f71aff | 68 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
69 | #define for_each_irq_pin(entry, head) \ |
70 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 71 | |
1da177e4 | 72 | /* |
54168ed7 IM |
73 | * Is the SiS APIC rmw bug present ? |
74 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
75 | */ |
76 | int sis_apic_bug = -1; | |
77 | ||
efa2559f YL |
78 | static DEFINE_SPINLOCK(ioapic_lock); |
79 | static DEFINE_SPINLOCK(vector_lock); | |
80 | ||
1da177e4 LT |
81 | /* |
82 | * # of IRQ routing registers | |
83 | */ | |
84 | int nr_ioapic_registers[MAX_IO_APICS]; | |
85 | ||
9f640ccb | 86 | /* I/O APIC entries */ |
b5ba7e6d | 87 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
88 | int nr_ioapics; |
89 | ||
2a4ab640 FT |
90 | /* IO APIC gsi routing info */ |
91 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
92 | ||
584f734d | 93 | /* MP IRQ source entries */ |
c2c21745 | 94 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
95 | |
96 | /* # of MP IRQ source entries */ | |
97 | int mp_irq_entries; | |
98 | ||
bc07844a TG |
99 | /* Number of legacy interrupts */ |
100 | static int nr_legacy_irqs __read_mostly = NR_IRQS_LEGACY; | |
101 | /* GSI interrupts */ | |
102 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
103 | ||
8732fc4b AS |
104 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
105 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
106 | #endif | |
107 | ||
108 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
109 | ||
efa2559f YL |
110 | int skip_ioapic_setup; |
111 | ||
65a4e574 IM |
112 | void arch_disable_smp_support(void) |
113 | { | |
114 | #ifdef CONFIG_PCI | |
115 | noioapicquirk = 1; | |
116 | noioapicreroute = -1; | |
117 | #endif | |
118 | skip_ioapic_setup = 1; | |
119 | } | |
120 | ||
54168ed7 | 121 | static int __init parse_noapic(char *str) |
efa2559f YL |
122 | { |
123 | /* disable IO-APIC */ | |
65a4e574 | 124 | arch_disable_smp_support(); |
efa2559f YL |
125 | return 0; |
126 | } | |
127 | early_param("noapic", parse_noapic); | |
66759a01 | 128 | |
0b8f1efa YL |
129 | struct irq_pin_list { |
130 | int apic, pin; | |
131 | struct irq_pin_list *next; | |
132 | }; | |
133 | ||
85ac16d0 | 134 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
135 | { |
136 | struct irq_pin_list *pin; | |
0b8f1efa YL |
137 | |
138 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
139 | |
140 | return pin; | |
141 | } | |
142 | ||
8e13d697 JF |
143 | /* |
144 | * This is performance-critical, we want to do it O(1) | |
145 | * | |
146 | * Most irqs are mapped 1:1 with pins. | |
147 | */ | |
a1420f39 | 148 | struct irq_cfg { |
0f978f45 | 149 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
150 | cpumask_var_t domain; |
151 | cpumask_var_t old_domain; | |
497c9a19 | 152 | unsigned move_cleanup_count; |
a1420f39 | 153 | u8 vector; |
497c9a19 | 154 | u8 move_in_progress : 1; |
a1420f39 YL |
155 | }; |
156 | ||
a1420f39 | 157 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
158 | #ifdef CONFIG_SPARSE_IRQ |
159 | static struct irq_cfg irq_cfgx[] = { | |
160 | #else | |
d6c88a50 | 161 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 162 | #endif |
22f65d31 MT |
163 | [0] = { .vector = IRQ0_VECTOR, }, |
164 | [1] = { .vector = IRQ1_VECTOR, }, | |
165 | [2] = { .vector = IRQ2_VECTOR, }, | |
166 | [3] = { .vector = IRQ3_VECTOR, }, | |
167 | [4] = { .vector = IRQ4_VECTOR, }, | |
168 | [5] = { .vector = IRQ5_VECTOR, }, | |
169 | [6] = { .vector = IRQ6_VECTOR, }, | |
170 | [7] = { .vector = IRQ7_VECTOR, }, | |
171 | [8] = { .vector = IRQ8_VECTOR, }, | |
172 | [9] = { .vector = IRQ9_VECTOR, }, | |
173 | [10] = { .vector = IRQ10_VECTOR, }, | |
174 | [11] = { .vector = IRQ11_VECTOR, }, | |
175 | [12] = { .vector = IRQ12_VECTOR, }, | |
176 | [13] = { .vector = IRQ13_VECTOR, }, | |
177 | [14] = { .vector = IRQ14_VECTOR, }, | |
178 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
179 | }; |
180 | ||
bc07844a TG |
181 | void __init io_apic_disable_legacy(void) |
182 | { | |
183 | nr_legacy_irqs = 0; | |
184 | nr_irqs_gsi = 0; | |
185 | } | |
186 | ||
13a0c3c2 | 187 | int __init arch_early_irq_init(void) |
8f09cd20 | 188 | { |
0b8f1efa YL |
189 | struct irq_cfg *cfg; |
190 | struct irq_desc *desc; | |
191 | int count; | |
dad213ae | 192 | int node; |
0b8f1efa | 193 | int i; |
d6c88a50 | 194 | |
0b8f1efa YL |
195 | cfg = irq_cfgx; |
196 | count = ARRAY_SIZE(irq_cfgx); | |
dad213ae | 197 | node= cpu_to_node(boot_cpu_id); |
8f09cd20 | 198 | |
0b8f1efa YL |
199 | for (i = 0; i < count; i++) { |
200 | desc = irq_to_desc(i); | |
201 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
202 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
203 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
bc07844a | 204 | if (i < nr_legacy_irqs) |
22f65d31 | 205 | cpumask_setall(cfg[i].domain); |
0b8f1efa | 206 | } |
13a0c3c2 YL |
207 | |
208 | return 0; | |
0b8f1efa | 209 | } |
8f09cd20 | 210 | |
0b8f1efa | 211 | #ifdef CONFIG_SPARSE_IRQ |
d6c88a50 | 212 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 213 | { |
0b8f1efa YL |
214 | struct irq_cfg *cfg = NULL; |
215 | struct irq_desc *desc; | |
1da177e4 | 216 | |
0b8f1efa YL |
217 | desc = irq_to_desc(irq); |
218 | if (desc) | |
219 | cfg = desc->chip_data; | |
0f978f45 | 220 | |
0b8f1efa | 221 | return cfg; |
8f09cd20 | 222 | } |
d6c88a50 | 223 | |
85ac16d0 | 224 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 225 | { |
0b8f1efa | 226 | struct irq_cfg *cfg; |
0f978f45 | 227 | |
0b8f1efa | 228 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 229 | if (cfg) { |
79f55997 | 230 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
231 | kfree(cfg); |
232 | cfg = NULL; | |
79f55997 | 233 | } else if (!zalloc_cpumask_var_node(&cfg->old_domain, |
80855f73 | 234 | GFP_ATOMIC, node)) { |
22f65d31 MT |
235 | free_cpumask_var(cfg->domain); |
236 | kfree(cfg); | |
237 | cfg = NULL; | |
22f65d31 MT |
238 | } |
239 | } | |
0f978f45 | 240 | |
0b8f1efa | 241 | return cfg; |
8f09cd20 YL |
242 | } |
243 | ||
85ac16d0 | 244 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 245 | { |
0b8f1efa | 246 | struct irq_cfg *cfg; |
d6c88a50 | 247 | |
0b8f1efa YL |
248 | cfg = desc->chip_data; |
249 | if (!cfg) { | |
85ac16d0 | 250 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
251 | if (!desc->chip_data) { |
252 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
253 | BUG_ON(1); | |
254 | } | |
255 | } | |
1da177e4 | 256 | |
13a0c3c2 | 257 | return 0; |
0b8f1efa | 258 | } |
0f978f45 | 259 | |
fcef5911 | 260 | /* for move_irq_desc */ |
48a1b10a | 261 | static void |
85ac16d0 | 262 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 263 | { |
48a1b10a YL |
264 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
265 | ||
266 | cfg->irq_2_pin = NULL; | |
267 | old_entry = old_cfg->irq_2_pin; | |
268 | if (!old_entry) | |
269 | return; | |
0f978f45 | 270 | |
85ac16d0 | 271 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
272 | if (!entry) |
273 | return; | |
0f978f45 | 274 | |
48a1b10a YL |
275 | entry->apic = old_entry->apic; |
276 | entry->pin = old_entry->pin; | |
277 | head = entry; | |
278 | tail = entry; | |
279 | old_entry = old_entry->next; | |
280 | while (old_entry) { | |
85ac16d0 | 281 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
282 | if (!entry) { |
283 | entry = head; | |
284 | while (entry) { | |
285 | head = entry->next; | |
286 | kfree(entry); | |
287 | entry = head; | |
288 | } | |
289 | /* still use the old one */ | |
290 | return; | |
291 | } | |
292 | entry->apic = old_entry->apic; | |
293 | entry->pin = old_entry->pin; | |
294 | tail->next = entry; | |
295 | tail = entry; | |
296 | old_entry = old_entry->next; | |
297 | } | |
0f978f45 | 298 | |
48a1b10a YL |
299 | tail->next = NULL; |
300 | cfg->irq_2_pin = head; | |
0f978f45 | 301 | } |
0f978f45 | 302 | |
48a1b10a | 303 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 304 | { |
48a1b10a | 305 | struct irq_pin_list *entry, *next; |
0f978f45 | 306 | |
48a1b10a YL |
307 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
308 | return; | |
301e6190 | 309 | |
48a1b10a | 310 | entry = old_cfg->irq_2_pin; |
0f978f45 | 311 | |
48a1b10a YL |
312 | while (entry) { |
313 | next = entry->next; | |
314 | kfree(entry); | |
315 | entry = next; | |
316 | } | |
317 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 318 | } |
0f978f45 | 319 | |
48a1b10a | 320 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 321 | struct irq_desc *desc, int node) |
0f978f45 | 322 | { |
48a1b10a YL |
323 | struct irq_cfg *cfg; |
324 | struct irq_cfg *old_cfg; | |
0f978f45 | 325 | |
85ac16d0 | 326 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 327 | |
48a1b10a YL |
328 | if (!cfg) |
329 | return; | |
330 | ||
331 | desc->chip_data = cfg; | |
332 | ||
333 | old_cfg = old_desc->chip_data; | |
334 | ||
335 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
336 | ||
85ac16d0 | 337 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 338 | } |
1da177e4 | 339 | |
48a1b10a YL |
340 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
341 | { | |
342 | kfree(old_cfg); | |
343 | } | |
344 | ||
345 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
346 | { | |
347 | struct irq_cfg *old_cfg, *cfg; | |
348 | ||
349 | old_cfg = old_desc->chip_data; | |
350 | cfg = desc->chip_data; | |
351 | ||
352 | if (old_cfg == cfg) | |
353 | return; | |
354 | ||
355 | if (old_cfg) { | |
356 | free_irq_2_pin(old_cfg, cfg); | |
357 | free_irq_cfg(old_cfg); | |
358 | old_desc->chip_data = NULL; | |
359 | } | |
360 | } | |
fcef5911 | 361 | /* end for move_irq_desc */ |
48a1b10a | 362 | |
0b8f1efa YL |
363 | #else |
364 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
365 | { | |
366 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 367 | } |
1da177e4 | 368 | |
0b8f1efa YL |
369 | #endif |
370 | ||
130fe05d LT |
371 | struct io_apic { |
372 | unsigned int index; | |
373 | unsigned int unused[3]; | |
374 | unsigned int data; | |
0280f7c4 SS |
375 | unsigned int unused2[11]; |
376 | unsigned int eoi; | |
130fe05d LT |
377 | }; |
378 | ||
379 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
380 | { | |
381 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 382 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
383 | } |
384 | ||
0280f7c4 SS |
385 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
386 | { | |
387 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
388 | writel(vector, &io_apic->eoi); | |
389 | } | |
390 | ||
130fe05d LT |
391 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
392 | { | |
393 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
394 | writel(reg, &io_apic->index); | |
395 | return readl(&io_apic->data); | |
396 | } | |
397 | ||
398 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
399 | { | |
400 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
401 | writel(reg, &io_apic->index); | |
402 | writel(value, &io_apic->data); | |
403 | } | |
404 | ||
405 | /* | |
406 | * Re-write a value: to be used for read-modify-write | |
407 | * cycles where the read already set up the index register. | |
408 | * | |
409 | * Older SiS APIC requires we rewrite the index register | |
410 | */ | |
411 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
412 | { | |
54168ed7 | 413 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
414 | |
415 | if (sis_apic_bug) | |
416 | writel(reg, &io_apic->index); | |
130fe05d LT |
417 | writel(value, &io_apic->data); |
418 | } | |
419 | ||
3145e941 | 420 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
421 | { |
422 | struct irq_pin_list *entry; | |
423 | unsigned long flags; | |
047c8fdb YL |
424 | |
425 | spin_lock_irqsave(&ioapic_lock, flags); | |
2977fb3f | 426 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
427 | unsigned int reg; |
428 | int pin; | |
429 | ||
047c8fdb YL |
430 | pin = entry->pin; |
431 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
432 | /* Is the remote IRR bit set? */ | |
433 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
434 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
435 | return true; | |
436 | } | |
047c8fdb YL |
437 | } |
438 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
439 | ||
440 | return false; | |
441 | } | |
047c8fdb | 442 | |
cf4c6a2f AK |
443 | union entry_union { |
444 | struct { u32 w1, w2; }; | |
445 | struct IO_APIC_route_entry entry; | |
446 | }; | |
447 | ||
448 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
449 | { | |
450 | union entry_union eu; | |
451 | unsigned long flags; | |
452 | spin_lock_irqsave(&ioapic_lock, flags); | |
453 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
454 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
455 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
456 | return eu.entry; | |
457 | } | |
458 | ||
f9dadfa7 LT |
459 | /* |
460 | * When we write a new IO APIC routing entry, we need to write the high | |
461 | * word first! If the mask bit in the low word is clear, we will enable | |
462 | * the interrupt, and we need to make sure the entry is fully populated | |
463 | * before that happens. | |
464 | */ | |
d15512f4 AK |
465 | static void |
466 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 467 | { |
50a8d4d2 F |
468 | union entry_union eu = {{0, 0}}; |
469 | ||
cf4c6a2f | 470 | eu.entry = e; |
f9dadfa7 LT |
471 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
472 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
473 | } |
474 | ||
ca97ab90 | 475 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
476 | { |
477 | unsigned long flags; | |
478 | spin_lock_irqsave(&ioapic_lock, flags); | |
479 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
480 | spin_unlock_irqrestore(&ioapic_lock, flags); |
481 | } | |
482 | ||
483 | /* | |
484 | * When we mask an IO APIC routing entry, we need to write the low | |
485 | * word first, in order to set the mask bit before we change the | |
486 | * high bits! | |
487 | */ | |
488 | static void ioapic_mask_entry(int apic, int pin) | |
489 | { | |
490 | unsigned long flags; | |
491 | union entry_union eu = { .entry.mask = 1 }; | |
492 | ||
cf4c6a2f AK |
493 | spin_lock_irqsave(&ioapic_lock, flags); |
494 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
495 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
496 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
497 | } | |
498 | ||
1da177e4 LT |
499 | /* |
500 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
501 | * shared ISA-space IRQs, so we have to support them. We are super | |
502 | * fast in the common case, and fast for shared ISA-space IRQs. | |
503 | */ | |
f3d1915a CG |
504 | static int |
505 | add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin) | |
1da177e4 | 506 | { |
2977fb3f | 507 | struct irq_pin_list **last, *entry; |
0f978f45 | 508 | |
2977fb3f CG |
509 | /* don't allow duplicates */ |
510 | last = &cfg->irq_2_pin; | |
511 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 512 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 513 | return 0; |
2977fb3f | 514 | last = &entry->next; |
1da177e4 | 515 | } |
0f978f45 | 516 | |
875e68ec | 517 | entry = get_one_free_irq_2_pin(node); |
a7428cd2 | 518 | if (!entry) { |
f3d1915a CG |
519 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
520 | node, apic, pin); | |
521 | return -ENOMEM; | |
a7428cd2 | 522 | } |
1da177e4 LT |
523 | entry->apic = apic; |
524 | entry->pin = pin; | |
875e68ec | 525 | |
2977fb3f | 526 | *last = entry; |
f3d1915a CG |
527 | return 0; |
528 | } | |
529 | ||
530 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
531 | { | |
532 | if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin)) | |
533 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); | |
1da177e4 LT |
534 | } |
535 | ||
536 | /* | |
537 | * Reroute an IRQ to a different pin. | |
538 | */ | |
85ac16d0 | 539 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
540 | int oldapic, int oldpin, |
541 | int newapic, int newpin) | |
1da177e4 | 542 | { |
535b6429 | 543 | struct irq_pin_list *entry; |
1da177e4 | 544 | |
2977fb3f | 545 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
546 | if (entry->apic == oldapic && entry->pin == oldpin) { |
547 | entry->apic = newapic; | |
548 | entry->pin = newpin; | |
0f978f45 | 549 | /* every one is different, right? */ |
4eea6fff | 550 | return; |
0f978f45 | 551 | } |
1da177e4 | 552 | } |
0f978f45 | 553 | |
4eea6fff JF |
554 | /* old apic/pin didn't exist, so just add new ones */ |
555 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
556 | } |
557 | ||
2f210deb JF |
558 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
559 | int mask_and, int mask_or, | |
560 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 CG |
561 | { |
562 | int pin; | |
87783be4 | 563 | struct irq_pin_list *entry; |
047c8fdb | 564 | |
2977fb3f | 565 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
87783be4 CG |
566 | unsigned int reg; |
567 | pin = entry->pin; | |
568 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
569 | reg &= mask_and; | |
570 | reg |= mask_or; | |
571 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
572 | if (final) | |
573 | final(entry); | |
574 | } | |
575 | } | |
047c8fdb | 576 | |
3145e941 | 577 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 578 | { |
3145e941 | 579 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 580 | } |
047c8fdb | 581 | |
7f3e632f | 582 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 583 | { |
87783be4 CG |
584 | /* |
585 | * Synchronize the IO-APIC and the CPU by doing | |
586 | * a dummy read from the IO-APIC | |
587 | */ | |
588 | struct io_apic __iomem *io_apic; | |
589 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 590 | readl(&io_apic->data); |
1da177e4 LT |
591 | } |
592 | ||
3145e941 | 593 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 594 | { |
3145e941 | 595 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 | 596 | } |
1da177e4 | 597 | |
3145e941 | 598 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 599 | { |
3145e941 | 600 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
601 | IO_APIC_REDIR_MASKED, NULL); |
602 | } | |
1da177e4 | 603 | |
3145e941 | 604 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 605 | { |
3145e941 | 606 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
607 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
608 | } | |
047c8fdb | 609 | |
3145e941 | 610 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 611 | { |
3145e941 | 612 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
613 | unsigned long flags; |
614 | ||
3145e941 YL |
615 | BUG_ON(!cfg); |
616 | ||
1da177e4 | 617 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 618 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
619 | spin_unlock_irqrestore(&ioapic_lock, flags); |
620 | } | |
621 | ||
3145e941 | 622 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 623 | { |
3145e941 | 624 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
625 | unsigned long flags; |
626 | ||
627 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 628 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
629 | spin_unlock_irqrestore(&ioapic_lock, flags); |
630 | } | |
631 | ||
3145e941 YL |
632 | static void mask_IO_APIC_irq(unsigned int irq) |
633 | { | |
634 | struct irq_desc *desc = irq_to_desc(irq); | |
635 | ||
636 | mask_IO_APIC_irq_desc(desc); | |
637 | } | |
638 | static void unmask_IO_APIC_irq(unsigned int irq) | |
639 | { | |
640 | struct irq_desc *desc = irq_to_desc(irq); | |
641 | ||
642 | unmask_IO_APIC_irq_desc(desc); | |
643 | } | |
644 | ||
1da177e4 LT |
645 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
646 | { | |
647 | struct IO_APIC_route_entry entry; | |
36062448 | 648 | |
1da177e4 | 649 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 650 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
651 | if (entry.delivery_mode == dest_SMI) |
652 | return; | |
1da177e4 LT |
653 | /* |
654 | * Disable it in the IO-APIC irq-routing table: | |
655 | */ | |
f9dadfa7 | 656 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
657 | } |
658 | ||
54168ed7 | 659 | static void clear_IO_APIC (void) |
1da177e4 LT |
660 | { |
661 | int apic, pin; | |
662 | ||
663 | for (apic = 0; apic < nr_ioapics; apic++) | |
664 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
665 | clear_IO_APIC_pin(apic, pin); | |
666 | } | |
667 | ||
54168ed7 | 668 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
669 | /* |
670 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
671 | * specific CPU-side IRQs. | |
672 | */ | |
673 | ||
674 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
675 | static int pirq_entries[MAX_PIRQS] = { |
676 | [0 ... MAX_PIRQS - 1] = -1 | |
677 | }; | |
1da177e4 | 678 | |
1da177e4 LT |
679 | static int __init ioapic_pirq_setup(char *str) |
680 | { | |
681 | int i, max; | |
682 | int ints[MAX_PIRQS+1]; | |
683 | ||
684 | get_options(str, ARRAY_SIZE(ints), ints); | |
685 | ||
1da177e4 LT |
686 | apic_printk(APIC_VERBOSE, KERN_INFO |
687 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
688 | max = MAX_PIRQS; | |
689 | if (ints[0] < MAX_PIRQS) | |
690 | max = ints[0]; | |
691 | ||
692 | for (i = 0; i < max; i++) { | |
693 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
694 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
695 | /* | |
696 | * PIRQs are mapped upside down, usually. | |
697 | */ | |
698 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
699 | } | |
700 | return 1; | |
701 | } | |
702 | ||
703 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
704 | #endif /* CONFIG_X86_32 */ |
705 | ||
b24696bc FY |
706 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
707 | { | |
708 | int apic; | |
709 | struct IO_APIC_route_entry **ioapic_entries; | |
710 | ||
711 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
712 | GFP_ATOMIC); | |
713 | if (!ioapic_entries) | |
714 | return 0; | |
715 | ||
716 | for (apic = 0; apic < nr_ioapics; apic++) { | |
717 | ioapic_entries[apic] = | |
718 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
719 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
720 | if (!ioapic_entries[apic]) | |
721 | goto nomem; | |
722 | } | |
723 | ||
724 | return ioapic_entries; | |
725 | ||
726 | nomem: | |
727 | while (--apic >= 0) | |
728 | kfree(ioapic_entries[apic]); | |
729 | kfree(ioapic_entries); | |
730 | ||
731 | return 0; | |
732 | } | |
54168ed7 IM |
733 | |
734 | /* | |
05c3dc2c | 735 | * Saves all the IO-APIC RTE's |
54168ed7 | 736 | */ |
b24696bc | 737 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 738 | { |
54168ed7 IM |
739 | int apic, pin; |
740 | ||
b24696bc FY |
741 | if (!ioapic_entries) |
742 | return -ENOMEM; | |
54168ed7 IM |
743 | |
744 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
745 | if (!ioapic_entries[apic]) |
746 | return -ENOMEM; | |
54168ed7 | 747 | |
05c3dc2c | 748 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 749 | ioapic_entries[apic][pin] = |
54168ed7 | 750 | ioapic_read_entry(apic, pin); |
b24696bc | 751 | } |
5ffa4eb2 | 752 | |
54168ed7 IM |
753 | return 0; |
754 | } | |
755 | ||
b24696bc FY |
756 | /* |
757 | * Mask all IO APIC entries. | |
758 | */ | |
759 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
760 | { |
761 | int apic, pin; | |
762 | ||
b24696bc FY |
763 | if (!ioapic_entries) |
764 | return; | |
765 | ||
05c3dc2c | 766 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 767 | if (!ioapic_entries[apic]) |
05c3dc2c | 768 | break; |
b24696bc | 769 | |
05c3dc2c SS |
770 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
771 | struct IO_APIC_route_entry entry; | |
772 | ||
b24696bc | 773 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
774 | if (!entry.mask) { |
775 | entry.mask = 1; | |
776 | ioapic_write_entry(apic, pin, entry); | |
777 | } | |
778 | } | |
779 | } | |
780 | } | |
781 | ||
b24696bc FY |
782 | /* |
783 | * Restore IO APIC entries which was saved in ioapic_entries. | |
784 | */ | |
785 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
786 | { |
787 | int apic, pin; | |
788 | ||
b24696bc FY |
789 | if (!ioapic_entries) |
790 | return -ENOMEM; | |
791 | ||
5ffa4eb2 | 792 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
793 | if (!ioapic_entries[apic]) |
794 | return -ENOMEM; | |
795 | ||
54168ed7 IM |
796 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
797 | ioapic_write_entry(apic, pin, | |
b24696bc | 798 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 799 | } |
b24696bc | 800 | return 0; |
54168ed7 IM |
801 | } |
802 | ||
b24696bc FY |
803 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
804 | { | |
805 | int apic; | |
806 | ||
807 | for (apic = 0; apic < nr_ioapics; apic++) | |
808 | kfree(ioapic_entries[apic]); | |
809 | ||
810 | kfree(ioapic_entries); | |
54168ed7 | 811 | } |
1da177e4 LT |
812 | |
813 | /* | |
814 | * Find the IRQ entry number of a certain pin. | |
815 | */ | |
816 | static int find_irq_entry(int apic, int pin, int type) | |
817 | { | |
818 | int i; | |
819 | ||
820 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
821 | if (mp_irqs[i].irqtype == type && |
822 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
823 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
824 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
825 | return i; |
826 | ||
827 | return -1; | |
828 | } | |
829 | ||
830 | /* | |
831 | * Find the pin to which IRQ[irq] (ISA) is connected | |
832 | */ | |
fcfd636a | 833 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
834 | { |
835 | int i; | |
836 | ||
837 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 838 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 839 | |
d27e2b8e | 840 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
841 | (mp_irqs[i].irqtype == type) && |
842 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 843 | |
c2c21745 | 844 | return mp_irqs[i].dstirq; |
1da177e4 LT |
845 | } |
846 | return -1; | |
847 | } | |
848 | ||
fcfd636a EB |
849 | static int __init find_isa_irq_apic(int irq, int type) |
850 | { | |
851 | int i; | |
852 | ||
853 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 854 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 855 | |
73b2961b | 856 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
857 | (mp_irqs[i].irqtype == type) && |
858 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
859 | break; |
860 | } | |
861 | if (i < mp_irq_entries) { | |
862 | int apic; | |
54168ed7 | 863 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 864 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
865 | return apic; |
866 | } | |
867 | } | |
868 | ||
869 | return -1; | |
870 | } | |
871 | ||
c0a282c2 | 872 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
873 | /* |
874 | * EISA Edge/Level control register, ELCR | |
875 | */ | |
876 | static int EISA_ELCR(unsigned int irq) | |
877 | { | |
bc07844a | 878 | if (irq < nr_legacy_irqs) { |
1da177e4 LT |
879 | unsigned int port = 0x4d0 + (irq >> 3); |
880 | return (inb(port) >> (irq & 7)) & 1; | |
881 | } | |
882 | apic_printk(APIC_VERBOSE, KERN_INFO | |
883 | "Broken MPtable reports ISA irq %d\n", irq); | |
884 | return 0; | |
885 | } | |
54168ed7 | 886 | |
c0a282c2 | 887 | #endif |
1da177e4 | 888 | |
6728801d AS |
889 | /* ISA interrupts are always polarity zero edge triggered, |
890 | * when listed as conforming in the MP table. */ | |
891 | ||
892 | #define default_ISA_trigger(idx) (0) | |
893 | #define default_ISA_polarity(idx) (0) | |
894 | ||
1da177e4 LT |
895 | /* EISA interrupts are always polarity zero and can be edge or level |
896 | * trigger depending on the ELCR value. If an interrupt is listed as | |
897 | * EISA conforming in the MP table, that means its trigger type must | |
898 | * be read in from the ELCR */ | |
899 | ||
c2c21745 | 900 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 901 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
902 | |
903 | /* PCI interrupts are always polarity one level triggered, | |
904 | * when listed as conforming in the MP table. */ | |
905 | ||
906 | #define default_PCI_trigger(idx) (1) | |
907 | #define default_PCI_polarity(idx) (1) | |
908 | ||
909 | /* MCA interrupts are always polarity zero level triggered, | |
910 | * when listed as conforming in the MP table. */ | |
911 | ||
912 | #define default_MCA_trigger(idx) (1) | |
6728801d | 913 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 914 | |
61fd47e0 | 915 | static int MPBIOS_polarity(int idx) |
1da177e4 | 916 | { |
c2c21745 | 917 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
918 | int polarity; |
919 | ||
920 | /* | |
921 | * Determine IRQ line polarity (high active or low active): | |
922 | */ | |
c2c21745 | 923 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 924 | { |
54168ed7 IM |
925 | case 0: /* conforms, ie. bus-type dependent polarity */ |
926 | if (test_bit(bus, mp_bus_not_pci)) | |
927 | polarity = default_ISA_polarity(idx); | |
928 | else | |
929 | polarity = default_PCI_polarity(idx); | |
930 | break; | |
931 | case 1: /* high active */ | |
932 | { | |
933 | polarity = 0; | |
934 | break; | |
935 | } | |
936 | case 2: /* reserved */ | |
937 | { | |
938 | printk(KERN_WARNING "broken BIOS!!\n"); | |
939 | polarity = 1; | |
940 | break; | |
941 | } | |
942 | case 3: /* low active */ | |
943 | { | |
944 | polarity = 1; | |
945 | break; | |
946 | } | |
947 | default: /* invalid */ | |
948 | { | |
949 | printk(KERN_WARNING "broken BIOS!!\n"); | |
950 | polarity = 1; | |
951 | break; | |
952 | } | |
1da177e4 LT |
953 | } |
954 | return polarity; | |
955 | } | |
956 | ||
957 | static int MPBIOS_trigger(int idx) | |
958 | { | |
c2c21745 | 959 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
960 | int trigger; |
961 | ||
962 | /* | |
963 | * Determine IRQ trigger mode (edge or level sensitive): | |
964 | */ | |
c2c21745 | 965 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 966 | { |
54168ed7 IM |
967 | case 0: /* conforms, ie. bus-type dependent */ |
968 | if (test_bit(bus, mp_bus_not_pci)) | |
969 | trigger = default_ISA_trigger(idx); | |
970 | else | |
971 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 972 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
973 | switch (mp_bus_id_to_type[bus]) { |
974 | case MP_BUS_ISA: /* ISA pin */ | |
975 | { | |
976 | /* set before the switch */ | |
977 | break; | |
978 | } | |
979 | case MP_BUS_EISA: /* EISA pin */ | |
980 | { | |
981 | trigger = default_EISA_trigger(idx); | |
982 | break; | |
983 | } | |
984 | case MP_BUS_PCI: /* PCI pin */ | |
985 | { | |
986 | /* set before the switch */ | |
987 | break; | |
988 | } | |
989 | case MP_BUS_MCA: /* MCA pin */ | |
990 | { | |
991 | trigger = default_MCA_trigger(idx); | |
992 | break; | |
993 | } | |
994 | default: | |
995 | { | |
996 | printk(KERN_WARNING "broken BIOS!!\n"); | |
997 | trigger = 1; | |
998 | break; | |
999 | } | |
1000 | } | |
1001 | #endif | |
1da177e4 | 1002 | break; |
54168ed7 | 1003 | case 1: /* edge */ |
1da177e4 | 1004 | { |
54168ed7 | 1005 | trigger = 0; |
1da177e4 LT |
1006 | break; |
1007 | } | |
54168ed7 | 1008 | case 2: /* reserved */ |
1da177e4 | 1009 | { |
54168ed7 IM |
1010 | printk(KERN_WARNING "broken BIOS!!\n"); |
1011 | trigger = 1; | |
1da177e4 LT |
1012 | break; |
1013 | } | |
54168ed7 | 1014 | case 3: /* level */ |
1da177e4 | 1015 | { |
54168ed7 | 1016 | trigger = 1; |
1da177e4 LT |
1017 | break; |
1018 | } | |
54168ed7 | 1019 | default: /* invalid */ |
1da177e4 LT |
1020 | { |
1021 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1022 | trigger = 0; |
1da177e4 LT |
1023 | break; |
1024 | } | |
1025 | } | |
1026 | return trigger; | |
1027 | } | |
1028 | ||
1029 | static inline int irq_polarity(int idx) | |
1030 | { | |
1031 | return MPBIOS_polarity(idx); | |
1032 | } | |
1033 | ||
1034 | static inline int irq_trigger(int idx) | |
1035 | { | |
1036 | return MPBIOS_trigger(idx); | |
1037 | } | |
1038 | ||
efa2559f | 1039 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1040 | static int pin_2_irq(int idx, int apic, int pin) |
1041 | { | |
1042 | int irq, i; | |
c2c21745 | 1043 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1044 | |
1045 | /* | |
1046 | * Debugging check, we are in big trouble if this message pops up! | |
1047 | */ | |
c2c21745 | 1048 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1049 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1050 | ||
54168ed7 | 1051 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1052 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1053 | } else { |
643befed AS |
1054 | /* |
1055 | * PCI IRQs are mapped in order | |
1056 | */ | |
1057 | i = irq = 0; | |
1058 | while (i < apic) | |
1059 | irq += nr_ioapic_registers[i++]; | |
1060 | irq += pin; | |
d6c88a50 | 1061 | /* |
54168ed7 IM |
1062 | * For MPS mode, so far only needed by ES7000 platform |
1063 | */ | |
d6c88a50 TG |
1064 | if (ioapic_renumber_irq) |
1065 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1066 | } |
1067 | ||
54168ed7 | 1068 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1069 | /* |
1070 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1071 | */ | |
1072 | if ((pin >= 16) && (pin <= 23)) { | |
1073 | if (pirq_entries[pin-16] != -1) { | |
1074 | if (!pirq_entries[pin-16]) { | |
1075 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1076 | "disabling PIRQ%d\n", pin-16); | |
1077 | } else { | |
1078 | irq = pirq_entries[pin-16]; | |
1079 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1080 | "using PIRQ%d -> IRQ %d\n", | |
1081 | pin-16, irq); | |
1082 | } | |
1083 | } | |
1084 | } | |
54168ed7 IM |
1085 | #endif |
1086 | ||
1da177e4 LT |
1087 | return irq; |
1088 | } | |
1089 | ||
e20c06fd YL |
1090 | /* |
1091 | * Find a specific PCI IRQ entry. | |
1092 | * Not an __init, possibly needed by modules | |
1093 | */ | |
1094 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1095 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1096 | { |
1097 | int apic, i, best_guess = -1; | |
1098 | ||
1099 | apic_printk(APIC_DEBUG, | |
1100 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1101 | bus, slot, pin); | |
1102 | if (test_bit(bus, mp_bus_not_pci)) { | |
1103 | apic_printk(APIC_VERBOSE, | |
1104 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1105 | return -1; | |
1106 | } | |
1107 | for (i = 0; i < mp_irq_entries; i++) { | |
1108 | int lbus = mp_irqs[i].srcbus; | |
1109 | ||
1110 | for (apic = 0; apic < nr_ioapics; apic++) | |
1111 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1112 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1113 | break; | |
1114 | ||
1115 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1116 | !mp_irqs[i].irqtype && | |
1117 | (bus == lbus) && | |
1118 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1119 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1120 | ||
1121 | if (!(apic || IO_APIC_IRQ(irq))) | |
1122 | continue; | |
1123 | ||
1124 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1125 | set_io_apic_irq_attr(irq_attr, apic, |
1126 | mp_irqs[i].dstirq, | |
1127 | irq_trigger(i), | |
1128 | irq_polarity(i)); | |
e20c06fd YL |
1129 | return irq; |
1130 | } | |
1131 | /* | |
1132 | * Use the first all-but-pin matching entry as a | |
1133 | * best-guess fuzzy result for broken mptables. | |
1134 | */ | |
1135 | if (best_guess < 0) { | |
e5198075 YL |
1136 | set_io_apic_irq_attr(irq_attr, apic, |
1137 | mp_irqs[i].dstirq, | |
1138 | irq_trigger(i), | |
1139 | irq_polarity(i)); | |
e20c06fd YL |
1140 | best_guess = irq; |
1141 | } | |
1142 | } | |
1143 | } | |
1144 | return best_guess; | |
1145 | } | |
1146 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1147 | ||
497c9a19 YL |
1148 | void lock_vector_lock(void) |
1149 | { | |
1150 | /* Used to the online set of cpus does not change | |
1151 | * during assign_irq_vector. | |
1152 | */ | |
1153 | spin_lock(&vector_lock); | |
1154 | } | |
1da177e4 | 1155 | |
497c9a19 | 1156 | void unlock_vector_lock(void) |
1da177e4 | 1157 | { |
497c9a19 YL |
1158 | spin_unlock(&vector_lock); |
1159 | } | |
1da177e4 | 1160 | |
e7986739 MT |
1161 | static int |
1162 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1163 | { |
047c8fdb YL |
1164 | /* |
1165 | * NOTE! The local APIC isn't very good at handling | |
1166 | * multiple interrupts at the same interrupt level. | |
1167 | * As the interrupt level is determined by taking the | |
1168 | * vector number and shifting that right by 4, we | |
1169 | * want to spread these out a bit so that they don't | |
1170 | * all fall in the same interrupt level. | |
1171 | * | |
1172 | * Also, we've got to be careful not to trash gate | |
1173 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1174 | */ | |
54168ed7 IM |
1175 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1176 | unsigned int old_vector; | |
22f65d31 MT |
1177 | int cpu, err; |
1178 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1179 | |
54168ed7 IM |
1180 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1181 | return -EBUSY; | |
0a1ad60d | 1182 | |
22f65d31 MT |
1183 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1184 | return -ENOMEM; | |
ace80ab7 | 1185 | |
54168ed7 IM |
1186 | old_vector = cfg->vector; |
1187 | if (old_vector) { | |
22f65d31 MT |
1188 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1189 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1190 | if (!cpumask_empty(tmp_mask)) { | |
1191 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1192 | return 0; |
22f65d31 | 1193 | } |
54168ed7 | 1194 | } |
497c9a19 | 1195 | |
e7986739 | 1196 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1197 | err = -ENOSPC; |
1198 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1199 | int new_cpu; |
1200 | int vector, offset; | |
497c9a19 | 1201 | |
e2d40b18 | 1202 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1203 | |
54168ed7 IM |
1204 | vector = current_vector; |
1205 | offset = current_offset; | |
497c9a19 | 1206 | next: |
54168ed7 IM |
1207 | vector += 8; |
1208 | if (vector >= first_system_vector) { | |
e7986739 | 1209 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1210 | offset = (offset + 1) % 8; |
1211 | vector = FIRST_DEVICE_VECTOR + offset; | |
1212 | } | |
1213 | if (unlikely(current_vector == vector)) | |
1214 | continue; | |
b77b881f YL |
1215 | |
1216 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1217 | goto next; |
b77b881f | 1218 | |
22f65d31 | 1219 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1220 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1221 | goto next; | |
1222 | /* Found one! */ | |
1223 | current_vector = vector; | |
1224 | current_offset = offset; | |
1225 | if (old_vector) { | |
1226 | cfg->move_in_progress = 1; | |
22f65d31 | 1227 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1228 | } |
22f65d31 | 1229 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1230 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1231 | cfg->vector = vector; | |
22f65d31 MT |
1232 | cpumask_copy(cfg->domain, tmp_mask); |
1233 | err = 0; | |
1234 | break; | |
54168ed7 | 1235 | } |
22f65d31 MT |
1236 | free_cpumask_var(tmp_mask); |
1237 | return err; | |
497c9a19 YL |
1238 | } |
1239 | ||
e7986739 MT |
1240 | static int |
1241 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1242 | { |
1243 | int err; | |
ace80ab7 | 1244 | unsigned long flags; |
ace80ab7 EB |
1245 | |
1246 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1247 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1248 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1249 | return err; |
1250 | } | |
1251 | ||
3145e941 | 1252 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1253 | { |
497c9a19 YL |
1254 | int cpu, vector; |
1255 | ||
497c9a19 YL |
1256 | BUG_ON(!cfg->vector); |
1257 | ||
1258 | vector = cfg->vector; | |
22f65d31 | 1259 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1260 | per_cpu(vector_irq, cpu)[vector] = -1; |
1261 | ||
1262 | cfg->vector = 0; | |
22f65d31 | 1263 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1264 | |
1265 | if (likely(!cfg->move_in_progress)) | |
1266 | return; | |
22f65d31 | 1267 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1268 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1269 | vector++) { | |
1270 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1271 | continue; | |
1272 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1273 | break; | |
1274 | } | |
1275 | } | |
1276 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1277 | } |
1278 | ||
1279 | void __setup_vector_irq(int cpu) | |
1280 | { | |
1281 | /* Initialize vector_irq on a new cpu */ | |
1282 | /* This function must be called with vector_lock held */ | |
1283 | int irq, vector; | |
1284 | struct irq_cfg *cfg; | |
0b8f1efa | 1285 | struct irq_desc *desc; |
497c9a19 YL |
1286 | |
1287 | /* Mark the inuse vectors */ | |
0b8f1efa | 1288 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1289 | cfg = desc->chip_data; |
22f65d31 | 1290 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1291 | continue; |
1292 | vector = cfg->vector; | |
497c9a19 YL |
1293 | per_cpu(vector_irq, cpu)[vector] = irq; |
1294 | } | |
1295 | /* Mark the free vectors */ | |
1296 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1297 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1298 | if (irq < 0) | |
1299 | continue; | |
1300 | ||
1301 | cfg = irq_cfg(irq); | |
22f65d31 | 1302 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1303 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1304 | } |
1da177e4 | 1305 | } |
3fde6900 | 1306 | |
f5b9ed7a | 1307 | static struct irq_chip ioapic_chip; |
54168ed7 | 1308 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1309 | |
54168ed7 IM |
1310 | #define IOAPIC_AUTO -1 |
1311 | #define IOAPIC_EDGE 0 | |
1312 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1313 | |
047c8fdb | 1314 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1315 | static inline int IO_APIC_irq_trigger(int irq) |
1316 | { | |
d6c88a50 | 1317 | int apic, idx, pin; |
1d025192 | 1318 | |
d6c88a50 TG |
1319 | for (apic = 0; apic < nr_ioapics; apic++) { |
1320 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1321 | idx = find_irq_entry(apic, pin, mp_INT); | |
1322 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1323 | return irq_trigger(idx); | |
1324 | } | |
1325 | } | |
1326 | /* | |
54168ed7 IM |
1327 | * nonexistent IRQs are edge default |
1328 | */ | |
d6c88a50 | 1329 | return 0; |
1d025192 | 1330 | } |
047c8fdb YL |
1331 | #else |
1332 | static inline int IO_APIC_irq_trigger(int irq) | |
1333 | { | |
54168ed7 | 1334 | return 1; |
047c8fdb YL |
1335 | } |
1336 | #endif | |
1d025192 | 1337 | |
3145e941 | 1338 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1339 | { |
199751d7 | 1340 | |
6ebcc00e | 1341 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1342 | trigger == IOAPIC_LEVEL) |
08678b08 | 1343 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1344 | else |
1345 | desc->status &= ~IRQ_LEVEL; | |
1346 | ||
54168ed7 IM |
1347 | if (irq_remapped(irq)) { |
1348 | desc->status |= IRQ_MOVE_PCNTXT; | |
1349 | if (trigger) | |
1350 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1351 | handle_fasteoi_irq, | |
1352 | "fasteoi"); | |
1353 | else | |
1354 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1355 | handle_edge_irq, "edge"); | |
1356 | return; | |
1357 | } | |
29b61be6 | 1358 | |
047c8fdb YL |
1359 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1360 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1361 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1362 | handle_fasteoi_irq, |
1363 | "fasteoi"); | |
047c8fdb | 1364 | else |
a460e745 | 1365 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1366 | handle_edge_irq, "edge"); |
1da177e4 LT |
1367 | } |
1368 | ||
ca97ab90 JF |
1369 | int setup_ioapic_entry(int apic_id, int irq, |
1370 | struct IO_APIC_route_entry *entry, | |
1371 | unsigned int destination, int trigger, | |
0280f7c4 | 1372 | int polarity, int vector, int pin) |
1da177e4 | 1373 | { |
497c9a19 YL |
1374 | /* |
1375 | * add it to the IO-APIC irq-routing table: | |
1376 | */ | |
1377 | memset(entry,0,sizeof(*entry)); | |
1378 | ||
54168ed7 | 1379 | if (intr_remapping_enabled) { |
c8d46cf0 | 1380 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1381 | struct irte irte; |
1382 | struct IR_IO_APIC_route_entry *ir_entry = | |
1383 | (struct IR_IO_APIC_route_entry *) entry; | |
1384 | int index; | |
1385 | ||
1386 | if (!iommu) | |
c8d46cf0 | 1387 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1388 | |
1389 | index = alloc_irte(iommu, irq, 1); | |
1390 | if (index < 0) | |
c8d46cf0 | 1391 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1392 | |
1393 | memset(&irte, 0, sizeof(irte)); | |
1394 | ||
1395 | irte.present = 1; | |
9b5bc8dc | 1396 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1397 | /* |
1398 | * Trigger mode in the IRTE will always be edge, and the | |
1399 | * actual level or edge trigger will be setup in the IO-APIC | |
1400 | * RTE. This will help simplify level triggered irq migration. | |
1401 | * For more details, see the comments above explainig IO-APIC | |
1402 | * irq migration in the presence of interrupt-remapping. | |
1403 | */ | |
1404 | irte.trigger_mode = 0; | |
9b5bc8dc | 1405 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1406 | irte.vector = vector; |
1407 | irte.dest_id = IRTE_DEST(destination); | |
1408 | ||
f007e99c WH |
1409 | /* Set source-id of interrupt request */ |
1410 | set_ioapic_sid(&irte, apic_id); | |
1411 | ||
54168ed7 IM |
1412 | modify_irte(irq, &irte); |
1413 | ||
1414 | ir_entry->index2 = (index >> 15) & 0x1; | |
1415 | ir_entry->zero = 0; | |
1416 | ir_entry->format = 1; | |
1417 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1418 | /* |
1419 | * IO-APIC RTE will be configured with virtual vector. | |
1420 | * irq handler will do the explicit EOI to the io-apic. | |
1421 | */ | |
1422 | ir_entry->vector = pin; | |
29b61be6 | 1423 | } else { |
9b5bc8dc IM |
1424 | entry->delivery_mode = apic->irq_delivery_mode; |
1425 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1426 | entry->dest = destination; |
0280f7c4 | 1427 | entry->vector = vector; |
54168ed7 | 1428 | } |
497c9a19 | 1429 | |
54168ed7 | 1430 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1431 | entry->trigger = trigger; |
1432 | entry->polarity = polarity; | |
497c9a19 YL |
1433 | |
1434 | /* Mask level triggered irqs. | |
1435 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1436 | */ | |
1437 | if (trigger) | |
1438 | entry->mask = 1; | |
497c9a19 YL |
1439 | return 0; |
1440 | } | |
1441 | ||
c8d46cf0 | 1442 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1443 | int trigger, int polarity) |
497c9a19 YL |
1444 | { |
1445 | struct irq_cfg *cfg; | |
1da177e4 | 1446 | struct IO_APIC_route_entry entry; |
22f65d31 | 1447 | unsigned int dest; |
497c9a19 YL |
1448 | |
1449 | if (!IO_APIC_IRQ(irq)) | |
1450 | return; | |
1451 | ||
3145e941 | 1452 | cfg = desc->chip_data; |
497c9a19 | 1453 | |
fe402e1f | 1454 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1455 | return; |
1456 | ||
debccb3e | 1457 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1458 | |
1459 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1460 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1461 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1462 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1463 | irq, trigger, polarity); |
1464 | ||
1465 | ||
c8d46cf0 | 1466 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1467 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1468 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1469 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1470 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1471 | return; |
1472 | } | |
1473 | ||
3145e941 | 1474 | ioapic_register_intr(irq, desc, trigger); |
bc07844a | 1475 | if (irq < nr_legacy_irqs) |
497c9a19 YL |
1476 | disable_8259A_irq(irq); |
1477 | ||
c8d46cf0 | 1478 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1479 | } |
1480 | ||
b9c61b70 YL |
1481 | static struct { |
1482 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1483 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1484 | ||
497c9a19 YL |
1485 | static void __init setup_IO_APIC_irqs(void) |
1486 | { | |
b9c61b70 | 1487 | int apic_id = 0, pin, idx, irq; |
3c2cbd24 | 1488 | int notcon = 0; |
0b8f1efa | 1489 | struct irq_desc *desc; |
3145e941 | 1490 | struct irq_cfg *cfg; |
85ac16d0 | 1491 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1492 | |
1493 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1494 | ||
b9c61b70 YL |
1495 | #ifdef CONFIG_ACPI |
1496 | if (!acpi_disabled && acpi_ioapic) { | |
1497 | apic_id = mp_find_ioapic(0); | |
1498 | if (apic_id < 0) | |
1499 | apic_id = 0; | |
1500 | } | |
1501 | #endif | |
3c2cbd24 | 1502 | |
b9c61b70 YL |
1503 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1504 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1505 | if (idx == -1) { | |
1506 | if (!notcon) { | |
1507 | notcon = 1; | |
1508 | apic_printk(APIC_VERBOSE, | |
1509 | KERN_DEBUG " %d-%d", | |
1510 | mp_ioapics[apic_id].apicid, pin); | |
1511 | } else | |
1512 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1513 | mp_ioapics[apic_id].apicid, pin); | |
1514 | continue; | |
1515 | } | |
1516 | if (notcon) { | |
1517 | apic_printk(APIC_VERBOSE, | |
1518 | " (apicid-pin) not connected\n"); | |
1519 | notcon = 0; | |
1520 | } | |
33a201fa | 1521 | |
b9c61b70 | 1522 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1523 | |
b9c61b70 YL |
1524 | /* |
1525 | * Skip the timer IRQ if there's a quirk handler | |
1526 | * installed and if it returns 1: | |
1527 | */ | |
1528 | if (apic->multi_timer_check && | |
1529 | apic->multi_timer_check(apic_id, irq)) | |
1530 | continue; | |
36062448 | 1531 | |
b9c61b70 YL |
1532 | desc = irq_to_desc_alloc_node(irq, node); |
1533 | if (!desc) { | |
1534 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1535 | continue; | |
3c2cbd24 | 1536 | } |
b9c61b70 YL |
1537 | cfg = desc->chip_data; |
1538 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
4c6f18fc YL |
1539 | /* |
1540 | * don't mark it in pin_programmed, so later acpi could | |
1541 | * set it correctly when irq < 16 | |
1542 | */ | |
b9c61b70 YL |
1543 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1544 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1545 | } |
1546 | ||
3c2cbd24 CG |
1547 | if (notcon) |
1548 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1549 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1550 | } |
1551 | ||
1552 | /* | |
f7633ce5 | 1553 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1554 | */ |
c8d46cf0 | 1555 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1556 | int vector) |
1da177e4 LT |
1557 | { |
1558 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1559 | |
54168ed7 IM |
1560 | if (intr_remapping_enabled) |
1561 | return; | |
54168ed7 | 1562 | |
36062448 | 1563 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1564 | |
1565 | /* | |
1566 | * We use logical delivery to get the timer IRQ | |
1567 | * to the first CPU. | |
1568 | */ | |
9b5bc8dc | 1569 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1570 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1571 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1572 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1573 | entry.polarity = 0; |
1574 | entry.trigger = 0; | |
1575 | entry.vector = vector; | |
1576 | ||
1577 | /* | |
1578 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1579 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1580 | */ |
54168ed7 | 1581 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1582 | |
1583 | /* | |
1584 | * Add it to the IO-APIC irq-routing table: | |
1585 | */ | |
c8d46cf0 | 1586 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1587 | } |
1588 | ||
32f71aff MR |
1589 | |
1590 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1591 | { |
1592 | int apic, i; | |
1593 | union IO_APIC_reg_00 reg_00; | |
1594 | union IO_APIC_reg_01 reg_01; | |
1595 | union IO_APIC_reg_02 reg_02; | |
1596 | union IO_APIC_reg_03 reg_03; | |
1597 | unsigned long flags; | |
0f978f45 | 1598 | struct irq_cfg *cfg; |
0b8f1efa | 1599 | struct irq_desc *desc; |
8f09cd20 | 1600 | unsigned int irq; |
1da177e4 LT |
1601 | |
1602 | if (apic_verbosity == APIC_QUIET) | |
1603 | return; | |
1604 | ||
36062448 | 1605 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1606 | for (i = 0; i < nr_ioapics; i++) |
1607 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1608 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1609 | |
1610 | /* | |
1611 | * We are a bit conservative about what we expect. We have to | |
1612 | * know about every hardware change ASAP. | |
1613 | */ | |
1614 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1615 | ||
1616 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1617 | ||
1618 | spin_lock_irqsave(&ioapic_lock, flags); | |
1619 | reg_00.raw = io_apic_read(apic, 0); | |
1620 | reg_01.raw = io_apic_read(apic, 1); | |
1621 | if (reg_01.bits.version >= 0x10) | |
1622 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1623 | if (reg_01.bits.version >= 0x20) |
1624 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1625 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1626 | ||
54168ed7 | 1627 | printk("\n"); |
b5ba7e6d | 1628 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1629 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1630 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1631 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1632 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1633 | |
54168ed7 | 1634 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1635 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1636 | |
1637 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1638 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1639 | |
1640 | /* | |
1641 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1642 | * but the value of reg_02 is read as the previous read register | |
1643 | * value, so ignore it if reg_02 == reg_01. | |
1644 | */ | |
1645 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1646 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1647 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1648 | } |
1649 | ||
1650 | /* | |
1651 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1652 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1653 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1654 | */ | |
1655 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1656 | reg_03.raw != reg_01.raw) { | |
1657 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1658 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1659 | } |
1660 | ||
1661 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1662 | ||
d83e94ac YL |
1663 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1664 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1665 | |
1666 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1667 | struct IO_APIC_route_entry entry; | |
1668 | ||
cf4c6a2f | 1669 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1670 | |
54168ed7 IM |
1671 | printk(KERN_DEBUG " %02x %03X ", |
1672 | i, | |
1673 | entry.dest | |
1674 | ); | |
1da177e4 LT |
1675 | |
1676 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1677 | entry.mask, | |
1678 | entry.trigger, | |
1679 | entry.irr, | |
1680 | entry.polarity, | |
1681 | entry.delivery_status, | |
1682 | entry.dest_mode, | |
1683 | entry.delivery_mode, | |
1684 | entry.vector | |
1685 | ); | |
1686 | } | |
1687 | } | |
1da177e4 | 1688 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1689 | for_each_irq_desc(irq, desc) { |
1690 | struct irq_pin_list *entry; | |
1691 | ||
0b8f1efa YL |
1692 | cfg = desc->chip_data; |
1693 | entry = cfg->irq_2_pin; | |
0f978f45 | 1694 | if (!entry) |
1da177e4 | 1695 | continue; |
8f09cd20 | 1696 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1697 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1698 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1699 | printk("\n"); |
1700 | } | |
1701 | ||
1702 | printk(KERN_INFO ".................................... done.\n"); | |
1703 | ||
1704 | return; | |
1705 | } | |
1706 | ||
251e1e44 | 1707 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1708 | { |
251e1e44 | 1709 | int i; |
1da177e4 LT |
1710 | |
1711 | if (apic_verbosity == APIC_QUIET) | |
1712 | return; | |
1713 | ||
251e1e44 IM |
1714 | printk(KERN_DEBUG); |
1715 | ||
1716 | for (i = 0; i < 8; i++) | |
1717 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1718 | ||
1719 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1720 | } |
1721 | ||
32f71aff | 1722 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1723 | { |
97a52714 | 1724 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1725 | u64 icr; |
1da177e4 LT |
1726 | |
1727 | if (apic_verbosity == APIC_QUIET) | |
1728 | return; | |
1729 | ||
251e1e44 | 1730 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1731 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1732 | v = apic_read(APIC_ID); |
54168ed7 | 1733 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1734 | v = apic_read(APIC_LVR); |
1735 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1736 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1737 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1738 | |
1739 | v = apic_read(APIC_TASKPRI); | |
1740 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1741 | ||
54168ed7 | 1742 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1743 | if (!APIC_XAPIC(ver)) { |
1744 | v = apic_read(APIC_ARBPRI); | |
1745 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1746 | v & APIC_ARBPRI_MASK); | |
1747 | } | |
1da177e4 LT |
1748 | v = apic_read(APIC_PROCPRI); |
1749 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1750 | } | |
1751 | ||
a11b5abe YL |
1752 | /* |
1753 | * Remote read supported only in the 82489DX and local APIC for | |
1754 | * Pentium processors. | |
1755 | */ | |
1756 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1757 | v = apic_read(APIC_RRR); | |
1758 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1759 | } | |
1760 | ||
1da177e4 LT |
1761 | v = apic_read(APIC_LDR); |
1762 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1763 | if (!x2apic_enabled()) { |
1764 | v = apic_read(APIC_DFR); | |
1765 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1766 | } | |
1da177e4 LT |
1767 | v = apic_read(APIC_SPIV); |
1768 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1769 | ||
1770 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1771 | print_APIC_field(APIC_ISR); |
1da177e4 | 1772 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1773 | print_APIC_field(APIC_TMR); |
1da177e4 | 1774 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1775 | print_APIC_field(APIC_IRR); |
1da177e4 | 1776 | |
54168ed7 IM |
1777 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1778 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1779 | apic_write(APIC_ESR, 0); |
54168ed7 | 1780 | |
1da177e4 LT |
1781 | v = apic_read(APIC_ESR); |
1782 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1783 | } | |
1784 | ||
7ab6af7a | 1785 | icr = apic_icr_read(); |
0c425cec IM |
1786 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1787 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1788 | |
1789 | v = apic_read(APIC_LVTT); | |
1790 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1791 | ||
1792 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1793 | v = apic_read(APIC_LVTPC); | |
1794 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1795 | } | |
1796 | v = apic_read(APIC_LVT0); | |
1797 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1798 | v = apic_read(APIC_LVT1); | |
1799 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1800 | ||
1801 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1802 | v = apic_read(APIC_LVTERR); | |
1803 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1804 | } | |
1805 | ||
1806 | v = apic_read(APIC_TMICT); | |
1807 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1808 | v = apic_read(APIC_TMCCT); | |
1809 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1810 | v = apic_read(APIC_TDCR); | |
1811 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1812 | |
1813 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1814 | v = apic_read(APIC_EFEAT); | |
1815 | maxlvt = (v >> 16) & 0xff; | |
1816 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1817 | v = apic_read(APIC_ECTRL); | |
1818 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1819 | for (i = 0; i < maxlvt; i++) { | |
1820 | v = apic_read(APIC_EILVTn(i)); | |
1821 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1822 | } | |
1823 | } | |
1da177e4 LT |
1824 | printk("\n"); |
1825 | } | |
1826 | ||
32f71aff | 1827 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1828 | { |
ffd5aae7 YL |
1829 | int cpu; |
1830 | ||
1831 | preempt_disable(); | |
1832 | for_each_online_cpu(cpu) | |
1833 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1834 | preempt_enable(); | |
1da177e4 LT |
1835 | } |
1836 | ||
32f71aff | 1837 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1838 | { |
1da177e4 LT |
1839 | unsigned int v; |
1840 | unsigned long flags; | |
1841 | ||
bc07844a | 1842 | if (apic_verbosity == APIC_QUIET || !nr_legacy_irqs) |
1da177e4 LT |
1843 | return; |
1844 | ||
1845 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1846 | ||
1847 | spin_lock_irqsave(&i8259A_lock, flags); | |
1848 | ||
1849 | v = inb(0xa1) << 8 | inb(0x21); | |
1850 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1851 | ||
1852 | v = inb(0xa0) << 8 | inb(0x20); | |
1853 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1854 | ||
54168ed7 IM |
1855 | outb(0x0b,0xa0); |
1856 | outb(0x0b,0x20); | |
1da177e4 | 1857 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1858 | outb(0x0a,0xa0); |
1859 | outb(0x0a,0x20); | |
1da177e4 LT |
1860 | |
1861 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1862 | ||
1863 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1864 | ||
1865 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1866 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1867 | } | |
1868 | ||
32f71aff MR |
1869 | __apicdebuginit(int) print_all_ICs(void) |
1870 | { | |
1871 | print_PIC(); | |
4797f6b0 YL |
1872 | |
1873 | /* don't print out if apic is not there */ | |
8312136f | 1874 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1875 | return 0; |
1876 | ||
32f71aff MR |
1877 | print_all_local_APICs(); |
1878 | print_IO_APIC(); | |
1879 | ||
1880 | return 0; | |
1881 | } | |
1882 | ||
1883 | fs_initcall(print_all_ICs); | |
1884 | ||
1da177e4 | 1885 | |
efa2559f YL |
1886 | /* Where if anywhere is the i8259 connect in external int mode */ |
1887 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1888 | ||
54168ed7 | 1889 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1890 | { |
1891 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1892 | int i8259_apic, i8259_pin; |
54168ed7 | 1893 | int apic; |
1da177e4 LT |
1894 | unsigned long flags; |
1895 | ||
1da177e4 LT |
1896 | /* |
1897 | * The number of IO-APIC IRQ registers (== #pins): | |
1898 | */ | |
fcfd636a | 1899 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1900 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1901 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1902 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1903 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1904 | } | |
bc07844a TG |
1905 | |
1906 | if (!nr_legacy_irqs) | |
1907 | return; | |
1908 | ||
54168ed7 | 1909 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1910 | int pin; |
1911 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1912 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1913 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1914 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1915 | |
fcfd636a EB |
1916 | /* If the interrupt line is enabled and in ExtInt mode |
1917 | * I have found the pin where the i8259 is connected. | |
1918 | */ | |
1919 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1920 | ioapic_i8259.apic = apic; | |
1921 | ioapic_i8259.pin = pin; | |
1922 | goto found_i8259; | |
1923 | } | |
1924 | } | |
1925 | } | |
1926 | found_i8259: | |
1927 | /* Look to see what if the MP table has reported the ExtINT */ | |
1928 | /* If we could not find the appropriate pin by looking at the ioapic | |
1929 | * the i8259 probably is not connected the ioapic but give the | |
1930 | * mptable a chance anyway. | |
1931 | */ | |
1932 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1933 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1934 | /* Trust the MP table if nothing is setup in the hardware */ | |
1935 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1936 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1937 | ioapic_i8259.pin = i8259_pin; | |
1938 | ioapic_i8259.apic = i8259_apic; | |
1939 | } | |
1940 | /* Complain if the MP table and the hardware disagree */ | |
1941 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1942 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1943 | { | |
1944 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1945 | } |
1946 | ||
1947 | /* | |
1948 | * Do not trust the IO-APIC being empty at bootup | |
1949 | */ | |
1950 | clear_IO_APIC(); | |
1951 | } | |
1952 | ||
1953 | /* | |
1954 | * Not an __init, needed by the reboot code | |
1955 | */ | |
1956 | void disable_IO_APIC(void) | |
1957 | { | |
1958 | /* | |
1959 | * Clear the IO-APIC before rebooting: | |
1960 | */ | |
1961 | clear_IO_APIC(); | |
1962 | ||
bc07844a TG |
1963 | if (!nr_legacy_irqs) |
1964 | return; | |
1965 | ||
650927ef | 1966 | /* |
0b968d23 | 1967 | * If the i8259 is routed through an IOAPIC |
650927ef | 1968 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1969 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1970 | * |
1971 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1972 | * as virtual wire B is little complex (need to configure both | |
1973 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
1974 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 1975 | */ |
7c6d9f97 | 1976 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1977 | struct IO_APIC_route_entry entry; |
650927ef EB |
1978 | |
1979 | memset(&entry, 0, sizeof(entry)); | |
1980 | entry.mask = 0; /* Enabled */ | |
1981 | entry.trigger = 0; /* Edge */ | |
1982 | entry.irr = 0; | |
1983 | entry.polarity = 0; /* High */ | |
1984 | entry.delivery_status = 0; | |
1985 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1986 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1987 | entry.vector = 0; |
54168ed7 | 1988 | entry.dest = read_apic_id(); |
650927ef EB |
1989 | |
1990 | /* | |
1991 | * Add it to the IO-APIC irq-routing table: | |
1992 | */ | |
cf4c6a2f | 1993 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1994 | } |
54168ed7 | 1995 | |
7c6d9f97 SS |
1996 | /* |
1997 | * Use virtual wire A mode when interrupt remapping is enabled. | |
1998 | */ | |
8312136f | 1999 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
2000 | disconnect_bsp_APIC(!intr_remapping_enabled && |
2001 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
2002 | } |
2003 | ||
54168ed7 | 2004 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2005 | /* |
2006 | * function to set the IO-APIC physical IDs based on the | |
2007 | * values stored in the MPC table. | |
2008 | * | |
2009 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2010 | */ | |
2011 | ||
de934103 | 2012 | void __init setup_ioapic_ids_from_mpc(void) |
1da177e4 LT |
2013 | { |
2014 | union IO_APIC_reg_00 reg_00; | |
2015 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2016 | int apic_id; |
1da177e4 LT |
2017 | int i; |
2018 | unsigned char old_id; | |
2019 | unsigned long flags; | |
2020 | ||
de934103 | 2021 | if (acpi_ioapic) |
d49c4288 | 2022 | return; |
ca05fea6 NP |
2023 | /* |
2024 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2025 | * no meaning without the serial APIC bus. | |
2026 | */ | |
7c5c1e42 SL |
2027 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2028 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2029 | return; |
1da177e4 LT |
2030 | /* |
2031 | * This is broken; anything with a real cpu count has to | |
2032 | * circumvent this idiocy regardless. | |
2033 | */ | |
d190cb87 | 2034 | phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
2035 | |
2036 | /* | |
2037 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2038 | */ | |
c8d46cf0 | 2039 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2040 | |
2041 | /* Read the register 0 value */ | |
2042 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2043 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2044 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2045 | |
c8d46cf0 | 2046 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2047 | |
c8d46cf0 | 2048 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2049 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2050 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2051 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2052 | reg_00.bits.ID); | |
c8d46cf0 | 2053 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2054 | } |
2055 | ||
1da177e4 LT |
2056 | /* |
2057 | * Sanity check, is the ID really free? Every APIC in a | |
2058 | * system must have a unique ID or we get lots of nice | |
2059 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2060 | */ | |
d1d7cae8 | 2061 | if (apic->check_apicid_used(phys_id_present_map, |
c8d46cf0 | 2062 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2063 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2064 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2065 | for (i = 0; i < get_physical_broadcast(); i++) |
2066 | if (!physid_isset(i, phys_id_present_map)) | |
2067 | break; | |
2068 | if (i >= get_physical_broadcast()) | |
2069 | panic("Max APIC ID exceeded!\n"); | |
2070 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2071 | i); | |
2072 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2073 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2074 | } else { |
2075 | physid_mask_t tmp; | |
8058714a | 2076 | tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2077 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2078 | "phys_id_present_map\n", | |
c8d46cf0 | 2079 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2080 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2081 | } | |
2082 | ||
2083 | ||
2084 | /* | |
2085 | * We need to adjust the IRQ routing table | |
2086 | * if the ID changed. | |
2087 | */ | |
c8d46cf0 | 2088 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2089 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2090 | if (mp_irqs[i].dstapic == old_id) |
2091 | mp_irqs[i].dstapic | |
c8d46cf0 | 2092 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2093 | |
2094 | /* | |
2095 | * Read the right value from the MPC table and | |
2096 | * write it into the ID register. | |
36062448 | 2097 | */ |
1da177e4 LT |
2098 | apic_printk(APIC_VERBOSE, KERN_INFO |
2099 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2100 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2101 | |
c8d46cf0 | 2102 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2103 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2104 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2105 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2106 | |
2107 | /* | |
2108 | * Sanity check | |
2109 | */ | |
2110 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2111 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2112 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2113 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2114 | printk("could not set ID!\n"); |
2115 | else | |
2116 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2117 | } | |
2118 | } | |
54168ed7 | 2119 | #endif |
1da177e4 | 2120 | |
7ce0bcfd | 2121 | int no_timer_check __initdata; |
8542b200 ZA |
2122 | |
2123 | static int __init notimercheck(char *s) | |
2124 | { | |
2125 | no_timer_check = 1; | |
2126 | return 1; | |
2127 | } | |
2128 | __setup("no_timer_check", notimercheck); | |
2129 | ||
1da177e4 LT |
2130 | /* |
2131 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2132 | * about the timer IRQ. We do the following to work around the situation: | |
2133 | * | |
2134 | * - timer IRQ defaults to IO-APIC IRQ | |
2135 | * - if this function detects that timer IRQs are defunct, then we fall | |
2136 | * back to ISA timer IRQs | |
2137 | */ | |
f0a7a5c9 | 2138 | static int __init timer_irq_works(void) |
1da177e4 LT |
2139 | { |
2140 | unsigned long t1 = jiffies; | |
4aae0702 | 2141 | unsigned long flags; |
1da177e4 | 2142 | |
8542b200 ZA |
2143 | if (no_timer_check) |
2144 | return 1; | |
2145 | ||
4aae0702 | 2146 | local_save_flags(flags); |
1da177e4 LT |
2147 | local_irq_enable(); |
2148 | /* Let ten ticks pass... */ | |
2149 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2150 | local_irq_restore(flags); |
1da177e4 LT |
2151 | |
2152 | /* | |
2153 | * Expect a few ticks at least, to be sure some possible | |
2154 | * glue logic does not lock up after one or two first | |
2155 | * ticks in a non-ExtINT mode. Also the local APIC | |
2156 | * might have cached one ExtINT interrupt. Finally, at | |
2157 | * least one tick may be lost due to delays. | |
2158 | */ | |
54168ed7 IM |
2159 | |
2160 | /* jiffies wrap? */ | |
1d16b53e | 2161 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2162 | return 1; |
1da177e4 LT |
2163 | return 0; |
2164 | } | |
2165 | ||
2166 | /* | |
2167 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2168 | * number of pending IRQ events unhandled. These cases are very rare, | |
2169 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2170 | * better to do it this way as thus we do not have to be aware of | |
2171 | * 'pending' interrupts in the IRQ path, except at this point. | |
2172 | */ | |
2173 | /* | |
2174 | * Edge triggered needs to resend any interrupt | |
2175 | * that was delayed but this is now handled in the device | |
2176 | * independent code. | |
2177 | */ | |
2178 | ||
2179 | /* | |
2180 | * Starting up a edge-triggered IO-APIC interrupt is | |
2181 | * nasty - we need to make sure that we get the edge. | |
2182 | * If it is already asserted for some reason, we need | |
2183 | * return 1 to indicate that is was pending. | |
2184 | * | |
2185 | * This is not complete - we should be able to fake | |
2186 | * an edge even if it isn't on the 8259A... | |
2187 | */ | |
54168ed7 | 2188 | |
f5b9ed7a | 2189 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2190 | { |
2191 | int was_pending = 0; | |
2192 | unsigned long flags; | |
0b8f1efa | 2193 | struct irq_cfg *cfg; |
1da177e4 LT |
2194 | |
2195 | spin_lock_irqsave(&ioapic_lock, flags); | |
bc07844a | 2196 | if (irq < nr_legacy_irqs) { |
1da177e4 LT |
2197 | disable_8259A_irq(irq); |
2198 | if (i8259A_irq_pending(irq)) | |
2199 | was_pending = 1; | |
2200 | } | |
0b8f1efa | 2201 | cfg = irq_cfg(irq); |
3145e941 | 2202 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2203 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2204 | ||
2205 | return was_pending; | |
2206 | } | |
2207 | ||
ace80ab7 | 2208 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2209 | { |
54168ed7 IM |
2210 | |
2211 | struct irq_cfg *cfg = irq_cfg(irq); | |
2212 | unsigned long flags; | |
2213 | ||
2214 | spin_lock_irqsave(&vector_lock, flags); | |
dac5f412 | 2215 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2216 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2217 | |
2218 | return 1; | |
2219 | } | |
497c9a19 | 2220 | |
54168ed7 IM |
2221 | /* |
2222 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2223 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2224 | * handled with the level-triggered descriptor, but that one has slightly | |
2225 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2226 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2227 | * races. | |
2228 | */ | |
497c9a19 | 2229 | |
54168ed7 | 2230 | #ifdef CONFIG_SMP |
e85abf8f GH |
2231 | static void send_cleanup_vector(struct irq_cfg *cfg) |
2232 | { | |
2233 | cpumask_var_t cleanup_mask; | |
2234 | ||
2235 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2236 | unsigned int i; | |
2237 | cfg->move_cleanup_count = 0; | |
2238 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2239 | cfg->move_cleanup_count++; | |
2240 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2241 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2242 | } else { | |
2243 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
2244 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
2245 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2246 | free_cpumask_var(cleanup_mask); | |
2247 | } | |
2248 | cfg->move_in_progress = 0; | |
2249 | } | |
2250 | ||
4420471f | 2251 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2252 | { |
2253 | int apic, pin; | |
2254 | struct irq_pin_list *entry; | |
2255 | u8 vector = cfg->vector; | |
2256 | ||
2977fb3f | 2257 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2258 | unsigned int reg; |
2259 | ||
e85abf8f GH |
2260 | apic = entry->apic; |
2261 | pin = entry->pin; | |
2262 | /* | |
2263 | * With interrupt-remapping, destination information comes | |
2264 | * from interrupt-remapping table entry. | |
2265 | */ | |
2266 | if (!irq_remapped(irq)) | |
2267 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2268 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2269 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2270 | reg |= vector; | |
2271 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2272 | } |
2273 | } | |
2274 | ||
4420471f IM |
2275 | static int |
2276 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
2277 | ||
e85abf8f GH |
2278 | /* |
2279 | * Either sets desc->affinity to a valid value, and returns | |
2280 | * ->cpu_mask_to_apicid of that, or returns BAD_APICID and | |
2281 | * leaves desc->affinity untouched. | |
2282 | */ | |
2283 | static unsigned int | |
2284 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
2285 | { | |
2286 | struct irq_cfg *cfg; | |
2287 | unsigned int irq; | |
2288 | ||
2289 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
2290 | return BAD_APICID; | |
2291 | ||
2292 | irq = desc->irq; | |
2293 | cfg = desc->chip_data; | |
2294 | if (assign_irq_vector(irq, cfg, mask)) | |
2295 | return BAD_APICID; | |
2296 | ||
e85abf8f GH |
2297 | cpumask_copy(desc->affinity, mask); |
2298 | ||
2299 | return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); | |
2300 | } | |
2301 | ||
4420471f | 2302 | static int |
e85abf8f GH |
2303 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2304 | { | |
2305 | struct irq_cfg *cfg; | |
2306 | unsigned long flags; | |
2307 | unsigned int dest; | |
2308 | unsigned int irq; | |
4420471f | 2309 | int ret = -1; |
e85abf8f GH |
2310 | |
2311 | irq = desc->irq; | |
2312 | cfg = desc->chip_data; | |
2313 | ||
2314 | spin_lock_irqsave(&ioapic_lock, flags); | |
2315 | dest = set_desc_affinity(desc, mask); | |
2316 | if (dest != BAD_APICID) { | |
2317 | /* Only the high 8 bits are valid. */ | |
2318 | dest = SET_APIC_LOGICAL_ID(dest); | |
2319 | __target_IO_APIC_irq(irq, dest, cfg); | |
4420471f | 2320 | ret = 0; |
e85abf8f GH |
2321 | } |
2322 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4420471f IM |
2323 | |
2324 | return ret; | |
e85abf8f GH |
2325 | } |
2326 | ||
4420471f | 2327 | static int |
e85abf8f GH |
2328 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2329 | { | |
2330 | struct irq_desc *desc; | |
2331 | ||
2332 | desc = irq_to_desc(irq); | |
2333 | ||
4420471f | 2334 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2335 | } |
497c9a19 | 2336 | |
54168ed7 | 2337 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2338 | |
54168ed7 IM |
2339 | /* |
2340 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2341 | * | |
0280f7c4 SS |
2342 | * For both level and edge triggered, irq migration is a simple atomic |
2343 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2344 | * |
0280f7c4 SS |
2345 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2346 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2347 | * Real vector that is used for interrupting cpu will be coming from | |
2348 | * the interrupt-remapping table entry. | |
54168ed7 | 2349 | */ |
d5dedd45 | 2350 | static int |
e7986739 | 2351 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2352 | { |
54168ed7 | 2353 | struct irq_cfg *cfg; |
54168ed7 | 2354 | struct irte irte; |
54168ed7 | 2355 | unsigned int dest; |
3145e941 | 2356 | unsigned int irq; |
d5dedd45 | 2357 | int ret = -1; |
497c9a19 | 2358 | |
22f65d31 | 2359 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2360 | return ret; |
497c9a19 | 2361 | |
3145e941 | 2362 | irq = desc->irq; |
54168ed7 | 2363 | if (get_irte(irq, &irte)) |
d5dedd45 | 2364 | return ret; |
497c9a19 | 2365 | |
3145e941 YL |
2366 | cfg = desc->chip_data; |
2367 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2368 | return ret; |
54168ed7 | 2369 | |
debccb3e | 2370 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2371 | |
54168ed7 IM |
2372 | irte.vector = cfg->vector; |
2373 | irte.dest_id = IRTE_DEST(dest); | |
2374 | ||
2375 | /* | |
2376 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2377 | */ | |
2378 | modify_irte(irq, &irte); | |
2379 | ||
22f65d31 MT |
2380 | if (cfg->move_in_progress) |
2381 | send_cleanup_vector(cfg); | |
54168ed7 | 2382 | |
7f7ace0c | 2383 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2384 | |
2385 | return 0; | |
54168ed7 IM |
2386 | } |
2387 | ||
54168ed7 IM |
2388 | /* |
2389 | * Migrates the IRQ destination in the process context. | |
2390 | */ | |
d5dedd45 | 2391 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2392 | const struct cpumask *mask) |
54168ed7 | 2393 | { |
d5dedd45 | 2394 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2395 | } |
d5dedd45 | 2396 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2397 | const struct cpumask *mask) |
3145e941 YL |
2398 | { |
2399 | struct irq_desc *desc = irq_to_desc(irq); | |
2400 | ||
d5dedd45 | 2401 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2402 | } |
29b61be6 | 2403 | #else |
d5dedd45 | 2404 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2405 | const struct cpumask *mask) |
2406 | { | |
d5dedd45 | 2407 | return 0; |
29b61be6 | 2408 | } |
54168ed7 IM |
2409 | #endif |
2410 | ||
2411 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2412 | { | |
2413 | unsigned vector, me; | |
8f2466f4 | 2414 | |
54168ed7 | 2415 | ack_APIC_irq(); |
54168ed7 | 2416 | exit_idle(); |
54168ed7 IM |
2417 | irq_enter(); |
2418 | ||
2419 | me = smp_processor_id(); | |
2420 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2421 | unsigned int irq; | |
68a8ca59 | 2422 | unsigned int irr; |
54168ed7 IM |
2423 | struct irq_desc *desc; |
2424 | struct irq_cfg *cfg; | |
2425 | irq = __get_cpu_var(vector_irq)[vector]; | |
2426 | ||
0b8f1efa YL |
2427 | if (irq == -1) |
2428 | continue; | |
2429 | ||
54168ed7 IM |
2430 | desc = irq_to_desc(irq); |
2431 | if (!desc) | |
2432 | continue; | |
2433 | ||
2434 | cfg = irq_cfg(irq); | |
2435 | spin_lock(&desc->lock); | |
2436 | if (!cfg->move_cleanup_count) | |
2437 | goto unlock; | |
2438 | ||
22f65d31 | 2439 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2440 | goto unlock; |
2441 | ||
68a8ca59 SS |
2442 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2443 | /* | |
2444 | * Check if the vector that needs to be cleanedup is | |
2445 | * registered at the cpu's IRR. If so, then this is not | |
2446 | * the best time to clean it up. Lets clean it up in the | |
2447 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2448 | * to myself. | |
2449 | */ | |
2450 | if (irr & (1 << (vector % 32))) { | |
2451 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2452 | goto unlock; | |
2453 | } | |
54168ed7 IM |
2454 | __get_cpu_var(vector_irq)[vector] = -1; |
2455 | cfg->move_cleanup_count--; | |
2456 | unlock: | |
2457 | spin_unlock(&desc->lock); | |
2458 | } | |
2459 | ||
2460 | irq_exit(); | |
2461 | } | |
2462 | ||
3145e941 | 2463 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2464 | { |
3145e941 YL |
2465 | struct irq_desc *desc = *descp; |
2466 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2467 | unsigned vector, me; |
2468 | ||
fcef5911 | 2469 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2470 | return; |
2471 | ||
2472 | vector = ~get_irq_regs()->orig_ax; | |
2473 | me = smp_processor_id(); | |
10b888d6 | 2474 | |
fcef5911 | 2475 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2476 | send_cleanup_vector(cfg); |
497c9a19 YL |
2477 | } |
2478 | #else | |
3145e941 | 2479 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2480 | #endif |
3145e941 | 2481 | |
1d025192 YL |
2482 | static void ack_apic_edge(unsigned int irq) |
2483 | { | |
3145e941 YL |
2484 | struct irq_desc *desc = irq_to_desc(irq); |
2485 | ||
2486 | irq_complete_move(&desc); | |
1d025192 YL |
2487 | move_native_irq(irq); |
2488 | ack_APIC_irq(); | |
2489 | } | |
2490 | ||
3eb2cce8 | 2491 | atomic_t irq_mis_count; |
3eb2cce8 | 2492 | |
047c8fdb YL |
2493 | static void ack_apic_level(unsigned int irq) |
2494 | { | |
3145e941 | 2495 | struct irq_desc *desc = irq_to_desc(irq); |
3eb2cce8 YL |
2496 | unsigned long v; |
2497 | int i; | |
3145e941 | 2498 | struct irq_cfg *cfg; |
54168ed7 | 2499 | int do_unmask_irq = 0; |
047c8fdb | 2500 | |
3145e941 | 2501 | irq_complete_move(&desc); |
047c8fdb | 2502 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2503 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2504 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2505 | do_unmask_irq = 1; |
3145e941 | 2506 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2507 | } |
047c8fdb YL |
2508 | #endif |
2509 | ||
3eb2cce8 | 2510 | /* |
916a0fe7 JF |
2511 | * It appears there is an erratum which affects at least version 0x11 |
2512 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2513 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2514 | * erroneously delivered as edge-triggered one but the respective IRR | |
2515 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2516 | * message but it will never arrive and further interrupts are blocked | |
2517 | * from the source. The exact reason is so far unknown, but the | |
2518 | * phenomenon was observed when two consecutive interrupt requests | |
2519 | * from a given source get delivered to the same CPU and the source is | |
2520 | * temporarily disabled in between. | |
2521 | * | |
2522 | * A workaround is to simulate an EOI message manually. We achieve it | |
2523 | * by setting the trigger mode to edge and then to level when the edge | |
2524 | * trigger mode gets detected in the TMR of a local APIC for a | |
2525 | * level-triggered interrupt. We mask the source for the time of the | |
2526 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2527 | * The idea is from Manfred Spraul. --macro | |
2528 | */ | |
3145e941 YL |
2529 | cfg = desc->chip_data; |
2530 | i = cfg->vector; | |
3eb2cce8 | 2531 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2532 | |
54168ed7 IM |
2533 | /* |
2534 | * We must acknowledge the irq before we move it or the acknowledge will | |
2535 | * not propagate properly. | |
2536 | */ | |
2537 | ack_APIC_irq(); | |
2538 | ||
2539 | /* Now we can move and renable the irq */ | |
2540 | if (unlikely(do_unmask_irq)) { | |
2541 | /* Only migrate the irq if the ack has been received. | |
2542 | * | |
2543 | * On rare occasions the broadcast level triggered ack gets | |
2544 | * delayed going to ioapics, and if we reprogram the | |
2545 | * vector while Remote IRR is still set the irq will never | |
2546 | * fire again. | |
2547 | * | |
2548 | * To prevent this scenario we read the Remote IRR bit | |
2549 | * of the ioapic. This has two effects. | |
2550 | * - On any sane system the read of the ioapic will | |
2551 | * flush writes (and acks) going to the ioapic from | |
2552 | * this cpu. | |
2553 | * - We get to see if the ACK has actually been delivered. | |
2554 | * | |
2555 | * Based on failed experiments of reprogramming the | |
2556 | * ioapic entry from outside of irq context starting | |
2557 | * with masking the ioapic entry and then polling until | |
2558 | * Remote IRR was clear before reprogramming the | |
2559 | * ioapic I don't trust the Remote IRR bit to be | |
2560 | * completey accurate. | |
2561 | * | |
2562 | * However there appears to be no other way to plug | |
2563 | * this race, so if the Remote IRR bit is not | |
2564 | * accurate and is causing problems then it is a hardware bug | |
2565 | * and you can go talk to the chipset vendor about it. | |
2566 | */ | |
3145e941 YL |
2567 | cfg = desc->chip_data; |
2568 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2569 | move_masked_irq(irq); |
3145e941 | 2570 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2571 | } |
1d025192 | 2572 | |
916a0fe7 | 2573 | /* Tail end of version 0x11 I/O APIC bug workaround */ |
1d025192 YL |
2574 | if (!(v & (1 << (i & 0x1f)))) { |
2575 | atomic_inc(&irq_mis_count); | |
2576 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2577 | __mask_and_edge_IO_APIC_irq(cfg); |
2578 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2579 | spin_unlock(&ioapic_lock); |
2580 | } | |
3eb2cce8 | 2581 | } |
1d025192 | 2582 | |
d0b03bd1 | 2583 | #ifdef CONFIG_INTR_REMAP |
25629d81 SS |
2584 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2585 | { | |
25629d81 SS |
2586 | struct irq_pin_list *entry; |
2587 | ||
2977fb3f CG |
2588 | for_each_irq_pin(entry, cfg->irq_2_pin) |
2589 | io_apic_eoi(entry->apic, entry->pin); | |
25629d81 SS |
2590 | } |
2591 | ||
2592 | static void | |
2593 | eoi_ioapic_irq(struct irq_desc *desc) | |
2594 | { | |
2595 | struct irq_cfg *cfg; | |
2596 | unsigned long flags; | |
2597 | unsigned int irq; | |
2598 | ||
2599 | irq = desc->irq; | |
2600 | cfg = desc->chip_data; | |
2601 | ||
2602 | spin_lock_irqsave(&ioapic_lock, flags); | |
2603 | __eoi_ioapic_irq(irq, cfg); | |
2604 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2605 | } | |
2606 | ||
d0b03bd1 HW |
2607 | static void ir_ack_apic_edge(unsigned int irq) |
2608 | { | |
5d0ae2db | 2609 | ack_APIC_irq(); |
d0b03bd1 HW |
2610 | } |
2611 | ||
2612 | static void ir_ack_apic_level(unsigned int irq) | |
2613 | { | |
5d0ae2db WH |
2614 | struct irq_desc *desc = irq_to_desc(irq); |
2615 | ||
2616 | ack_APIC_irq(); | |
2617 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2618 | } |
2619 | #endif /* CONFIG_INTR_REMAP */ | |
2620 | ||
f5b9ed7a | 2621 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2622 | .name = "IO-APIC", |
2623 | .startup = startup_ioapic_irq, | |
2624 | .mask = mask_IO_APIC_irq, | |
2625 | .unmask = unmask_IO_APIC_irq, | |
2626 | .ack = ack_apic_edge, | |
2627 | .eoi = ack_apic_level, | |
54d5d424 | 2628 | #ifdef CONFIG_SMP |
d6c88a50 | 2629 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2630 | #endif |
ace80ab7 | 2631 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2632 | }; |
2633 | ||
54168ed7 | 2634 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2635 | .name = "IR-IO-APIC", |
2636 | .startup = startup_ioapic_irq, | |
2637 | .mask = mask_IO_APIC_irq, | |
2638 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2639 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2640 | .ack = ir_ack_apic_edge, |
2641 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2642 | #ifdef CONFIG_SMP |
d6c88a50 | 2643 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2644 | #endif |
54168ed7 IM |
2645 | #endif |
2646 | .retrigger = ioapic_retrigger_irq, | |
2647 | }; | |
1da177e4 LT |
2648 | |
2649 | static inline void init_IO_APIC_traps(void) | |
2650 | { | |
2651 | int irq; | |
08678b08 | 2652 | struct irq_desc *desc; |
da51a821 | 2653 | struct irq_cfg *cfg; |
1da177e4 LT |
2654 | |
2655 | /* | |
2656 | * NOTE! The local APIC isn't very good at handling | |
2657 | * multiple interrupts at the same interrupt level. | |
2658 | * As the interrupt level is determined by taking the | |
2659 | * vector number and shifting that right by 4, we | |
2660 | * want to spread these out a bit so that they don't | |
2661 | * all fall in the same interrupt level. | |
2662 | * | |
2663 | * Also, we've got to be careful not to trash gate | |
2664 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2665 | */ | |
0b8f1efa | 2666 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2667 | cfg = desc->chip_data; |
2668 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2669 | /* |
2670 | * Hmm.. We don't have an entry for this, | |
2671 | * so default to an old-fashioned 8259 | |
2672 | * interrupt if we can.. | |
2673 | */ | |
bc07844a | 2674 | if (irq < nr_legacy_irqs) |
1da177e4 | 2675 | make_8259A_irq(irq); |
0b8f1efa | 2676 | else |
1da177e4 | 2677 | /* Strange. Oh, well.. */ |
08678b08 | 2678 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2679 | } |
2680 | } | |
2681 | } | |
2682 | ||
f5b9ed7a IM |
2683 | /* |
2684 | * The local APIC irq-chip implementation: | |
2685 | */ | |
1da177e4 | 2686 | |
36062448 | 2687 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2688 | { |
2689 | unsigned long v; | |
2690 | ||
2691 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2692 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2693 | } |
2694 | ||
36062448 | 2695 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2696 | { |
f5b9ed7a | 2697 | unsigned long v; |
1da177e4 | 2698 | |
f5b9ed7a | 2699 | v = apic_read(APIC_LVT0); |
593f4a78 | 2700 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2701 | } |
1da177e4 | 2702 | |
3145e941 | 2703 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2704 | { |
2705 | ack_APIC_irq(); | |
2706 | } | |
2707 | ||
f5b9ed7a | 2708 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2709 | .name = "local-APIC", |
f5b9ed7a IM |
2710 | .mask = mask_lapic_irq, |
2711 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2712 | .ack = ack_lapic_irq, |
1da177e4 LT |
2713 | }; |
2714 | ||
3145e941 | 2715 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2716 | { |
08678b08 | 2717 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2718 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2719 | "edge"); | |
c88ac1df MR |
2720 | } |
2721 | ||
e9427101 | 2722 | static void __init setup_nmi(void) |
1da177e4 LT |
2723 | { |
2724 | /* | |
36062448 | 2725 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2726 | * We put the 8259A master into AEOI mode and |
2727 | * unmask on all local APICs LVT0 as NMI. | |
2728 | * | |
2729 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2730 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2731 | * the NMI handler or the timer interrupt. | |
36062448 | 2732 | */ |
1da177e4 LT |
2733 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2734 | ||
e9427101 | 2735 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2736 | |
2737 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2738 | } | |
2739 | ||
2740 | /* | |
2741 | * This looks a bit hackish but it's about the only one way of sending | |
2742 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2743 | * not support the ExtINT mode, unfortunately. We need to send these | |
2744 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2745 | * 8259A interrupt line asserted until INTA. --macro | |
2746 | */ | |
28acf285 | 2747 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2748 | { |
fcfd636a | 2749 | int apic, pin, i; |
1da177e4 LT |
2750 | struct IO_APIC_route_entry entry0, entry1; |
2751 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2752 | |
fcfd636a | 2753 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2754 | if (pin == -1) { |
2755 | WARN_ON_ONCE(1); | |
2756 | return; | |
2757 | } | |
fcfd636a | 2758 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2759 | if (apic == -1) { |
2760 | WARN_ON_ONCE(1); | |
1da177e4 | 2761 | return; |
956fb531 | 2762 | } |
1da177e4 | 2763 | |
cf4c6a2f | 2764 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2765 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2766 | |
2767 | memset(&entry1, 0, sizeof(entry1)); | |
2768 | ||
2769 | entry1.dest_mode = 0; /* physical delivery */ | |
2770 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2771 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2772 | entry1.delivery_mode = dest_ExtINT; |
2773 | entry1.polarity = entry0.polarity; | |
2774 | entry1.trigger = 0; | |
2775 | entry1.vector = 0; | |
2776 | ||
cf4c6a2f | 2777 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2778 | |
2779 | save_control = CMOS_READ(RTC_CONTROL); | |
2780 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2781 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2782 | RTC_FREQ_SELECT); | |
2783 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2784 | ||
2785 | i = 100; | |
2786 | while (i-- > 0) { | |
2787 | mdelay(10); | |
2788 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2789 | i -= 10; | |
2790 | } | |
2791 | ||
2792 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2793 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2794 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2795 | |
cf4c6a2f | 2796 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2797 | } |
2798 | ||
efa2559f | 2799 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2800 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2801 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2802 | { |
2803 | disable_timer_pin_1 = 1; | |
2804 | return 0; | |
2805 | } | |
54168ed7 | 2806 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2807 | |
2808 | int timer_through_8259 __initdata; | |
2809 | ||
1da177e4 LT |
2810 | /* |
2811 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2812 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2813 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2814 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2815 | * |
2816 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2817 | */ |
8542b200 | 2818 | static inline void __init check_timer(void) |
1da177e4 | 2819 | { |
3145e941 YL |
2820 | struct irq_desc *desc = irq_to_desc(0); |
2821 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2822 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2823 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2824 | unsigned long flags; |
047c8fdb | 2825 | int no_pin1 = 0; |
4aae0702 IM |
2826 | |
2827 | local_irq_save(flags); | |
d4d25dec | 2828 | |
1da177e4 LT |
2829 | /* |
2830 | * get/set the timer IRQ vector: | |
2831 | */ | |
2832 | disable_8259A_irq(0); | |
fe402e1f | 2833 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2834 | |
2835 | /* | |
d11d5794 MR |
2836 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2837 | * wire has to be disabled in the local APIC. Also | |
2838 | * timer interrupts need to be acknowledged manually in | |
2839 | * the 8259A for the i82489DX when using the NMI | |
2840 | * watchdog as that APIC treats NMIs as level-triggered. | |
2841 | * The AEOI mode will finish them in the 8259A | |
2842 | * automatically. | |
1da177e4 | 2843 | */ |
593f4a78 | 2844 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2845 | init_8259A(1); |
54168ed7 | 2846 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2847 | { |
2848 | unsigned int ver; | |
2849 | ||
2850 | ver = apic_read(APIC_LVR); | |
2851 | ver = GET_APIC_VERSION(ver); | |
2852 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2853 | } | |
54168ed7 | 2854 | #endif |
1da177e4 | 2855 | |
fcfd636a EB |
2856 | pin1 = find_isa_irq_pin(0, mp_INT); |
2857 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2858 | pin2 = ioapic_i8259.pin; | |
2859 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2860 | |
49a66a0b MR |
2861 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2862 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2863 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2864 | |
691874fa MR |
2865 | /* |
2866 | * Some BIOS writers are clueless and report the ExtINTA | |
2867 | * I/O APIC input from the cascaded 8259A as the timer | |
2868 | * interrupt input. So just in case, if only one pin | |
2869 | * was found above, try it both directly and through the | |
2870 | * 8259A. | |
2871 | */ | |
2872 | if (pin1 == -1) { | |
54168ed7 IM |
2873 | if (intr_remapping_enabled) |
2874 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2875 | pin1 = pin2; |
2876 | apic1 = apic2; | |
2877 | no_pin1 = 1; | |
2878 | } else if (pin2 == -1) { | |
2879 | pin2 = pin1; | |
2880 | apic2 = apic1; | |
2881 | } | |
2882 | ||
1da177e4 LT |
2883 | if (pin1 != -1) { |
2884 | /* | |
2885 | * Ok, does IRQ0 through the IOAPIC work? | |
2886 | */ | |
691874fa | 2887 | if (no_pin1) { |
85ac16d0 | 2888 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2889 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2890 | } else { |
2891 | /* for edge trigger, setup_IO_APIC_irq already | |
2892 | * leave it unmasked. | |
2893 | * so only need to unmask if it is level-trigger | |
2894 | * do we really have level trigger timer? | |
2895 | */ | |
2896 | int idx; | |
2897 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2898 | if (idx != -1 && irq_trigger(idx)) | |
2899 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 2900 | } |
1da177e4 LT |
2901 | if (timer_irq_works()) { |
2902 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2903 | setup_nmi(); |
2904 | enable_8259A_irq(0); | |
1da177e4 | 2905 | } |
66759a01 CE |
2906 | if (disable_timer_pin_1 > 0) |
2907 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2908 | goto out; |
1da177e4 | 2909 | } |
54168ed7 IM |
2910 | if (intr_remapping_enabled) |
2911 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2912 | local_irq_disable(); |
fcfd636a | 2913 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2914 | if (!no_pin1) |
49a66a0b MR |
2915 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2916 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2917 | |
49a66a0b MR |
2918 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2919 | "(IRQ0) through the 8259A ...\n"); | |
2920 | apic_printk(APIC_QUIET, KERN_INFO | |
2921 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2922 | /* |
2923 | * legacy devices should be connected to IO APIC #0 | |
2924 | */ | |
85ac16d0 | 2925 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2926 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
ecd29476 | 2927 | enable_8259A_irq(0); |
1da177e4 | 2928 | if (timer_irq_works()) { |
49a66a0b | 2929 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2930 | timer_through_8259 = 1; |
1da177e4 | 2931 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2932 | disable_8259A_irq(0); |
1da177e4 | 2933 | setup_nmi(); |
60134ebe | 2934 | enable_8259A_irq(0); |
1da177e4 | 2935 | } |
4aae0702 | 2936 | goto out; |
1da177e4 LT |
2937 | } |
2938 | /* | |
2939 | * Cleanup, just in case ... | |
2940 | */ | |
f72dccac | 2941 | local_irq_disable(); |
ecd29476 | 2942 | disable_8259A_irq(0); |
fcfd636a | 2943 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2944 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2945 | } |
1da177e4 LT |
2946 | |
2947 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2948 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2949 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2950 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2951 | } |
54168ed7 | 2952 | #ifdef CONFIG_X86_32 |
d11d5794 | 2953 | timer_ack = 0; |
54168ed7 | 2954 | #endif |
1da177e4 | 2955 | |
49a66a0b MR |
2956 | apic_printk(APIC_QUIET, KERN_INFO |
2957 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2958 | |
3145e941 | 2959 | lapic_register_intr(0, desc); |
497c9a19 | 2960 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
2961 | enable_8259A_irq(0); |
2962 | ||
2963 | if (timer_irq_works()) { | |
49a66a0b | 2964 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2965 | goto out; |
1da177e4 | 2966 | } |
f72dccac | 2967 | local_irq_disable(); |
e67465f1 | 2968 | disable_8259A_irq(0); |
497c9a19 | 2969 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2970 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2971 | |
49a66a0b MR |
2972 | apic_printk(APIC_QUIET, KERN_INFO |
2973 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2974 | |
1da177e4 LT |
2975 | init_8259A(0); |
2976 | make_8259A_irq(0); | |
593f4a78 | 2977 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2978 | |
2979 | unlock_ExtINT_logic(); | |
2980 | ||
2981 | if (timer_irq_works()) { | |
49a66a0b | 2982 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2983 | goto out; |
1da177e4 | 2984 | } |
f72dccac | 2985 | local_irq_disable(); |
49a66a0b | 2986 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2987 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2988 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2989 | out: |
2990 | local_irq_restore(flags); | |
1da177e4 LT |
2991 | } |
2992 | ||
2993 | /* | |
af174783 MR |
2994 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2995 | * to devices. However there may be an I/O APIC pin available for | |
2996 | * this interrupt regardless. The pin may be left unconnected, but | |
2997 | * typically it will be reused as an ExtINT cascade interrupt for | |
2998 | * the master 8259A. In the MPS case such a pin will normally be | |
2999 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3000 | * there is no provision for ExtINT interrupts, and in the absence | |
3001 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3002 | * interrupt, that is edge-triggered and unmasked by default. We | |
3003 | * used to do this, but it caused problems on some systems because | |
3004 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3005 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3006 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3007 | * the I/O APIC in all cases now. No actual device should request | |
3008 | * it anyway. --macro | |
1da177e4 | 3009 | */ |
bc07844a | 3010 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
3011 | |
3012 | void __init setup_IO_APIC(void) | |
3013 | { | |
54168ed7 | 3014 | |
54168ed7 IM |
3015 | /* |
3016 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3017 | */ | |
bc07844a | 3018 | io_apic_irqs = nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 3019 | |
54168ed7 | 3020 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3021 | /* |
54168ed7 IM |
3022 | * Set up IO-APIC IRQ routing. |
3023 | */ | |
de934103 TG |
3024 | x86_init.mpparse.setup_ioapic_ids(); |
3025 | ||
1da177e4 LT |
3026 | sync_Arb_IDs(); |
3027 | setup_IO_APIC_irqs(); | |
3028 | init_IO_APIC_traps(); | |
bc07844a TG |
3029 | if (nr_legacy_irqs) |
3030 | check_timer(); | |
1da177e4 LT |
3031 | } |
3032 | ||
3033 | /* | |
54168ed7 IM |
3034 | * Called after all the initialization is done. If we didnt find any |
3035 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3036 | */ |
36062448 | 3037 | |
1da177e4 LT |
3038 | static int __init io_apic_bug_finalize(void) |
3039 | { | |
d6c88a50 TG |
3040 | if (sis_apic_bug == -1) |
3041 | sis_apic_bug = 0; | |
3042 | return 0; | |
1da177e4 LT |
3043 | } |
3044 | ||
3045 | late_initcall(io_apic_bug_finalize); | |
3046 | ||
3047 | struct sysfs_ioapic_data { | |
3048 | struct sys_device dev; | |
3049 | struct IO_APIC_route_entry entry[0]; | |
3050 | }; | |
54168ed7 | 3051 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3052 | |
438510f6 | 3053 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3054 | { |
3055 | struct IO_APIC_route_entry *entry; | |
3056 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3057 | int i; |
36062448 | 3058 | |
1da177e4 LT |
3059 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3060 | entry = data->entry; | |
54168ed7 IM |
3061 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3062 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3063 | |
3064 | return 0; | |
3065 | } | |
3066 | ||
3067 | static int ioapic_resume(struct sys_device *dev) | |
3068 | { | |
3069 | struct IO_APIC_route_entry *entry; | |
3070 | struct sysfs_ioapic_data *data; | |
3071 | unsigned long flags; | |
3072 | union IO_APIC_reg_00 reg_00; | |
3073 | int i; | |
36062448 | 3074 | |
1da177e4 LT |
3075 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3076 | entry = data->entry; | |
3077 | ||
3078 | spin_lock_irqsave(&ioapic_lock, flags); | |
3079 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3080 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3081 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3082 | io_apic_write(dev->id, 0, reg_00.raw); |
3083 | } | |
1da177e4 | 3084 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3085 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3086 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3087 | |
3088 | return 0; | |
3089 | } | |
3090 | ||
3091 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3092 | .name = "ioapic", |
1da177e4 LT |
3093 | .suspend = ioapic_suspend, |
3094 | .resume = ioapic_resume, | |
3095 | }; | |
3096 | ||
3097 | static int __init ioapic_init_sysfs(void) | |
3098 | { | |
54168ed7 IM |
3099 | struct sys_device * dev; |
3100 | int i, size, error; | |
1da177e4 LT |
3101 | |
3102 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3103 | if (error) | |
3104 | return error; | |
3105 | ||
54168ed7 | 3106 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3107 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3108 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3109 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3110 | if (!mp_ioapic_data[i]) { |
3111 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3112 | continue; | |
3113 | } | |
1da177e4 | 3114 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3115 | dev->id = i; |
1da177e4 LT |
3116 | dev->cls = &ioapic_sysdev_class; |
3117 | error = sysdev_register(dev); | |
3118 | if (error) { | |
3119 | kfree(mp_ioapic_data[i]); | |
3120 | mp_ioapic_data[i] = NULL; | |
3121 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3122 | continue; | |
3123 | } | |
3124 | } | |
3125 | ||
3126 | return 0; | |
3127 | } | |
3128 | ||
3129 | device_initcall(ioapic_init_sysfs); | |
3130 | ||
3fc471ed | 3131 | /* |
95d77884 | 3132 | * Dynamic irq allocate and deallocation |
3fc471ed | 3133 | */ |
d047f53a | 3134 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3135 | { |
ace80ab7 | 3136 | /* Allocate an unused irq */ |
54168ed7 IM |
3137 | unsigned int irq; |
3138 | unsigned int new; | |
3fc471ed | 3139 | unsigned long flags; |
0b8f1efa | 3140 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3141 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3142 | |
3143 | irq = 0; | |
abcaa2b8 YL |
3144 | if (irq_want < nr_irqs_gsi) |
3145 | irq_want = nr_irqs_gsi; | |
3146 | ||
ace80ab7 | 3147 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3148 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3149 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3150 | if (!desc_new) { |
3151 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3152 | continue; |
0b8f1efa YL |
3153 | } |
3154 | cfg_new = desc_new->chip_data; | |
3155 | ||
3156 | if (cfg_new->vector != 0) | |
ace80ab7 | 3157 | continue; |
d047f53a | 3158 | |
15e957d0 | 3159 | desc_new = move_irq_desc(desc_new, node); |
d047f53a | 3160 | |
fe402e1f | 3161 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3162 | irq = new; |
3163 | break; | |
3164 | } | |
3165 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3166 | |
199751d7 | 3167 | if (irq > 0) { |
3fc471ed | 3168 | dynamic_irq_init(irq); |
0b8f1efa YL |
3169 | /* restore it, in case dynamic_irq_init clear it */ |
3170 | if (desc_new) | |
3171 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3172 | } |
3173 | return irq; | |
3174 | } | |
3175 | ||
199751d7 YL |
3176 | int create_irq(void) |
3177 | { | |
d047f53a | 3178 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3179 | unsigned int irq_want; |
54168ed7 IM |
3180 | int irq; |
3181 | ||
be5d5350 | 3182 | irq_want = nr_irqs_gsi; |
d047f53a | 3183 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3184 | |
3185 | if (irq == 0) | |
3186 | irq = -1; | |
3187 | ||
3188 | return irq; | |
199751d7 YL |
3189 | } |
3190 | ||
3fc471ed EB |
3191 | void destroy_irq(unsigned int irq) |
3192 | { | |
3193 | unsigned long flags; | |
0b8f1efa YL |
3194 | struct irq_cfg *cfg; |
3195 | struct irq_desc *desc; | |
3fc471ed | 3196 | |
0b8f1efa YL |
3197 | /* store it, in case dynamic_irq_cleanup clear it */ |
3198 | desc = irq_to_desc(irq); | |
3199 | cfg = desc->chip_data; | |
3fc471ed | 3200 | dynamic_irq_cleanup(irq); |
0b8f1efa | 3201 | /* connect back irq_cfg */ |
25f6e89b | 3202 | desc->chip_data = cfg; |
3fc471ed | 3203 | |
54168ed7 | 3204 | free_irte(irq); |
3fc471ed | 3205 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3206 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3207 | spin_unlock_irqrestore(&vector_lock, flags); |
3208 | } | |
3fc471ed | 3209 | |
2d3fcc1c | 3210 | /* |
27b46d76 | 3211 | * MSI message composition |
2d3fcc1c EB |
3212 | */ |
3213 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3214 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3215 | { |
497c9a19 YL |
3216 | struct irq_cfg *cfg; |
3217 | int err; | |
2d3fcc1c EB |
3218 | unsigned dest; |
3219 | ||
f1182638 JB |
3220 | if (disable_apic) |
3221 | return -ENXIO; | |
3222 | ||
3145e941 | 3223 | cfg = irq_cfg(irq); |
fe402e1f | 3224 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3225 | if (err) |
3226 | return err; | |
2d3fcc1c | 3227 | |
debccb3e | 3228 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3229 | |
54168ed7 IM |
3230 | if (irq_remapped(irq)) { |
3231 | struct irte irte; | |
3232 | int ir_index; | |
3233 | u16 sub_handle; | |
3234 | ||
3235 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3236 | BUG_ON(ir_index == -1); | |
3237 | ||
3238 | memset (&irte, 0, sizeof(irte)); | |
3239 | ||
3240 | irte.present = 1; | |
9b5bc8dc | 3241 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3242 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3243 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3244 | irte.vector = cfg->vector; |
3245 | irte.dest_id = IRTE_DEST(dest); | |
3246 | ||
f007e99c WH |
3247 | /* Set source-id of interrupt request */ |
3248 | set_msi_sid(&irte, pdev); | |
3249 | ||
54168ed7 IM |
3250 | modify_irte(irq, &irte); |
3251 | ||
3252 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3253 | msg->data = sub_handle; | |
3254 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3255 | MSI_ADDR_IR_SHV | | |
3256 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3257 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3258 | } else { |
9d783ba0 SS |
3259 | if (x2apic_enabled()) |
3260 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3261 | MSI_ADDR_EXT_DEST_ID(dest); | |
3262 | else | |
3263 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3264 | ||
54168ed7 IM |
3265 | msg->address_lo = |
3266 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3267 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3268 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3269 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3270 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3271 | MSI_ADDR_REDIRECTION_CPU: |
3272 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3273 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3274 | |
54168ed7 IM |
3275 | msg->data = |
3276 | MSI_DATA_TRIGGER_EDGE | | |
3277 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3278 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3279 | MSI_DATA_DELIVERY_FIXED: |
3280 | MSI_DATA_DELIVERY_LOWPRI) | | |
3281 | MSI_DATA_VECTOR(cfg->vector); | |
3282 | } | |
497c9a19 | 3283 | return err; |
2d3fcc1c EB |
3284 | } |
3285 | ||
3b7d1921 | 3286 | #ifdef CONFIG_SMP |
d5dedd45 | 3287 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3288 | { |
3145e941 | 3289 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3290 | struct irq_cfg *cfg; |
3b7d1921 EB |
3291 | struct msi_msg msg; |
3292 | unsigned int dest; | |
3b7d1921 | 3293 | |
22f65d31 MT |
3294 | dest = set_desc_affinity(desc, mask); |
3295 | if (dest == BAD_APICID) | |
d5dedd45 | 3296 | return -1; |
2d3fcc1c | 3297 | |
3145e941 | 3298 | cfg = desc->chip_data; |
2d3fcc1c | 3299 | |
3145e941 | 3300 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3301 | |
3302 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3303 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3304 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3305 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3306 | ||
3145e941 | 3307 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3308 | |
3309 | return 0; | |
2d3fcc1c | 3310 | } |
54168ed7 IM |
3311 | #ifdef CONFIG_INTR_REMAP |
3312 | /* | |
3313 | * Migrate the MSI irq to another cpumask. This migration is | |
3314 | * done in the process context using interrupt-remapping hardware. | |
3315 | */ | |
d5dedd45 | 3316 | static int |
e7986739 | 3317 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3318 | { |
3145e941 | 3319 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3320 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3321 | unsigned int dest; |
54168ed7 | 3322 | struct irte irte; |
54168ed7 IM |
3323 | |
3324 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3325 | return -1; |
54168ed7 | 3326 | |
22f65d31 MT |
3327 | dest = set_desc_affinity(desc, mask); |
3328 | if (dest == BAD_APICID) | |
d5dedd45 | 3329 | return -1; |
54168ed7 | 3330 | |
54168ed7 IM |
3331 | irte.vector = cfg->vector; |
3332 | irte.dest_id = IRTE_DEST(dest); | |
3333 | ||
3334 | /* | |
3335 | * atomically update the IRTE with the new destination and vector. | |
3336 | */ | |
3337 | modify_irte(irq, &irte); | |
3338 | ||
3339 | /* | |
3340 | * After this point, all the interrupts will start arriving | |
3341 | * at the new destination. So, time to cleanup the previous | |
3342 | * vector allocation. | |
3343 | */ | |
22f65d31 MT |
3344 | if (cfg->move_in_progress) |
3345 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3346 | |
3347 | return 0; | |
54168ed7 | 3348 | } |
3145e941 | 3349 | |
54168ed7 | 3350 | #endif |
3b7d1921 | 3351 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3352 | |
3b7d1921 EB |
3353 | /* |
3354 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3355 | * which implement the MSI or MSI-X Capability Structure. | |
3356 | */ | |
3357 | static struct irq_chip msi_chip = { | |
3358 | .name = "PCI-MSI", | |
3359 | .unmask = unmask_msi_irq, | |
3360 | .mask = mask_msi_irq, | |
1d025192 | 3361 | .ack = ack_apic_edge, |
3b7d1921 EB |
3362 | #ifdef CONFIG_SMP |
3363 | .set_affinity = set_msi_irq_affinity, | |
3364 | #endif | |
3365 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3366 | }; |
3367 | ||
54168ed7 IM |
3368 | static struct irq_chip msi_ir_chip = { |
3369 | .name = "IR-PCI-MSI", | |
3370 | .unmask = unmask_msi_irq, | |
3371 | .mask = mask_msi_irq, | |
a1e38ca5 | 3372 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3373 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3374 | #ifdef CONFIG_SMP |
3375 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3376 | #endif |
54168ed7 IM |
3377 | #endif |
3378 | .retrigger = ioapic_retrigger_irq, | |
3379 | }; | |
3380 | ||
3381 | /* | |
3382 | * Map the PCI dev to the corresponding remapping hardware unit | |
3383 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3384 | * in it. | |
3385 | */ | |
3386 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3387 | { | |
3388 | struct intel_iommu *iommu; | |
3389 | int index; | |
3390 | ||
3391 | iommu = map_dev_to_ir(dev); | |
3392 | if (!iommu) { | |
3393 | printk(KERN_ERR | |
3394 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3395 | return -ENOENT; | |
3396 | } | |
3397 | ||
3398 | index = alloc_irte(iommu, irq, nvec); | |
3399 | if (index < 0) { | |
3400 | printk(KERN_ERR | |
3401 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3402 | pci_name(dev)); |
54168ed7 IM |
3403 | return -ENOSPC; |
3404 | } | |
3405 | return index; | |
3406 | } | |
1d025192 | 3407 | |
3145e941 | 3408 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3409 | { |
3410 | int ret; | |
3411 | struct msi_msg msg; | |
3412 | ||
3413 | ret = msi_compose_msg(dev, irq, &msg); | |
3414 | if (ret < 0) | |
3415 | return ret; | |
3416 | ||
3145e941 | 3417 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3418 | write_msi_msg(irq, &msg); |
3419 | ||
54168ed7 IM |
3420 | if (irq_remapped(irq)) { |
3421 | struct irq_desc *desc = irq_to_desc(irq); | |
3422 | /* | |
3423 | * irq migration in process context | |
3424 | */ | |
3425 | desc->status |= IRQ_MOVE_PCNTXT; | |
3426 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3427 | } else | |
54168ed7 | 3428 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3429 | |
c81bba49 YL |
3430 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3431 | ||
1d025192 YL |
3432 | return 0; |
3433 | } | |
3434 | ||
047c8fdb YL |
3435 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3436 | { | |
54168ed7 IM |
3437 | unsigned int irq; |
3438 | int ret, sub_handle; | |
0b8f1efa | 3439 | struct msi_desc *msidesc; |
54168ed7 | 3440 | unsigned int irq_want; |
1cc18521 | 3441 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3442 | int index = 0; |
d047f53a | 3443 | int node; |
54168ed7 | 3444 | |
1c8d7b0a MW |
3445 | /* x86 doesn't support multiple MSI yet */ |
3446 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3447 | return 1; | |
3448 | ||
d047f53a | 3449 | node = dev_to_node(&dev->dev); |
be5d5350 | 3450 | irq_want = nr_irqs_gsi; |
54168ed7 | 3451 | sub_handle = 0; |
0b8f1efa | 3452 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3453 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3454 | if (irq == 0) |
3455 | return -1; | |
f1ee5548 | 3456 | irq_want = irq + 1; |
54168ed7 IM |
3457 | if (!intr_remapping_enabled) |
3458 | goto no_ir; | |
3459 | ||
3460 | if (!sub_handle) { | |
3461 | /* | |
3462 | * allocate the consecutive block of IRTE's | |
3463 | * for 'nvec' | |
3464 | */ | |
3465 | index = msi_alloc_irte(dev, irq, nvec); | |
3466 | if (index < 0) { | |
3467 | ret = index; | |
3468 | goto error; | |
3469 | } | |
3470 | } else { | |
3471 | iommu = map_dev_to_ir(dev); | |
3472 | if (!iommu) { | |
3473 | ret = -ENOENT; | |
3474 | goto error; | |
3475 | } | |
3476 | /* | |
3477 | * setup the mapping between the irq and the IRTE | |
3478 | * base index, the sub_handle pointing to the | |
3479 | * appropriate interrupt remap table entry. | |
3480 | */ | |
3481 | set_irte_irq(irq, iommu, index, sub_handle); | |
3482 | } | |
3483 | no_ir: | |
0b8f1efa | 3484 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3485 | if (ret < 0) |
3486 | goto error; | |
3487 | sub_handle++; | |
3488 | } | |
3489 | return 0; | |
047c8fdb YL |
3490 | |
3491 | error: | |
54168ed7 IM |
3492 | destroy_irq(irq); |
3493 | return ret; | |
047c8fdb YL |
3494 | } |
3495 | ||
3b7d1921 EB |
3496 | void arch_teardown_msi_irq(unsigned int irq) |
3497 | { | |
f7feaca7 | 3498 | destroy_irq(irq); |
3b7d1921 EB |
3499 | } |
3500 | ||
9d783ba0 | 3501 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3502 | #ifdef CONFIG_SMP |
d5dedd45 | 3503 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3504 | { |
3145e941 | 3505 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3506 | struct irq_cfg *cfg; |
3507 | struct msi_msg msg; | |
3508 | unsigned int dest; | |
54168ed7 | 3509 | |
22f65d31 MT |
3510 | dest = set_desc_affinity(desc, mask); |
3511 | if (dest == BAD_APICID) | |
d5dedd45 | 3512 | return -1; |
54168ed7 | 3513 | |
3145e941 | 3514 | cfg = desc->chip_data; |
54168ed7 IM |
3515 | |
3516 | dmar_msi_read(irq, &msg); | |
3517 | ||
3518 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3519 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3520 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3521 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3522 | ||
3523 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3524 | |
3525 | return 0; | |
54168ed7 | 3526 | } |
3145e941 | 3527 | |
54168ed7 IM |
3528 | #endif /* CONFIG_SMP */ |
3529 | ||
8f7007aa | 3530 | static struct irq_chip dmar_msi_type = { |
54168ed7 IM |
3531 | .name = "DMAR_MSI", |
3532 | .unmask = dmar_msi_unmask, | |
3533 | .mask = dmar_msi_mask, | |
3534 | .ack = ack_apic_edge, | |
3535 | #ifdef CONFIG_SMP | |
3536 | .set_affinity = dmar_msi_set_affinity, | |
3537 | #endif | |
3538 | .retrigger = ioapic_retrigger_irq, | |
3539 | }; | |
3540 | ||
3541 | int arch_setup_dmar_msi(unsigned int irq) | |
3542 | { | |
3543 | int ret; | |
3544 | struct msi_msg msg; | |
2d3fcc1c | 3545 | |
54168ed7 IM |
3546 | ret = msi_compose_msg(NULL, irq, &msg); |
3547 | if (ret < 0) | |
3548 | return ret; | |
3549 | dmar_msi_write(irq, &msg); | |
3550 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3551 | "edge"); | |
3552 | return 0; | |
3553 | } | |
3554 | #endif | |
3555 | ||
58ac1e76 | 3556 | #ifdef CONFIG_HPET_TIMER |
3557 | ||
3558 | #ifdef CONFIG_SMP | |
d5dedd45 | 3559 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3560 | { |
3145e941 | 3561 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3562 | struct irq_cfg *cfg; |
58ac1e76 | 3563 | struct msi_msg msg; |
3564 | unsigned int dest; | |
58ac1e76 | 3565 | |
22f65d31 MT |
3566 | dest = set_desc_affinity(desc, mask); |
3567 | if (dest == BAD_APICID) | |
d5dedd45 | 3568 | return -1; |
58ac1e76 | 3569 | |
3145e941 | 3570 | cfg = desc->chip_data; |
58ac1e76 | 3571 | |
3572 | hpet_msi_read(irq, &msg); | |
3573 | ||
3574 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3575 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3576 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3577 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3578 | ||
3579 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3580 | |
3581 | return 0; | |
58ac1e76 | 3582 | } |
3145e941 | 3583 | |
58ac1e76 | 3584 | #endif /* CONFIG_SMP */ |
3585 | ||
1cc18521 | 3586 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3587 | .name = "HPET_MSI", |
3588 | .unmask = hpet_msi_unmask, | |
3589 | .mask = hpet_msi_mask, | |
3590 | .ack = ack_apic_edge, | |
3591 | #ifdef CONFIG_SMP | |
3592 | .set_affinity = hpet_msi_set_affinity, | |
3593 | #endif | |
3594 | .retrigger = ioapic_retrigger_irq, | |
3595 | }; | |
3596 | ||
3597 | int arch_setup_hpet_msi(unsigned int irq) | |
3598 | { | |
3599 | int ret; | |
3600 | struct msi_msg msg; | |
6ec3cfec | 3601 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3602 | |
3603 | ret = msi_compose_msg(NULL, irq, &msg); | |
3604 | if (ret < 0) | |
3605 | return ret; | |
3606 | ||
3607 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3608 | desc->status |= IRQ_MOVE_PCNTXT; |
58ac1e76 | 3609 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, |
3610 | "edge"); | |
c81bba49 | 3611 | |
58ac1e76 | 3612 | return 0; |
3613 | } | |
3614 | #endif | |
3615 | ||
54168ed7 | 3616 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3617 | /* |
3618 | * Hypertransport interrupt support | |
3619 | */ | |
3620 | #ifdef CONFIG_HT_IRQ | |
3621 | ||
3622 | #ifdef CONFIG_SMP | |
3623 | ||
497c9a19 | 3624 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3625 | { |
ec68307c EB |
3626 | struct ht_irq_msg msg; |
3627 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3628 | |
497c9a19 | 3629 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3630 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3631 | |
497c9a19 | 3632 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3633 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3634 | |
ec68307c | 3635 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3636 | } |
3637 | ||
d5dedd45 | 3638 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3639 | { |
3145e941 | 3640 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3641 | struct irq_cfg *cfg; |
8b955b0d | 3642 | unsigned int dest; |
8b955b0d | 3643 | |
22f65d31 MT |
3644 | dest = set_desc_affinity(desc, mask); |
3645 | if (dest == BAD_APICID) | |
d5dedd45 | 3646 | return -1; |
8b955b0d | 3647 | |
3145e941 | 3648 | cfg = desc->chip_data; |
8b955b0d | 3649 | |
497c9a19 | 3650 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3651 | |
3652 | return 0; | |
8b955b0d | 3653 | } |
3145e941 | 3654 | |
8b955b0d EB |
3655 | #endif |
3656 | ||
c37e108d | 3657 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3658 | .name = "PCI-HT", |
3659 | .mask = mask_ht_irq, | |
3660 | .unmask = unmask_ht_irq, | |
1d025192 | 3661 | .ack = ack_apic_edge, |
8b955b0d EB |
3662 | #ifdef CONFIG_SMP |
3663 | .set_affinity = set_ht_irq_affinity, | |
3664 | #endif | |
3665 | .retrigger = ioapic_retrigger_irq, | |
3666 | }; | |
3667 | ||
3668 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3669 | { | |
497c9a19 YL |
3670 | struct irq_cfg *cfg; |
3671 | int err; | |
8b955b0d | 3672 | |
f1182638 JB |
3673 | if (disable_apic) |
3674 | return -ENXIO; | |
3675 | ||
3145e941 | 3676 | cfg = irq_cfg(irq); |
fe402e1f | 3677 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3678 | if (!err) { |
ec68307c | 3679 | struct ht_irq_msg msg; |
8b955b0d | 3680 | unsigned dest; |
8b955b0d | 3681 | |
debccb3e IM |
3682 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3683 | apic->target_cpus()); | |
8b955b0d | 3684 | |
ec68307c | 3685 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3686 | |
ec68307c EB |
3687 | msg.address_lo = |
3688 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3689 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3690 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3691 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3692 | HT_IRQ_LOW_DM_PHYSICAL : |
3693 | HT_IRQ_LOW_DM_LOGICAL) | | |
3694 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3695 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3696 | HT_IRQ_LOW_MT_FIXED : |
3697 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3698 | HT_IRQ_LOW_IRQ_MASKED; | |
3699 | ||
ec68307c | 3700 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3701 | |
a460e745 IM |
3702 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3703 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3704 | |
3705 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3706 | } |
497c9a19 | 3707 | return err; |
8b955b0d EB |
3708 | } |
3709 | #endif /* CONFIG_HT_IRQ */ | |
3710 | ||
03b48632 | 3711 | #ifdef CONFIG_X86_UV |
4173a0e7 DN |
3712 | /* |
3713 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3714 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3715 | */ | |
3716 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3717 | unsigned long mmr_offset) | |
3718 | { | |
22f65d31 | 3719 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3720 | struct irq_cfg *cfg; |
3721 | int mmr_pnode; | |
3722 | unsigned long mmr_value; | |
3723 | struct uv_IO_APIC_route_entry *entry; | |
3724 | unsigned long flags; | |
3725 | int err; | |
3726 | ||
1cbac972 CG |
3727 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3728 | ||
3145e941 YL |
3729 | cfg = irq_cfg(irq); |
3730 | ||
e7986739 | 3731 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3732 | if (err != 0) |
3733 | return err; | |
3734 | ||
3735 | spin_lock_irqsave(&vector_lock, flags); | |
3736 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3737 | irq_name); | |
3738 | spin_unlock_irqrestore(&vector_lock, flags); | |
3739 | ||
4173a0e7 DN |
3740 | mmr_value = 0; |
3741 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
1cbac972 CG |
3742 | entry->vector = cfg->vector; |
3743 | entry->delivery_mode = apic->irq_delivery_mode; | |
3744 | entry->dest_mode = apic->irq_dest_mode; | |
3745 | entry->polarity = 0; | |
3746 | entry->trigger = 0; | |
3747 | entry->mask = 0; | |
3748 | entry->dest = apic->cpu_mask_to_apicid(eligible_cpu); | |
4173a0e7 DN |
3749 | |
3750 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3751 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3752 | ||
2a5ef416 JS |
3753 | if (cfg->move_in_progress) |
3754 | send_cleanup_vector(cfg); | |
3755 | ||
4173a0e7 DN |
3756 | return irq; |
3757 | } | |
3758 | ||
3759 | /* | |
3760 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3761 | * longer allowed to be sent. | |
3762 | */ | |
3763 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3764 | { | |
3765 | unsigned long mmr_value; | |
3766 | struct uv_IO_APIC_route_entry *entry; | |
3767 | int mmr_pnode; | |
3768 | ||
1cbac972 CG |
3769 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3770 | ||
4173a0e7 DN |
3771 | mmr_value = 0; |
3772 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
4173a0e7 DN |
3773 | entry->mask = 1; |
3774 | ||
3775 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3776 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3777 | } | |
3778 | #endif /* CONFIG_X86_64 */ | |
3779 | ||
9d6a4d08 YL |
3780 | int __init io_apic_get_redir_entries (int ioapic) |
3781 | { | |
3782 | union IO_APIC_reg_01 reg_01; | |
3783 | unsigned long flags; | |
3784 | ||
3785 | spin_lock_irqsave(&ioapic_lock, flags); | |
3786 | reg_01.raw = io_apic_read(ioapic, 1); | |
3787 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3788 | ||
3789 | return reg_01.bits.entries; | |
3790 | } | |
3791 | ||
be5d5350 | 3792 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3793 | { |
be5d5350 YL |
3794 | int nr = 0; |
3795 | ||
cc6c5006 YL |
3796 | nr = acpi_probe_gsi(); |
3797 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3798 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3799 | } else { |
3800 | /* for acpi=off or acpi is not compiled in */ | |
3801 | int idx; | |
3802 | ||
3803 | nr = 0; | |
3804 | for (idx = 0; idx < nr_ioapics; idx++) | |
3805 | nr += io_apic_get_redir_entries(idx) + 1; | |
3806 | ||
3807 | if (nr > nr_irqs_gsi) | |
3808 | nr_irqs_gsi = nr; | |
3809 | } | |
3810 | ||
3811 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3812 | } |
3813 | ||
4a046d17 YL |
3814 | #ifdef CONFIG_SPARSE_IRQ |
3815 | int __init arch_probe_nr_irqs(void) | |
3816 | { | |
3817 | int nr; | |
3818 | ||
f1ee5548 YL |
3819 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3820 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3821 | |
f1ee5548 YL |
3822 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3823 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3824 | /* | |
3825 | * for MSI and HT dyn irq | |
3826 | */ | |
3827 | nr += nr_irqs_gsi * 16; | |
3828 | #endif | |
3829 | if (nr < nr_irqs) | |
4a046d17 YL |
3830 | nr_irqs = nr; |
3831 | ||
3832 | return 0; | |
3833 | } | |
3834 | #endif | |
3835 | ||
e5198075 YL |
3836 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3837 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3838 | { |
3839 | struct irq_desc *desc; | |
3840 | struct irq_cfg *cfg; | |
3841 | int node; | |
e5198075 YL |
3842 | int ioapic, pin; |
3843 | int trigger, polarity; | |
5ef21837 | 3844 | |
e5198075 | 3845 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3846 | if (!IO_APIC_IRQ(irq)) { |
3847 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3848 | ioapic); | |
3849 | return -EINVAL; | |
3850 | } | |
3851 | ||
3852 | if (dev) | |
3853 | node = dev_to_node(dev); | |
3854 | else | |
3855 | node = cpu_to_node(boot_cpu_id); | |
3856 | ||
3857 | desc = irq_to_desc_alloc_node(irq, node); | |
3858 | if (!desc) { | |
3859 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3860 | return 0; | |
3861 | } | |
3862 | ||
e5198075 YL |
3863 | pin = irq_attr->ioapic_pin; |
3864 | trigger = irq_attr->trigger; | |
3865 | polarity = irq_attr->polarity; | |
3866 | ||
5ef21837 YL |
3867 | /* |
3868 | * IRQs < 16 are already in the irq_2_pin[] map | |
3869 | */ | |
bc07844a | 3870 | if (irq >= nr_legacy_irqs) { |
5ef21837 | 3871 | cfg = desc->chip_data; |
f3d1915a CG |
3872 | if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { |
3873 | printk(KERN_INFO "can not add pin %d for irq %d\n", | |
3874 | pin, irq); | |
3875 | return 0; | |
3876 | } | |
5ef21837 YL |
3877 | } |
3878 | ||
e5198075 | 3879 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3880 | |
3881 | return 0; | |
3882 | } | |
3883 | ||
e5198075 YL |
3884 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3885 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3886 | { |
e5198075 | 3887 | int ioapic, pin; |
5ef21837 YL |
3888 | /* |
3889 | * Avoid pin reprogramming. PRTs typically include entries | |
3890 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3891 | * we only program the IOAPIC on the first. | |
3892 | */ | |
e5198075 YL |
3893 | ioapic = irq_attr->ioapic; |
3894 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3895 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3896 | pr_debug("Pin %d-%d already programmed\n", | |
3897 | mp_ioapics[ioapic].apicid, pin); | |
3898 | return 0; | |
3899 | } | |
3900 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3901 | ||
e5198075 | 3902 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3903 | } |
3904 | ||
2a4ab640 FT |
3905 | u8 __init io_apic_unique_id(u8 id) |
3906 | { | |
3907 | #ifdef CONFIG_X86_32 | |
3908 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3909 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3910 | return io_apic_get_unique_id(nr_ioapics, id); | |
3911 | else | |
3912 | return id; | |
3913 | #else | |
3914 | int i; | |
3915 | DECLARE_BITMAP(used, 256); | |
1da177e4 | 3916 | |
2a4ab640 FT |
3917 | bitmap_zero(used, 256); |
3918 | for (i = 0; i < nr_ioapics; i++) { | |
3919 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3920 | __set_bit(ia->apicid, used); | |
3921 | } | |
3922 | if (!test_bit(id, used)) | |
3923 | return id; | |
3924 | return find_first_zero_bit(used, 256); | |
3925 | #endif | |
3926 | } | |
1da177e4 | 3927 | |
54168ed7 | 3928 | #ifdef CONFIG_X86_32 |
36062448 | 3929 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3930 | { |
3931 | union IO_APIC_reg_00 reg_00; | |
3932 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3933 | physid_mask_t tmp; | |
3934 | unsigned long flags; | |
3935 | int i = 0; | |
3936 | ||
3937 | /* | |
36062448 PC |
3938 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3939 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3940 | * supports up to 16 on one shared APIC bus. |
36062448 | 3941 | * |
1da177e4 LT |
3942 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3943 | * advantage of new APIC bus architecture. | |
3944 | */ | |
3945 | ||
3946 | if (physids_empty(apic_id_map)) | |
d190cb87 | 3947 | apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
3948 | |
3949 | spin_lock_irqsave(&ioapic_lock, flags); | |
3950 | reg_00.raw = io_apic_read(ioapic, 0); | |
3951 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3952 | ||
3953 | if (apic_id >= get_physical_broadcast()) { | |
3954 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3955 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3956 | apic_id = reg_00.bits.ID; | |
3957 | } | |
3958 | ||
3959 | /* | |
36062448 | 3960 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3961 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3962 | */ | |
d1d7cae8 | 3963 | if (apic->check_apicid_used(apic_id_map, apic_id)) { |
1da177e4 LT |
3964 | |
3965 | for (i = 0; i < get_physical_broadcast(); i++) { | |
d1d7cae8 | 3966 | if (!apic->check_apicid_used(apic_id_map, i)) |
1da177e4 LT |
3967 | break; |
3968 | } | |
3969 | ||
3970 | if (i == get_physical_broadcast()) | |
3971 | panic("Max apic_id exceeded!\n"); | |
3972 | ||
3973 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3974 | "trying %d\n", ioapic, apic_id, i); | |
3975 | ||
3976 | apic_id = i; | |
36062448 | 3977 | } |
1da177e4 | 3978 | |
8058714a | 3979 | tmp = apic->apicid_to_cpu_present(apic_id); |
1da177e4 LT |
3980 | physids_or(apic_id_map, apic_id_map, tmp); |
3981 | ||
3982 | if (reg_00.bits.ID != apic_id) { | |
3983 | reg_00.bits.ID = apic_id; | |
3984 | ||
3985 | spin_lock_irqsave(&ioapic_lock, flags); | |
3986 | io_apic_write(ioapic, 0, reg_00.raw); | |
3987 | reg_00.raw = io_apic_read(ioapic, 0); | |
3988 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3989 | ||
3990 | /* Sanity check */ | |
6070f9ec AD |
3991 | if (reg_00.bits.ID != apic_id) { |
3992 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3993 | return -1; | |
3994 | } | |
1da177e4 LT |
3995 | } |
3996 | ||
3997 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3998 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3999 | ||
4000 | return apic_id; | |
4001 | } | |
58f892e0 | 4002 | #endif |
1da177e4 | 4003 | |
36062448 | 4004 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
4005 | { |
4006 | union IO_APIC_reg_01 reg_01; | |
4007 | unsigned long flags; | |
4008 | ||
4009 | spin_lock_irqsave(&ioapic_lock, flags); | |
4010 | reg_01.raw = io_apic_read(ioapic, 1); | |
4011 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4012 | ||
4013 | return reg_01.bits.version; | |
4014 | } | |
4015 | ||
61fd47e0 SL |
4016 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
4017 | { | |
4018 | int i; | |
4019 | ||
4020 | if (skip_ioapic_setup) | |
4021 | return -1; | |
4022 | ||
4023 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
4024 | if (mp_irqs[i].irqtype == mp_INT && |
4025 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
4026 | break; |
4027 | if (i >= mp_irq_entries) | |
4028 | return -1; | |
4029 | ||
4030 | *trigger = irq_trigger(i); | |
4031 | *polarity = irq_polarity(i); | |
4032 | return 0; | |
4033 | } | |
4034 | ||
497c9a19 YL |
4035 | /* |
4036 | * This function currently is only a helper for the i386 smp boot process where | |
4037 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4038 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4039 | */ |
4040 | #ifdef CONFIG_SMP | |
4041 | void __init setup_ioapic_dest(void) | |
4042 | { | |
b9c61b70 | 4043 | int pin, ioapic = 0, irq, irq_entry; |
6c2e9403 | 4044 | struct irq_desc *desc; |
22f65d31 | 4045 | const struct cpumask *mask; |
497c9a19 YL |
4046 | |
4047 | if (skip_ioapic_setup == 1) | |
4048 | return; | |
4049 | ||
b9c61b70 YL |
4050 | #ifdef CONFIG_ACPI |
4051 | if (!acpi_disabled && acpi_ioapic) { | |
4052 | ioapic = mp_find_ioapic(0); | |
4053 | if (ioapic < 0) | |
4054 | ioapic = 0; | |
4055 | } | |
4056 | #endif | |
6c2e9403 | 4057 | |
b9c61b70 YL |
4058 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4059 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4060 | if (irq_entry == -1) | |
4061 | continue; | |
4062 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4063 | |
b9c61b70 | 4064 | desc = irq_to_desc(irq); |
6c2e9403 | 4065 | |
b9c61b70 YL |
4066 | /* |
4067 | * Honour affinities which have been set in early boot | |
4068 | */ | |
4069 | if (desc->status & | |
4070 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4071 | mask = desc->affinity; | |
4072 | else | |
4073 | mask = apic->target_cpus(); | |
497c9a19 | 4074 | |
b9c61b70 YL |
4075 | if (intr_remapping_enabled) |
4076 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4077 | else | |
4078 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4079 | } |
b9c61b70 | 4080 | |
497c9a19 YL |
4081 | } |
4082 | #endif | |
4083 | ||
54168ed7 IM |
4084 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4085 | ||
4086 | static struct resource *ioapic_resources; | |
4087 | ||
ffc43836 | 4088 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
4089 | { |
4090 | unsigned long n; | |
4091 | struct resource *res; | |
4092 | char *mem; | |
4093 | int i; | |
4094 | ||
4095 | if (nr_ioapics <= 0) | |
4096 | return NULL; | |
4097 | ||
4098 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4099 | n *= nr_ioapics; | |
4100 | ||
4101 | mem = alloc_bootmem(n); | |
4102 | res = (void *)mem; | |
4103 | ||
ffc43836 | 4104 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 4105 | |
ffc43836 CG |
4106 | for (i = 0; i < nr_ioapics; i++) { |
4107 | res[i].name = mem; | |
4108 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4109 | sprintf(mem, "IOAPIC %u", i); | |
4110 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
54168ed7 IM |
4111 | } |
4112 | ||
4113 | ioapic_resources = res; | |
4114 | ||
4115 | return res; | |
4116 | } | |
54168ed7 | 4117 | |
f3294a33 YL |
4118 | void __init ioapic_init_mappings(void) |
4119 | { | |
4120 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4121 | struct resource *ioapic_res; |
d6c88a50 | 4122 | int i; |
f3294a33 | 4123 | |
ffc43836 | 4124 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
4125 | for (i = 0; i < nr_ioapics; i++) { |
4126 | if (smp_found_config) { | |
b5ba7e6d | 4127 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4128 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4129 | if (!ioapic_phys) { |
4130 | printk(KERN_ERR | |
4131 | "WARNING: bogus zero IO-APIC " | |
4132 | "address found in MPTABLE, " | |
4133 | "disabling IO/APIC support!\n"); | |
4134 | smp_found_config = 0; | |
4135 | skip_ioapic_setup = 1; | |
4136 | goto fake_ioapic_page; | |
4137 | } | |
54168ed7 | 4138 | #endif |
f3294a33 | 4139 | } else { |
54168ed7 | 4140 | #ifdef CONFIG_X86_32 |
f3294a33 | 4141 | fake_ioapic_page: |
54168ed7 | 4142 | #endif |
f3294a33 | 4143 | ioapic_phys = (unsigned long) |
54168ed7 | 4144 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4145 | ioapic_phys = __pa(ioapic_phys); |
4146 | } | |
4147 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4148 | apic_printk(APIC_VERBOSE, |
4149 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4150 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4151 | idx++; |
54168ed7 | 4152 | |
ffc43836 CG |
4153 | ioapic_res->start = ioapic_phys; |
4154 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4155 | ioapic_res++; | |
f3294a33 YL |
4156 | } |
4157 | } | |
4158 | ||
857fdc53 | 4159 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
4160 | { |
4161 | int i; | |
4162 | struct resource *r = ioapic_resources; | |
4163 | ||
4164 | if (!r) { | |
857fdc53 | 4165 | if (nr_ioapics > 0) |
04c93ce4 BZ |
4166 | printk(KERN_ERR |
4167 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 4168 | return; |
54168ed7 IM |
4169 | } |
4170 | ||
4171 | for (i = 0; i < nr_ioapics; i++) { | |
4172 | insert_resource(&iomem_resource, r); | |
4173 | r++; | |
4174 | } | |
54168ed7 | 4175 | } |
2a4ab640 FT |
4176 | |
4177 | int mp_find_ioapic(int gsi) | |
4178 | { | |
4179 | int i = 0; | |
4180 | ||
4181 | /* Find the IOAPIC that manages this GSI. */ | |
4182 | for (i = 0; i < nr_ioapics; i++) { | |
4183 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
4184 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
4185 | return i; | |
4186 | } | |
54168ed7 | 4187 | |
2a4ab640 FT |
4188 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
4189 | return -1; | |
4190 | } | |
4191 | ||
4192 | int mp_find_ioapic_pin(int ioapic, int gsi) | |
4193 | { | |
4194 | if (WARN_ON(ioapic == -1)) | |
4195 | return -1; | |
4196 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
4197 | return -1; | |
4198 | ||
4199 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
4200 | } | |
4201 | ||
4202 | static int bad_ioapic(unsigned long address) | |
4203 | { | |
4204 | if (nr_ioapics >= MAX_IO_APICS) { | |
4205 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
4206 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
4207 | return 1; | |
4208 | } | |
4209 | if (!address) { | |
4210 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
4211 | " found in table, skipping!\n"); | |
4212 | return 1; | |
4213 | } | |
54168ed7 IM |
4214 | return 0; |
4215 | } | |
4216 | ||
2a4ab640 FT |
4217 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4218 | { | |
4219 | int idx = 0; | |
4220 | ||
4221 | if (bad_ioapic(address)) | |
4222 | return; | |
4223 | ||
4224 | idx = nr_ioapics; | |
4225 | ||
4226 | mp_ioapics[idx].type = MP_IOAPIC; | |
4227 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4228 | mp_ioapics[idx].apicaddr = address; | |
4229 | ||
4230 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4231 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4232 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4233 | ||
4234 | /* | |
4235 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4236 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4237 | */ | |
4238 | mp_gsi_routing[idx].gsi_base = gsi_base; | |
4239 | mp_gsi_routing[idx].gsi_end = gsi_base + | |
4240 | io_apic_get_redir_entries(idx); | |
4241 | ||
4242 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4243 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4244 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4245 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4246 | ||
4247 | nr_ioapics++; | |
4248 | } |