Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
1da177e4 | 63 | |
7b6aa335 | 64 | #include <asm/apic.h> |
1da177e4 | 65 | |
32f71aff | 66 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
67 | #define for_each_irq_pin(entry, head) \ |
68 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 69 | |
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
dade7716 TG |
76 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
77 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 78 | |
1da177e4 LT |
79 | /* |
80 | * # of IRQ routing registers | |
81 | */ | |
82 | int nr_ioapic_registers[MAX_IO_APICS]; | |
83 | ||
9f640ccb | 84 | /* I/O APIC entries */ |
b5ba7e6d | 85 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
86 | int nr_ioapics; |
87 | ||
2a4ab640 FT |
88 | /* IO APIC gsi routing info */ |
89 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
90 | ||
a4384df3 EB |
91 | /* The one past the highest gsi number used */ |
92 | u32 gsi_top; | |
5777372a | 93 | |
584f734d | 94 | /* MP IRQ source entries */ |
c2c21745 | 95 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
96 | |
97 | /* # of MP IRQ source entries */ | |
98 | int mp_irq_entries; | |
99 | ||
bc07844a TG |
100 | /* GSI interrupts */ |
101 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
102 | ||
8732fc4b AS |
103 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
104 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
105 | #endif | |
106 | ||
107 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
108 | ||
efa2559f YL |
109 | int skip_ioapic_setup; |
110 | ||
65a4e574 IM |
111 | void arch_disable_smp_support(void) |
112 | { | |
113 | #ifdef CONFIG_PCI | |
114 | noioapicquirk = 1; | |
115 | noioapicreroute = -1; | |
116 | #endif | |
117 | skip_ioapic_setup = 1; | |
118 | } | |
119 | ||
54168ed7 | 120 | static int __init parse_noapic(char *str) |
efa2559f YL |
121 | { |
122 | /* disable IO-APIC */ | |
65a4e574 | 123 | arch_disable_smp_support(); |
efa2559f YL |
124 | return 0; |
125 | } | |
126 | early_param("noapic", parse_noapic); | |
66759a01 | 127 | |
2d8009ba FT |
128 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
129 | void mp_save_irq(struct mpc_intsrc *m) | |
130 | { | |
131 | int i; | |
132 | ||
133 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
134 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
135 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
136 | m->srcbusirq, m->dstapic, m->dstirq); | |
137 | ||
138 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 139 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
140 | return; |
141 | } | |
142 | ||
0e3fa13f | 143 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
144 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
145 | panic("Max # of irq sources exceeded!!\n"); | |
146 | } | |
147 | ||
0b8f1efa YL |
148 | struct irq_pin_list { |
149 | int apic, pin; | |
150 | struct irq_pin_list *next; | |
151 | }; | |
152 | ||
7e495529 | 153 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 154 | { |
2ee39065 | 155 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
0b8f1efa YL |
156 | } |
157 | ||
2d8009ba | 158 | |
a1420f39 | 159 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa | 160 | #ifdef CONFIG_SPARSE_IRQ |
97943390 | 161 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
0b8f1efa | 162 | #else |
97943390 | 163 | static struct irq_cfg irq_cfgx[NR_IRQS]; |
0b8f1efa | 164 | #endif |
a1420f39 | 165 | |
13a0c3c2 | 166 | int __init arch_early_irq_init(void) |
8f09cd20 | 167 | { |
0b8f1efa | 168 | struct irq_cfg *cfg; |
60c69948 | 169 | int count, node, i; |
d6c88a50 | 170 | |
1f91233c JP |
171 | if (!legacy_pic->nr_legacy_irqs) { |
172 | nr_irqs_gsi = 0; | |
173 | io_apic_irqs = ~0UL; | |
174 | } | |
175 | ||
0b8f1efa YL |
176 | cfg = irq_cfgx; |
177 | count = ARRAY_SIZE(irq_cfgx); | |
f6e9456c | 178 | node = cpu_to_node(0); |
8f09cd20 | 179 | |
fbc6bff0 TG |
180 | /* Make sure the legacy interrupts are marked in the bitmap */ |
181 | irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); | |
182 | ||
0b8f1efa | 183 | for (i = 0; i < count; i++) { |
60c69948 | 184 | set_irq_chip_data(i, &cfg[i]); |
2ee39065 TG |
185 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); |
186 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); | |
97943390 SS |
187 | /* |
188 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
189 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
190 | */ | |
54b56170 | 191 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
192 | cfg[i].vector = IRQ0_VECTOR + i; |
193 | cpumask_set_cpu(0, cfg[i].domain); | |
194 | } | |
0b8f1efa | 195 | } |
13a0c3c2 YL |
196 | |
197 | return 0; | |
0b8f1efa | 198 | } |
8f09cd20 | 199 | |
0b8f1efa | 200 | #ifdef CONFIG_SPARSE_IRQ |
48b26501 | 201 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 202 | { |
60c69948 | 203 | return get_irq_chip_data(irq); |
8f09cd20 | 204 | } |
d6c88a50 | 205 | |
f981a3dc | 206 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
8f09cd20 | 207 | { |
0b8f1efa | 208 | struct irq_cfg *cfg; |
0f978f45 | 209 | |
2ee39065 | 210 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); |
6e2fff50 TG |
211 | if (!cfg) |
212 | return NULL; | |
2ee39065 | 213 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) |
6e2fff50 | 214 | goto out_cfg; |
2ee39065 | 215 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) |
6e2fff50 | 216 | goto out_domain; |
0b8f1efa | 217 | return cfg; |
6e2fff50 TG |
218 | out_domain: |
219 | free_cpumask_var(cfg->domain); | |
220 | out_cfg: | |
221 | kfree(cfg); | |
222 | return NULL; | |
8f09cd20 YL |
223 | } |
224 | ||
f981a3dc | 225 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) |
08c33db6 | 226 | { |
fbc6bff0 TG |
227 | if (!cfg) |
228 | return; | |
229 | set_irq_chip_data(at, NULL); | |
08c33db6 TG |
230 | free_cpumask_var(cfg->domain); |
231 | free_cpumask_var(cfg->old_domain); | |
232 | kfree(cfg); | |
233 | } | |
234 | ||
0b8f1efa | 235 | #else |
08c33db6 | 236 | |
9338ad6f | 237 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
238 | { |
239 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 240 | } |
1da177e4 | 241 | |
f981a3dc | 242 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
08c33db6 TG |
243 | { |
244 | return irq_cfgx + irq; | |
245 | } | |
246 | ||
f981a3dc | 247 | static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { } |
08c33db6 | 248 | |
0b8f1efa YL |
249 | #endif |
250 | ||
08c33db6 TG |
251 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) |
252 | { | |
253 | int res = irq_alloc_desc_at(at, node); | |
254 | struct irq_cfg *cfg; | |
255 | ||
256 | if (res < 0) { | |
257 | if (res != -EEXIST) | |
258 | return NULL; | |
259 | cfg = get_irq_chip_data(at); | |
260 | if (cfg) | |
261 | return cfg; | |
262 | } | |
263 | ||
f981a3dc | 264 | cfg = alloc_irq_cfg(at, node); |
08c33db6 TG |
265 | if (cfg) |
266 | set_irq_chip_data(at, cfg); | |
267 | else | |
268 | irq_free_desc(at); | |
269 | return cfg; | |
270 | } | |
271 | ||
272 | static int alloc_irq_from(unsigned int from, int node) | |
273 | { | |
274 | return irq_alloc_desc_from(from, node); | |
275 | } | |
276 | ||
277 | static void free_irq_at(unsigned int at, struct irq_cfg *cfg) | |
278 | { | |
f981a3dc | 279 | free_irq_cfg(at, cfg); |
08c33db6 TG |
280 | irq_free_desc(at); |
281 | } | |
282 | ||
130fe05d LT |
283 | struct io_apic { |
284 | unsigned int index; | |
285 | unsigned int unused[3]; | |
286 | unsigned int data; | |
0280f7c4 SS |
287 | unsigned int unused2[11]; |
288 | unsigned int eoi; | |
130fe05d LT |
289 | }; |
290 | ||
291 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
292 | { | |
293 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 294 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
295 | } |
296 | ||
0280f7c4 SS |
297 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
298 | { | |
299 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
300 | writel(vector, &io_apic->eoi); | |
301 | } | |
302 | ||
130fe05d LT |
303 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
304 | { | |
305 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
306 | writel(reg, &io_apic->index); | |
307 | return readl(&io_apic->data); | |
308 | } | |
309 | ||
310 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
311 | { | |
312 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
313 | writel(reg, &io_apic->index); | |
314 | writel(value, &io_apic->data); | |
315 | } | |
316 | ||
317 | /* | |
318 | * Re-write a value: to be used for read-modify-write | |
319 | * cycles where the read already set up the index register. | |
320 | * | |
321 | * Older SiS APIC requires we rewrite the index register | |
322 | */ | |
323 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
324 | { | |
54168ed7 | 325 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
326 | |
327 | if (sis_apic_bug) | |
328 | writel(reg, &io_apic->index); | |
130fe05d LT |
329 | writel(value, &io_apic->data); |
330 | } | |
331 | ||
3145e941 | 332 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
333 | { |
334 | struct irq_pin_list *entry; | |
335 | unsigned long flags; | |
047c8fdb | 336 | |
dade7716 | 337 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 338 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
339 | unsigned int reg; |
340 | int pin; | |
341 | ||
047c8fdb YL |
342 | pin = entry->pin; |
343 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
344 | /* Is the remote IRR bit set? */ | |
345 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 346 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
347 | return true; |
348 | } | |
047c8fdb | 349 | } |
dade7716 | 350 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
351 | |
352 | return false; | |
353 | } | |
047c8fdb | 354 | |
cf4c6a2f AK |
355 | union entry_union { |
356 | struct { u32 w1, w2; }; | |
357 | struct IO_APIC_route_entry entry; | |
358 | }; | |
359 | ||
360 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
361 | { | |
362 | union entry_union eu; | |
363 | unsigned long flags; | |
dade7716 | 364 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
365 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
366 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
dade7716 | 367 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
368 | return eu.entry; |
369 | } | |
370 | ||
f9dadfa7 LT |
371 | /* |
372 | * When we write a new IO APIC routing entry, we need to write the high | |
373 | * word first! If the mask bit in the low word is clear, we will enable | |
374 | * the interrupt, and we need to make sure the entry is fully populated | |
375 | * before that happens. | |
376 | */ | |
d15512f4 AK |
377 | static void |
378 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 379 | { |
50a8d4d2 F |
380 | union entry_union eu = {{0, 0}}; |
381 | ||
cf4c6a2f | 382 | eu.entry = e; |
f9dadfa7 LT |
383 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
384 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
385 | } |
386 | ||
1a8ce7ff | 387 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
388 | { |
389 | unsigned long flags; | |
dade7716 | 390 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 391 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 392 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
393 | } |
394 | ||
395 | /* | |
396 | * When we mask an IO APIC routing entry, we need to write the low | |
397 | * word first, in order to set the mask bit before we change the | |
398 | * high bits! | |
399 | */ | |
400 | static void ioapic_mask_entry(int apic, int pin) | |
401 | { | |
402 | unsigned long flags; | |
403 | union entry_union eu = { .entry.mask = 1 }; | |
404 | ||
dade7716 | 405 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
406 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
407 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 408 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
409 | } |
410 | ||
1da177e4 LT |
411 | /* |
412 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
413 | * shared ISA-space IRQs, so we have to support them. We are super | |
414 | * fast in the common case, and fast for shared ISA-space IRQs. | |
415 | */ | |
f3d1915a | 416 | static int |
7e495529 | 417 | __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 418 | { |
2977fb3f | 419 | struct irq_pin_list **last, *entry; |
0f978f45 | 420 | |
2977fb3f CG |
421 | /* don't allow duplicates */ |
422 | last = &cfg->irq_2_pin; | |
423 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 424 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 425 | return 0; |
2977fb3f | 426 | last = &entry->next; |
1da177e4 | 427 | } |
0f978f45 | 428 | |
7e495529 | 429 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 430 | if (!entry) { |
f3d1915a CG |
431 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
432 | node, apic, pin); | |
433 | return -ENOMEM; | |
a7428cd2 | 434 | } |
1da177e4 LT |
435 | entry->apic = apic; |
436 | entry->pin = pin; | |
875e68ec | 437 | |
2977fb3f | 438 | *last = entry; |
f3d1915a CG |
439 | return 0; |
440 | } | |
441 | ||
442 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
443 | { | |
7e495529 | 444 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 445 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
446 | } |
447 | ||
448 | /* | |
449 | * Reroute an IRQ to a different pin. | |
450 | */ | |
85ac16d0 | 451 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
452 | int oldapic, int oldpin, |
453 | int newapic, int newpin) | |
1da177e4 | 454 | { |
535b6429 | 455 | struct irq_pin_list *entry; |
1da177e4 | 456 | |
2977fb3f | 457 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
458 | if (entry->apic == oldapic && entry->pin == oldpin) { |
459 | entry->apic = newapic; | |
460 | entry->pin = newpin; | |
0f978f45 | 461 | /* every one is different, right? */ |
4eea6fff | 462 | return; |
0f978f45 | 463 | } |
1da177e4 | 464 | } |
0f978f45 | 465 | |
4eea6fff JF |
466 | /* old apic/pin didn't exist, so just add new ones */ |
467 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
468 | } |
469 | ||
c29d9db3 SS |
470 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
471 | int mask_and, int mask_or, | |
472 | void (*final)(struct irq_pin_list *entry)) | |
473 | { | |
474 | unsigned int reg, pin; | |
475 | ||
476 | pin = entry->pin; | |
477 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
478 | reg &= mask_and; | |
479 | reg |= mask_or; | |
480 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
481 | if (final) | |
482 | final(entry); | |
483 | } | |
484 | ||
2f210deb JF |
485 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
486 | int mask_and, int mask_or, | |
487 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 488 | { |
87783be4 | 489 | struct irq_pin_list *entry; |
047c8fdb | 490 | |
c29d9db3 SS |
491 | for_each_irq_pin(entry, cfg->irq_2_pin) |
492 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
493 | } | |
494 | ||
495 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
496 | { | |
497 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
498 | IO_APIC_REDIR_MASKED, NULL); | |
499 | } | |
500 | ||
501 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
502 | { | |
503 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
504 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 505 | } |
047c8fdb | 506 | |
7f3e632f | 507 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 508 | { |
87783be4 CG |
509 | /* |
510 | * Synchronize the IO-APIC and the CPU by doing | |
511 | * a dummy read from the IO-APIC | |
512 | */ | |
513 | struct io_apic __iomem *io_apic; | |
514 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 515 | readl(&io_apic->data); |
1da177e4 LT |
516 | } |
517 | ||
dd5f15e5 | 518 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 519 | { |
dd5f15e5 TG |
520 | unsigned long flags; |
521 | ||
522 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 523 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 524 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 525 | } |
1da177e4 | 526 | |
90297c5f | 527 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 528 | { |
90297c5f | 529 | mask_ioapic(data->chip_data); |
dd5f15e5 | 530 | } |
3145e941 | 531 | |
dd5f15e5 TG |
532 | static void __unmask_ioapic(struct irq_cfg *cfg) |
533 | { | |
534 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
535 | } |
536 | ||
dd5f15e5 | 537 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
538 | { |
539 | unsigned long flags; | |
540 | ||
dade7716 | 541 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 542 | __unmask_ioapic(cfg); |
dade7716 | 543 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
544 | } |
545 | ||
90297c5f | 546 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 547 | { |
90297c5f | 548 | unmask_ioapic(data->chip_data); |
3145e941 YL |
549 | } |
550 | ||
1da177e4 LT |
551 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
552 | { | |
553 | struct IO_APIC_route_entry entry; | |
36062448 | 554 | |
1da177e4 | 555 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 556 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
557 | if (entry.delivery_mode == dest_SMI) |
558 | return; | |
1da177e4 LT |
559 | /* |
560 | * Disable it in the IO-APIC irq-routing table: | |
561 | */ | |
f9dadfa7 | 562 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
563 | } |
564 | ||
54168ed7 | 565 | static void clear_IO_APIC (void) |
1da177e4 LT |
566 | { |
567 | int apic, pin; | |
568 | ||
569 | for (apic = 0; apic < nr_ioapics; apic++) | |
570 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
571 | clear_IO_APIC_pin(apic, pin); | |
572 | } | |
573 | ||
54168ed7 | 574 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
575 | /* |
576 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
577 | * specific CPU-side IRQs. | |
578 | */ | |
579 | ||
580 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
581 | static int pirq_entries[MAX_PIRQS] = { |
582 | [0 ... MAX_PIRQS - 1] = -1 | |
583 | }; | |
1da177e4 | 584 | |
1da177e4 LT |
585 | static int __init ioapic_pirq_setup(char *str) |
586 | { | |
587 | int i, max; | |
588 | int ints[MAX_PIRQS+1]; | |
589 | ||
590 | get_options(str, ARRAY_SIZE(ints), ints); | |
591 | ||
1da177e4 LT |
592 | apic_printk(APIC_VERBOSE, KERN_INFO |
593 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
594 | max = MAX_PIRQS; | |
595 | if (ints[0] < MAX_PIRQS) | |
596 | max = ints[0]; | |
597 | ||
598 | for (i = 0; i < max; i++) { | |
599 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
600 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
601 | /* | |
602 | * PIRQs are mapped upside down, usually. | |
603 | */ | |
604 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
605 | } | |
606 | return 1; | |
607 | } | |
608 | ||
609 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
610 | #endif /* CONFIG_X86_32 */ |
611 | ||
b24696bc FY |
612 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
613 | { | |
614 | int apic; | |
615 | struct IO_APIC_route_entry **ioapic_entries; | |
616 | ||
617 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
2ee39065 | 618 | GFP_KERNEL); |
b24696bc FY |
619 | if (!ioapic_entries) |
620 | return 0; | |
621 | ||
622 | for (apic = 0; apic < nr_ioapics; apic++) { | |
623 | ioapic_entries[apic] = | |
624 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
2ee39065 | 625 | nr_ioapic_registers[apic], GFP_KERNEL); |
b24696bc FY |
626 | if (!ioapic_entries[apic]) |
627 | goto nomem; | |
628 | } | |
629 | ||
630 | return ioapic_entries; | |
631 | ||
632 | nomem: | |
633 | while (--apic >= 0) | |
634 | kfree(ioapic_entries[apic]); | |
635 | kfree(ioapic_entries); | |
636 | ||
637 | return 0; | |
638 | } | |
54168ed7 IM |
639 | |
640 | /* | |
05c3dc2c | 641 | * Saves all the IO-APIC RTE's |
54168ed7 | 642 | */ |
b24696bc | 643 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 644 | { |
54168ed7 IM |
645 | int apic, pin; |
646 | ||
b24696bc FY |
647 | if (!ioapic_entries) |
648 | return -ENOMEM; | |
54168ed7 IM |
649 | |
650 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
651 | if (!ioapic_entries[apic]) |
652 | return -ENOMEM; | |
54168ed7 | 653 | |
05c3dc2c | 654 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 655 | ioapic_entries[apic][pin] = |
54168ed7 | 656 | ioapic_read_entry(apic, pin); |
b24696bc | 657 | } |
5ffa4eb2 | 658 | |
54168ed7 IM |
659 | return 0; |
660 | } | |
661 | ||
b24696bc FY |
662 | /* |
663 | * Mask all IO APIC entries. | |
664 | */ | |
665 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
666 | { |
667 | int apic, pin; | |
668 | ||
b24696bc FY |
669 | if (!ioapic_entries) |
670 | return; | |
671 | ||
05c3dc2c | 672 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 673 | if (!ioapic_entries[apic]) |
05c3dc2c | 674 | break; |
b24696bc | 675 | |
05c3dc2c SS |
676 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
677 | struct IO_APIC_route_entry entry; | |
678 | ||
b24696bc | 679 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
680 | if (!entry.mask) { |
681 | entry.mask = 1; | |
682 | ioapic_write_entry(apic, pin, entry); | |
683 | } | |
684 | } | |
685 | } | |
686 | } | |
687 | ||
b24696bc FY |
688 | /* |
689 | * Restore IO APIC entries which was saved in ioapic_entries. | |
690 | */ | |
691 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
692 | { |
693 | int apic, pin; | |
694 | ||
b24696bc FY |
695 | if (!ioapic_entries) |
696 | return -ENOMEM; | |
697 | ||
5ffa4eb2 | 698 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
699 | if (!ioapic_entries[apic]) |
700 | return -ENOMEM; | |
701 | ||
54168ed7 IM |
702 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
703 | ioapic_write_entry(apic, pin, | |
b24696bc | 704 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 705 | } |
b24696bc | 706 | return 0; |
54168ed7 IM |
707 | } |
708 | ||
b24696bc FY |
709 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
710 | { | |
711 | int apic; | |
712 | ||
713 | for (apic = 0; apic < nr_ioapics; apic++) | |
714 | kfree(ioapic_entries[apic]); | |
715 | ||
716 | kfree(ioapic_entries); | |
54168ed7 | 717 | } |
1da177e4 LT |
718 | |
719 | /* | |
720 | * Find the IRQ entry number of a certain pin. | |
721 | */ | |
722 | static int find_irq_entry(int apic, int pin, int type) | |
723 | { | |
724 | int i; | |
725 | ||
726 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
727 | if (mp_irqs[i].irqtype == type && |
728 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
729 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
730 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
731 | return i; |
732 | ||
733 | return -1; | |
734 | } | |
735 | ||
736 | /* | |
737 | * Find the pin to which IRQ[irq] (ISA) is connected | |
738 | */ | |
fcfd636a | 739 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
740 | { |
741 | int i; | |
742 | ||
743 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 744 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 745 | |
d27e2b8e | 746 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
747 | (mp_irqs[i].irqtype == type) && |
748 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 749 | |
c2c21745 | 750 | return mp_irqs[i].dstirq; |
1da177e4 LT |
751 | } |
752 | return -1; | |
753 | } | |
754 | ||
fcfd636a EB |
755 | static int __init find_isa_irq_apic(int irq, int type) |
756 | { | |
757 | int i; | |
758 | ||
759 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 760 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 761 | |
73b2961b | 762 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
763 | (mp_irqs[i].irqtype == type) && |
764 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
765 | break; |
766 | } | |
767 | if (i < mp_irq_entries) { | |
768 | int apic; | |
54168ed7 | 769 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 770 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
771 | return apic; |
772 | } | |
773 | } | |
774 | ||
775 | return -1; | |
776 | } | |
777 | ||
c0a282c2 | 778 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
779 | /* |
780 | * EISA Edge/Level control register, ELCR | |
781 | */ | |
782 | static int EISA_ELCR(unsigned int irq) | |
783 | { | |
b81bb373 | 784 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
785 | unsigned int port = 0x4d0 + (irq >> 3); |
786 | return (inb(port) >> (irq & 7)) & 1; | |
787 | } | |
788 | apic_printk(APIC_VERBOSE, KERN_INFO | |
789 | "Broken MPtable reports ISA irq %d\n", irq); | |
790 | return 0; | |
791 | } | |
54168ed7 | 792 | |
c0a282c2 | 793 | #endif |
1da177e4 | 794 | |
6728801d AS |
795 | /* ISA interrupts are always polarity zero edge triggered, |
796 | * when listed as conforming in the MP table. */ | |
797 | ||
798 | #define default_ISA_trigger(idx) (0) | |
799 | #define default_ISA_polarity(idx) (0) | |
800 | ||
1da177e4 LT |
801 | /* EISA interrupts are always polarity zero and can be edge or level |
802 | * trigger depending on the ELCR value. If an interrupt is listed as | |
803 | * EISA conforming in the MP table, that means its trigger type must | |
804 | * be read in from the ELCR */ | |
805 | ||
c2c21745 | 806 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 807 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
808 | |
809 | /* PCI interrupts are always polarity one level triggered, | |
810 | * when listed as conforming in the MP table. */ | |
811 | ||
812 | #define default_PCI_trigger(idx) (1) | |
813 | #define default_PCI_polarity(idx) (1) | |
814 | ||
815 | /* MCA interrupts are always polarity zero level triggered, | |
816 | * when listed as conforming in the MP table. */ | |
817 | ||
818 | #define default_MCA_trigger(idx) (1) | |
6728801d | 819 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 820 | |
61fd47e0 | 821 | static int MPBIOS_polarity(int idx) |
1da177e4 | 822 | { |
c2c21745 | 823 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
824 | int polarity; |
825 | ||
826 | /* | |
827 | * Determine IRQ line polarity (high active or low active): | |
828 | */ | |
c2c21745 | 829 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 830 | { |
54168ed7 IM |
831 | case 0: /* conforms, ie. bus-type dependent polarity */ |
832 | if (test_bit(bus, mp_bus_not_pci)) | |
833 | polarity = default_ISA_polarity(idx); | |
834 | else | |
835 | polarity = default_PCI_polarity(idx); | |
836 | break; | |
837 | case 1: /* high active */ | |
838 | { | |
839 | polarity = 0; | |
840 | break; | |
841 | } | |
842 | case 2: /* reserved */ | |
843 | { | |
844 | printk(KERN_WARNING "broken BIOS!!\n"); | |
845 | polarity = 1; | |
846 | break; | |
847 | } | |
848 | case 3: /* low active */ | |
849 | { | |
850 | polarity = 1; | |
851 | break; | |
852 | } | |
853 | default: /* invalid */ | |
854 | { | |
855 | printk(KERN_WARNING "broken BIOS!!\n"); | |
856 | polarity = 1; | |
857 | break; | |
858 | } | |
1da177e4 LT |
859 | } |
860 | return polarity; | |
861 | } | |
862 | ||
863 | static int MPBIOS_trigger(int idx) | |
864 | { | |
c2c21745 | 865 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
866 | int trigger; |
867 | ||
868 | /* | |
869 | * Determine IRQ trigger mode (edge or level sensitive): | |
870 | */ | |
c2c21745 | 871 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 872 | { |
54168ed7 IM |
873 | case 0: /* conforms, ie. bus-type dependent */ |
874 | if (test_bit(bus, mp_bus_not_pci)) | |
875 | trigger = default_ISA_trigger(idx); | |
876 | else | |
877 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 878 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
879 | switch (mp_bus_id_to_type[bus]) { |
880 | case MP_BUS_ISA: /* ISA pin */ | |
881 | { | |
882 | /* set before the switch */ | |
883 | break; | |
884 | } | |
885 | case MP_BUS_EISA: /* EISA pin */ | |
886 | { | |
887 | trigger = default_EISA_trigger(idx); | |
888 | break; | |
889 | } | |
890 | case MP_BUS_PCI: /* PCI pin */ | |
891 | { | |
892 | /* set before the switch */ | |
893 | break; | |
894 | } | |
895 | case MP_BUS_MCA: /* MCA pin */ | |
896 | { | |
897 | trigger = default_MCA_trigger(idx); | |
898 | break; | |
899 | } | |
900 | default: | |
901 | { | |
902 | printk(KERN_WARNING "broken BIOS!!\n"); | |
903 | trigger = 1; | |
904 | break; | |
905 | } | |
906 | } | |
907 | #endif | |
1da177e4 | 908 | break; |
54168ed7 | 909 | case 1: /* edge */ |
1da177e4 | 910 | { |
54168ed7 | 911 | trigger = 0; |
1da177e4 LT |
912 | break; |
913 | } | |
54168ed7 | 914 | case 2: /* reserved */ |
1da177e4 | 915 | { |
54168ed7 IM |
916 | printk(KERN_WARNING "broken BIOS!!\n"); |
917 | trigger = 1; | |
1da177e4 LT |
918 | break; |
919 | } | |
54168ed7 | 920 | case 3: /* level */ |
1da177e4 | 921 | { |
54168ed7 | 922 | trigger = 1; |
1da177e4 LT |
923 | break; |
924 | } | |
54168ed7 | 925 | default: /* invalid */ |
1da177e4 LT |
926 | { |
927 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 928 | trigger = 0; |
1da177e4 LT |
929 | break; |
930 | } | |
931 | } | |
932 | return trigger; | |
933 | } | |
934 | ||
935 | static inline int irq_polarity(int idx) | |
936 | { | |
937 | return MPBIOS_polarity(idx); | |
938 | } | |
939 | ||
940 | static inline int irq_trigger(int idx) | |
941 | { | |
942 | return MPBIOS_trigger(idx); | |
943 | } | |
944 | ||
945 | static int pin_2_irq(int idx, int apic, int pin) | |
946 | { | |
d464207c | 947 | int irq; |
c2c21745 | 948 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
949 | |
950 | /* | |
951 | * Debugging check, we are in big trouble if this message pops up! | |
952 | */ | |
c2c21745 | 953 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
954 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
955 | ||
54168ed7 | 956 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 957 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 958 | } else { |
d464207c | 959 | u32 gsi = mp_gsi_routing[apic].gsi_base + pin; |
988856ee EB |
960 | |
961 | if (gsi >= NR_IRQS_LEGACY) | |
962 | irq = gsi; | |
963 | else | |
a4384df3 | 964 | irq = gsi_top + gsi; |
1da177e4 LT |
965 | } |
966 | ||
54168ed7 | 967 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
968 | /* |
969 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
970 | */ | |
971 | if ((pin >= 16) && (pin <= 23)) { | |
972 | if (pirq_entries[pin-16] != -1) { | |
973 | if (!pirq_entries[pin-16]) { | |
974 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
975 | "disabling PIRQ%d\n", pin-16); | |
976 | } else { | |
977 | irq = pirq_entries[pin-16]; | |
978 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
979 | "using PIRQ%d -> IRQ %d\n", | |
980 | pin-16, irq); | |
981 | } | |
982 | } | |
983 | } | |
54168ed7 IM |
984 | #endif |
985 | ||
1da177e4 LT |
986 | return irq; |
987 | } | |
988 | ||
e20c06fd YL |
989 | /* |
990 | * Find a specific PCI IRQ entry. | |
991 | * Not an __init, possibly needed by modules | |
992 | */ | |
993 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 994 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
995 | { |
996 | int apic, i, best_guess = -1; | |
997 | ||
998 | apic_printk(APIC_DEBUG, | |
999 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1000 | bus, slot, pin); | |
1001 | if (test_bit(bus, mp_bus_not_pci)) { | |
1002 | apic_printk(APIC_VERBOSE, | |
1003 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1004 | return -1; | |
1005 | } | |
1006 | for (i = 0; i < mp_irq_entries; i++) { | |
1007 | int lbus = mp_irqs[i].srcbus; | |
1008 | ||
1009 | for (apic = 0; apic < nr_ioapics; apic++) | |
1010 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1011 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1012 | break; | |
1013 | ||
1014 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1015 | !mp_irqs[i].irqtype && | |
1016 | (bus == lbus) && | |
1017 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1018 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1019 | ||
1020 | if (!(apic || IO_APIC_IRQ(irq))) | |
1021 | continue; | |
1022 | ||
1023 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1024 | set_io_apic_irq_attr(irq_attr, apic, |
1025 | mp_irqs[i].dstirq, | |
1026 | irq_trigger(i), | |
1027 | irq_polarity(i)); | |
e20c06fd YL |
1028 | return irq; |
1029 | } | |
1030 | /* | |
1031 | * Use the first all-but-pin matching entry as a | |
1032 | * best-guess fuzzy result for broken mptables. | |
1033 | */ | |
1034 | if (best_guess < 0) { | |
e5198075 YL |
1035 | set_io_apic_irq_attr(irq_attr, apic, |
1036 | mp_irqs[i].dstirq, | |
1037 | irq_trigger(i), | |
1038 | irq_polarity(i)); | |
e20c06fd YL |
1039 | best_guess = irq; |
1040 | } | |
1041 | } | |
1042 | } | |
1043 | return best_guess; | |
1044 | } | |
1045 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1046 | ||
497c9a19 YL |
1047 | void lock_vector_lock(void) |
1048 | { | |
1049 | /* Used to the online set of cpus does not change | |
1050 | * during assign_irq_vector. | |
1051 | */ | |
dade7716 | 1052 | raw_spin_lock(&vector_lock); |
497c9a19 | 1053 | } |
1da177e4 | 1054 | |
497c9a19 | 1055 | void unlock_vector_lock(void) |
1da177e4 | 1056 | { |
dade7716 | 1057 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1058 | } |
1da177e4 | 1059 | |
e7986739 MT |
1060 | static int |
1061 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1062 | { |
047c8fdb YL |
1063 | /* |
1064 | * NOTE! The local APIC isn't very good at handling | |
1065 | * multiple interrupts at the same interrupt level. | |
1066 | * As the interrupt level is determined by taking the | |
1067 | * vector number and shifting that right by 4, we | |
1068 | * want to spread these out a bit so that they don't | |
1069 | * all fall in the same interrupt level. | |
1070 | * | |
1071 | * Also, we've got to be careful not to trash gate | |
1072 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1073 | */ | |
6579b474 | 1074 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1075 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1076 | unsigned int old_vector; |
22f65d31 MT |
1077 | int cpu, err; |
1078 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1079 | |
23359a88 | 1080 | if (cfg->move_in_progress) |
54168ed7 | 1081 | return -EBUSY; |
0a1ad60d | 1082 | |
22f65d31 MT |
1083 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1084 | return -ENOMEM; | |
ace80ab7 | 1085 | |
54168ed7 IM |
1086 | old_vector = cfg->vector; |
1087 | if (old_vector) { | |
22f65d31 MT |
1088 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1089 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1090 | if (!cpumask_empty(tmp_mask)) { | |
1091 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1092 | return 0; |
22f65d31 | 1093 | } |
54168ed7 | 1094 | } |
497c9a19 | 1095 | |
e7986739 | 1096 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1097 | err = -ENOSPC; |
1098 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1099 | int new_cpu; |
1100 | int vector, offset; | |
497c9a19 | 1101 | |
e2d40b18 | 1102 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1103 | |
54168ed7 IM |
1104 | vector = current_vector; |
1105 | offset = current_offset; | |
497c9a19 | 1106 | next: |
54168ed7 IM |
1107 | vector += 8; |
1108 | if (vector >= first_system_vector) { | |
e7986739 | 1109 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1110 | offset = (offset + 1) % 8; |
6579b474 | 1111 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1112 | } |
1113 | if (unlikely(current_vector == vector)) | |
1114 | continue; | |
b77b881f YL |
1115 | |
1116 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1117 | goto next; |
b77b881f | 1118 | |
22f65d31 | 1119 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1120 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1121 | goto next; | |
1122 | /* Found one! */ | |
1123 | current_vector = vector; | |
1124 | current_offset = offset; | |
1125 | if (old_vector) { | |
1126 | cfg->move_in_progress = 1; | |
22f65d31 | 1127 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1128 | } |
22f65d31 | 1129 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1130 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1131 | cfg->vector = vector; | |
22f65d31 MT |
1132 | cpumask_copy(cfg->domain, tmp_mask); |
1133 | err = 0; | |
1134 | break; | |
54168ed7 | 1135 | } |
22f65d31 MT |
1136 | free_cpumask_var(tmp_mask); |
1137 | return err; | |
497c9a19 YL |
1138 | } |
1139 | ||
9338ad6f | 1140 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1141 | { |
1142 | int err; | |
ace80ab7 | 1143 | unsigned long flags; |
ace80ab7 | 1144 | |
dade7716 | 1145 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1146 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1147 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1148 | return err; |
1149 | } | |
1150 | ||
3145e941 | 1151 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1152 | { |
497c9a19 YL |
1153 | int cpu, vector; |
1154 | ||
497c9a19 YL |
1155 | BUG_ON(!cfg->vector); |
1156 | ||
1157 | vector = cfg->vector; | |
22f65d31 | 1158 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1159 | per_cpu(vector_irq, cpu)[vector] = -1; |
1160 | ||
1161 | cfg->vector = 0; | |
22f65d31 | 1162 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1163 | |
1164 | if (likely(!cfg->move_in_progress)) | |
1165 | return; | |
22f65d31 | 1166 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1167 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1168 | vector++) { | |
1169 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1170 | continue; | |
1171 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1172 | break; | |
1173 | } | |
1174 | } | |
1175 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1176 | } |
1177 | ||
1178 | void __setup_vector_irq(int cpu) | |
1179 | { | |
1180 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1181 | int irq, vector; |
1182 | struct irq_cfg *cfg; | |
1183 | ||
9d133e5d SS |
1184 | /* |
1185 | * vector_lock will make sure that we don't run into irq vector | |
1186 | * assignments that might be happening on another cpu in parallel, | |
1187 | * while we setup our initial vector to irq mappings. | |
1188 | */ | |
dade7716 | 1189 | raw_spin_lock(&vector_lock); |
497c9a19 | 1190 | /* Mark the inuse vectors */ |
ad9f4334 TG |
1191 | for_each_active_irq(irq) { |
1192 | cfg = get_irq_chip_data(irq); | |
1193 | if (!cfg) | |
1194 | continue; | |
36e9e1ea SS |
1195 | /* |
1196 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1197 | * will be part of the irq_cfg's domain. | |
1198 | */ | |
1199 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1200 | cpumask_set_cpu(cpu, cfg->domain); | |
1201 | ||
22f65d31 | 1202 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1203 | continue; |
1204 | vector = cfg->vector; | |
497c9a19 YL |
1205 | per_cpu(vector_irq, cpu)[vector] = irq; |
1206 | } | |
1207 | /* Mark the free vectors */ | |
1208 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1209 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1210 | if (irq < 0) | |
1211 | continue; | |
1212 | ||
1213 | cfg = irq_cfg(irq); | |
22f65d31 | 1214 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1215 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1216 | } |
dade7716 | 1217 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1218 | } |
3fde6900 | 1219 | |
f5b9ed7a | 1220 | static struct irq_chip ioapic_chip; |
54168ed7 | 1221 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1222 | |
54168ed7 IM |
1223 | #define IOAPIC_AUTO -1 |
1224 | #define IOAPIC_EDGE 0 | |
1225 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1226 | |
047c8fdb | 1227 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1228 | static inline int IO_APIC_irq_trigger(int irq) |
1229 | { | |
d6c88a50 | 1230 | int apic, idx, pin; |
1d025192 | 1231 | |
d6c88a50 TG |
1232 | for (apic = 0; apic < nr_ioapics; apic++) { |
1233 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1234 | idx = find_irq_entry(apic, pin, mp_INT); | |
1235 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1236 | return irq_trigger(idx); | |
1237 | } | |
1238 | } | |
1239 | /* | |
54168ed7 IM |
1240 | * nonexistent IRQs are edge default |
1241 | */ | |
d6c88a50 | 1242 | return 0; |
1d025192 | 1243 | } |
047c8fdb YL |
1244 | #else |
1245 | static inline int IO_APIC_irq_trigger(int irq) | |
1246 | { | |
54168ed7 | 1247 | return 1; |
047c8fdb YL |
1248 | } |
1249 | #endif | |
1d025192 | 1250 | |
60c69948 | 1251 | static void ioapic_register_intr(unsigned int irq, unsigned long trigger) |
1da177e4 | 1252 | { |
199751d7 | 1253 | |
6ebcc00e | 1254 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1255 | trigger == IOAPIC_LEVEL) |
60c69948 | 1256 | irq_set_status_flags(irq, IRQ_LEVEL); |
047c8fdb | 1257 | else |
60c69948 | 1258 | irq_clear_status_flags(irq, IRQ_LEVEL); |
047c8fdb | 1259 | |
1a0730d6 | 1260 | if (irq_remapped(get_irq_chip_data(irq))) { |
60c69948 | 1261 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
54168ed7 IM |
1262 | if (trigger) |
1263 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1264 | handle_fasteoi_irq, | |
1265 | "fasteoi"); | |
1266 | else | |
1267 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1268 | handle_edge_irq, "edge"); | |
1269 | return; | |
1270 | } | |
29b61be6 | 1271 | |
047c8fdb YL |
1272 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1273 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1274 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1275 | handle_fasteoi_irq, |
1276 | "fasteoi"); | |
047c8fdb | 1277 | else |
a460e745 | 1278 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1279 | handle_edge_irq, "edge"); |
1da177e4 LT |
1280 | } |
1281 | ||
1a8ce7ff TG |
1282 | static int setup_ioapic_entry(int apic_id, int irq, |
1283 | struct IO_APIC_route_entry *entry, | |
1284 | unsigned int destination, int trigger, | |
1285 | int polarity, int vector, int pin) | |
1da177e4 | 1286 | { |
497c9a19 YL |
1287 | /* |
1288 | * add it to the IO-APIC irq-routing table: | |
1289 | */ | |
1290 | memset(entry,0,sizeof(*entry)); | |
1291 | ||
54168ed7 | 1292 | if (intr_remapping_enabled) { |
c8d46cf0 | 1293 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1294 | struct irte irte; |
1295 | struct IR_IO_APIC_route_entry *ir_entry = | |
1296 | (struct IR_IO_APIC_route_entry *) entry; | |
1297 | int index; | |
1298 | ||
1299 | if (!iommu) | |
c8d46cf0 | 1300 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1301 | |
1302 | index = alloc_irte(iommu, irq, 1); | |
1303 | if (index < 0) | |
c8d46cf0 | 1304 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 | 1305 | |
62a92f4c | 1306 | prepare_irte(&irte, vector, destination); |
54168ed7 | 1307 | |
f007e99c WH |
1308 | /* Set source-id of interrupt request */ |
1309 | set_ioapic_sid(&irte, apic_id); | |
1310 | ||
54168ed7 IM |
1311 | modify_irte(irq, &irte); |
1312 | ||
1313 | ir_entry->index2 = (index >> 15) & 0x1; | |
1314 | ir_entry->zero = 0; | |
1315 | ir_entry->format = 1; | |
1316 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1317 | /* |
1318 | * IO-APIC RTE will be configured with virtual vector. | |
1319 | * irq handler will do the explicit EOI to the io-apic. | |
1320 | */ | |
1321 | ir_entry->vector = pin; | |
29b61be6 | 1322 | } else { |
9b5bc8dc IM |
1323 | entry->delivery_mode = apic->irq_delivery_mode; |
1324 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1325 | entry->dest = destination; |
0280f7c4 | 1326 | entry->vector = vector; |
54168ed7 | 1327 | } |
497c9a19 | 1328 | |
54168ed7 | 1329 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1330 | entry->trigger = trigger; |
1331 | entry->polarity = polarity; | |
497c9a19 YL |
1332 | |
1333 | /* Mask level triggered irqs. | |
1334 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1335 | */ | |
1336 | if (trigger) | |
1337 | entry->mask = 1; | |
497c9a19 YL |
1338 | return 0; |
1339 | } | |
1340 | ||
60c69948 TG |
1341 | static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq, |
1342 | struct irq_cfg *cfg, int trigger, int polarity) | |
497c9a19 | 1343 | { |
1da177e4 | 1344 | struct IO_APIC_route_entry entry; |
22f65d31 | 1345 | unsigned int dest; |
497c9a19 YL |
1346 | |
1347 | if (!IO_APIC_IRQ(irq)) | |
1348 | return; | |
69c89efb SS |
1349 | /* |
1350 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1351 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1352 | * the cfg->domain. | |
1353 | */ | |
28c6a0ba | 1354 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1355 | apic->vector_allocation_domain(0, cfg->domain); |
1356 | ||
fe402e1f | 1357 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1358 | return; |
1359 | ||
debccb3e | 1360 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1361 | |
1362 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1363 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1364 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1365 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1366 | irq, trigger, polarity); |
1367 | ||
1368 | ||
c8d46cf0 | 1369 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1370 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1371 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1372 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1373 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1374 | return; |
1375 | } | |
1376 | ||
60c69948 | 1377 | ioapic_register_intr(irq, trigger); |
b81bb373 | 1378 | if (irq < legacy_pic->nr_legacy_irqs) |
4305df94 | 1379 | legacy_pic->mask(irq); |
497c9a19 | 1380 | |
c8d46cf0 | 1381 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1382 | } |
1383 | ||
b9c61b70 YL |
1384 | static struct { |
1385 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1386 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1387 | ||
497c9a19 YL |
1388 | static void __init setup_IO_APIC_irqs(void) |
1389 | { | |
fbc6bff0 | 1390 | int apic_id, pin, idx, irq, notcon = 0; |
f6e9456c | 1391 | int node = cpu_to_node(0); |
fbc6bff0 | 1392 | struct irq_cfg *cfg; |
1da177e4 LT |
1393 | |
1394 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1395 | ||
fad53995 | 1396 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) |
b9c61b70 YL |
1397 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1398 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1399 | if (idx == -1) { | |
1400 | if (!notcon) { | |
1401 | notcon = 1; | |
1402 | apic_printk(APIC_VERBOSE, | |
1403 | KERN_DEBUG " %d-%d", | |
1404 | mp_ioapics[apic_id].apicid, pin); | |
1405 | } else | |
1406 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1407 | mp_ioapics[apic_id].apicid, pin); | |
1408 | continue; | |
1409 | } | |
1410 | if (notcon) { | |
1411 | apic_printk(APIC_VERBOSE, | |
1412 | " (apicid-pin) not connected\n"); | |
1413 | notcon = 0; | |
1414 | } | |
33a201fa | 1415 | |
b9c61b70 | 1416 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1417 | |
fad53995 EB |
1418 | if ((apic_id > 0) && (irq > 16)) |
1419 | continue; | |
1420 | ||
b9c61b70 YL |
1421 | /* |
1422 | * Skip the timer IRQ if there's a quirk handler | |
1423 | * installed and if it returns 1: | |
1424 | */ | |
1425 | if (apic->multi_timer_check && | |
1426 | apic->multi_timer_check(apic_id, irq)) | |
1427 | continue; | |
36062448 | 1428 | |
fbc6bff0 TG |
1429 | cfg = alloc_irq_and_cfg_at(irq, node); |
1430 | if (!cfg) | |
b9c61b70 | 1431 | continue; |
fbc6bff0 | 1432 | |
b9c61b70 | 1433 | add_pin_to_irq_node(cfg, node, apic_id, pin); |
4c6f18fc YL |
1434 | /* |
1435 | * don't mark it in pin_programmed, so later acpi could | |
1436 | * set it correctly when irq < 16 | |
1437 | */ | |
60c69948 TG |
1438 | setup_ioapic_irq(apic_id, pin, irq, cfg, irq_trigger(idx), |
1439 | irq_polarity(idx)); | |
1da177e4 LT |
1440 | } |
1441 | ||
3c2cbd24 CG |
1442 | if (notcon) |
1443 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1444 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1445 | } |
1446 | ||
18dce6ba YL |
1447 | /* |
1448 | * for the gsit that is not in first ioapic | |
1449 | * but could not use acpi_register_gsi() | |
1450 | * like some special sci in IBM x3330 | |
1451 | */ | |
1452 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1453 | { | |
fbc6bff0 | 1454 | int apic_id = 0, pin, idx, irq, node = cpu_to_node(0); |
18dce6ba YL |
1455 | struct irq_cfg *cfg; |
1456 | ||
1457 | /* | |
1458 | * Convert 'gsi' to 'ioapic.pin'. | |
1459 | */ | |
1460 | apic_id = mp_find_ioapic(gsi); | |
1461 | if (apic_id < 0) | |
1462 | return; | |
1463 | ||
1464 | pin = mp_find_ioapic_pin(apic_id, gsi); | |
1465 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1466 | if (idx == -1) | |
1467 | return; | |
1468 | ||
1469 | irq = pin_2_irq(idx, apic_id, pin); | |
fe6dab4e YL |
1470 | |
1471 | /* Only handle the non legacy irqs on secondary ioapics */ | |
1472 | if (apic_id == 0 || irq < NR_IRQS_LEGACY) | |
18dce6ba | 1473 | return; |
fe6dab4e | 1474 | |
fbc6bff0 TG |
1475 | cfg = alloc_irq_and_cfg_at(irq, node); |
1476 | if (!cfg) | |
18dce6ba | 1477 | return; |
18dce6ba | 1478 | |
18dce6ba YL |
1479 | add_pin_to_irq_node(cfg, node, apic_id, pin); |
1480 | ||
1481 | if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) { | |
1482 | pr_debug("Pin %d-%d already programmed\n", | |
1483 | mp_ioapics[apic_id].apicid, pin); | |
1484 | return; | |
1485 | } | |
1486 | set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed); | |
1487 | ||
60c69948 | 1488 | setup_ioapic_irq(apic_id, pin, irq, cfg, |
18dce6ba YL |
1489 | irq_trigger(idx), irq_polarity(idx)); |
1490 | } | |
1491 | ||
1da177e4 | 1492 | /* |
f7633ce5 | 1493 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1494 | */ |
c8d46cf0 | 1495 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1496 | int vector) |
1da177e4 LT |
1497 | { |
1498 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1499 | |
54168ed7 IM |
1500 | if (intr_remapping_enabled) |
1501 | return; | |
54168ed7 | 1502 | |
36062448 | 1503 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1504 | |
1505 | /* | |
1506 | * We use logical delivery to get the timer IRQ | |
1507 | * to the first CPU. | |
1508 | */ | |
9b5bc8dc | 1509 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1510 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1511 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1512 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1513 | entry.polarity = 0; |
1514 | entry.trigger = 0; | |
1515 | entry.vector = vector; | |
1516 | ||
1517 | /* | |
1518 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1519 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1520 | */ |
54168ed7 | 1521 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1522 | |
1523 | /* | |
1524 | * Add it to the IO-APIC irq-routing table: | |
1525 | */ | |
c8d46cf0 | 1526 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1527 | } |
1528 | ||
32f71aff MR |
1529 | |
1530 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1531 | { |
1532 | int apic, i; | |
1533 | union IO_APIC_reg_00 reg_00; | |
1534 | union IO_APIC_reg_01 reg_01; | |
1535 | union IO_APIC_reg_02 reg_02; | |
1536 | union IO_APIC_reg_03 reg_03; | |
1537 | unsigned long flags; | |
0f978f45 | 1538 | struct irq_cfg *cfg; |
8f09cd20 | 1539 | unsigned int irq; |
1da177e4 | 1540 | |
36062448 | 1541 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1542 | for (i = 0; i < nr_ioapics; i++) |
1543 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1544 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1545 | |
1546 | /* | |
1547 | * We are a bit conservative about what we expect. We have to | |
1548 | * know about every hardware change ASAP. | |
1549 | */ | |
1550 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1551 | ||
1552 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1553 | ||
dade7716 | 1554 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
1555 | reg_00.raw = io_apic_read(apic, 0); |
1556 | reg_01.raw = io_apic_read(apic, 1); | |
1557 | if (reg_01.bits.version >= 0x10) | |
1558 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1559 | if (reg_01.bits.version >= 0x20) |
1560 | reg_03.raw = io_apic_read(apic, 3); | |
dade7716 | 1561 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1562 | |
54168ed7 | 1563 | printk("\n"); |
b5ba7e6d | 1564 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1565 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1566 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1567 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1568 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1569 | |
54168ed7 | 1570 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1571 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1572 | |
1573 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1574 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1575 | |
1576 | /* | |
1577 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1578 | * but the value of reg_02 is read as the previous read register | |
1579 | * value, so ignore it if reg_02 == reg_01. | |
1580 | */ | |
1581 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1582 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1583 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1584 | } |
1585 | ||
1586 | /* | |
1587 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1588 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1589 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1590 | */ | |
1591 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1592 | reg_03.raw != reg_01.raw) { | |
1593 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1594 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1595 | } |
1596 | ||
1597 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1598 | ||
d83e94ac | 1599 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
3235dc3f | 1600 | " Stat Dmod Deli Vect:\n"); |
1da177e4 LT |
1601 | |
1602 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1603 | struct IO_APIC_route_entry entry; | |
1604 | ||
cf4c6a2f | 1605 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1606 | |
54168ed7 IM |
1607 | printk(KERN_DEBUG " %02x %03X ", |
1608 | i, | |
1609 | entry.dest | |
1610 | ); | |
1da177e4 LT |
1611 | |
1612 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1613 | entry.mask, | |
1614 | entry.trigger, | |
1615 | entry.irr, | |
1616 | entry.polarity, | |
1617 | entry.delivery_status, | |
1618 | entry.dest_mode, | |
1619 | entry.delivery_mode, | |
1620 | entry.vector | |
1621 | ); | |
1622 | } | |
1623 | } | |
1da177e4 | 1624 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1625 | for_each_active_irq(irq) { |
0b8f1efa YL |
1626 | struct irq_pin_list *entry; |
1627 | ||
ad9f4334 | 1628 | cfg = get_irq_chip_data(irq); |
05e40760 DK |
1629 | if (!cfg) |
1630 | continue; | |
0b8f1efa | 1631 | entry = cfg->irq_2_pin; |
0f978f45 | 1632 | if (!entry) |
1da177e4 | 1633 | continue; |
8f09cd20 | 1634 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1635 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1636 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1637 | printk("\n"); |
1638 | } | |
1639 | ||
1640 | printk(KERN_INFO ".................................... done.\n"); | |
1641 | ||
1642 | return; | |
1643 | } | |
1644 | ||
251e1e44 | 1645 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1646 | { |
251e1e44 | 1647 | int i; |
1da177e4 | 1648 | |
251e1e44 IM |
1649 | printk(KERN_DEBUG); |
1650 | ||
1651 | for (i = 0; i < 8; i++) | |
1652 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1653 | ||
1654 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1655 | } |
1656 | ||
32f71aff | 1657 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1658 | { |
97a52714 | 1659 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1660 | u64 icr; |
1da177e4 | 1661 | |
251e1e44 | 1662 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1663 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1664 | v = apic_read(APIC_ID); |
54168ed7 | 1665 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1666 | v = apic_read(APIC_LVR); |
1667 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1668 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1669 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1670 | |
1671 | v = apic_read(APIC_TASKPRI); | |
1672 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1673 | ||
54168ed7 | 1674 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1675 | if (!APIC_XAPIC(ver)) { |
1676 | v = apic_read(APIC_ARBPRI); | |
1677 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1678 | v & APIC_ARBPRI_MASK); | |
1679 | } | |
1da177e4 LT |
1680 | v = apic_read(APIC_PROCPRI); |
1681 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1682 | } | |
1683 | ||
a11b5abe YL |
1684 | /* |
1685 | * Remote read supported only in the 82489DX and local APIC for | |
1686 | * Pentium processors. | |
1687 | */ | |
1688 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1689 | v = apic_read(APIC_RRR); | |
1690 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1691 | } | |
1692 | ||
1da177e4 LT |
1693 | v = apic_read(APIC_LDR); |
1694 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1695 | if (!x2apic_enabled()) { |
1696 | v = apic_read(APIC_DFR); | |
1697 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1698 | } | |
1da177e4 LT |
1699 | v = apic_read(APIC_SPIV); |
1700 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1701 | ||
1702 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1703 | print_APIC_field(APIC_ISR); |
1da177e4 | 1704 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1705 | print_APIC_field(APIC_TMR); |
1da177e4 | 1706 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1707 | print_APIC_field(APIC_IRR); |
1da177e4 | 1708 | |
54168ed7 IM |
1709 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1710 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1711 | apic_write(APIC_ESR, 0); |
54168ed7 | 1712 | |
1da177e4 LT |
1713 | v = apic_read(APIC_ESR); |
1714 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1715 | } | |
1716 | ||
7ab6af7a | 1717 | icr = apic_icr_read(); |
0c425cec IM |
1718 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1719 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1720 | |
1721 | v = apic_read(APIC_LVTT); | |
1722 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1723 | ||
1724 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1725 | v = apic_read(APIC_LVTPC); | |
1726 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1727 | } | |
1728 | v = apic_read(APIC_LVT0); | |
1729 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1730 | v = apic_read(APIC_LVT1); | |
1731 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1732 | ||
1733 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1734 | v = apic_read(APIC_LVTERR); | |
1735 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1736 | } | |
1737 | ||
1738 | v = apic_read(APIC_TMICT); | |
1739 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1740 | v = apic_read(APIC_TMCCT); | |
1741 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1742 | v = apic_read(APIC_TDCR); | |
1743 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1744 | |
1745 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1746 | v = apic_read(APIC_EFEAT); | |
1747 | maxlvt = (v >> 16) & 0xff; | |
1748 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1749 | v = apic_read(APIC_ECTRL); | |
1750 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1751 | for (i = 0; i < maxlvt; i++) { | |
1752 | v = apic_read(APIC_EILVTn(i)); | |
1753 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1754 | } | |
1755 | } | |
1da177e4 LT |
1756 | printk("\n"); |
1757 | } | |
1758 | ||
2626eb2b | 1759 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1760 | { |
ffd5aae7 YL |
1761 | int cpu; |
1762 | ||
2626eb2b CG |
1763 | if (!maxcpu) |
1764 | return; | |
1765 | ||
ffd5aae7 | 1766 | preempt_disable(); |
2626eb2b CG |
1767 | for_each_online_cpu(cpu) { |
1768 | if (cpu >= maxcpu) | |
1769 | break; | |
ffd5aae7 | 1770 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1771 | } |
ffd5aae7 | 1772 | preempt_enable(); |
1da177e4 LT |
1773 | } |
1774 | ||
32f71aff | 1775 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1776 | { |
1da177e4 LT |
1777 | unsigned int v; |
1778 | unsigned long flags; | |
1779 | ||
b81bb373 | 1780 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1781 | return; |
1782 | ||
1783 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1784 | ||
5619c280 | 1785 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1786 | |
1787 | v = inb(0xa1) << 8 | inb(0x21); | |
1788 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1789 | ||
1790 | v = inb(0xa0) << 8 | inb(0x20); | |
1791 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1792 | ||
54168ed7 IM |
1793 | outb(0x0b,0xa0); |
1794 | outb(0x0b,0x20); | |
1da177e4 | 1795 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1796 | outb(0x0a,0xa0); |
1797 | outb(0x0a,0x20); | |
1da177e4 | 1798 | |
5619c280 | 1799 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1800 | |
1801 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1802 | ||
1803 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1804 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1805 | } | |
1806 | ||
2626eb2b CG |
1807 | static int __initdata show_lapic = 1; |
1808 | static __init int setup_show_lapic(char *arg) | |
1809 | { | |
1810 | int num = -1; | |
1811 | ||
1812 | if (strcmp(arg, "all") == 0) { | |
1813 | show_lapic = CONFIG_NR_CPUS; | |
1814 | } else { | |
1815 | get_option(&arg, &num); | |
1816 | if (num >= 0) | |
1817 | show_lapic = num; | |
1818 | } | |
1819 | ||
1820 | return 1; | |
1821 | } | |
1822 | __setup("show_lapic=", setup_show_lapic); | |
1823 | ||
1824 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1825 | { |
2626eb2b CG |
1826 | if (apic_verbosity == APIC_QUIET) |
1827 | return 0; | |
1828 | ||
32f71aff | 1829 | print_PIC(); |
4797f6b0 YL |
1830 | |
1831 | /* don't print out if apic is not there */ | |
8312136f | 1832 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1833 | return 0; |
1834 | ||
2626eb2b | 1835 | print_local_APICs(show_lapic); |
32f71aff MR |
1836 | print_IO_APIC(); |
1837 | ||
1838 | return 0; | |
1839 | } | |
1840 | ||
2626eb2b | 1841 | fs_initcall(print_ICs); |
32f71aff | 1842 | |
1da177e4 | 1843 | |
efa2559f YL |
1844 | /* Where if anywhere is the i8259 connect in external int mode */ |
1845 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1846 | ||
54168ed7 | 1847 | void __init enable_IO_APIC(void) |
1da177e4 | 1848 | { |
fcfd636a | 1849 | int i8259_apic, i8259_pin; |
54168ed7 | 1850 | int apic; |
bc07844a | 1851 | |
b81bb373 | 1852 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1853 | return; |
1854 | ||
54168ed7 | 1855 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1856 | int pin; |
1857 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1858 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1859 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1860 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1861 | |
fcfd636a EB |
1862 | /* If the interrupt line is enabled and in ExtInt mode |
1863 | * I have found the pin where the i8259 is connected. | |
1864 | */ | |
1865 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1866 | ioapic_i8259.apic = apic; | |
1867 | ioapic_i8259.pin = pin; | |
1868 | goto found_i8259; | |
1869 | } | |
1870 | } | |
1871 | } | |
1872 | found_i8259: | |
1873 | /* Look to see what if the MP table has reported the ExtINT */ | |
1874 | /* If we could not find the appropriate pin by looking at the ioapic | |
1875 | * the i8259 probably is not connected the ioapic but give the | |
1876 | * mptable a chance anyway. | |
1877 | */ | |
1878 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1879 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1880 | /* Trust the MP table if nothing is setup in the hardware */ | |
1881 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1882 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1883 | ioapic_i8259.pin = i8259_pin; | |
1884 | ioapic_i8259.apic = i8259_apic; | |
1885 | } | |
1886 | /* Complain if the MP table and the hardware disagree */ | |
1887 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1888 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1889 | { | |
1890 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1891 | } |
1892 | ||
1893 | /* | |
1894 | * Do not trust the IO-APIC being empty at bootup | |
1895 | */ | |
1896 | clear_IO_APIC(); | |
1897 | } | |
1898 | ||
1899 | /* | |
1900 | * Not an __init, needed by the reboot code | |
1901 | */ | |
1902 | void disable_IO_APIC(void) | |
1903 | { | |
1904 | /* | |
1905 | * Clear the IO-APIC before rebooting: | |
1906 | */ | |
1907 | clear_IO_APIC(); | |
1908 | ||
b81bb373 | 1909 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1910 | return; |
1911 | ||
650927ef | 1912 | /* |
0b968d23 | 1913 | * If the i8259 is routed through an IOAPIC |
650927ef | 1914 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1915 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1916 | * |
1917 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1918 | * as virtual wire B is little complex (need to configure both | |
1919 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
1920 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 1921 | */ |
7c6d9f97 | 1922 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1923 | struct IO_APIC_route_entry entry; |
650927ef EB |
1924 | |
1925 | memset(&entry, 0, sizeof(entry)); | |
1926 | entry.mask = 0; /* Enabled */ | |
1927 | entry.trigger = 0; /* Edge */ | |
1928 | entry.irr = 0; | |
1929 | entry.polarity = 0; /* High */ | |
1930 | entry.delivery_status = 0; | |
1931 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1932 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1933 | entry.vector = 0; |
54168ed7 | 1934 | entry.dest = read_apic_id(); |
650927ef EB |
1935 | |
1936 | /* | |
1937 | * Add it to the IO-APIC irq-routing table: | |
1938 | */ | |
cf4c6a2f | 1939 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1940 | } |
54168ed7 | 1941 | |
7c6d9f97 SS |
1942 | /* |
1943 | * Use virtual wire A mode when interrupt remapping is enabled. | |
1944 | */ | |
8312136f | 1945 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
1946 | disconnect_bsp_APIC(!intr_remapping_enabled && |
1947 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
1948 | } |
1949 | ||
54168ed7 | 1950 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1951 | /* |
1952 | * function to set the IO-APIC physical IDs based on the | |
1953 | * values stored in the MPC table. | |
1954 | * | |
1955 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1956 | */ | |
a38c5380 | 1957 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1958 | { |
1959 | union IO_APIC_reg_00 reg_00; | |
1960 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 1961 | int apic_id; |
1da177e4 LT |
1962 | int i; |
1963 | unsigned char old_id; | |
1964 | unsigned long flags; | |
1965 | ||
1966 | /* | |
1967 | * This is broken; anything with a real cpu count has to | |
1968 | * circumvent this idiocy regardless. | |
1969 | */ | |
7abc0753 | 1970 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1971 | |
1972 | /* | |
1973 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1974 | */ | |
c8d46cf0 | 1975 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
1976 | |
1977 | /* Read the register 0 value */ | |
dade7716 | 1978 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 1979 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 1980 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1981 | |
c8d46cf0 | 1982 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 1983 | |
c8d46cf0 | 1984 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 1985 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 1986 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
1987 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1988 | reg_00.bits.ID); | |
c8d46cf0 | 1989 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
1990 | } |
1991 | ||
1da177e4 LT |
1992 | /* |
1993 | * Sanity check, is the ID really free? Every APIC in a | |
1994 | * system must have a unique ID or we get lots of nice | |
1995 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1996 | */ | |
7abc0753 | 1997 | if (apic->check_apicid_used(&phys_id_present_map, |
c8d46cf0 | 1998 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 1999 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2000 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2001 | for (i = 0; i < get_physical_broadcast(); i++) |
2002 | if (!physid_isset(i, phys_id_present_map)) | |
2003 | break; | |
2004 | if (i >= get_physical_broadcast()) | |
2005 | panic("Max APIC ID exceeded!\n"); | |
2006 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2007 | i); | |
2008 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2009 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2010 | } else { |
2011 | physid_mask_t tmp; | |
7abc0753 | 2012 | apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp); |
1da177e4 LT |
2013 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2014 | "phys_id_present_map\n", | |
c8d46cf0 | 2015 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2016 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2017 | } | |
2018 | ||
1da177e4 LT |
2019 | /* |
2020 | * We need to adjust the IRQ routing table | |
2021 | * if the ID changed. | |
2022 | */ | |
c8d46cf0 | 2023 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2024 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2025 | if (mp_irqs[i].dstapic == old_id) |
2026 | mp_irqs[i].dstapic | |
c8d46cf0 | 2027 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2028 | |
2029 | /* | |
60d79fd9 YL |
2030 | * Update the ID register according to the right value |
2031 | * from the MPC table if they are different. | |
36062448 | 2032 | */ |
60d79fd9 YL |
2033 | if (mp_ioapics[apic_id].apicid == reg_00.bits.ID) |
2034 | continue; | |
2035 | ||
1da177e4 LT |
2036 | apic_printk(APIC_VERBOSE, KERN_INFO |
2037 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2038 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2039 | |
c8d46cf0 | 2040 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
dade7716 | 2041 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2042 | io_apic_write(apic_id, 0, reg_00.raw); |
dade7716 | 2043 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2044 | |
2045 | /* | |
2046 | * Sanity check | |
2047 | */ | |
dade7716 | 2048 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2049 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2050 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2051 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2052 | printk("could not set ID!\n"); |
2053 | else | |
2054 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2055 | } | |
2056 | } | |
a38c5380 SAS |
2057 | |
2058 | void __init setup_ioapic_ids_from_mpc(void) | |
2059 | { | |
2060 | ||
2061 | if (acpi_ioapic) | |
2062 | return; | |
2063 | /* | |
2064 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2065 | * no meaning without the serial APIC bus. | |
2066 | */ | |
2067 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2068 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
2069 | return; | |
2070 | setup_ioapic_ids_from_mpc_nocheck(); | |
2071 | } | |
54168ed7 | 2072 | #endif |
1da177e4 | 2073 | |
7ce0bcfd | 2074 | int no_timer_check __initdata; |
8542b200 ZA |
2075 | |
2076 | static int __init notimercheck(char *s) | |
2077 | { | |
2078 | no_timer_check = 1; | |
2079 | return 1; | |
2080 | } | |
2081 | __setup("no_timer_check", notimercheck); | |
2082 | ||
1da177e4 LT |
2083 | /* |
2084 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2085 | * about the timer IRQ. We do the following to work around the situation: | |
2086 | * | |
2087 | * - timer IRQ defaults to IO-APIC IRQ | |
2088 | * - if this function detects that timer IRQs are defunct, then we fall | |
2089 | * back to ISA timer IRQs | |
2090 | */ | |
f0a7a5c9 | 2091 | static int __init timer_irq_works(void) |
1da177e4 LT |
2092 | { |
2093 | unsigned long t1 = jiffies; | |
4aae0702 | 2094 | unsigned long flags; |
1da177e4 | 2095 | |
8542b200 ZA |
2096 | if (no_timer_check) |
2097 | return 1; | |
2098 | ||
4aae0702 | 2099 | local_save_flags(flags); |
1da177e4 LT |
2100 | local_irq_enable(); |
2101 | /* Let ten ticks pass... */ | |
2102 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2103 | local_irq_restore(flags); |
1da177e4 LT |
2104 | |
2105 | /* | |
2106 | * Expect a few ticks at least, to be sure some possible | |
2107 | * glue logic does not lock up after one or two first | |
2108 | * ticks in a non-ExtINT mode. Also the local APIC | |
2109 | * might have cached one ExtINT interrupt. Finally, at | |
2110 | * least one tick may be lost due to delays. | |
2111 | */ | |
54168ed7 IM |
2112 | |
2113 | /* jiffies wrap? */ | |
1d16b53e | 2114 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2115 | return 1; |
1da177e4 LT |
2116 | return 0; |
2117 | } | |
2118 | ||
2119 | /* | |
2120 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2121 | * number of pending IRQ events unhandled. These cases are very rare, | |
2122 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2123 | * better to do it this way as thus we do not have to be aware of | |
2124 | * 'pending' interrupts in the IRQ path, except at this point. | |
2125 | */ | |
2126 | /* | |
2127 | * Edge triggered needs to resend any interrupt | |
2128 | * that was delayed but this is now handled in the device | |
2129 | * independent code. | |
2130 | */ | |
2131 | ||
2132 | /* | |
2133 | * Starting up a edge-triggered IO-APIC interrupt is | |
2134 | * nasty - we need to make sure that we get the edge. | |
2135 | * If it is already asserted for some reason, we need | |
2136 | * return 1 to indicate that is was pending. | |
2137 | * | |
2138 | * This is not complete - we should be able to fake | |
2139 | * an edge even if it isn't on the 8259A... | |
2140 | */ | |
54168ed7 | 2141 | |
61a38ce3 | 2142 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 2143 | { |
61a38ce3 | 2144 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
2145 | unsigned long flags; |
2146 | ||
dade7716 | 2147 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 | 2148 | if (irq < legacy_pic->nr_legacy_irqs) { |
4305df94 | 2149 | legacy_pic->mask(irq); |
b81bb373 | 2150 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2151 | was_pending = 1; |
2152 | } | |
61a38ce3 | 2153 | __unmask_ioapic(data->chip_data); |
dade7716 | 2154 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2155 | |
2156 | return was_pending; | |
2157 | } | |
2158 | ||
90297c5f | 2159 | static int ioapic_retrigger_irq(struct irq_data *data) |
1da177e4 | 2160 | { |
90297c5f | 2161 | struct irq_cfg *cfg = data->chip_data; |
54168ed7 IM |
2162 | unsigned long flags; |
2163 | ||
dade7716 | 2164 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2165 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2166 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2167 | |
2168 | return 1; | |
2169 | } | |
497c9a19 | 2170 | |
54168ed7 IM |
2171 | /* |
2172 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2173 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2174 | * handled with the level-triggered descriptor, but that one has slightly | |
2175 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2176 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2177 | * races. | |
2178 | */ | |
497c9a19 | 2179 | |
54168ed7 | 2180 | #ifdef CONFIG_SMP |
9338ad6f | 2181 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2182 | { |
2183 | cpumask_var_t cleanup_mask; | |
2184 | ||
2185 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2186 | unsigned int i; | |
e85abf8f GH |
2187 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2188 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2189 | } else { | |
2190 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2191 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2192 | free_cpumask_var(cleanup_mask); | |
2193 | } | |
2194 | cfg->move_in_progress = 0; | |
2195 | } | |
2196 | ||
4420471f | 2197 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2198 | { |
2199 | int apic, pin; | |
2200 | struct irq_pin_list *entry; | |
2201 | u8 vector = cfg->vector; | |
2202 | ||
2977fb3f | 2203 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2204 | unsigned int reg; |
2205 | ||
e85abf8f GH |
2206 | apic = entry->apic; |
2207 | pin = entry->pin; | |
2208 | /* | |
2209 | * With interrupt-remapping, destination information comes | |
2210 | * from interrupt-remapping table entry. | |
2211 | */ | |
1a0730d6 | 2212 | if (!irq_remapped(cfg)) |
e85abf8f GH |
2213 | io_apic_write(apic, 0x11 + pin*2, dest); |
2214 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2215 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2216 | reg |= vector; | |
2217 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2218 | } |
2219 | } | |
2220 | ||
2221 | /* | |
f7e909ea | 2222 | * Either sets data->affinity to a valid value, and returns |
18374d89 | 2223 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
f7e909ea | 2224 | * leaves data->affinity untouched. |
e85abf8f | 2225 | */ |
f7e909ea TG |
2226 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2227 | unsigned int *dest_id) | |
e85abf8f | 2228 | { |
f7e909ea | 2229 | struct irq_cfg *cfg = data->chip_data; |
e85abf8f GH |
2230 | |
2231 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2232 | return -1; |
e85abf8f | 2233 | |
f7e909ea | 2234 | if (assign_irq_vector(data->irq, data->chip_data, mask)) |
18374d89 | 2235 | return -1; |
e85abf8f | 2236 | |
f7e909ea | 2237 | cpumask_copy(data->affinity, mask); |
e85abf8f | 2238 | |
f7e909ea | 2239 | *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain); |
18374d89 | 2240 | return 0; |
e85abf8f GH |
2241 | } |
2242 | ||
4420471f | 2243 | static int |
f7e909ea TG |
2244 | ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2245 | bool force) | |
e85abf8f | 2246 | { |
f7e909ea | 2247 | unsigned int dest, irq = data->irq; |
e85abf8f | 2248 | unsigned long flags; |
f7e909ea | 2249 | int ret; |
e85abf8f | 2250 | |
dade7716 | 2251 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
f7e909ea | 2252 | ret = __ioapic_set_affinity(data, mask, &dest); |
18374d89 | 2253 | if (!ret) { |
e85abf8f GH |
2254 | /* Only the high 8 bits are valid. */ |
2255 | dest = SET_APIC_LOGICAL_ID(dest); | |
f7e909ea | 2256 | __target_IO_APIC_irq(irq, dest, data->chip_data); |
e85abf8f | 2257 | } |
dade7716 | 2258 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f | 2259 | return ret; |
e85abf8f GH |
2260 | } |
2261 | ||
54168ed7 | 2262 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2263 | |
54168ed7 IM |
2264 | /* |
2265 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2266 | * | |
0280f7c4 SS |
2267 | * For both level and edge triggered, irq migration is a simple atomic |
2268 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2269 | * |
0280f7c4 SS |
2270 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2271 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2272 | * Real vector that is used for interrupting cpu will be coming from | |
2273 | * the interrupt-remapping table entry. | |
54168ed7 | 2274 | */ |
d5dedd45 | 2275 | static int |
f19f5ecc TG |
2276 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2277 | bool force) | |
497c9a19 | 2278 | { |
f19f5ecc TG |
2279 | struct irq_cfg *cfg = data->chip_data; |
2280 | unsigned int dest, irq = data->irq; | |
54168ed7 | 2281 | struct irte irte; |
497c9a19 | 2282 | |
22f65d31 | 2283 | if (!cpumask_intersects(mask, cpu_online_mask)) |
f19f5ecc | 2284 | return -EINVAL; |
497c9a19 | 2285 | |
54168ed7 | 2286 | if (get_irte(irq, &irte)) |
f19f5ecc | 2287 | return -EBUSY; |
497c9a19 | 2288 | |
3145e941 | 2289 | if (assign_irq_vector(irq, cfg, mask)) |
f19f5ecc | 2290 | return -EBUSY; |
54168ed7 | 2291 | |
debccb3e | 2292 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2293 | |
54168ed7 IM |
2294 | irte.vector = cfg->vector; |
2295 | irte.dest_id = IRTE_DEST(dest); | |
2296 | ||
2297 | /* | |
2298 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2299 | */ | |
2300 | modify_irte(irq, &irte); | |
2301 | ||
22f65d31 MT |
2302 | if (cfg->move_in_progress) |
2303 | send_cleanup_vector(cfg); | |
54168ed7 | 2304 | |
f19f5ecc | 2305 | cpumask_copy(data->affinity, mask); |
d5dedd45 | 2306 | return 0; |
54168ed7 IM |
2307 | } |
2308 | ||
29b61be6 | 2309 | #else |
f19f5ecc TG |
2310 | static inline int |
2311 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
2312 | bool force) | |
29b61be6 | 2313 | { |
d5dedd45 | 2314 | return 0; |
29b61be6 | 2315 | } |
54168ed7 IM |
2316 | #endif |
2317 | ||
2318 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2319 | { | |
2320 | unsigned vector, me; | |
8f2466f4 | 2321 | |
54168ed7 | 2322 | ack_APIC_irq(); |
54168ed7 | 2323 | exit_idle(); |
54168ed7 IM |
2324 | irq_enter(); |
2325 | ||
2326 | me = smp_processor_id(); | |
2327 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2328 | unsigned int irq; | |
68a8ca59 | 2329 | unsigned int irr; |
54168ed7 IM |
2330 | struct irq_desc *desc; |
2331 | struct irq_cfg *cfg; | |
0a3aee0d | 2332 | irq = __this_cpu_read(vector_irq[vector]); |
54168ed7 | 2333 | |
0b8f1efa YL |
2334 | if (irq == -1) |
2335 | continue; | |
2336 | ||
54168ed7 IM |
2337 | desc = irq_to_desc(irq); |
2338 | if (!desc) | |
2339 | continue; | |
2340 | ||
2341 | cfg = irq_cfg(irq); | |
239007b8 | 2342 | raw_spin_lock(&desc->lock); |
54168ed7 | 2343 | |
7f41c2e1 SS |
2344 | /* |
2345 | * Check if the irq migration is in progress. If so, we | |
2346 | * haven't received the cleanup request yet for this irq. | |
2347 | */ | |
2348 | if (cfg->move_in_progress) | |
2349 | goto unlock; | |
2350 | ||
22f65d31 | 2351 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2352 | goto unlock; |
2353 | ||
68a8ca59 SS |
2354 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2355 | /* | |
2356 | * Check if the vector that needs to be cleanedup is | |
2357 | * registered at the cpu's IRR. If so, then this is not | |
2358 | * the best time to clean it up. Lets clean it up in the | |
2359 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2360 | * to myself. | |
2361 | */ | |
2362 | if (irr & (1 << (vector % 32))) { | |
2363 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2364 | goto unlock; | |
2365 | } | |
0a3aee0d | 2366 | __this_cpu_write(vector_irq[vector], -1); |
54168ed7 | 2367 | unlock: |
239007b8 | 2368 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2369 | } |
2370 | ||
2371 | irq_exit(); | |
2372 | } | |
2373 | ||
dd5f15e5 | 2374 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2375 | { |
a5e74b84 | 2376 | unsigned me; |
54168ed7 | 2377 | |
fcef5911 | 2378 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2379 | return; |
2380 | ||
54168ed7 | 2381 | me = smp_processor_id(); |
10b888d6 | 2382 | |
fcef5911 | 2383 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2384 | send_cleanup_vector(cfg); |
497c9a19 | 2385 | } |
a5e74b84 | 2386 | |
dd5f15e5 | 2387 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2388 | { |
dd5f15e5 | 2389 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2390 | } |
2391 | ||
2392 | void irq_force_complete_move(int irq) | |
2393 | { | |
dd5f15e5 | 2394 | struct irq_cfg *cfg = get_irq_chip_data(irq); |
a5e74b84 | 2395 | |
bbd391a1 PB |
2396 | if (!cfg) |
2397 | return; | |
2398 | ||
dd5f15e5 | 2399 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2400 | } |
497c9a19 | 2401 | #else |
dd5f15e5 | 2402 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2403 | #endif |
3145e941 | 2404 | |
90297c5f | 2405 | static void ack_apic_edge(struct irq_data *data) |
1d025192 | 2406 | { |
90297c5f TG |
2407 | irq_complete_move(data->chip_data); |
2408 | move_native_irq(data->irq); | |
1d025192 YL |
2409 | ack_APIC_irq(); |
2410 | } | |
2411 | ||
3eb2cce8 | 2412 | atomic_t irq_mis_count; |
3eb2cce8 | 2413 | |
c29d9db3 SS |
2414 | /* |
2415 | * IO-APIC versions below 0x20 don't support EOI register. | |
2416 | * For the record, here is the information about various versions: | |
2417 | * 0Xh 82489DX | |
2418 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2419 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2420 | * 30h-FFh Reserved | |
2421 | * | |
2422 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2423 | * version as 0x2. This is an error with documentation and these ICH chips | |
2424 | * use io-apic's of version 0x20. | |
2425 | * | |
2426 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2427 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2428 | * mode to edge and then back to level, with RTE being masked during this. | |
2429 | */ | |
dd5f15e5 | 2430 | static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
b3ec0a37 SS |
2431 | { |
2432 | struct irq_pin_list *entry; | |
dd5f15e5 | 2433 | unsigned long flags; |
b3ec0a37 | 2434 | |
dd5f15e5 | 2435 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b3ec0a37 | 2436 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
c29d9db3 SS |
2437 | if (mp_ioapics[entry->apic].apicver >= 0x20) { |
2438 | /* | |
2439 | * Intr-remapping uses pin number as the virtual vector | |
2440 | * in the RTE. Actual vector is programmed in | |
2441 | * intr-remapping table entry. Hence for the io-apic | |
2442 | * EOI we use the pin number. | |
2443 | */ | |
1a0730d6 | 2444 | if (irq_remapped(cfg)) |
c29d9db3 SS |
2445 | io_apic_eoi(entry->apic, entry->pin); |
2446 | else | |
2447 | io_apic_eoi(entry->apic, cfg->vector); | |
2448 | } else { | |
2449 | __mask_and_edge_IO_APIC_irq(entry); | |
2450 | __unmask_and_level_IO_APIC_irq(entry); | |
2451 | } | |
b3ec0a37 | 2452 | } |
dade7716 | 2453 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
b3ec0a37 SS |
2454 | } |
2455 | ||
90297c5f | 2456 | static void ack_apic_level(struct irq_data *data) |
047c8fdb | 2457 | { |
90297c5f TG |
2458 | struct irq_cfg *cfg = data->chip_data; |
2459 | int i, do_unmask_irq = 0, irq = data->irq; | |
3eb2cce8 | 2460 | unsigned long v; |
047c8fdb | 2461 | |
dd5f15e5 | 2462 | irq_complete_move(cfg); |
047c8fdb | 2463 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2464 | /* If we are moving the irq we need to mask it */ |
4720dd1b | 2465 | if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2466 | do_unmask_irq = 1; |
dd5f15e5 | 2467 | mask_ioapic(cfg); |
54168ed7 | 2468 | } |
047c8fdb YL |
2469 | #endif |
2470 | ||
3eb2cce8 | 2471 | /* |
916a0fe7 JF |
2472 | * It appears there is an erratum which affects at least version 0x11 |
2473 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2474 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2475 | * erroneously delivered as edge-triggered one but the respective IRR | |
2476 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2477 | * message but it will never arrive and further interrupts are blocked | |
2478 | * from the source. The exact reason is so far unknown, but the | |
2479 | * phenomenon was observed when two consecutive interrupt requests | |
2480 | * from a given source get delivered to the same CPU and the source is | |
2481 | * temporarily disabled in between. | |
2482 | * | |
2483 | * A workaround is to simulate an EOI message manually. We achieve it | |
2484 | * by setting the trigger mode to edge and then to level when the edge | |
2485 | * trigger mode gets detected in the TMR of a local APIC for a | |
2486 | * level-triggered interrupt. We mask the source for the time of the | |
2487 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2488 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2489 | * |
2490 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2491 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2492 | * destination that is handling the corresponding interrupt. This | |
2493 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2494 | * level-triggered io-apic interrupt will be seen as an edge | |
2495 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2496 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2497 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2498 | * supporting EOI register, we do an explicit EOI to clear the | |
2499 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2500 | * we use the above logic (mask+edge followed by unmask+level) from | |
2501 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2502 | */ |
3145e941 | 2503 | i = cfg->vector; |
3eb2cce8 | 2504 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2505 | |
54168ed7 IM |
2506 | /* |
2507 | * We must acknowledge the irq before we move it or the acknowledge will | |
2508 | * not propagate properly. | |
2509 | */ | |
2510 | ack_APIC_irq(); | |
2511 | ||
1c83995b SS |
2512 | /* |
2513 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2514 | * message via io-apic EOI register write or simulating it using | |
2515 | * mask+edge followed by unnask+level logic) manually when the | |
2516 | * level triggered interrupt is seen as the edge triggered interrupt | |
2517 | * at the cpu. | |
2518 | */ | |
ca64c47c MR |
2519 | if (!(v & (1 << (i & 0x1f)))) { |
2520 | atomic_inc(&irq_mis_count); | |
2521 | ||
dd5f15e5 | 2522 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2523 | } |
2524 | ||
54168ed7 IM |
2525 | /* Now we can move and renable the irq */ |
2526 | if (unlikely(do_unmask_irq)) { | |
2527 | /* Only migrate the irq if the ack has been received. | |
2528 | * | |
2529 | * On rare occasions the broadcast level triggered ack gets | |
2530 | * delayed going to ioapics, and if we reprogram the | |
2531 | * vector while Remote IRR is still set the irq will never | |
2532 | * fire again. | |
2533 | * | |
2534 | * To prevent this scenario we read the Remote IRR bit | |
2535 | * of the ioapic. This has two effects. | |
2536 | * - On any sane system the read of the ioapic will | |
2537 | * flush writes (and acks) going to the ioapic from | |
2538 | * this cpu. | |
2539 | * - We get to see if the ACK has actually been delivered. | |
2540 | * | |
2541 | * Based on failed experiments of reprogramming the | |
2542 | * ioapic entry from outside of irq context starting | |
2543 | * with masking the ioapic entry and then polling until | |
2544 | * Remote IRR was clear before reprogramming the | |
2545 | * ioapic I don't trust the Remote IRR bit to be | |
2546 | * completey accurate. | |
2547 | * | |
2548 | * However there appears to be no other way to plug | |
2549 | * this race, so if the Remote IRR bit is not | |
2550 | * accurate and is causing problems then it is a hardware bug | |
2551 | * and you can go talk to the chipset vendor about it. | |
2552 | */ | |
3145e941 | 2553 | if (!io_apic_level_ack_pending(cfg)) |
54168ed7 | 2554 | move_masked_irq(irq); |
dd5f15e5 | 2555 | unmask_ioapic(cfg); |
54168ed7 | 2556 | } |
3eb2cce8 | 2557 | } |
1d025192 | 2558 | |
d0b03bd1 | 2559 | #ifdef CONFIG_INTR_REMAP |
90297c5f | 2560 | static void ir_ack_apic_edge(struct irq_data *data) |
d0b03bd1 | 2561 | { |
5d0ae2db | 2562 | ack_APIC_irq(); |
d0b03bd1 HW |
2563 | } |
2564 | ||
90297c5f | 2565 | static void ir_ack_apic_level(struct irq_data *data) |
d0b03bd1 | 2566 | { |
5d0ae2db | 2567 | ack_APIC_irq(); |
90297c5f | 2568 | eoi_ioapic_irq(data->irq, data->chip_data); |
d0b03bd1 HW |
2569 | } |
2570 | #endif /* CONFIG_INTR_REMAP */ | |
2571 | ||
f5b9ed7a | 2572 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2573 | .name = "IO-APIC", |
2574 | .irq_startup = startup_ioapic_irq, | |
2575 | .irq_mask = mask_ioapic_irq, | |
2576 | .irq_unmask = unmask_ioapic_irq, | |
2577 | .irq_ack = ack_apic_edge, | |
2578 | .irq_eoi = ack_apic_level, | |
54d5d424 | 2579 | #ifdef CONFIG_SMP |
f7e909ea | 2580 | .irq_set_affinity = ioapic_set_affinity, |
54d5d424 | 2581 | #endif |
f7e909ea | 2582 | .irq_retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2583 | }; |
2584 | ||
54168ed7 | 2585 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
f19f5ecc TG |
2586 | .name = "IR-IO-APIC", |
2587 | .irq_startup = startup_ioapic_irq, | |
2588 | .irq_mask = mask_ioapic_irq, | |
2589 | .irq_unmask = unmask_ioapic_irq, | |
a1e38ca5 | 2590 | #ifdef CONFIG_INTR_REMAP |
f19f5ecc TG |
2591 | .irq_ack = ir_ack_apic_edge, |
2592 | .irq_eoi = ir_ack_apic_level, | |
54168ed7 | 2593 | #ifdef CONFIG_SMP |
f19f5ecc | 2594 | .irq_set_affinity = ir_ioapic_set_affinity, |
a1e38ca5 | 2595 | #endif |
54168ed7 | 2596 | #endif |
f19f5ecc | 2597 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 | 2598 | }; |
1da177e4 LT |
2599 | |
2600 | static inline void init_IO_APIC_traps(void) | |
2601 | { | |
da51a821 | 2602 | struct irq_cfg *cfg; |
ad9f4334 | 2603 | unsigned int irq; |
1da177e4 LT |
2604 | |
2605 | /* | |
2606 | * NOTE! The local APIC isn't very good at handling | |
2607 | * multiple interrupts at the same interrupt level. | |
2608 | * As the interrupt level is determined by taking the | |
2609 | * vector number and shifting that right by 4, we | |
2610 | * want to spread these out a bit so that they don't | |
2611 | * all fall in the same interrupt level. | |
2612 | * | |
2613 | * Also, we've got to be careful not to trash gate | |
2614 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2615 | */ | |
ad9f4334 TG |
2616 | for_each_active_irq(irq) { |
2617 | cfg = get_irq_chip_data(irq); | |
0b8f1efa | 2618 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2619 | /* |
2620 | * Hmm.. We don't have an entry for this, | |
2621 | * so default to an old-fashioned 8259 | |
2622 | * interrupt if we can.. | |
2623 | */ | |
b81bb373 JP |
2624 | if (irq < legacy_pic->nr_legacy_irqs) |
2625 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2626 | else |
1da177e4 | 2627 | /* Strange. Oh, well.. */ |
ad9f4334 | 2628 | set_irq_chip(irq, &no_irq_chip); |
1da177e4 LT |
2629 | } |
2630 | } | |
2631 | } | |
2632 | ||
f5b9ed7a IM |
2633 | /* |
2634 | * The local APIC irq-chip implementation: | |
2635 | */ | |
1da177e4 | 2636 | |
90297c5f | 2637 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2638 | { |
2639 | unsigned long v; | |
2640 | ||
2641 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2642 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2643 | } |
2644 | ||
90297c5f | 2645 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2646 | { |
f5b9ed7a | 2647 | unsigned long v; |
1da177e4 | 2648 | |
f5b9ed7a | 2649 | v = apic_read(APIC_LVT0); |
593f4a78 | 2650 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2651 | } |
1da177e4 | 2652 | |
90297c5f | 2653 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2654 | { |
2655 | ack_APIC_irq(); | |
2656 | } | |
2657 | ||
f5b9ed7a | 2658 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2659 | .name = "local-APIC", |
90297c5f TG |
2660 | .irq_mask = mask_lapic_irq, |
2661 | .irq_unmask = unmask_lapic_irq, | |
2662 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2663 | }; |
2664 | ||
60c69948 | 2665 | static void lapic_register_intr(int irq) |
c88ac1df | 2666 | { |
60c69948 | 2667 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c88ac1df MR |
2668 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2669 | "edge"); | |
c88ac1df MR |
2670 | } |
2671 | ||
1da177e4 LT |
2672 | /* |
2673 | * This looks a bit hackish but it's about the only one way of sending | |
2674 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2675 | * not support the ExtINT mode, unfortunately. We need to send these | |
2676 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2677 | * 8259A interrupt line asserted until INTA. --macro | |
2678 | */ | |
28acf285 | 2679 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2680 | { |
fcfd636a | 2681 | int apic, pin, i; |
1da177e4 LT |
2682 | struct IO_APIC_route_entry entry0, entry1; |
2683 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2684 | |
fcfd636a | 2685 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2686 | if (pin == -1) { |
2687 | WARN_ON_ONCE(1); | |
2688 | return; | |
2689 | } | |
fcfd636a | 2690 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2691 | if (apic == -1) { |
2692 | WARN_ON_ONCE(1); | |
1da177e4 | 2693 | return; |
956fb531 | 2694 | } |
1da177e4 | 2695 | |
cf4c6a2f | 2696 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2697 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2698 | |
2699 | memset(&entry1, 0, sizeof(entry1)); | |
2700 | ||
2701 | entry1.dest_mode = 0; /* physical delivery */ | |
2702 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2703 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2704 | entry1.delivery_mode = dest_ExtINT; |
2705 | entry1.polarity = entry0.polarity; | |
2706 | entry1.trigger = 0; | |
2707 | entry1.vector = 0; | |
2708 | ||
cf4c6a2f | 2709 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2710 | |
2711 | save_control = CMOS_READ(RTC_CONTROL); | |
2712 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2713 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2714 | RTC_FREQ_SELECT); | |
2715 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2716 | ||
2717 | i = 100; | |
2718 | while (i-- > 0) { | |
2719 | mdelay(10); | |
2720 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2721 | i -= 10; | |
2722 | } | |
2723 | ||
2724 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2725 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2726 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2727 | |
cf4c6a2f | 2728 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2729 | } |
2730 | ||
efa2559f | 2731 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2732 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2733 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2734 | { |
2735 | disable_timer_pin_1 = 1; | |
2736 | return 0; | |
2737 | } | |
54168ed7 | 2738 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2739 | |
2740 | int timer_through_8259 __initdata; | |
2741 | ||
1da177e4 LT |
2742 | /* |
2743 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2744 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2745 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2746 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2747 | * |
2748 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2749 | */ |
8542b200 | 2750 | static inline void __init check_timer(void) |
1da177e4 | 2751 | { |
60c69948 | 2752 | struct irq_cfg *cfg = get_irq_chip_data(0); |
f6e9456c | 2753 | int node = cpu_to_node(0); |
fcfd636a | 2754 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2755 | unsigned long flags; |
047c8fdb | 2756 | int no_pin1 = 0; |
4aae0702 IM |
2757 | |
2758 | local_irq_save(flags); | |
d4d25dec | 2759 | |
1da177e4 LT |
2760 | /* |
2761 | * get/set the timer IRQ vector: | |
2762 | */ | |
4305df94 | 2763 | legacy_pic->mask(0); |
fe402e1f | 2764 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2765 | |
2766 | /* | |
d11d5794 MR |
2767 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2768 | * wire has to be disabled in the local APIC. Also | |
2769 | * timer interrupts need to be acknowledged manually in | |
2770 | * the 8259A for the i82489DX when using the NMI | |
2771 | * watchdog as that APIC treats NMIs as level-triggered. | |
2772 | * The AEOI mode will finish them in the 8259A | |
2773 | * automatically. | |
1da177e4 | 2774 | */ |
593f4a78 | 2775 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2776 | legacy_pic->init(1); |
1da177e4 | 2777 | |
fcfd636a EB |
2778 | pin1 = find_isa_irq_pin(0, mp_INT); |
2779 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2780 | pin2 = ioapic_i8259.pin; | |
2781 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2782 | |
49a66a0b MR |
2783 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2784 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2785 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2786 | |
691874fa MR |
2787 | /* |
2788 | * Some BIOS writers are clueless and report the ExtINTA | |
2789 | * I/O APIC input from the cascaded 8259A as the timer | |
2790 | * interrupt input. So just in case, if only one pin | |
2791 | * was found above, try it both directly and through the | |
2792 | * 8259A. | |
2793 | */ | |
2794 | if (pin1 == -1) { | |
54168ed7 IM |
2795 | if (intr_remapping_enabled) |
2796 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2797 | pin1 = pin2; |
2798 | apic1 = apic2; | |
2799 | no_pin1 = 1; | |
2800 | } else if (pin2 == -1) { | |
2801 | pin2 = pin1; | |
2802 | apic2 = apic1; | |
2803 | } | |
2804 | ||
1da177e4 LT |
2805 | if (pin1 != -1) { |
2806 | /* | |
2807 | * Ok, does IRQ0 through the IOAPIC work? | |
2808 | */ | |
691874fa | 2809 | if (no_pin1) { |
85ac16d0 | 2810 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2811 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac | 2812 | } else { |
60c69948 | 2813 | /* for edge trigger, setup_ioapic_irq already |
f72dccac YL |
2814 | * leave it unmasked. |
2815 | * so only need to unmask if it is level-trigger | |
2816 | * do we really have level trigger timer? | |
2817 | */ | |
2818 | int idx; | |
2819 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2820 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2821 | unmask_ioapic(cfg); |
691874fa | 2822 | } |
1da177e4 | 2823 | if (timer_irq_works()) { |
66759a01 CE |
2824 | if (disable_timer_pin_1 > 0) |
2825 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2826 | goto out; |
1da177e4 | 2827 | } |
54168ed7 IM |
2828 | if (intr_remapping_enabled) |
2829 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2830 | local_irq_disable(); |
fcfd636a | 2831 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2832 | if (!no_pin1) |
49a66a0b MR |
2833 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2834 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2835 | |
49a66a0b MR |
2836 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2837 | "(IRQ0) through the 8259A ...\n"); | |
2838 | apic_printk(APIC_QUIET, KERN_INFO | |
2839 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2840 | /* |
2841 | * legacy devices should be connected to IO APIC #0 | |
2842 | */ | |
85ac16d0 | 2843 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2844 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2845 | legacy_pic->unmask(0); |
1da177e4 | 2846 | if (timer_irq_works()) { |
49a66a0b | 2847 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2848 | timer_through_8259 = 1; |
4aae0702 | 2849 | goto out; |
1da177e4 LT |
2850 | } |
2851 | /* | |
2852 | * Cleanup, just in case ... | |
2853 | */ | |
f72dccac | 2854 | local_irq_disable(); |
4305df94 | 2855 | legacy_pic->mask(0); |
fcfd636a | 2856 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2857 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2858 | } |
1da177e4 | 2859 | |
49a66a0b MR |
2860 | apic_printk(APIC_QUIET, KERN_INFO |
2861 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2862 | |
60c69948 | 2863 | lapic_register_intr(0); |
497c9a19 | 2864 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2865 | legacy_pic->unmask(0); |
1da177e4 LT |
2866 | |
2867 | if (timer_irq_works()) { | |
49a66a0b | 2868 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2869 | goto out; |
1da177e4 | 2870 | } |
f72dccac | 2871 | local_irq_disable(); |
4305df94 | 2872 | legacy_pic->mask(0); |
497c9a19 | 2873 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2874 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2875 | |
49a66a0b MR |
2876 | apic_printk(APIC_QUIET, KERN_INFO |
2877 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2878 | |
b81bb373 JP |
2879 | legacy_pic->init(0); |
2880 | legacy_pic->make_irq(0); | |
593f4a78 | 2881 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2882 | |
2883 | unlock_ExtINT_logic(); | |
2884 | ||
2885 | if (timer_irq_works()) { | |
49a66a0b | 2886 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2887 | goto out; |
1da177e4 | 2888 | } |
f72dccac | 2889 | local_irq_disable(); |
49a66a0b | 2890 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2891 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2892 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2893 | out: |
2894 | local_irq_restore(flags); | |
1da177e4 LT |
2895 | } |
2896 | ||
2897 | /* | |
af174783 MR |
2898 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2899 | * to devices. However there may be an I/O APIC pin available for | |
2900 | * this interrupt regardless. The pin may be left unconnected, but | |
2901 | * typically it will be reused as an ExtINT cascade interrupt for | |
2902 | * the master 8259A. In the MPS case such a pin will normally be | |
2903 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2904 | * there is no provision for ExtINT interrupts, and in the absence | |
2905 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2906 | * interrupt, that is edge-triggered and unmasked by default. We | |
2907 | * used to do this, but it caused problems on some systems because | |
2908 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2909 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2910 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2911 | * the I/O APIC in all cases now. No actual device should request | |
2912 | * it anyway. --macro | |
1da177e4 | 2913 | */ |
bc07844a | 2914 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
2915 | |
2916 | void __init setup_IO_APIC(void) | |
2917 | { | |
54168ed7 | 2918 | |
54168ed7 IM |
2919 | /* |
2920 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2921 | */ | |
b81bb373 | 2922 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2923 | |
54168ed7 | 2924 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 2925 | /* |
54168ed7 IM |
2926 | * Set up IO-APIC IRQ routing. |
2927 | */ | |
de934103 TG |
2928 | x86_init.mpparse.setup_ioapic_ids(); |
2929 | ||
1da177e4 LT |
2930 | sync_Arb_IDs(); |
2931 | setup_IO_APIC_irqs(); | |
2932 | init_IO_APIC_traps(); | |
b81bb373 | 2933 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 2934 | check_timer(); |
1da177e4 LT |
2935 | } |
2936 | ||
2937 | /* | |
54168ed7 IM |
2938 | * Called after all the initialization is done. If we didnt find any |
2939 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 2940 | */ |
36062448 | 2941 | |
1da177e4 LT |
2942 | static int __init io_apic_bug_finalize(void) |
2943 | { | |
d6c88a50 TG |
2944 | if (sis_apic_bug == -1) |
2945 | sis_apic_bug = 0; | |
2946 | return 0; | |
1da177e4 LT |
2947 | } |
2948 | ||
2949 | late_initcall(io_apic_bug_finalize); | |
2950 | ||
2951 | struct sysfs_ioapic_data { | |
2952 | struct sys_device dev; | |
2953 | struct IO_APIC_route_entry entry[0]; | |
2954 | }; | |
54168ed7 | 2955 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 2956 | |
438510f6 | 2957 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2958 | { |
2959 | struct IO_APIC_route_entry *entry; | |
2960 | struct sysfs_ioapic_data *data; | |
1da177e4 | 2961 | int i; |
36062448 | 2962 | |
1da177e4 LT |
2963 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2964 | entry = data->entry; | |
54168ed7 IM |
2965 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
2966 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
2967 | |
2968 | return 0; | |
2969 | } | |
2970 | ||
2971 | static int ioapic_resume(struct sys_device *dev) | |
2972 | { | |
2973 | struct IO_APIC_route_entry *entry; | |
2974 | struct sysfs_ioapic_data *data; | |
2975 | unsigned long flags; | |
2976 | union IO_APIC_reg_00 reg_00; | |
2977 | int i; | |
36062448 | 2978 | |
1da177e4 LT |
2979 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2980 | entry = data->entry; | |
2981 | ||
dade7716 | 2982 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2983 | reg_00.raw = io_apic_read(dev->id, 0); |
b5ba7e6d JSR |
2984 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
2985 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
2986 | io_apic_write(dev->id, 0, reg_00.raw); |
2987 | } | |
dade7716 | 2988 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2989 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2990 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
2991 | |
2992 | return 0; | |
2993 | } | |
2994 | ||
2995 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2996 | .name = "ioapic", |
1da177e4 LT |
2997 | .suspend = ioapic_suspend, |
2998 | .resume = ioapic_resume, | |
2999 | }; | |
3000 | ||
3001 | static int __init ioapic_init_sysfs(void) | |
3002 | { | |
54168ed7 IM |
3003 | struct sys_device * dev; |
3004 | int i, size, error; | |
1da177e4 LT |
3005 | |
3006 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3007 | if (error) | |
3008 | return error; | |
3009 | ||
54168ed7 | 3010 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3011 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3012 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3013 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3014 | if (!mp_ioapic_data[i]) { |
3015 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3016 | continue; | |
3017 | } | |
1da177e4 | 3018 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3019 | dev->id = i; |
1da177e4 LT |
3020 | dev->cls = &ioapic_sysdev_class; |
3021 | error = sysdev_register(dev); | |
3022 | if (error) { | |
3023 | kfree(mp_ioapic_data[i]); | |
3024 | mp_ioapic_data[i] = NULL; | |
3025 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3026 | continue; | |
3027 | } | |
3028 | } | |
3029 | ||
3030 | return 0; | |
3031 | } | |
3032 | ||
3033 | device_initcall(ioapic_init_sysfs); | |
3034 | ||
3fc471ed | 3035 | /* |
95d77884 | 3036 | * Dynamic irq allocate and deallocation |
3fc471ed | 3037 | */ |
fbc6bff0 | 3038 | unsigned int create_irq_nr(unsigned int from, int node) |
3fc471ed | 3039 | { |
fbc6bff0 | 3040 | struct irq_cfg *cfg; |
3fc471ed | 3041 | unsigned long flags; |
fbc6bff0 TG |
3042 | unsigned int ret = 0; |
3043 | int irq; | |
d047f53a | 3044 | |
fbc6bff0 TG |
3045 | if (from < nr_irqs_gsi) |
3046 | from = nr_irqs_gsi; | |
d047f53a | 3047 | |
fbc6bff0 TG |
3048 | irq = alloc_irq_from(from, node); |
3049 | if (irq < 0) | |
3050 | return 0; | |
3051 | cfg = alloc_irq_cfg(irq, node); | |
3052 | if (!cfg) { | |
3053 | free_irq_at(irq, NULL); | |
3054 | return 0; | |
ace80ab7 | 3055 | } |
3fc471ed | 3056 | |
fbc6bff0 TG |
3057 | raw_spin_lock_irqsave(&vector_lock, flags); |
3058 | if (!__assign_irq_vector(irq, cfg, apic->target_cpus())) | |
3059 | ret = irq; | |
3060 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3061 | |
fbc6bff0 TG |
3062 | if (ret) { |
3063 | set_irq_chip_data(irq, cfg); | |
3064 | irq_clear_status_flags(irq, IRQ_NOREQUEST); | |
3065 | } else { | |
3066 | free_irq_at(irq, cfg); | |
3067 | } | |
3068 | return ret; | |
3fc471ed EB |
3069 | } |
3070 | ||
199751d7 YL |
3071 | int create_irq(void) |
3072 | { | |
f6e9456c | 3073 | int node = cpu_to_node(0); |
be5d5350 | 3074 | unsigned int irq_want; |
54168ed7 IM |
3075 | int irq; |
3076 | ||
be5d5350 | 3077 | irq_want = nr_irqs_gsi; |
d047f53a | 3078 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3079 | |
3080 | if (irq == 0) | |
3081 | irq = -1; | |
3082 | ||
3083 | return irq; | |
199751d7 YL |
3084 | } |
3085 | ||
3fc471ed EB |
3086 | void destroy_irq(unsigned int irq) |
3087 | { | |
fbc6bff0 | 3088 | struct irq_cfg *cfg = get_irq_chip_data(irq); |
3fc471ed | 3089 | unsigned long flags; |
3fc471ed | 3090 | |
fbc6bff0 | 3091 | irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); |
3fc471ed | 3092 | |
7b79462a | 3093 | if (irq_remapped(cfg)) |
9717967c | 3094 | free_irte(irq); |
dade7716 | 3095 | raw_spin_lock_irqsave(&vector_lock, flags); |
fbc6bff0 | 3096 | __clear_irq_vector(irq, cfg); |
dade7716 | 3097 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
fbc6bff0 | 3098 | free_irq_at(irq, cfg); |
3fc471ed | 3099 | } |
3fc471ed | 3100 | |
2d3fcc1c | 3101 | /* |
27b46d76 | 3102 | * MSI message composition |
2d3fcc1c EB |
3103 | */ |
3104 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3105 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3106 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3107 | { |
497c9a19 YL |
3108 | struct irq_cfg *cfg; |
3109 | int err; | |
2d3fcc1c EB |
3110 | unsigned dest; |
3111 | ||
f1182638 JB |
3112 | if (disable_apic) |
3113 | return -ENXIO; | |
3114 | ||
3145e941 | 3115 | cfg = irq_cfg(irq); |
fe402e1f | 3116 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3117 | if (err) |
3118 | return err; | |
2d3fcc1c | 3119 | |
debccb3e | 3120 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3121 | |
1a0730d6 | 3122 | if (irq_remapped(get_irq_chip_data(irq))) { |
54168ed7 IM |
3123 | struct irte irte; |
3124 | int ir_index; | |
3125 | u16 sub_handle; | |
3126 | ||
3127 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3128 | BUG_ON(ir_index == -1); | |
3129 | ||
62a92f4c | 3130 | prepare_irte(&irte, cfg->vector, dest); |
54168ed7 | 3131 | |
f007e99c | 3132 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3133 | if (pdev) |
3134 | set_msi_sid(&irte, pdev); | |
3135 | else | |
3136 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3137 | |
54168ed7 IM |
3138 | modify_irte(irq, &irte); |
3139 | ||
3140 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3141 | msg->data = sub_handle; | |
3142 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3143 | MSI_ADDR_IR_SHV | | |
3144 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3145 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3146 | } else { |
9d783ba0 SS |
3147 | if (x2apic_enabled()) |
3148 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3149 | MSI_ADDR_EXT_DEST_ID(dest); | |
3150 | else | |
3151 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3152 | ||
54168ed7 IM |
3153 | msg->address_lo = |
3154 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3155 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3156 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3157 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3158 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3159 | MSI_ADDR_REDIRECTION_CPU: |
3160 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3161 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3162 | |
54168ed7 IM |
3163 | msg->data = |
3164 | MSI_DATA_TRIGGER_EDGE | | |
3165 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3166 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3167 | MSI_DATA_DELIVERY_FIXED: |
3168 | MSI_DATA_DELIVERY_LOWPRI) | | |
3169 | MSI_DATA_VECTOR(cfg->vector); | |
3170 | } | |
497c9a19 | 3171 | return err; |
2d3fcc1c EB |
3172 | } |
3173 | ||
3b7d1921 | 3174 | #ifdef CONFIG_SMP |
5346b2a7 TG |
3175 | static int |
3176 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
2d3fcc1c | 3177 | { |
5346b2a7 | 3178 | struct irq_cfg *cfg = data->chip_data; |
3b7d1921 EB |
3179 | struct msi_msg msg; |
3180 | unsigned int dest; | |
3b7d1921 | 3181 | |
5346b2a7 | 3182 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3183 | return -1; |
2d3fcc1c | 3184 | |
5346b2a7 | 3185 | __get_cached_msi_msg(data->msi_desc, &msg); |
3b7d1921 EB |
3186 | |
3187 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3188 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3189 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3190 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3191 | ||
5346b2a7 | 3192 | __write_msi_msg(data->msi_desc, &msg); |
d5dedd45 YL |
3193 | |
3194 | return 0; | |
2d3fcc1c | 3195 | } |
54168ed7 IM |
3196 | #ifdef CONFIG_INTR_REMAP |
3197 | /* | |
3198 | * Migrate the MSI irq to another cpumask. This migration is | |
3199 | * done in the process context using interrupt-remapping hardware. | |
3200 | */ | |
d5dedd45 | 3201 | static int |
b5d1c465 TG |
3202 | ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, |
3203 | bool force) | |
54168ed7 | 3204 | { |
b5d1c465 TG |
3205 | struct irq_cfg *cfg = data->chip_data; |
3206 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3207 | struct irte irte; |
54168ed7 IM |
3208 | |
3209 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3210 | return -1; |
54168ed7 | 3211 | |
b5d1c465 | 3212 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3213 | return -1; |
54168ed7 | 3214 | |
54168ed7 IM |
3215 | irte.vector = cfg->vector; |
3216 | irte.dest_id = IRTE_DEST(dest); | |
3217 | ||
3218 | /* | |
3219 | * atomically update the IRTE with the new destination and vector. | |
3220 | */ | |
3221 | modify_irte(irq, &irte); | |
3222 | ||
3223 | /* | |
3224 | * After this point, all the interrupts will start arriving | |
3225 | * at the new destination. So, time to cleanup the previous | |
3226 | * vector allocation. | |
3227 | */ | |
22f65d31 MT |
3228 | if (cfg->move_in_progress) |
3229 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3230 | |
3231 | return 0; | |
54168ed7 | 3232 | } |
3145e941 | 3233 | |
54168ed7 | 3234 | #endif |
3b7d1921 | 3235 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3236 | |
3b7d1921 EB |
3237 | /* |
3238 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3239 | * which implement the MSI or MSI-X Capability Structure. | |
3240 | */ | |
3241 | static struct irq_chip msi_chip = { | |
5346b2a7 TG |
3242 | .name = "PCI-MSI", |
3243 | .irq_unmask = unmask_msi_irq, | |
3244 | .irq_mask = mask_msi_irq, | |
3245 | .irq_ack = ack_apic_edge, | |
3b7d1921 | 3246 | #ifdef CONFIG_SMP |
5346b2a7 | 3247 | .irq_set_affinity = msi_set_affinity, |
3b7d1921 | 3248 | #endif |
5346b2a7 | 3249 | .irq_retrigger = ioapic_retrigger_irq, |
2d3fcc1c EB |
3250 | }; |
3251 | ||
54168ed7 | 3252 | static struct irq_chip msi_ir_chip = { |
b5d1c465 TG |
3253 | .name = "IR-PCI-MSI", |
3254 | .irq_unmask = unmask_msi_irq, | |
3255 | .irq_mask = mask_msi_irq, | |
a1e38ca5 | 3256 | #ifdef CONFIG_INTR_REMAP |
b5d1c465 | 3257 | .irq_ack = ir_ack_apic_edge, |
54168ed7 | 3258 | #ifdef CONFIG_SMP |
b5d1c465 | 3259 | .irq_set_affinity = ir_msi_set_affinity, |
a1e38ca5 | 3260 | #endif |
54168ed7 | 3261 | #endif |
b5d1c465 | 3262 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3263 | }; |
3264 | ||
3265 | /* | |
3266 | * Map the PCI dev to the corresponding remapping hardware unit | |
3267 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3268 | * in it. | |
3269 | */ | |
3270 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3271 | { | |
3272 | struct intel_iommu *iommu; | |
3273 | int index; | |
3274 | ||
3275 | iommu = map_dev_to_ir(dev); | |
3276 | if (!iommu) { | |
3277 | printk(KERN_ERR | |
3278 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3279 | return -ENOENT; | |
3280 | } | |
3281 | ||
3282 | index = alloc_irte(iommu, irq, nvec); | |
3283 | if (index < 0) { | |
3284 | printk(KERN_ERR | |
3285 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3286 | pci_name(dev)); |
54168ed7 IM |
3287 | return -ENOSPC; |
3288 | } | |
3289 | return index; | |
3290 | } | |
1d025192 | 3291 | |
3145e941 | 3292 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 | 3293 | { |
1d025192 | 3294 | struct msi_msg msg; |
60c69948 | 3295 | int ret; |
1d025192 | 3296 | |
c8bc6f3c | 3297 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3298 | if (ret < 0) |
3299 | return ret; | |
3300 | ||
3145e941 | 3301 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3302 | write_msi_msg(irq, &msg); |
3303 | ||
1a0730d6 | 3304 | if (irq_remapped(get_irq_chip_data(irq))) { |
60c69948 | 3305 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
54168ed7 IM |
3306 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); |
3307 | } else | |
54168ed7 | 3308 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3309 | |
c81bba49 YL |
3310 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3311 | ||
1d025192 YL |
3312 | return 0; |
3313 | } | |
3314 | ||
294ee6f8 | 3315 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
047c8fdb | 3316 | { |
60c69948 TG |
3317 | int node, ret, sub_handle, index = 0; |
3318 | unsigned int irq, irq_want; | |
0b8f1efa | 3319 | struct msi_desc *msidesc; |
1cc18521 | 3320 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3321 | |
1c8d7b0a MW |
3322 | /* x86 doesn't support multiple MSI yet */ |
3323 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3324 | return 1; | |
3325 | ||
d047f53a | 3326 | node = dev_to_node(&dev->dev); |
be5d5350 | 3327 | irq_want = nr_irqs_gsi; |
54168ed7 | 3328 | sub_handle = 0; |
0b8f1efa | 3329 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3330 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3331 | if (irq == 0) |
3332 | return -1; | |
f1ee5548 | 3333 | irq_want = irq + 1; |
54168ed7 IM |
3334 | if (!intr_remapping_enabled) |
3335 | goto no_ir; | |
3336 | ||
3337 | if (!sub_handle) { | |
3338 | /* | |
3339 | * allocate the consecutive block of IRTE's | |
3340 | * for 'nvec' | |
3341 | */ | |
3342 | index = msi_alloc_irte(dev, irq, nvec); | |
3343 | if (index < 0) { | |
3344 | ret = index; | |
3345 | goto error; | |
3346 | } | |
3347 | } else { | |
3348 | iommu = map_dev_to_ir(dev); | |
3349 | if (!iommu) { | |
3350 | ret = -ENOENT; | |
3351 | goto error; | |
3352 | } | |
3353 | /* | |
3354 | * setup the mapping between the irq and the IRTE | |
3355 | * base index, the sub_handle pointing to the | |
3356 | * appropriate interrupt remap table entry. | |
3357 | */ | |
3358 | set_irte_irq(irq, iommu, index, sub_handle); | |
3359 | } | |
3360 | no_ir: | |
0b8f1efa | 3361 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3362 | if (ret < 0) |
3363 | goto error; | |
3364 | sub_handle++; | |
3365 | } | |
3366 | return 0; | |
047c8fdb YL |
3367 | |
3368 | error: | |
54168ed7 IM |
3369 | destroy_irq(irq); |
3370 | return ret; | |
047c8fdb YL |
3371 | } |
3372 | ||
294ee6f8 | 3373 | void native_teardown_msi_irq(unsigned int irq) |
3b7d1921 | 3374 | { |
f7feaca7 | 3375 | destroy_irq(irq); |
3b7d1921 EB |
3376 | } |
3377 | ||
9d783ba0 | 3378 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3379 | #ifdef CONFIG_SMP |
fe52b2d2 TG |
3380 | static int |
3381 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
3382 | bool force) | |
54168ed7 | 3383 | { |
fe52b2d2 TG |
3384 | struct irq_cfg *cfg = data->chip_data; |
3385 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3386 | struct msi_msg msg; |
54168ed7 | 3387 | |
fe52b2d2 | 3388 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3389 | return -1; |
54168ed7 | 3390 | |
54168ed7 IM |
3391 | dmar_msi_read(irq, &msg); |
3392 | ||
3393 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3394 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3395 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3396 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
086e8ced | 3397 | msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); |
54168ed7 IM |
3398 | |
3399 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3400 | |
3401 | return 0; | |
54168ed7 | 3402 | } |
3145e941 | 3403 | |
54168ed7 IM |
3404 | #endif /* CONFIG_SMP */ |
3405 | ||
8f7007aa | 3406 | static struct irq_chip dmar_msi_type = { |
fe52b2d2 TG |
3407 | .name = "DMAR_MSI", |
3408 | .irq_unmask = dmar_msi_unmask, | |
3409 | .irq_mask = dmar_msi_mask, | |
3410 | .irq_ack = ack_apic_edge, | |
54168ed7 | 3411 | #ifdef CONFIG_SMP |
fe52b2d2 | 3412 | .irq_set_affinity = dmar_msi_set_affinity, |
54168ed7 | 3413 | #endif |
fe52b2d2 | 3414 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3415 | }; |
3416 | ||
3417 | int arch_setup_dmar_msi(unsigned int irq) | |
3418 | { | |
3419 | int ret; | |
3420 | struct msi_msg msg; | |
2d3fcc1c | 3421 | |
c8bc6f3c | 3422 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3423 | if (ret < 0) |
3424 | return ret; | |
3425 | dmar_msi_write(irq, &msg); | |
3426 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3427 | "edge"); | |
3428 | return 0; | |
3429 | } | |
3430 | #endif | |
3431 | ||
58ac1e76 | 3432 | #ifdef CONFIG_HPET_TIMER |
3433 | ||
3434 | #ifdef CONFIG_SMP | |
d0fbca8f TG |
3435 | static int hpet_msi_set_affinity(struct irq_data *data, |
3436 | const struct cpumask *mask, bool force) | |
58ac1e76 | 3437 | { |
d0fbca8f | 3438 | struct irq_cfg *cfg = data->chip_data; |
58ac1e76 | 3439 | struct msi_msg msg; |
3440 | unsigned int dest; | |
58ac1e76 | 3441 | |
0e09ddf2 | 3442 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3443 | return -1; |
58ac1e76 | 3444 | |
d0fbca8f | 3445 | hpet_msi_read(data->handler_data, &msg); |
58ac1e76 | 3446 | |
3447 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3448 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3449 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3450 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3451 | ||
d0fbca8f | 3452 | hpet_msi_write(data->handler_data, &msg); |
d5dedd45 YL |
3453 | |
3454 | return 0; | |
58ac1e76 | 3455 | } |
3145e941 | 3456 | |
58ac1e76 | 3457 | #endif /* CONFIG_SMP */ |
3458 | ||
c8bc6f3c | 3459 | static struct irq_chip ir_hpet_msi_type = { |
b5d1c465 TG |
3460 | .name = "IR-HPET_MSI", |
3461 | .irq_unmask = hpet_msi_unmask, | |
3462 | .irq_mask = hpet_msi_mask, | |
c8bc6f3c | 3463 | #ifdef CONFIG_INTR_REMAP |
b5d1c465 | 3464 | .irq_ack = ir_ack_apic_edge, |
c8bc6f3c | 3465 | #ifdef CONFIG_SMP |
b5d1c465 | 3466 | .irq_set_affinity = ir_msi_set_affinity, |
c8bc6f3c SS |
3467 | #endif |
3468 | #endif | |
b5d1c465 | 3469 | .irq_retrigger = ioapic_retrigger_irq, |
c8bc6f3c SS |
3470 | }; |
3471 | ||
1cc18521 | 3472 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3473 | .name = "HPET_MSI", |
d0fbca8f TG |
3474 | .irq_unmask = hpet_msi_unmask, |
3475 | .irq_mask = hpet_msi_mask, | |
90297c5f | 3476 | .irq_ack = ack_apic_edge, |
58ac1e76 | 3477 | #ifdef CONFIG_SMP |
d0fbca8f | 3478 | .irq_set_affinity = hpet_msi_set_affinity, |
58ac1e76 | 3479 | #endif |
90297c5f | 3480 | .irq_retrigger = ioapic_retrigger_irq, |
58ac1e76 | 3481 | }; |
3482 | ||
c8bc6f3c | 3483 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3484 | { |
58ac1e76 | 3485 | struct msi_msg msg; |
d0fbca8f | 3486 | int ret; |
58ac1e76 | 3487 | |
c8bc6f3c SS |
3488 | if (intr_remapping_enabled) { |
3489 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3490 | int index; | |
3491 | ||
3492 | if (!iommu) | |
3493 | return -1; | |
3494 | ||
3495 | index = alloc_irte(iommu, irq, 1); | |
3496 | if (index < 0) | |
3497 | return -1; | |
3498 | } | |
3499 | ||
3500 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3501 | if (ret < 0) |
3502 | return ret; | |
3503 | ||
d0fbca8f | 3504 | hpet_msi_write(get_irq_data(irq), &msg); |
60c69948 | 3505 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
1a0730d6 | 3506 | if (irq_remapped(get_irq_chip_data(irq))) |
c8bc6f3c SS |
3507 | set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type, |
3508 | handle_edge_irq, "edge"); | |
3509 | else | |
3510 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, | |
3511 | handle_edge_irq, "edge"); | |
c81bba49 | 3512 | |
58ac1e76 | 3513 | return 0; |
3514 | } | |
3515 | #endif | |
3516 | ||
54168ed7 | 3517 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3518 | /* |
3519 | * Hypertransport interrupt support | |
3520 | */ | |
3521 | #ifdef CONFIG_HT_IRQ | |
3522 | ||
3523 | #ifdef CONFIG_SMP | |
3524 | ||
497c9a19 | 3525 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3526 | { |
ec68307c EB |
3527 | struct ht_irq_msg msg; |
3528 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3529 | |
497c9a19 | 3530 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3531 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3532 | |
497c9a19 | 3533 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3534 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3535 | |
ec68307c | 3536 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3537 | } |
3538 | ||
be5b7bf7 TG |
3539 | static int |
3540 | ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
8b955b0d | 3541 | { |
be5b7bf7 | 3542 | struct irq_cfg *cfg = data->chip_data; |
8b955b0d | 3543 | unsigned int dest; |
8b955b0d | 3544 | |
be5b7bf7 | 3545 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3546 | return -1; |
8b955b0d | 3547 | |
be5b7bf7 | 3548 | target_ht_irq(data->irq, dest, cfg->vector); |
d5dedd45 | 3549 | return 0; |
8b955b0d | 3550 | } |
3145e941 | 3551 | |
8b955b0d EB |
3552 | #endif |
3553 | ||
c37e108d | 3554 | static struct irq_chip ht_irq_chip = { |
be5b7bf7 TG |
3555 | .name = "PCI-HT", |
3556 | .irq_mask = mask_ht_irq, | |
3557 | .irq_unmask = unmask_ht_irq, | |
3558 | .irq_ack = ack_apic_edge, | |
8b955b0d | 3559 | #ifdef CONFIG_SMP |
be5b7bf7 | 3560 | .irq_set_affinity = ht_set_affinity, |
8b955b0d | 3561 | #endif |
be5b7bf7 | 3562 | .irq_retrigger = ioapic_retrigger_irq, |
8b955b0d EB |
3563 | }; |
3564 | ||
3565 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3566 | { | |
497c9a19 YL |
3567 | struct irq_cfg *cfg; |
3568 | int err; | |
8b955b0d | 3569 | |
f1182638 JB |
3570 | if (disable_apic) |
3571 | return -ENXIO; | |
3572 | ||
3145e941 | 3573 | cfg = irq_cfg(irq); |
fe402e1f | 3574 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3575 | if (!err) { |
ec68307c | 3576 | struct ht_irq_msg msg; |
8b955b0d | 3577 | unsigned dest; |
8b955b0d | 3578 | |
debccb3e IM |
3579 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3580 | apic->target_cpus()); | |
8b955b0d | 3581 | |
ec68307c | 3582 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3583 | |
ec68307c EB |
3584 | msg.address_lo = |
3585 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3586 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3587 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3588 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3589 | HT_IRQ_LOW_DM_PHYSICAL : |
3590 | HT_IRQ_LOW_DM_LOGICAL) | | |
3591 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3592 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3593 | HT_IRQ_LOW_MT_FIXED : |
3594 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3595 | HT_IRQ_LOW_IRQ_MASKED; | |
3596 | ||
ec68307c | 3597 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3598 | |
a460e745 IM |
3599 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3600 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3601 | |
3602 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3603 | } |
497c9a19 | 3604 | return err; |
8b955b0d EB |
3605 | } |
3606 | #endif /* CONFIG_HT_IRQ */ | |
3607 | ||
9d6a4d08 YL |
3608 | int __init io_apic_get_redir_entries (int ioapic) |
3609 | { | |
3610 | union IO_APIC_reg_01 reg_01; | |
3611 | unsigned long flags; | |
3612 | ||
dade7716 | 3613 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3614 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3615 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3616 | |
4b6b19a1 EB |
3617 | /* The register returns the maximum index redir index |
3618 | * supported, which is one less than the total number of redir | |
3619 | * entries. | |
3620 | */ | |
3621 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3622 | } |
3623 | ||
23f9b267 | 3624 | static void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3625 | { |
4afc51a8 | 3626 | int nr; |
be5d5350 | 3627 | |
a4384df3 | 3628 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3629 | if (nr > nr_irqs_gsi) |
be5d5350 | 3630 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3631 | |
3632 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3633 | } |
3634 | ||
7b586d71 JF |
3635 | int get_nr_irqs_gsi(void) |
3636 | { | |
3637 | return nr_irqs_gsi; | |
3638 | } | |
3639 | ||
4a046d17 YL |
3640 | #ifdef CONFIG_SPARSE_IRQ |
3641 | int __init arch_probe_nr_irqs(void) | |
3642 | { | |
3643 | int nr; | |
3644 | ||
f1ee5548 YL |
3645 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3646 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3647 | |
f1ee5548 YL |
3648 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3649 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3650 | /* | |
3651 | * for MSI and HT dyn irq | |
3652 | */ | |
3653 | nr += nr_irqs_gsi * 16; | |
3654 | #endif | |
3655 | if (nr < nr_irqs) | |
4a046d17 YL |
3656 | nr_irqs = nr; |
3657 | ||
b683de2b | 3658 | return NR_IRQS_LEGACY; |
4a046d17 YL |
3659 | } |
3660 | #endif | |
3661 | ||
e5198075 YL |
3662 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3663 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3664 | { |
5ef21837 YL |
3665 | struct irq_cfg *cfg; |
3666 | int node; | |
e5198075 YL |
3667 | int ioapic, pin; |
3668 | int trigger, polarity; | |
5ef21837 | 3669 | |
e5198075 | 3670 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3671 | if (!IO_APIC_IRQ(irq)) { |
3672 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3673 | ioapic); | |
3674 | return -EINVAL; | |
3675 | } | |
3676 | ||
3677 | if (dev) | |
3678 | node = dev_to_node(dev); | |
3679 | else | |
f6e9456c | 3680 | node = cpu_to_node(0); |
5ef21837 | 3681 | |
fbc6bff0 TG |
3682 | cfg = alloc_irq_and_cfg_at(irq, node); |
3683 | if (!cfg) | |
5ef21837 | 3684 | return 0; |
5ef21837 | 3685 | |
e5198075 YL |
3686 | pin = irq_attr->ioapic_pin; |
3687 | trigger = irq_attr->trigger; | |
3688 | polarity = irq_attr->polarity; | |
3689 | ||
5ef21837 YL |
3690 | /* |
3691 | * IRQs < 16 are already in the irq_2_pin[] map | |
3692 | */ | |
b81bb373 | 3693 | if (irq >= legacy_pic->nr_legacy_irqs) { |
7e495529 | 3694 | if (__add_pin_to_irq_node(cfg, node, ioapic, pin)) { |
f3d1915a CG |
3695 | printk(KERN_INFO "can not add pin %d for irq %d\n", |
3696 | pin, irq); | |
3697 | return 0; | |
3698 | } | |
5ef21837 YL |
3699 | } |
3700 | ||
60c69948 | 3701 | setup_ioapic_irq(ioapic, pin, irq, cfg, trigger, polarity); |
5ef21837 YL |
3702 | |
3703 | return 0; | |
3704 | } | |
3705 | ||
e5198075 YL |
3706 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3707 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3708 | { |
e5198075 | 3709 | int ioapic, pin; |
5ef21837 YL |
3710 | /* |
3711 | * Avoid pin reprogramming. PRTs typically include entries | |
3712 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3713 | * we only program the IOAPIC on the first. | |
3714 | */ | |
e5198075 YL |
3715 | ioapic = irq_attr->ioapic; |
3716 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3717 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3718 | pr_debug("Pin %d-%d already programmed\n", | |
3719 | mp_ioapics[ioapic].apicid, pin); | |
3720 | return 0; | |
3721 | } | |
3722 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3723 | ||
e5198075 | 3724 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3725 | } |
3726 | ||
2a4ab640 FT |
3727 | u8 __init io_apic_unique_id(u8 id) |
3728 | { | |
3729 | #ifdef CONFIG_X86_32 | |
3730 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3731 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3732 | return io_apic_get_unique_id(nr_ioapics, id); | |
3733 | else | |
3734 | return id; | |
3735 | #else | |
3736 | int i; | |
3737 | DECLARE_BITMAP(used, 256); | |
1da177e4 | 3738 | |
2a4ab640 FT |
3739 | bitmap_zero(used, 256); |
3740 | for (i = 0; i < nr_ioapics; i++) { | |
3741 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3742 | __set_bit(ia->apicid, used); | |
3743 | } | |
3744 | if (!test_bit(id, used)) | |
3745 | return id; | |
3746 | return find_first_zero_bit(used, 256); | |
3747 | #endif | |
3748 | } | |
1da177e4 | 3749 | |
54168ed7 | 3750 | #ifdef CONFIG_X86_32 |
36062448 | 3751 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3752 | { |
3753 | union IO_APIC_reg_00 reg_00; | |
3754 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3755 | physid_mask_t tmp; | |
3756 | unsigned long flags; | |
3757 | int i = 0; | |
3758 | ||
3759 | /* | |
36062448 PC |
3760 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3761 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3762 | * supports up to 16 on one shared APIC bus. |
36062448 | 3763 | * |
1da177e4 LT |
3764 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3765 | * advantage of new APIC bus architecture. | |
3766 | */ | |
3767 | ||
3768 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3769 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3770 | |
dade7716 | 3771 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3772 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3773 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3774 | |
3775 | if (apic_id >= get_physical_broadcast()) { | |
3776 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3777 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3778 | apic_id = reg_00.bits.ID; | |
3779 | } | |
3780 | ||
3781 | /* | |
36062448 | 3782 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3783 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3784 | */ | |
7abc0753 | 3785 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3786 | |
3787 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3788 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3789 | break; |
3790 | } | |
3791 | ||
3792 | if (i == get_physical_broadcast()) | |
3793 | panic("Max apic_id exceeded!\n"); | |
3794 | ||
3795 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3796 | "trying %d\n", ioapic, apic_id, i); | |
3797 | ||
3798 | apic_id = i; | |
36062448 | 3799 | } |
1da177e4 | 3800 | |
7abc0753 | 3801 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3802 | physids_or(apic_id_map, apic_id_map, tmp); |
3803 | ||
3804 | if (reg_00.bits.ID != apic_id) { | |
3805 | reg_00.bits.ID = apic_id; | |
3806 | ||
dade7716 | 3807 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3808 | io_apic_write(ioapic, 0, reg_00.raw); |
3809 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3810 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3811 | |
3812 | /* Sanity check */ | |
6070f9ec AD |
3813 | if (reg_00.bits.ID != apic_id) { |
3814 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3815 | return -1; | |
3816 | } | |
1da177e4 LT |
3817 | } |
3818 | ||
3819 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3820 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3821 | ||
3822 | return apic_id; | |
3823 | } | |
58f892e0 | 3824 | #endif |
1da177e4 | 3825 | |
36062448 | 3826 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3827 | { |
3828 | union IO_APIC_reg_01 reg_01; | |
3829 | unsigned long flags; | |
3830 | ||
dade7716 | 3831 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3832 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3833 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3834 | |
3835 | return reg_01.bits.version; | |
3836 | } | |
3837 | ||
9a0a91bb | 3838 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 3839 | { |
9a0a91bb | 3840 | int ioapic, pin, idx; |
61fd47e0 SL |
3841 | |
3842 | if (skip_ioapic_setup) | |
3843 | return -1; | |
3844 | ||
9a0a91bb EB |
3845 | ioapic = mp_find_ioapic(gsi); |
3846 | if (ioapic < 0) | |
61fd47e0 SL |
3847 | return -1; |
3848 | ||
9a0a91bb EB |
3849 | pin = mp_find_ioapic_pin(ioapic, gsi); |
3850 | if (pin < 0) | |
3851 | return -1; | |
3852 | ||
3853 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
3854 | if (idx < 0) | |
61fd47e0 SL |
3855 | return -1; |
3856 | ||
9a0a91bb EB |
3857 | *trigger = irq_trigger(idx); |
3858 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
3859 | return 0; |
3860 | } | |
3861 | ||
497c9a19 YL |
3862 | /* |
3863 | * This function currently is only a helper for the i386 smp boot process where | |
3864 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 3865 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
3866 | */ |
3867 | #ifdef CONFIG_SMP | |
3868 | void __init setup_ioapic_dest(void) | |
3869 | { | |
fad53995 | 3870 | int pin, ioapic, irq, irq_entry; |
6c2e9403 | 3871 | struct irq_desc *desc; |
22f65d31 | 3872 | const struct cpumask *mask; |
497c9a19 YL |
3873 | |
3874 | if (skip_ioapic_setup == 1) | |
3875 | return; | |
3876 | ||
fad53995 | 3877 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b9c61b70 YL |
3878 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
3879 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
3880 | if (irq_entry == -1) | |
3881 | continue; | |
3882 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 3883 | |
fad53995 EB |
3884 | if ((ioapic > 0) && (irq > 16)) |
3885 | continue; | |
3886 | ||
b9c61b70 | 3887 | desc = irq_to_desc(irq); |
6c2e9403 | 3888 | |
b9c61b70 YL |
3889 | /* |
3890 | * Honour affinities which have been set in early boot | |
3891 | */ | |
3892 | if (desc->status & | |
3893 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
f7e909ea | 3894 | mask = desc->irq_data.affinity; |
b9c61b70 YL |
3895 | else |
3896 | mask = apic->target_cpus(); | |
497c9a19 | 3897 | |
b9c61b70 | 3898 | if (intr_remapping_enabled) |
f19f5ecc | 3899 | ir_ioapic_set_affinity(&desc->irq_data, mask, false); |
b9c61b70 | 3900 | else |
f7e909ea | 3901 | ioapic_set_affinity(&desc->irq_data, mask, false); |
497c9a19 | 3902 | } |
b9c61b70 | 3903 | |
497c9a19 YL |
3904 | } |
3905 | #endif | |
3906 | ||
54168ed7 IM |
3907 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3908 | ||
3909 | static struct resource *ioapic_resources; | |
3910 | ||
ffc43836 | 3911 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
3912 | { |
3913 | unsigned long n; | |
3914 | struct resource *res; | |
3915 | char *mem; | |
3916 | int i; | |
3917 | ||
3918 | if (nr_ioapics <= 0) | |
3919 | return NULL; | |
3920 | ||
3921 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3922 | n *= nr_ioapics; | |
3923 | ||
3924 | mem = alloc_bootmem(n); | |
3925 | res = (void *)mem; | |
3926 | ||
ffc43836 | 3927 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 3928 | |
ffc43836 CG |
3929 | for (i = 0; i < nr_ioapics; i++) { |
3930 | res[i].name = mem; | |
3931 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 3932 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 3933 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
3934 | } |
3935 | ||
3936 | ioapic_resources = res; | |
3937 | ||
3938 | return res; | |
3939 | } | |
54168ed7 | 3940 | |
23f9b267 | 3941 | void __init ioapic_and_gsi_init(void) |
f3294a33 YL |
3942 | { |
3943 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 3944 | struct resource *ioapic_res; |
d6c88a50 | 3945 | int i; |
f3294a33 | 3946 | |
ffc43836 | 3947 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
3948 | for (i = 0; i < nr_ioapics; i++) { |
3949 | if (smp_found_config) { | |
b5ba7e6d | 3950 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 3951 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
3952 | if (!ioapic_phys) { |
3953 | printk(KERN_ERR | |
3954 | "WARNING: bogus zero IO-APIC " | |
3955 | "address found in MPTABLE, " | |
3956 | "disabling IO/APIC support!\n"); | |
3957 | smp_found_config = 0; | |
3958 | skip_ioapic_setup = 1; | |
3959 | goto fake_ioapic_page; | |
3960 | } | |
54168ed7 | 3961 | #endif |
f3294a33 | 3962 | } else { |
54168ed7 | 3963 | #ifdef CONFIG_X86_32 |
f3294a33 | 3964 | fake_ioapic_page: |
54168ed7 | 3965 | #endif |
e79c65a9 | 3966 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3967 | ioapic_phys = __pa(ioapic_phys); |
3968 | } | |
3969 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
3970 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
3971 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
3972 | ioapic_phys); | |
f3294a33 | 3973 | idx++; |
54168ed7 | 3974 | |
ffc43836 | 3975 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 3976 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 3977 | ioapic_res++; |
f3294a33 | 3978 | } |
23f9b267 TG |
3979 | |
3980 | probe_nr_irqs_gsi(); | |
f3294a33 YL |
3981 | } |
3982 | ||
857fdc53 | 3983 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
3984 | { |
3985 | int i; | |
3986 | struct resource *r = ioapic_resources; | |
3987 | ||
3988 | if (!r) { | |
857fdc53 | 3989 | if (nr_ioapics > 0) |
04c93ce4 BZ |
3990 | printk(KERN_ERR |
3991 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 3992 | return; |
54168ed7 IM |
3993 | } |
3994 | ||
3995 | for (i = 0; i < nr_ioapics; i++) { | |
3996 | insert_resource(&iomem_resource, r); | |
3997 | r++; | |
3998 | } | |
54168ed7 | 3999 | } |
2a4ab640 | 4000 | |
eddb0c55 | 4001 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
4002 | { |
4003 | int i = 0; | |
4004 | ||
678301ec PB |
4005 | if (nr_ioapics == 0) |
4006 | return -1; | |
4007 | ||
2a4ab640 FT |
4008 | /* Find the IOAPIC that manages this GSI. */ |
4009 | for (i = 0; i < nr_ioapics; i++) { | |
4010 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
4011 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
4012 | return i; | |
4013 | } | |
54168ed7 | 4014 | |
2a4ab640 FT |
4015 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
4016 | return -1; | |
4017 | } | |
4018 | ||
eddb0c55 | 4019 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 FT |
4020 | { |
4021 | if (WARN_ON(ioapic == -1)) | |
4022 | return -1; | |
4023 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
4024 | return -1; | |
4025 | ||
4026 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
4027 | } | |
4028 | ||
4029 | static int bad_ioapic(unsigned long address) | |
4030 | { | |
4031 | if (nr_ioapics >= MAX_IO_APICS) { | |
4032 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
4033 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
4034 | return 1; | |
4035 | } | |
4036 | if (!address) { | |
4037 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
4038 | " found in table, skipping!\n"); | |
4039 | return 1; | |
4040 | } | |
54168ed7 IM |
4041 | return 0; |
4042 | } | |
4043 | ||
2a4ab640 FT |
4044 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4045 | { | |
4046 | int idx = 0; | |
7716a5c4 | 4047 | int entries; |
2a4ab640 FT |
4048 | |
4049 | if (bad_ioapic(address)) | |
4050 | return; | |
4051 | ||
4052 | idx = nr_ioapics; | |
4053 | ||
4054 | mp_ioapics[idx].type = MP_IOAPIC; | |
4055 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4056 | mp_ioapics[idx].apicaddr = address; | |
4057 | ||
4058 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4059 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4060 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4061 | ||
4062 | /* | |
4063 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4064 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4065 | */ | |
7716a5c4 | 4066 | entries = io_apic_get_redir_entries(idx); |
2a4ab640 | 4067 | mp_gsi_routing[idx].gsi_base = gsi_base; |
7716a5c4 EB |
4068 | mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1; |
4069 | ||
4070 | /* | |
4071 | * The number of IO-APIC IRQ registers (== #pins): | |
4072 | */ | |
4073 | nr_ioapic_registers[idx] = entries; | |
2a4ab640 | 4074 | |
a4384df3 EB |
4075 | if (mp_gsi_routing[idx].gsi_end >= gsi_top) |
4076 | gsi_top = mp_gsi_routing[idx].gsi_end + 1; | |
2a4ab640 FT |
4077 | |
4078 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4079 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4080 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4081 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4082 | ||
4083 | nr_ioapics++; | |
4084 | } | |
05ddafb1 JP |
4085 | |
4086 | /* Enable IOAPIC early just for system timer */ | |
4087 | void __init pre_init_apic_IRQ0(void) | |
4088 | { | |
4089 | struct irq_cfg *cfg; | |
05ddafb1 JP |
4090 | |
4091 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
4092 | #ifndef CONFIG_SMP | |
cb2ded37 YL |
4093 | physid_set_mask_of_physid(boot_cpu_physical_apicid, |
4094 | &phys_cpu_present_map); | |
05ddafb1 | 4095 | #endif |
fbc6bff0 TG |
4096 | /* Make sure the irq descriptor is set up */ |
4097 | cfg = alloc_irq_and_cfg_at(0, 0); | |
05ddafb1 JP |
4098 | |
4099 | setup_local_APIC(); | |
4100 | ||
05ddafb1 JP |
4101 | add_pin_to_irq_node(cfg, 0, 0, 0); |
4102 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); | |
4103 | ||
60c69948 | 4104 | setup_ioapic_irq(0, 0, 0, cfg, 0, 0); |
05ddafb1 | 4105 | } |