Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
4173a0e7 DN |
62 | #include <asm/uv/uv_hub.h> |
63 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 64 | |
7b6aa335 | 65 | #include <asm/apic.h> |
1da177e4 | 66 | |
32f71aff MR |
67 | #define __apicdebuginit(type) static type __init |
68 | ||
1da177e4 | 69 | /* |
54168ed7 IM |
70 | * Is the SiS APIC rmw bug present ? |
71 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
72 | */ |
73 | int sis_apic_bug = -1; | |
74 | ||
efa2559f YL |
75 | static DEFINE_SPINLOCK(ioapic_lock); |
76 | static DEFINE_SPINLOCK(vector_lock); | |
77 | ||
1da177e4 LT |
78 | /* |
79 | * # of IRQ routing registers | |
80 | */ | |
81 | int nr_ioapic_registers[MAX_IO_APICS]; | |
82 | ||
9f640ccb | 83 | /* I/O APIC entries */ |
b5ba7e6d | 84 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
85 | int nr_ioapics; |
86 | ||
584f734d | 87 | /* MP IRQ source entries */ |
c2c21745 | 88 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
89 | |
90 | /* # of MP IRQ source entries */ | |
91 | int mp_irq_entries; | |
92 | ||
8732fc4b AS |
93 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
94 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
95 | #endif | |
96 | ||
97 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
98 | ||
efa2559f YL |
99 | int skip_ioapic_setup; |
100 | ||
65a4e574 IM |
101 | void arch_disable_smp_support(void) |
102 | { | |
103 | #ifdef CONFIG_PCI | |
104 | noioapicquirk = 1; | |
105 | noioapicreroute = -1; | |
106 | #endif | |
107 | skip_ioapic_setup = 1; | |
108 | } | |
109 | ||
54168ed7 | 110 | static int __init parse_noapic(char *str) |
efa2559f YL |
111 | { |
112 | /* disable IO-APIC */ | |
65a4e574 | 113 | arch_disable_smp_support(); |
efa2559f YL |
114 | return 0; |
115 | } | |
116 | early_param("noapic", parse_noapic); | |
66759a01 | 117 | |
0f978f45 | 118 | struct irq_pin_list; |
0b8f1efa YL |
119 | |
120 | /* | |
121 | * This is performance-critical, we want to do it O(1) | |
122 | * | |
123 | * the indexing order of this array favors 1:1 mappings | |
124 | * between pins and IRQs. | |
125 | */ | |
126 | ||
127 | struct irq_pin_list { | |
128 | int apic, pin; | |
129 | struct irq_pin_list *next; | |
130 | }; | |
131 | ||
132 | static struct irq_pin_list *get_one_free_irq_2_pin(int cpu) | |
133 | { | |
134 | struct irq_pin_list *pin; | |
135 | int node; | |
136 | ||
137 | node = cpu_to_node(cpu); | |
138 | ||
139 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
140 | |
141 | return pin; | |
142 | } | |
143 | ||
a1420f39 | 144 | struct irq_cfg { |
0f978f45 | 145 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
146 | cpumask_var_t domain; |
147 | cpumask_var_t old_domain; | |
497c9a19 | 148 | unsigned move_cleanup_count; |
a1420f39 | 149 | u8 vector; |
497c9a19 | 150 | u8 move_in_progress : 1; |
a1420f39 YL |
151 | }; |
152 | ||
a1420f39 | 153 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
154 | #ifdef CONFIG_SPARSE_IRQ |
155 | static struct irq_cfg irq_cfgx[] = { | |
156 | #else | |
d6c88a50 | 157 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 158 | #endif |
22f65d31 MT |
159 | [0] = { .vector = IRQ0_VECTOR, }, |
160 | [1] = { .vector = IRQ1_VECTOR, }, | |
161 | [2] = { .vector = IRQ2_VECTOR, }, | |
162 | [3] = { .vector = IRQ3_VECTOR, }, | |
163 | [4] = { .vector = IRQ4_VECTOR, }, | |
164 | [5] = { .vector = IRQ5_VECTOR, }, | |
165 | [6] = { .vector = IRQ6_VECTOR, }, | |
166 | [7] = { .vector = IRQ7_VECTOR, }, | |
167 | [8] = { .vector = IRQ8_VECTOR, }, | |
168 | [9] = { .vector = IRQ9_VECTOR, }, | |
169 | [10] = { .vector = IRQ10_VECTOR, }, | |
170 | [11] = { .vector = IRQ11_VECTOR, }, | |
171 | [12] = { .vector = IRQ12_VECTOR, }, | |
172 | [13] = { .vector = IRQ13_VECTOR, }, | |
173 | [14] = { .vector = IRQ14_VECTOR, }, | |
174 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
175 | }; |
176 | ||
13a0c3c2 | 177 | int __init arch_early_irq_init(void) |
8f09cd20 | 178 | { |
0b8f1efa YL |
179 | struct irq_cfg *cfg; |
180 | struct irq_desc *desc; | |
181 | int count; | |
182 | int i; | |
d6c88a50 | 183 | |
0b8f1efa YL |
184 | cfg = irq_cfgx; |
185 | count = ARRAY_SIZE(irq_cfgx); | |
8f09cd20 | 186 | |
0b8f1efa YL |
187 | for (i = 0; i < count; i++) { |
188 | desc = irq_to_desc(i); | |
189 | desc->chip_data = &cfg[i]; | |
22f65d31 MT |
190 | alloc_bootmem_cpumask_var(&cfg[i].domain); |
191 | alloc_bootmem_cpumask_var(&cfg[i].old_domain); | |
192 | if (i < NR_IRQS_LEGACY) | |
193 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 194 | } |
13a0c3c2 YL |
195 | |
196 | return 0; | |
0b8f1efa | 197 | } |
8f09cd20 | 198 | |
0b8f1efa | 199 | #ifdef CONFIG_SPARSE_IRQ |
d6c88a50 | 200 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 201 | { |
0b8f1efa YL |
202 | struct irq_cfg *cfg = NULL; |
203 | struct irq_desc *desc; | |
1da177e4 | 204 | |
0b8f1efa YL |
205 | desc = irq_to_desc(irq); |
206 | if (desc) | |
207 | cfg = desc->chip_data; | |
0f978f45 | 208 | |
0b8f1efa | 209 | return cfg; |
8f09cd20 | 210 | } |
d6c88a50 | 211 | |
0b8f1efa | 212 | static struct irq_cfg *get_one_free_irq_cfg(int cpu) |
8f09cd20 | 213 | { |
0b8f1efa YL |
214 | struct irq_cfg *cfg; |
215 | int node; | |
216 | ||
217 | node = cpu_to_node(cpu); | |
0f978f45 | 218 | |
0b8f1efa | 219 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 220 | if (cfg) { |
80855f73 | 221 | if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
222 | kfree(cfg); |
223 | cfg = NULL; | |
80855f73 MT |
224 | } else if (!alloc_cpumask_var_node(&cfg->old_domain, |
225 | GFP_ATOMIC, node)) { | |
22f65d31 MT |
226 | free_cpumask_var(cfg->domain); |
227 | kfree(cfg); | |
228 | cfg = NULL; | |
229 | } else { | |
230 | cpumask_clear(cfg->domain); | |
231 | cpumask_clear(cfg->old_domain); | |
232 | } | |
233 | } | |
0f978f45 | 234 | |
0b8f1efa | 235 | return cfg; |
8f09cd20 YL |
236 | } |
237 | ||
13a0c3c2 | 238 | int arch_init_chip_data(struct irq_desc *desc, int cpu) |
0f978f45 | 239 | { |
0b8f1efa | 240 | struct irq_cfg *cfg; |
d6c88a50 | 241 | |
0b8f1efa YL |
242 | cfg = desc->chip_data; |
243 | if (!cfg) { | |
244 | desc->chip_data = get_one_free_irq_cfg(cpu); | |
245 | if (!desc->chip_data) { | |
246 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
247 | BUG_ON(1); | |
248 | } | |
249 | } | |
1da177e4 | 250 | |
13a0c3c2 | 251 | return 0; |
0b8f1efa | 252 | } |
0f978f45 | 253 | |
fcef5911 | 254 | /* for move_irq_desc */ |
48a1b10a YL |
255 | static void |
256 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu) | |
0f978f45 | 257 | { |
48a1b10a YL |
258 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
259 | ||
260 | cfg->irq_2_pin = NULL; | |
261 | old_entry = old_cfg->irq_2_pin; | |
262 | if (!old_entry) | |
263 | return; | |
0f978f45 | 264 | |
48a1b10a YL |
265 | entry = get_one_free_irq_2_pin(cpu); |
266 | if (!entry) | |
267 | return; | |
0f978f45 | 268 | |
48a1b10a YL |
269 | entry->apic = old_entry->apic; |
270 | entry->pin = old_entry->pin; | |
271 | head = entry; | |
272 | tail = entry; | |
273 | old_entry = old_entry->next; | |
274 | while (old_entry) { | |
275 | entry = get_one_free_irq_2_pin(cpu); | |
276 | if (!entry) { | |
277 | entry = head; | |
278 | while (entry) { | |
279 | head = entry->next; | |
280 | kfree(entry); | |
281 | entry = head; | |
282 | } | |
283 | /* still use the old one */ | |
284 | return; | |
285 | } | |
286 | entry->apic = old_entry->apic; | |
287 | entry->pin = old_entry->pin; | |
288 | tail->next = entry; | |
289 | tail = entry; | |
290 | old_entry = old_entry->next; | |
291 | } | |
0f978f45 | 292 | |
48a1b10a YL |
293 | tail->next = NULL; |
294 | cfg->irq_2_pin = head; | |
0f978f45 | 295 | } |
0f978f45 | 296 | |
48a1b10a | 297 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 298 | { |
48a1b10a | 299 | struct irq_pin_list *entry, *next; |
0f978f45 | 300 | |
48a1b10a YL |
301 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
302 | return; | |
301e6190 | 303 | |
48a1b10a | 304 | entry = old_cfg->irq_2_pin; |
0f978f45 | 305 | |
48a1b10a YL |
306 | while (entry) { |
307 | next = entry->next; | |
308 | kfree(entry); | |
309 | entry = next; | |
310 | } | |
311 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 312 | } |
0f978f45 | 313 | |
48a1b10a YL |
314 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
315 | struct irq_desc *desc, int cpu) | |
0f978f45 | 316 | { |
48a1b10a YL |
317 | struct irq_cfg *cfg; |
318 | struct irq_cfg *old_cfg; | |
0f978f45 | 319 | |
48a1b10a | 320 | cfg = get_one_free_irq_cfg(cpu); |
301e6190 | 321 | |
48a1b10a YL |
322 | if (!cfg) |
323 | return; | |
324 | ||
325 | desc->chip_data = cfg; | |
326 | ||
327 | old_cfg = old_desc->chip_data; | |
328 | ||
329 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
330 | ||
331 | init_copy_irq_2_pin(old_cfg, cfg, cpu); | |
0f978f45 | 332 | } |
1da177e4 | 333 | |
48a1b10a YL |
334 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
335 | { | |
336 | kfree(old_cfg); | |
337 | } | |
338 | ||
339 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
340 | { | |
341 | struct irq_cfg *old_cfg, *cfg; | |
342 | ||
343 | old_cfg = old_desc->chip_data; | |
344 | cfg = desc->chip_data; | |
345 | ||
346 | if (old_cfg == cfg) | |
347 | return; | |
348 | ||
349 | if (old_cfg) { | |
350 | free_irq_2_pin(old_cfg, cfg); | |
351 | free_irq_cfg(old_cfg); | |
352 | old_desc->chip_data = NULL; | |
353 | } | |
354 | } | |
fcef5911 | 355 | /* end for move_irq_desc */ |
48a1b10a | 356 | |
0b8f1efa YL |
357 | #else |
358 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
359 | { | |
360 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 361 | } |
1da177e4 | 362 | |
0b8f1efa YL |
363 | #endif |
364 | ||
130fe05d LT |
365 | struct io_apic { |
366 | unsigned int index; | |
367 | unsigned int unused[3]; | |
368 | unsigned int data; | |
0280f7c4 SS |
369 | unsigned int unused2[11]; |
370 | unsigned int eoi; | |
130fe05d LT |
371 | }; |
372 | ||
373 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
374 | { | |
375 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 376 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
377 | } |
378 | ||
0280f7c4 SS |
379 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
380 | { | |
381 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
382 | writel(vector, &io_apic->eoi); | |
383 | } | |
384 | ||
130fe05d LT |
385 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
386 | { | |
387 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
388 | writel(reg, &io_apic->index); | |
389 | return readl(&io_apic->data); | |
390 | } | |
391 | ||
392 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
393 | { | |
394 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
395 | writel(reg, &io_apic->index); | |
396 | writel(value, &io_apic->data); | |
397 | } | |
398 | ||
399 | /* | |
400 | * Re-write a value: to be used for read-modify-write | |
401 | * cycles where the read already set up the index register. | |
402 | * | |
403 | * Older SiS APIC requires we rewrite the index register | |
404 | */ | |
405 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
406 | { | |
54168ed7 | 407 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
408 | |
409 | if (sis_apic_bug) | |
410 | writel(reg, &io_apic->index); | |
130fe05d LT |
411 | writel(value, &io_apic->data); |
412 | } | |
413 | ||
3145e941 | 414 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
415 | { |
416 | struct irq_pin_list *entry; | |
417 | unsigned long flags; | |
047c8fdb YL |
418 | |
419 | spin_lock_irqsave(&ioapic_lock, flags); | |
420 | entry = cfg->irq_2_pin; | |
421 | for (;;) { | |
422 | unsigned int reg; | |
423 | int pin; | |
424 | ||
425 | if (!entry) | |
426 | break; | |
427 | pin = entry->pin; | |
428 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
429 | /* Is the remote IRR bit set? */ | |
430 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
431 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
432 | return true; | |
433 | } | |
434 | if (!entry->next) | |
435 | break; | |
436 | entry = entry->next; | |
437 | } | |
438 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
439 | ||
440 | return false; | |
441 | } | |
047c8fdb | 442 | |
cf4c6a2f AK |
443 | union entry_union { |
444 | struct { u32 w1, w2; }; | |
445 | struct IO_APIC_route_entry entry; | |
446 | }; | |
447 | ||
448 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
449 | { | |
450 | union entry_union eu; | |
451 | unsigned long flags; | |
452 | spin_lock_irqsave(&ioapic_lock, flags); | |
453 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
454 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
455 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
456 | return eu.entry; | |
457 | } | |
458 | ||
f9dadfa7 LT |
459 | /* |
460 | * When we write a new IO APIC routing entry, we need to write the high | |
461 | * word first! If the mask bit in the low word is clear, we will enable | |
462 | * the interrupt, and we need to make sure the entry is fully populated | |
463 | * before that happens. | |
464 | */ | |
d15512f4 AK |
465 | static void |
466 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 467 | { |
cf4c6a2f AK |
468 | union entry_union eu; |
469 | eu.entry = e; | |
f9dadfa7 LT |
470 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
471 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
472 | } |
473 | ||
ca97ab90 | 474 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
475 | { |
476 | unsigned long flags; | |
477 | spin_lock_irqsave(&ioapic_lock, flags); | |
478 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
479 | spin_unlock_irqrestore(&ioapic_lock, flags); |
480 | } | |
481 | ||
482 | /* | |
483 | * When we mask an IO APIC routing entry, we need to write the low | |
484 | * word first, in order to set the mask bit before we change the | |
485 | * high bits! | |
486 | */ | |
487 | static void ioapic_mask_entry(int apic, int pin) | |
488 | { | |
489 | unsigned long flags; | |
490 | union entry_union eu = { .entry.mask = 1 }; | |
491 | ||
cf4c6a2f AK |
492 | spin_lock_irqsave(&ioapic_lock, flags); |
493 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
494 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
495 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
496 | } | |
497 | ||
497c9a19 | 498 | #ifdef CONFIG_SMP |
22f65d31 MT |
499 | static void send_cleanup_vector(struct irq_cfg *cfg) |
500 | { | |
501 | cpumask_var_t cleanup_mask; | |
502 | ||
503 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
504 | unsigned int i; | |
505 | cfg->move_cleanup_count = 0; | |
506 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
507 | cfg->move_cleanup_count++; | |
508 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
dac5f412 | 509 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); |
22f65d31 MT |
510 | } else { |
511 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
512 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
dac5f412 | 513 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
22f65d31 MT |
514 | free_cpumask_var(cleanup_mask); |
515 | } | |
516 | cfg->move_in_progress = 0; | |
517 | } | |
518 | ||
3145e941 | 519 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
497c9a19 YL |
520 | { |
521 | int apic, pin; | |
497c9a19 | 522 | struct irq_pin_list *entry; |
3145e941 | 523 | u8 vector = cfg->vector; |
497c9a19 | 524 | |
497c9a19 YL |
525 | entry = cfg->irq_2_pin; |
526 | for (;;) { | |
527 | unsigned int reg; | |
528 | ||
529 | if (!entry) | |
530 | break; | |
531 | ||
532 | apic = entry->apic; | |
533 | pin = entry->pin; | |
54168ed7 IM |
534 | /* |
535 | * With interrupt-remapping, destination information comes | |
536 | * from interrupt-remapping table entry. | |
537 | */ | |
538 | if (!irq_remapped(irq)) | |
539 | io_apic_write(apic, 0x11 + pin*2, dest); | |
497c9a19 YL |
540 | reg = io_apic_read(apic, 0x10 + pin*2); |
541 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
542 | reg |= vector; | |
54168ed7 | 543 | io_apic_modify(apic, 0x10 + pin*2, reg); |
497c9a19 YL |
544 | if (!entry->next) |
545 | break; | |
546 | entry = entry->next; | |
547 | } | |
548 | } | |
efa2559f | 549 | |
e7986739 MT |
550 | static int |
551 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
efa2559f | 552 | |
22f65d31 | 553 | /* |
debccb3e IM |
554 | * Either sets desc->affinity to a valid value, and returns |
555 | * ->cpu_mask_to_apicid of that, or returns BAD_APICID and | |
556 | * leaves desc->affinity untouched. | |
22f65d31 MT |
557 | */ |
558 | static unsigned int | |
559 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 YL |
560 | { |
561 | struct irq_cfg *cfg; | |
3145e941 | 562 | unsigned int irq; |
497c9a19 | 563 | |
0de26520 | 564 | if (!cpumask_intersects(mask, cpu_online_mask)) |
22f65d31 | 565 | return BAD_APICID; |
497c9a19 | 566 | |
3145e941 YL |
567 | irq = desc->irq; |
568 | cfg = desc->chip_data; | |
569 | if (assign_irq_vector(irq, cfg, mask)) | |
22f65d31 | 570 | return BAD_APICID; |
497c9a19 | 571 | |
e06b1b56 RR |
572 | cpumask_copy(desc->affinity, mask); |
573 | ||
574 | return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); | |
22f65d31 | 575 | } |
3145e941 | 576 | |
d5dedd45 | 577 | static int |
22f65d31 | 578 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 YL |
579 | { |
580 | struct irq_cfg *cfg; | |
581 | unsigned long flags; | |
582 | unsigned int dest; | |
22f65d31 | 583 | unsigned int irq; |
d5dedd45 | 584 | int ret = -1; |
497c9a19 | 585 | |
22f65d31 MT |
586 | irq = desc->irq; |
587 | cfg = desc->chip_data; | |
497c9a19 | 588 | |
497c9a19 | 589 | spin_lock_irqsave(&ioapic_lock, flags); |
22f65d31 MT |
590 | dest = set_desc_affinity(desc, mask); |
591 | if (dest != BAD_APICID) { | |
592 | /* Only the high 8 bits are valid. */ | |
593 | dest = SET_APIC_LOGICAL_ID(dest); | |
594 | __target_IO_APIC_irq(irq, dest, cfg); | |
d5dedd45 | 595 | ret = 0; |
22f65d31 | 596 | } |
497c9a19 | 597 | spin_unlock_irqrestore(&ioapic_lock, flags); |
d5dedd45 YL |
598 | |
599 | return ret; | |
497c9a19 | 600 | } |
497c9a19 | 601 | |
d5dedd45 | 602 | static int |
22f65d31 | 603 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
3145e941 YL |
604 | { |
605 | struct irq_desc *desc; | |
497c9a19 | 606 | |
54168ed7 | 607 | desc = irq_to_desc(irq); |
3145e941 | 608 | |
d5dedd45 | 609 | return set_ioapic_affinity_irq_desc(desc, mask); |
497c9a19 | 610 | } |
497c9a19 YL |
611 | #endif /* CONFIG_SMP */ |
612 | ||
1da177e4 LT |
613 | /* |
614 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
615 | * shared ISA-space IRQs, so we have to support them. We are super | |
616 | * fast in the common case, and fast for shared ISA-space IRQs. | |
617 | */ | |
3145e941 | 618 | static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin) |
1da177e4 | 619 | { |
0f978f45 YL |
620 | struct irq_pin_list *entry; |
621 | ||
0f978f45 YL |
622 | entry = cfg->irq_2_pin; |
623 | if (!entry) { | |
0b8f1efa YL |
624 | entry = get_one_free_irq_2_pin(cpu); |
625 | if (!entry) { | |
626 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
627 | apic, pin); | |
628 | return; | |
629 | } | |
0f978f45 YL |
630 | cfg->irq_2_pin = entry; |
631 | entry->apic = apic; | |
632 | entry->pin = pin; | |
0f978f45 YL |
633 | return; |
634 | } | |
1da177e4 | 635 | |
0f978f45 YL |
636 | while (entry->next) { |
637 | /* not again, please */ | |
638 | if (entry->apic == apic && entry->pin == pin) | |
639 | return; | |
1da177e4 | 640 | |
0f978f45 | 641 | entry = entry->next; |
1da177e4 | 642 | } |
0f978f45 | 643 | |
0b8f1efa | 644 | entry->next = get_one_free_irq_2_pin(cpu); |
0f978f45 | 645 | entry = entry->next; |
1da177e4 LT |
646 | entry->apic = apic; |
647 | entry->pin = pin; | |
648 | } | |
649 | ||
650 | /* | |
651 | * Reroute an IRQ to a different pin. | |
652 | */ | |
3145e941 | 653 | static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu, |
1da177e4 LT |
654 | int oldapic, int oldpin, |
655 | int newapic, int newpin) | |
656 | { | |
0f978f45 YL |
657 | struct irq_pin_list *entry = cfg->irq_2_pin; |
658 | int replaced = 0; | |
1da177e4 | 659 | |
0f978f45 | 660 | while (entry) { |
1da177e4 LT |
661 | if (entry->apic == oldapic && entry->pin == oldpin) { |
662 | entry->apic = newapic; | |
663 | entry->pin = newpin; | |
0f978f45 YL |
664 | replaced = 1; |
665 | /* every one is different, right? */ | |
1da177e4 | 666 | break; |
0f978f45 YL |
667 | } |
668 | entry = entry->next; | |
1da177e4 | 669 | } |
0f978f45 YL |
670 | |
671 | /* why? call replace before add? */ | |
672 | if (!replaced) | |
3145e941 | 673 | add_pin_to_irq_cpu(cfg, cpu, newapic, newpin); |
1da177e4 LT |
674 | } |
675 | ||
3145e941 | 676 | static inline void io_apic_modify_irq(struct irq_cfg *cfg, |
87783be4 CG |
677 | int mask_and, int mask_or, |
678 | void (*final)(struct irq_pin_list *entry)) | |
679 | { | |
680 | int pin; | |
87783be4 | 681 | struct irq_pin_list *entry; |
047c8fdb | 682 | |
87783be4 CG |
683 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
684 | unsigned int reg; | |
685 | pin = entry->pin; | |
686 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
687 | reg &= mask_and; | |
688 | reg |= mask_or; | |
689 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
690 | if (final) | |
691 | final(entry); | |
692 | } | |
693 | } | |
047c8fdb | 694 | |
3145e941 | 695 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 696 | { |
3145e941 | 697 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 698 | } |
047c8fdb | 699 | |
4e738e2f | 700 | #ifdef CONFIG_X86_64 |
7f3e632f | 701 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 702 | { |
87783be4 CG |
703 | /* |
704 | * Synchronize the IO-APIC and the CPU by doing | |
705 | * a dummy read from the IO-APIC | |
706 | */ | |
707 | struct io_apic __iomem *io_apic; | |
708 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 709 | readl(&io_apic->data); |
1da177e4 LT |
710 | } |
711 | ||
3145e941 | 712 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 713 | { |
3145e941 | 714 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 CG |
715 | } |
716 | #else /* CONFIG_X86_32 */ | |
3145e941 | 717 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 718 | { |
3145e941 | 719 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL); |
87783be4 | 720 | } |
1da177e4 | 721 | |
3145e941 | 722 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 723 | { |
3145e941 | 724 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
725 | IO_APIC_REDIR_MASKED, NULL); |
726 | } | |
1da177e4 | 727 | |
3145e941 | 728 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 729 | { |
3145e941 | 730 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
731 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
732 | } | |
733 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 734 | |
3145e941 | 735 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 736 | { |
3145e941 | 737 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
738 | unsigned long flags; |
739 | ||
3145e941 YL |
740 | BUG_ON(!cfg); |
741 | ||
1da177e4 | 742 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 743 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
744 | spin_unlock_irqrestore(&ioapic_lock, flags); |
745 | } | |
746 | ||
3145e941 | 747 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 748 | { |
3145e941 | 749 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
750 | unsigned long flags; |
751 | ||
752 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 753 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
754 | spin_unlock_irqrestore(&ioapic_lock, flags); |
755 | } | |
756 | ||
3145e941 YL |
757 | static void mask_IO_APIC_irq(unsigned int irq) |
758 | { | |
759 | struct irq_desc *desc = irq_to_desc(irq); | |
760 | ||
761 | mask_IO_APIC_irq_desc(desc); | |
762 | } | |
763 | static void unmask_IO_APIC_irq(unsigned int irq) | |
764 | { | |
765 | struct irq_desc *desc = irq_to_desc(irq); | |
766 | ||
767 | unmask_IO_APIC_irq_desc(desc); | |
768 | } | |
769 | ||
1da177e4 LT |
770 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
771 | { | |
772 | struct IO_APIC_route_entry entry; | |
36062448 | 773 | |
1da177e4 | 774 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 775 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
776 | if (entry.delivery_mode == dest_SMI) |
777 | return; | |
1da177e4 LT |
778 | /* |
779 | * Disable it in the IO-APIC irq-routing table: | |
780 | */ | |
f9dadfa7 | 781 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
782 | } |
783 | ||
54168ed7 | 784 | static void clear_IO_APIC (void) |
1da177e4 LT |
785 | { |
786 | int apic, pin; | |
787 | ||
788 | for (apic = 0; apic < nr_ioapics; apic++) | |
789 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
790 | clear_IO_APIC_pin(apic, pin); | |
791 | } | |
792 | ||
54168ed7 | 793 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
794 | /* |
795 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
796 | * specific CPU-side IRQs. | |
797 | */ | |
798 | ||
799 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
800 | static int pirq_entries[MAX_PIRQS] = { |
801 | [0 ... MAX_PIRQS - 1] = -1 | |
802 | }; | |
1da177e4 | 803 | |
1da177e4 LT |
804 | static int __init ioapic_pirq_setup(char *str) |
805 | { | |
806 | int i, max; | |
807 | int ints[MAX_PIRQS+1]; | |
808 | ||
809 | get_options(str, ARRAY_SIZE(ints), ints); | |
810 | ||
1da177e4 LT |
811 | apic_printk(APIC_VERBOSE, KERN_INFO |
812 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
813 | max = MAX_PIRQS; | |
814 | if (ints[0] < MAX_PIRQS) | |
815 | max = ints[0]; | |
816 | ||
817 | for (i = 0; i < max; i++) { | |
818 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
819 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
820 | /* | |
821 | * PIRQs are mapped upside down, usually. | |
822 | */ | |
823 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
824 | } | |
825 | return 1; | |
826 | } | |
827 | ||
828 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
829 | #endif /* CONFIG_X86_32 */ |
830 | ||
831 | #ifdef CONFIG_INTR_REMAP | |
b24696bc FY |
832 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
833 | { | |
834 | int apic; | |
835 | struct IO_APIC_route_entry **ioapic_entries; | |
836 | ||
837 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
838 | GFP_ATOMIC); | |
839 | if (!ioapic_entries) | |
840 | return 0; | |
841 | ||
842 | for (apic = 0; apic < nr_ioapics; apic++) { | |
843 | ioapic_entries[apic] = | |
844 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
845 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
846 | if (!ioapic_entries[apic]) | |
847 | goto nomem; | |
848 | } | |
849 | ||
850 | return ioapic_entries; | |
851 | ||
852 | nomem: | |
853 | while (--apic >= 0) | |
854 | kfree(ioapic_entries[apic]); | |
855 | kfree(ioapic_entries); | |
856 | ||
857 | return 0; | |
858 | } | |
54168ed7 IM |
859 | |
860 | /* | |
05c3dc2c | 861 | * Saves all the IO-APIC RTE's |
54168ed7 | 862 | */ |
b24696bc | 863 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 864 | { |
54168ed7 IM |
865 | int apic, pin; |
866 | ||
b24696bc FY |
867 | if (!ioapic_entries) |
868 | return -ENOMEM; | |
54168ed7 IM |
869 | |
870 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
871 | if (!ioapic_entries[apic]) |
872 | return -ENOMEM; | |
54168ed7 | 873 | |
05c3dc2c | 874 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 875 | ioapic_entries[apic][pin] = |
54168ed7 | 876 | ioapic_read_entry(apic, pin); |
b24696bc | 877 | } |
5ffa4eb2 | 878 | |
54168ed7 IM |
879 | return 0; |
880 | } | |
881 | ||
b24696bc FY |
882 | /* |
883 | * Mask all IO APIC entries. | |
884 | */ | |
885 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
886 | { |
887 | int apic, pin; | |
888 | ||
b24696bc FY |
889 | if (!ioapic_entries) |
890 | return; | |
891 | ||
05c3dc2c | 892 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 893 | if (!ioapic_entries[apic]) |
05c3dc2c | 894 | break; |
b24696bc | 895 | |
05c3dc2c SS |
896 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
897 | struct IO_APIC_route_entry entry; | |
898 | ||
b24696bc | 899 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
900 | if (!entry.mask) { |
901 | entry.mask = 1; | |
902 | ioapic_write_entry(apic, pin, entry); | |
903 | } | |
904 | } | |
905 | } | |
906 | } | |
907 | ||
b24696bc FY |
908 | /* |
909 | * Restore IO APIC entries which was saved in ioapic_entries. | |
910 | */ | |
911 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
912 | { |
913 | int apic, pin; | |
914 | ||
b24696bc FY |
915 | if (!ioapic_entries) |
916 | return -ENOMEM; | |
917 | ||
5ffa4eb2 | 918 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
919 | if (!ioapic_entries[apic]) |
920 | return -ENOMEM; | |
921 | ||
54168ed7 IM |
922 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
923 | ioapic_write_entry(apic, pin, | |
b24696bc | 924 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 925 | } |
b24696bc | 926 | return 0; |
54168ed7 IM |
927 | } |
928 | ||
b24696bc FY |
929 | void reinit_intr_remapped_IO_APIC(int intr_remapping, |
930 | struct IO_APIC_route_entry **ioapic_entries) | |
931 | ||
54168ed7 IM |
932 | { |
933 | /* | |
934 | * for now plain restore of previous settings. | |
935 | * TBD: In the case of OS enabling interrupt-remapping, | |
936 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
937 | * table entries. for now, do a plain restore, and wait for | |
938 | * the setup_IO_APIC_irqs() to do proper initialization. | |
939 | */ | |
b24696bc FY |
940 | restore_IO_APIC_setup(ioapic_entries); |
941 | } | |
942 | ||
943 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) | |
944 | { | |
945 | int apic; | |
946 | ||
947 | for (apic = 0; apic < nr_ioapics; apic++) | |
948 | kfree(ioapic_entries[apic]); | |
949 | ||
950 | kfree(ioapic_entries); | |
54168ed7 IM |
951 | } |
952 | #endif | |
1da177e4 LT |
953 | |
954 | /* | |
955 | * Find the IRQ entry number of a certain pin. | |
956 | */ | |
957 | static int find_irq_entry(int apic, int pin, int type) | |
958 | { | |
959 | int i; | |
960 | ||
961 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
962 | if (mp_irqs[i].irqtype == type && |
963 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
964 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
965 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
966 | return i; |
967 | ||
968 | return -1; | |
969 | } | |
970 | ||
971 | /* | |
972 | * Find the pin to which IRQ[irq] (ISA) is connected | |
973 | */ | |
fcfd636a | 974 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
975 | { |
976 | int i; | |
977 | ||
978 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 979 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 980 | |
d27e2b8e | 981 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
982 | (mp_irqs[i].irqtype == type) && |
983 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 984 | |
c2c21745 | 985 | return mp_irqs[i].dstirq; |
1da177e4 LT |
986 | } |
987 | return -1; | |
988 | } | |
989 | ||
fcfd636a EB |
990 | static int __init find_isa_irq_apic(int irq, int type) |
991 | { | |
992 | int i; | |
993 | ||
994 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 995 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 996 | |
73b2961b | 997 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
998 | (mp_irqs[i].irqtype == type) && |
999 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
1000 | break; |
1001 | } | |
1002 | if (i < mp_irq_entries) { | |
1003 | int apic; | |
54168ed7 | 1004 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 1005 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
1006 | return apic; |
1007 | } | |
1008 | } | |
1009 | ||
1010 | return -1; | |
1011 | } | |
1012 | ||
1da177e4 LT |
1013 | /* |
1014 | * Find a specific PCI IRQ entry. | |
1015 | * Not an __init, possibly needed by modules | |
1016 | */ | |
1017 | static int pin_2_irq(int idx, int apic, int pin); | |
1018 | ||
1019 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
1020 | { | |
1021 | int apic, i, best_guess = -1; | |
1022 | ||
54168ed7 IM |
1023 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
1024 | bus, slot, pin); | |
ce6444d3 | 1025 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 1026 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
1027 | return -1; |
1028 | } | |
1029 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 1030 | int lbus = mp_irqs[i].srcbus; |
1da177e4 LT |
1031 | |
1032 | for (apic = 0; apic < nr_ioapics; apic++) | |
c2c21745 JSR |
1033 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || |
1034 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1da177e4 LT |
1035 | break; |
1036 | ||
47cab822 | 1037 | if (!test_bit(lbus, mp_bus_not_pci) && |
c2c21745 | 1038 | !mp_irqs[i].irqtype && |
1da177e4 | 1039 | (bus == lbus) && |
c2c21745 JSR |
1040 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { |
1041 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1da177e4 LT |
1042 | |
1043 | if (!(apic || IO_APIC_IRQ(irq))) | |
1044 | continue; | |
1045 | ||
c2c21745 | 1046 | if (pin == (mp_irqs[i].srcbusirq & 3)) |
1da177e4 LT |
1047 | return irq; |
1048 | /* | |
1049 | * Use the first all-but-pin matching entry as a | |
1050 | * best-guess fuzzy result for broken mptables. | |
1051 | */ | |
1052 | if (best_guess < 0) | |
1053 | best_guess = irq; | |
1054 | } | |
1055 | } | |
1056 | return best_guess; | |
1057 | } | |
54168ed7 | 1058 | |
129f6946 | 1059 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 1060 | |
c0a282c2 | 1061 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
1062 | /* |
1063 | * EISA Edge/Level control register, ELCR | |
1064 | */ | |
1065 | static int EISA_ELCR(unsigned int irq) | |
1066 | { | |
99d093d1 | 1067 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
1068 | unsigned int port = 0x4d0 + (irq >> 3); |
1069 | return (inb(port) >> (irq & 7)) & 1; | |
1070 | } | |
1071 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1072 | "Broken MPtable reports ISA irq %d\n", irq); | |
1073 | return 0; | |
1074 | } | |
54168ed7 | 1075 | |
c0a282c2 | 1076 | #endif |
1da177e4 | 1077 | |
6728801d AS |
1078 | /* ISA interrupts are always polarity zero edge triggered, |
1079 | * when listed as conforming in the MP table. */ | |
1080 | ||
1081 | #define default_ISA_trigger(idx) (0) | |
1082 | #define default_ISA_polarity(idx) (0) | |
1083 | ||
1da177e4 LT |
1084 | /* EISA interrupts are always polarity zero and can be edge or level |
1085 | * trigger depending on the ELCR value. If an interrupt is listed as | |
1086 | * EISA conforming in the MP table, that means its trigger type must | |
1087 | * be read in from the ELCR */ | |
1088 | ||
c2c21745 | 1089 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 1090 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
1091 | |
1092 | /* PCI interrupts are always polarity one level triggered, | |
1093 | * when listed as conforming in the MP table. */ | |
1094 | ||
1095 | #define default_PCI_trigger(idx) (1) | |
1096 | #define default_PCI_polarity(idx) (1) | |
1097 | ||
1098 | /* MCA interrupts are always polarity zero level triggered, | |
1099 | * when listed as conforming in the MP table. */ | |
1100 | ||
1101 | #define default_MCA_trigger(idx) (1) | |
6728801d | 1102 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 1103 | |
61fd47e0 | 1104 | static int MPBIOS_polarity(int idx) |
1da177e4 | 1105 | { |
c2c21745 | 1106 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1107 | int polarity; |
1108 | ||
1109 | /* | |
1110 | * Determine IRQ line polarity (high active or low active): | |
1111 | */ | |
c2c21745 | 1112 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 1113 | { |
54168ed7 IM |
1114 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1115 | if (test_bit(bus, mp_bus_not_pci)) | |
1116 | polarity = default_ISA_polarity(idx); | |
1117 | else | |
1118 | polarity = default_PCI_polarity(idx); | |
1119 | break; | |
1120 | case 1: /* high active */ | |
1121 | { | |
1122 | polarity = 0; | |
1123 | break; | |
1124 | } | |
1125 | case 2: /* reserved */ | |
1126 | { | |
1127 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1128 | polarity = 1; | |
1129 | break; | |
1130 | } | |
1131 | case 3: /* low active */ | |
1132 | { | |
1133 | polarity = 1; | |
1134 | break; | |
1135 | } | |
1136 | default: /* invalid */ | |
1137 | { | |
1138 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1139 | polarity = 1; | |
1140 | break; | |
1141 | } | |
1da177e4 LT |
1142 | } |
1143 | return polarity; | |
1144 | } | |
1145 | ||
1146 | static int MPBIOS_trigger(int idx) | |
1147 | { | |
c2c21745 | 1148 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1149 | int trigger; |
1150 | ||
1151 | /* | |
1152 | * Determine IRQ trigger mode (edge or level sensitive): | |
1153 | */ | |
c2c21745 | 1154 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 1155 | { |
54168ed7 IM |
1156 | case 0: /* conforms, ie. bus-type dependent */ |
1157 | if (test_bit(bus, mp_bus_not_pci)) | |
1158 | trigger = default_ISA_trigger(idx); | |
1159 | else | |
1160 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 1161 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
1162 | switch (mp_bus_id_to_type[bus]) { |
1163 | case MP_BUS_ISA: /* ISA pin */ | |
1164 | { | |
1165 | /* set before the switch */ | |
1166 | break; | |
1167 | } | |
1168 | case MP_BUS_EISA: /* EISA pin */ | |
1169 | { | |
1170 | trigger = default_EISA_trigger(idx); | |
1171 | break; | |
1172 | } | |
1173 | case MP_BUS_PCI: /* PCI pin */ | |
1174 | { | |
1175 | /* set before the switch */ | |
1176 | break; | |
1177 | } | |
1178 | case MP_BUS_MCA: /* MCA pin */ | |
1179 | { | |
1180 | trigger = default_MCA_trigger(idx); | |
1181 | break; | |
1182 | } | |
1183 | default: | |
1184 | { | |
1185 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1186 | trigger = 1; | |
1187 | break; | |
1188 | } | |
1189 | } | |
1190 | #endif | |
1da177e4 | 1191 | break; |
54168ed7 | 1192 | case 1: /* edge */ |
1da177e4 | 1193 | { |
54168ed7 | 1194 | trigger = 0; |
1da177e4 LT |
1195 | break; |
1196 | } | |
54168ed7 | 1197 | case 2: /* reserved */ |
1da177e4 | 1198 | { |
54168ed7 IM |
1199 | printk(KERN_WARNING "broken BIOS!!\n"); |
1200 | trigger = 1; | |
1da177e4 LT |
1201 | break; |
1202 | } | |
54168ed7 | 1203 | case 3: /* level */ |
1da177e4 | 1204 | { |
54168ed7 | 1205 | trigger = 1; |
1da177e4 LT |
1206 | break; |
1207 | } | |
54168ed7 | 1208 | default: /* invalid */ |
1da177e4 LT |
1209 | { |
1210 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1211 | trigger = 0; |
1da177e4 LT |
1212 | break; |
1213 | } | |
1214 | } | |
1215 | return trigger; | |
1216 | } | |
1217 | ||
1218 | static inline int irq_polarity(int idx) | |
1219 | { | |
1220 | return MPBIOS_polarity(idx); | |
1221 | } | |
1222 | ||
1223 | static inline int irq_trigger(int idx) | |
1224 | { | |
1225 | return MPBIOS_trigger(idx); | |
1226 | } | |
1227 | ||
efa2559f | 1228 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1229 | static int pin_2_irq(int idx, int apic, int pin) |
1230 | { | |
1231 | int irq, i; | |
c2c21745 | 1232 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1233 | |
1234 | /* | |
1235 | * Debugging check, we are in big trouble if this message pops up! | |
1236 | */ | |
c2c21745 | 1237 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1238 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1239 | ||
54168ed7 | 1240 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1241 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1242 | } else { |
643befed AS |
1243 | /* |
1244 | * PCI IRQs are mapped in order | |
1245 | */ | |
1246 | i = irq = 0; | |
1247 | while (i < apic) | |
1248 | irq += nr_ioapic_registers[i++]; | |
1249 | irq += pin; | |
d6c88a50 | 1250 | /* |
54168ed7 IM |
1251 | * For MPS mode, so far only needed by ES7000 platform |
1252 | */ | |
d6c88a50 TG |
1253 | if (ioapic_renumber_irq) |
1254 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1255 | } |
1256 | ||
54168ed7 | 1257 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1258 | /* |
1259 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1260 | */ | |
1261 | if ((pin >= 16) && (pin <= 23)) { | |
1262 | if (pirq_entries[pin-16] != -1) { | |
1263 | if (!pirq_entries[pin-16]) { | |
1264 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1265 | "disabling PIRQ%d\n", pin-16); | |
1266 | } else { | |
1267 | irq = pirq_entries[pin-16]; | |
1268 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1269 | "using PIRQ%d -> IRQ %d\n", | |
1270 | pin-16, irq); | |
1271 | } | |
1272 | } | |
1273 | } | |
54168ed7 IM |
1274 | #endif |
1275 | ||
1da177e4 LT |
1276 | return irq; |
1277 | } | |
1278 | ||
497c9a19 YL |
1279 | void lock_vector_lock(void) |
1280 | { | |
1281 | /* Used to the online set of cpus does not change | |
1282 | * during assign_irq_vector. | |
1283 | */ | |
1284 | spin_lock(&vector_lock); | |
1285 | } | |
1da177e4 | 1286 | |
497c9a19 | 1287 | void unlock_vector_lock(void) |
1da177e4 | 1288 | { |
497c9a19 YL |
1289 | spin_unlock(&vector_lock); |
1290 | } | |
1da177e4 | 1291 | |
e7986739 MT |
1292 | static int |
1293 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1294 | { |
047c8fdb YL |
1295 | /* |
1296 | * NOTE! The local APIC isn't very good at handling | |
1297 | * multiple interrupts at the same interrupt level. | |
1298 | * As the interrupt level is determined by taking the | |
1299 | * vector number and shifting that right by 4, we | |
1300 | * want to spread these out a bit so that they don't | |
1301 | * all fall in the same interrupt level. | |
1302 | * | |
1303 | * Also, we've got to be careful not to trash gate | |
1304 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1305 | */ | |
54168ed7 IM |
1306 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1307 | unsigned int old_vector; | |
22f65d31 MT |
1308 | int cpu, err; |
1309 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1310 | |
54168ed7 IM |
1311 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1312 | return -EBUSY; | |
0a1ad60d | 1313 | |
22f65d31 MT |
1314 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1315 | return -ENOMEM; | |
ace80ab7 | 1316 | |
54168ed7 IM |
1317 | old_vector = cfg->vector; |
1318 | if (old_vector) { | |
22f65d31 MT |
1319 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1320 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1321 | if (!cpumask_empty(tmp_mask)) { | |
1322 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1323 | return 0; |
22f65d31 | 1324 | } |
54168ed7 | 1325 | } |
497c9a19 | 1326 | |
e7986739 | 1327 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1328 | err = -ENOSPC; |
1329 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1330 | int new_cpu; |
1331 | int vector, offset; | |
497c9a19 | 1332 | |
e2d40b18 | 1333 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1334 | |
54168ed7 IM |
1335 | vector = current_vector; |
1336 | offset = current_offset; | |
497c9a19 | 1337 | next: |
54168ed7 IM |
1338 | vector += 8; |
1339 | if (vector >= first_system_vector) { | |
e7986739 | 1340 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1341 | offset = (offset + 1) % 8; |
1342 | vector = FIRST_DEVICE_VECTOR + offset; | |
1343 | } | |
1344 | if (unlikely(current_vector == vector)) | |
1345 | continue; | |
b77b881f YL |
1346 | |
1347 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1348 | goto next; |
b77b881f | 1349 | |
22f65d31 | 1350 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1351 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1352 | goto next; | |
1353 | /* Found one! */ | |
1354 | current_vector = vector; | |
1355 | current_offset = offset; | |
1356 | if (old_vector) { | |
1357 | cfg->move_in_progress = 1; | |
22f65d31 | 1358 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1359 | } |
22f65d31 | 1360 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1361 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1362 | cfg->vector = vector; | |
22f65d31 MT |
1363 | cpumask_copy(cfg->domain, tmp_mask); |
1364 | err = 0; | |
1365 | break; | |
54168ed7 | 1366 | } |
22f65d31 MT |
1367 | free_cpumask_var(tmp_mask); |
1368 | return err; | |
497c9a19 YL |
1369 | } |
1370 | ||
e7986739 MT |
1371 | static int |
1372 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1373 | { |
1374 | int err; | |
ace80ab7 | 1375 | unsigned long flags; |
ace80ab7 EB |
1376 | |
1377 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1378 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1379 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1380 | return err; |
1381 | } | |
1382 | ||
3145e941 | 1383 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1384 | { |
497c9a19 YL |
1385 | int cpu, vector; |
1386 | ||
497c9a19 YL |
1387 | BUG_ON(!cfg->vector); |
1388 | ||
1389 | vector = cfg->vector; | |
22f65d31 | 1390 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1391 | per_cpu(vector_irq, cpu)[vector] = -1; |
1392 | ||
1393 | cfg->vector = 0; | |
22f65d31 | 1394 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1395 | |
1396 | if (likely(!cfg->move_in_progress)) | |
1397 | return; | |
22f65d31 | 1398 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1399 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1400 | vector++) { | |
1401 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1402 | continue; | |
1403 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1404 | break; | |
1405 | } | |
1406 | } | |
1407 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1408 | } |
1409 | ||
1410 | void __setup_vector_irq(int cpu) | |
1411 | { | |
1412 | /* Initialize vector_irq on a new cpu */ | |
1413 | /* This function must be called with vector_lock held */ | |
1414 | int irq, vector; | |
1415 | struct irq_cfg *cfg; | |
0b8f1efa | 1416 | struct irq_desc *desc; |
497c9a19 YL |
1417 | |
1418 | /* Mark the inuse vectors */ | |
0b8f1efa | 1419 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1420 | cfg = desc->chip_data; |
22f65d31 | 1421 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1422 | continue; |
1423 | vector = cfg->vector; | |
497c9a19 YL |
1424 | per_cpu(vector_irq, cpu)[vector] = irq; |
1425 | } | |
1426 | /* Mark the free vectors */ | |
1427 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1428 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1429 | if (irq < 0) | |
1430 | continue; | |
1431 | ||
1432 | cfg = irq_cfg(irq); | |
22f65d31 | 1433 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1434 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1435 | } |
1da177e4 | 1436 | } |
3fde6900 | 1437 | |
f5b9ed7a | 1438 | static struct irq_chip ioapic_chip; |
54168ed7 | 1439 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1440 | |
54168ed7 IM |
1441 | #define IOAPIC_AUTO -1 |
1442 | #define IOAPIC_EDGE 0 | |
1443 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1444 | |
047c8fdb | 1445 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1446 | static inline int IO_APIC_irq_trigger(int irq) |
1447 | { | |
d6c88a50 | 1448 | int apic, idx, pin; |
1d025192 | 1449 | |
d6c88a50 TG |
1450 | for (apic = 0; apic < nr_ioapics; apic++) { |
1451 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1452 | idx = find_irq_entry(apic, pin, mp_INT); | |
1453 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1454 | return irq_trigger(idx); | |
1455 | } | |
1456 | } | |
1457 | /* | |
54168ed7 IM |
1458 | * nonexistent IRQs are edge default |
1459 | */ | |
d6c88a50 | 1460 | return 0; |
1d025192 | 1461 | } |
047c8fdb YL |
1462 | #else |
1463 | static inline int IO_APIC_irq_trigger(int irq) | |
1464 | { | |
54168ed7 | 1465 | return 1; |
047c8fdb YL |
1466 | } |
1467 | #endif | |
1d025192 | 1468 | |
3145e941 | 1469 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1470 | { |
199751d7 | 1471 | |
6ebcc00e | 1472 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1473 | trigger == IOAPIC_LEVEL) |
08678b08 | 1474 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1475 | else |
1476 | desc->status &= ~IRQ_LEVEL; | |
1477 | ||
54168ed7 IM |
1478 | if (irq_remapped(irq)) { |
1479 | desc->status |= IRQ_MOVE_PCNTXT; | |
1480 | if (trigger) | |
1481 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1482 | handle_fasteoi_irq, | |
1483 | "fasteoi"); | |
1484 | else | |
1485 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1486 | handle_edge_irq, "edge"); | |
1487 | return; | |
1488 | } | |
29b61be6 | 1489 | |
047c8fdb YL |
1490 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1491 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1492 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1493 | handle_fasteoi_irq, |
1494 | "fasteoi"); | |
047c8fdb | 1495 | else |
a460e745 | 1496 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1497 | handle_edge_irq, "edge"); |
1da177e4 LT |
1498 | } |
1499 | ||
ca97ab90 JF |
1500 | int setup_ioapic_entry(int apic_id, int irq, |
1501 | struct IO_APIC_route_entry *entry, | |
1502 | unsigned int destination, int trigger, | |
0280f7c4 | 1503 | int polarity, int vector, int pin) |
1da177e4 | 1504 | { |
497c9a19 YL |
1505 | /* |
1506 | * add it to the IO-APIC irq-routing table: | |
1507 | */ | |
1508 | memset(entry,0,sizeof(*entry)); | |
1509 | ||
54168ed7 | 1510 | if (intr_remapping_enabled) { |
c8d46cf0 | 1511 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1512 | struct irte irte; |
1513 | struct IR_IO_APIC_route_entry *ir_entry = | |
1514 | (struct IR_IO_APIC_route_entry *) entry; | |
1515 | int index; | |
1516 | ||
1517 | if (!iommu) | |
c8d46cf0 | 1518 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1519 | |
1520 | index = alloc_irte(iommu, irq, 1); | |
1521 | if (index < 0) | |
c8d46cf0 | 1522 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1523 | |
1524 | memset(&irte, 0, sizeof(irte)); | |
1525 | ||
1526 | irte.present = 1; | |
9b5bc8dc | 1527 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1528 | /* |
1529 | * Trigger mode in the IRTE will always be edge, and the | |
1530 | * actual level or edge trigger will be setup in the IO-APIC | |
1531 | * RTE. This will help simplify level triggered irq migration. | |
1532 | * For more details, see the comments above explainig IO-APIC | |
1533 | * irq migration in the presence of interrupt-remapping. | |
1534 | */ | |
1535 | irte.trigger_mode = 0; | |
9b5bc8dc | 1536 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1537 | irte.vector = vector; |
1538 | irte.dest_id = IRTE_DEST(destination); | |
1539 | ||
1540 | modify_irte(irq, &irte); | |
1541 | ||
1542 | ir_entry->index2 = (index >> 15) & 0x1; | |
1543 | ir_entry->zero = 0; | |
1544 | ir_entry->format = 1; | |
1545 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1546 | /* |
1547 | * IO-APIC RTE will be configured with virtual vector. | |
1548 | * irq handler will do the explicit EOI to the io-apic. | |
1549 | */ | |
1550 | ir_entry->vector = pin; | |
29b61be6 | 1551 | } else { |
9b5bc8dc IM |
1552 | entry->delivery_mode = apic->irq_delivery_mode; |
1553 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1554 | entry->dest = destination; |
0280f7c4 | 1555 | entry->vector = vector; |
54168ed7 | 1556 | } |
497c9a19 | 1557 | |
54168ed7 | 1558 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1559 | entry->trigger = trigger; |
1560 | entry->polarity = polarity; | |
497c9a19 YL |
1561 | |
1562 | /* Mask level triggered irqs. | |
1563 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1564 | */ | |
1565 | if (trigger) | |
1566 | entry->mask = 1; | |
497c9a19 YL |
1567 | return 0; |
1568 | } | |
1569 | ||
c8d46cf0 | 1570 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1571 | int trigger, int polarity) |
497c9a19 YL |
1572 | { |
1573 | struct irq_cfg *cfg; | |
1da177e4 | 1574 | struct IO_APIC_route_entry entry; |
22f65d31 | 1575 | unsigned int dest; |
497c9a19 YL |
1576 | |
1577 | if (!IO_APIC_IRQ(irq)) | |
1578 | return; | |
1579 | ||
3145e941 | 1580 | cfg = desc->chip_data; |
497c9a19 | 1581 | |
fe402e1f | 1582 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1583 | return; |
1584 | ||
debccb3e | 1585 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1586 | |
1587 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1588 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1589 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1590 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1591 | irq, trigger, polarity); |
1592 | ||
1593 | ||
c8d46cf0 | 1594 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1595 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1596 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1597 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1598 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1599 | return; |
1600 | } | |
1601 | ||
3145e941 | 1602 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1603 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1604 | disable_8259A_irq(irq); |
1605 | ||
c8d46cf0 | 1606 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1607 | } |
1608 | ||
1609 | static void __init setup_IO_APIC_irqs(void) | |
1610 | { | |
c8d46cf0 | 1611 | int apic_id, pin, idx, irq; |
3c2cbd24 | 1612 | int notcon = 0; |
0b8f1efa | 1613 | struct irq_desc *desc; |
3145e941 | 1614 | struct irq_cfg *cfg; |
0b8f1efa | 1615 | int cpu = boot_cpu_id; |
1da177e4 LT |
1616 | |
1617 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1618 | ||
c8d46cf0 IM |
1619 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1620 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { | |
20d225b9 | 1621 | |
c8d46cf0 | 1622 | idx = find_irq_entry(apic_id, pin, mp_INT); |
3c2cbd24 | 1623 | if (idx == -1) { |
2a554fb1 | 1624 | if (!notcon) { |
3c2cbd24 | 1625 | notcon = 1; |
2a554fb1 CG |
1626 | apic_printk(APIC_VERBOSE, |
1627 | KERN_DEBUG " %d-%d", | |
c8d46cf0 | 1628 | mp_ioapics[apic_id].apicid, pin); |
2a554fb1 CG |
1629 | } else |
1630 | apic_printk(APIC_VERBOSE, " %d-%d", | |
c8d46cf0 | 1631 | mp_ioapics[apic_id].apicid, pin); |
3c2cbd24 CG |
1632 | continue; |
1633 | } | |
56ffa1a0 CG |
1634 | if (notcon) { |
1635 | apic_printk(APIC_VERBOSE, | |
1636 | " (apicid-pin) not connected\n"); | |
1637 | notcon = 0; | |
1638 | } | |
3c2cbd24 | 1639 | |
c8d46cf0 | 1640 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa IM |
1641 | |
1642 | /* | |
1643 | * Skip the timer IRQ if there's a quirk handler | |
1644 | * installed and if it returns 1: | |
1645 | */ | |
1646 | if (apic->multi_timer_check && | |
1647 | apic->multi_timer_check(apic_id, irq)) | |
3c2cbd24 | 1648 | continue; |
33a201fa | 1649 | |
0b8f1efa YL |
1650 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
1651 | if (!desc) { | |
1652 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1653 | continue; | |
1654 | } | |
3145e941 | 1655 | cfg = desc->chip_data; |
c8d46cf0 | 1656 | add_pin_to_irq_cpu(cfg, cpu, apic_id, pin); |
36062448 | 1657 | |
c8d46cf0 | 1658 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
3c2cbd24 CG |
1659 | irq_trigger(idx), irq_polarity(idx)); |
1660 | } | |
1da177e4 LT |
1661 | } |
1662 | ||
3c2cbd24 CG |
1663 | if (notcon) |
1664 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1665 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1666 | } |
1667 | ||
1668 | /* | |
f7633ce5 | 1669 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1670 | */ |
c8d46cf0 | 1671 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1672 | int vector) |
1da177e4 LT |
1673 | { |
1674 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1675 | |
54168ed7 IM |
1676 | if (intr_remapping_enabled) |
1677 | return; | |
54168ed7 | 1678 | |
36062448 | 1679 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1680 | |
1681 | /* | |
1682 | * We use logical delivery to get the timer IRQ | |
1683 | * to the first CPU. | |
1684 | */ | |
9b5bc8dc | 1685 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1686 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1687 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1688 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1689 | entry.polarity = 0; |
1690 | entry.trigger = 0; | |
1691 | entry.vector = vector; | |
1692 | ||
1693 | /* | |
1694 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1695 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1696 | */ |
54168ed7 | 1697 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1698 | |
1699 | /* | |
1700 | * Add it to the IO-APIC irq-routing table: | |
1701 | */ | |
c8d46cf0 | 1702 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1703 | } |
1704 | ||
32f71aff MR |
1705 | |
1706 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1707 | { |
1708 | int apic, i; | |
1709 | union IO_APIC_reg_00 reg_00; | |
1710 | union IO_APIC_reg_01 reg_01; | |
1711 | union IO_APIC_reg_02 reg_02; | |
1712 | union IO_APIC_reg_03 reg_03; | |
1713 | unsigned long flags; | |
0f978f45 | 1714 | struct irq_cfg *cfg; |
0b8f1efa | 1715 | struct irq_desc *desc; |
8f09cd20 | 1716 | unsigned int irq; |
1da177e4 LT |
1717 | |
1718 | if (apic_verbosity == APIC_QUIET) | |
1719 | return; | |
1720 | ||
36062448 | 1721 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1722 | for (i = 0; i < nr_ioapics; i++) |
1723 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1724 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1725 | |
1726 | /* | |
1727 | * We are a bit conservative about what we expect. We have to | |
1728 | * know about every hardware change ASAP. | |
1729 | */ | |
1730 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1731 | ||
1732 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1733 | ||
1734 | spin_lock_irqsave(&ioapic_lock, flags); | |
1735 | reg_00.raw = io_apic_read(apic, 0); | |
1736 | reg_01.raw = io_apic_read(apic, 1); | |
1737 | if (reg_01.bits.version >= 0x10) | |
1738 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1739 | if (reg_01.bits.version >= 0x20) |
1740 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1741 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1742 | ||
54168ed7 | 1743 | printk("\n"); |
b5ba7e6d | 1744 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1745 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1746 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1747 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1748 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1749 | |
54168ed7 | 1750 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1751 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1752 | |
1753 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1754 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1755 | |
1756 | /* | |
1757 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1758 | * but the value of reg_02 is read as the previous read register | |
1759 | * value, so ignore it if reg_02 == reg_01. | |
1760 | */ | |
1761 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1762 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1763 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1764 | } |
1765 | ||
1766 | /* | |
1767 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1768 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1769 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1770 | */ | |
1771 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1772 | reg_03.raw != reg_01.raw) { | |
1773 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1774 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1775 | } |
1776 | ||
1777 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1778 | ||
d83e94ac YL |
1779 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1780 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1781 | |
1782 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1783 | struct IO_APIC_route_entry entry; | |
1784 | ||
cf4c6a2f | 1785 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1786 | |
54168ed7 IM |
1787 | printk(KERN_DEBUG " %02x %03X ", |
1788 | i, | |
1789 | entry.dest | |
1790 | ); | |
1da177e4 LT |
1791 | |
1792 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1793 | entry.mask, | |
1794 | entry.trigger, | |
1795 | entry.irr, | |
1796 | entry.polarity, | |
1797 | entry.delivery_status, | |
1798 | entry.dest_mode, | |
1799 | entry.delivery_mode, | |
1800 | entry.vector | |
1801 | ); | |
1802 | } | |
1803 | } | |
1da177e4 | 1804 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1805 | for_each_irq_desc(irq, desc) { |
1806 | struct irq_pin_list *entry; | |
1807 | ||
0b8f1efa YL |
1808 | cfg = desc->chip_data; |
1809 | entry = cfg->irq_2_pin; | |
0f978f45 | 1810 | if (!entry) |
1da177e4 | 1811 | continue; |
8f09cd20 | 1812 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1813 | for (;;) { |
1814 | printk("-> %d:%d", entry->apic, entry->pin); | |
1815 | if (!entry->next) | |
1816 | break; | |
0f978f45 | 1817 | entry = entry->next; |
1da177e4 LT |
1818 | } |
1819 | printk("\n"); | |
1820 | } | |
1821 | ||
1822 | printk(KERN_INFO ".................................... done.\n"); | |
1823 | ||
1824 | return; | |
1825 | } | |
1826 | ||
32f71aff | 1827 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1828 | { |
1829 | unsigned int v; | |
1830 | int i, j; | |
1831 | ||
1832 | if (apic_verbosity == APIC_QUIET) | |
1833 | return; | |
1834 | ||
1835 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1836 | for (i = 0; i < 8; i++) { | |
1837 | v = apic_read(base + i*0x10); | |
1838 | for (j = 0; j < 32; j++) { | |
1839 | if (v & (1<<j)) | |
1840 | printk("1"); | |
1841 | else | |
1842 | printk("0"); | |
1843 | } | |
1844 | printk("\n"); | |
1845 | } | |
1846 | } | |
1847 | ||
32f71aff | 1848 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1849 | { |
1850 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1851 | u64 icr; |
1da177e4 LT |
1852 | |
1853 | if (apic_verbosity == APIC_QUIET) | |
1854 | return; | |
1855 | ||
1856 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1857 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1858 | v = apic_read(APIC_ID); |
54168ed7 | 1859 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1860 | v = apic_read(APIC_LVR); |
1861 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1862 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1863 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1864 | |
1865 | v = apic_read(APIC_TASKPRI); | |
1866 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1867 | ||
54168ed7 | 1868 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1869 | if (!APIC_XAPIC(ver)) { |
1870 | v = apic_read(APIC_ARBPRI); | |
1871 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1872 | v & APIC_ARBPRI_MASK); | |
1873 | } | |
1da177e4 LT |
1874 | v = apic_read(APIC_PROCPRI); |
1875 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1876 | } | |
1877 | ||
a11b5abe YL |
1878 | /* |
1879 | * Remote read supported only in the 82489DX and local APIC for | |
1880 | * Pentium processors. | |
1881 | */ | |
1882 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1883 | v = apic_read(APIC_RRR); | |
1884 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1885 | } | |
1886 | ||
1da177e4 LT |
1887 | v = apic_read(APIC_LDR); |
1888 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1889 | if (!x2apic_enabled()) { |
1890 | v = apic_read(APIC_DFR); | |
1891 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1892 | } | |
1da177e4 LT |
1893 | v = apic_read(APIC_SPIV); |
1894 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1895 | ||
1896 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1897 | print_APIC_bitfield(APIC_ISR); | |
1898 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1899 | print_APIC_bitfield(APIC_TMR); | |
1900 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1901 | print_APIC_bitfield(APIC_IRR); | |
1902 | ||
54168ed7 IM |
1903 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1904 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1905 | apic_write(APIC_ESR, 0); |
54168ed7 | 1906 | |
1da177e4 LT |
1907 | v = apic_read(APIC_ESR); |
1908 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1909 | } | |
1910 | ||
7ab6af7a | 1911 | icr = apic_icr_read(); |
0c425cec IM |
1912 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1913 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1914 | |
1915 | v = apic_read(APIC_LVTT); | |
1916 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1917 | ||
1918 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1919 | v = apic_read(APIC_LVTPC); | |
1920 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1921 | } | |
1922 | v = apic_read(APIC_LVT0); | |
1923 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1924 | v = apic_read(APIC_LVT1); | |
1925 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1926 | ||
1927 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1928 | v = apic_read(APIC_LVTERR); | |
1929 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1930 | } | |
1931 | ||
1932 | v = apic_read(APIC_TMICT); | |
1933 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1934 | v = apic_read(APIC_TMCCT); | |
1935 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1936 | v = apic_read(APIC_TDCR); | |
1937 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1938 | printk("\n"); | |
1939 | } | |
1940 | ||
32f71aff | 1941 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1942 | { |
ffd5aae7 YL |
1943 | int cpu; |
1944 | ||
1945 | preempt_disable(); | |
1946 | for_each_online_cpu(cpu) | |
1947 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1948 | preempt_enable(); | |
1da177e4 LT |
1949 | } |
1950 | ||
32f71aff | 1951 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1952 | { |
1da177e4 LT |
1953 | unsigned int v; |
1954 | unsigned long flags; | |
1955 | ||
1956 | if (apic_verbosity == APIC_QUIET) | |
1957 | return; | |
1958 | ||
1959 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1960 | ||
1961 | spin_lock_irqsave(&i8259A_lock, flags); | |
1962 | ||
1963 | v = inb(0xa1) << 8 | inb(0x21); | |
1964 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1965 | ||
1966 | v = inb(0xa0) << 8 | inb(0x20); | |
1967 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1968 | ||
54168ed7 IM |
1969 | outb(0x0b,0xa0); |
1970 | outb(0x0b,0x20); | |
1da177e4 | 1971 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1972 | outb(0x0a,0xa0); |
1973 | outb(0x0a,0x20); | |
1da177e4 LT |
1974 | |
1975 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1976 | ||
1977 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1978 | ||
1979 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1980 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1981 | } | |
1982 | ||
32f71aff MR |
1983 | __apicdebuginit(int) print_all_ICs(void) |
1984 | { | |
1985 | print_PIC(); | |
1986 | print_all_local_APICs(); | |
1987 | print_IO_APIC(); | |
1988 | ||
1989 | return 0; | |
1990 | } | |
1991 | ||
1992 | fs_initcall(print_all_ICs); | |
1993 | ||
1da177e4 | 1994 | |
efa2559f YL |
1995 | /* Where if anywhere is the i8259 connect in external int mode */ |
1996 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1997 | ||
54168ed7 | 1998 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1999 | { |
2000 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 2001 | int i8259_apic, i8259_pin; |
54168ed7 | 2002 | int apic; |
1da177e4 LT |
2003 | unsigned long flags; |
2004 | ||
1da177e4 LT |
2005 | /* |
2006 | * The number of IO-APIC IRQ registers (== #pins): | |
2007 | */ | |
fcfd636a | 2008 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 2009 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 2010 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 2011 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
2012 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
2013 | } | |
54168ed7 | 2014 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
2015 | int pin; |
2016 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 2017 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 2018 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 2019 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 2020 | |
fcfd636a EB |
2021 | /* If the interrupt line is enabled and in ExtInt mode |
2022 | * I have found the pin where the i8259 is connected. | |
2023 | */ | |
2024 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
2025 | ioapic_i8259.apic = apic; | |
2026 | ioapic_i8259.pin = pin; | |
2027 | goto found_i8259; | |
2028 | } | |
2029 | } | |
2030 | } | |
2031 | found_i8259: | |
2032 | /* Look to see what if the MP table has reported the ExtINT */ | |
2033 | /* If we could not find the appropriate pin by looking at the ioapic | |
2034 | * the i8259 probably is not connected the ioapic but give the | |
2035 | * mptable a chance anyway. | |
2036 | */ | |
2037 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
2038 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
2039 | /* Trust the MP table if nothing is setup in the hardware */ | |
2040 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
2041 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
2042 | ioapic_i8259.pin = i8259_pin; | |
2043 | ioapic_i8259.apic = i8259_apic; | |
2044 | } | |
2045 | /* Complain if the MP table and the hardware disagree */ | |
2046 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
2047 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
2048 | { | |
2049 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
2050 | } |
2051 | ||
2052 | /* | |
2053 | * Do not trust the IO-APIC being empty at bootup | |
2054 | */ | |
2055 | clear_IO_APIC(); | |
2056 | } | |
2057 | ||
2058 | /* | |
2059 | * Not an __init, needed by the reboot code | |
2060 | */ | |
2061 | void disable_IO_APIC(void) | |
2062 | { | |
2063 | /* | |
2064 | * Clear the IO-APIC before rebooting: | |
2065 | */ | |
2066 | clear_IO_APIC(); | |
2067 | ||
650927ef | 2068 | /* |
0b968d23 | 2069 | * If the i8259 is routed through an IOAPIC |
650927ef | 2070 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2071 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
2072 | * |
2073 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
2074 | * as virtual wire B is little complex (need to configure both | |
2075 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
2076 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 2077 | */ |
7c6d9f97 | 2078 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 2079 | struct IO_APIC_route_entry entry; |
650927ef EB |
2080 | |
2081 | memset(&entry, 0, sizeof(entry)); | |
2082 | entry.mask = 0; /* Enabled */ | |
2083 | entry.trigger = 0; /* Edge */ | |
2084 | entry.irr = 0; | |
2085 | entry.polarity = 0; /* High */ | |
2086 | entry.delivery_status = 0; | |
2087 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2088 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2089 | entry.vector = 0; |
54168ed7 | 2090 | entry.dest = read_apic_id(); |
650927ef EB |
2091 | |
2092 | /* | |
2093 | * Add it to the IO-APIC irq-routing table: | |
2094 | */ | |
cf4c6a2f | 2095 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2096 | } |
54168ed7 | 2097 | |
7c6d9f97 SS |
2098 | /* |
2099 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2100 | */ | |
2101 | disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1); | |
1da177e4 LT |
2102 | } |
2103 | ||
54168ed7 | 2104 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2105 | /* |
2106 | * function to set the IO-APIC physical IDs based on the | |
2107 | * values stored in the MPC table. | |
2108 | * | |
2109 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2110 | */ | |
2111 | ||
1da177e4 LT |
2112 | static void __init setup_ioapic_ids_from_mpc(void) |
2113 | { | |
2114 | union IO_APIC_reg_00 reg_00; | |
2115 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2116 | int apic_id; |
1da177e4 LT |
2117 | int i; |
2118 | unsigned char old_id; | |
2119 | unsigned long flags; | |
2120 | ||
a4dbc34d | 2121 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2122 | return; |
d49c4288 | 2123 | |
ca05fea6 NP |
2124 | /* |
2125 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2126 | * no meaning without the serial APIC bus. | |
2127 | */ | |
7c5c1e42 SL |
2128 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2129 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2130 | return; |
1da177e4 LT |
2131 | /* |
2132 | * This is broken; anything with a real cpu count has to | |
2133 | * circumvent this idiocy regardless. | |
2134 | */ | |
d190cb87 | 2135 | phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
2136 | |
2137 | /* | |
2138 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2139 | */ | |
c8d46cf0 | 2140 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2141 | |
2142 | /* Read the register 0 value */ | |
2143 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2144 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2145 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2146 | |
c8d46cf0 | 2147 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2148 | |
c8d46cf0 | 2149 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2150 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2151 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2152 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2153 | reg_00.bits.ID); | |
c8d46cf0 | 2154 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2155 | } |
2156 | ||
1da177e4 LT |
2157 | /* |
2158 | * Sanity check, is the ID really free? Every APIC in a | |
2159 | * system must have a unique ID or we get lots of nice | |
2160 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2161 | */ | |
d1d7cae8 | 2162 | if (apic->check_apicid_used(phys_id_present_map, |
c8d46cf0 | 2163 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2164 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2165 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2166 | for (i = 0; i < get_physical_broadcast(); i++) |
2167 | if (!physid_isset(i, phys_id_present_map)) | |
2168 | break; | |
2169 | if (i >= get_physical_broadcast()) | |
2170 | panic("Max APIC ID exceeded!\n"); | |
2171 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2172 | i); | |
2173 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2174 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2175 | } else { |
2176 | physid_mask_t tmp; | |
8058714a | 2177 | tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2178 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2179 | "phys_id_present_map\n", | |
c8d46cf0 | 2180 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2181 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2182 | } | |
2183 | ||
2184 | ||
2185 | /* | |
2186 | * We need to adjust the IRQ routing table | |
2187 | * if the ID changed. | |
2188 | */ | |
c8d46cf0 | 2189 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2190 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2191 | if (mp_irqs[i].dstapic == old_id) |
2192 | mp_irqs[i].dstapic | |
c8d46cf0 | 2193 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2194 | |
2195 | /* | |
2196 | * Read the right value from the MPC table and | |
2197 | * write it into the ID register. | |
36062448 | 2198 | */ |
1da177e4 LT |
2199 | apic_printk(APIC_VERBOSE, KERN_INFO |
2200 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2201 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2202 | |
c8d46cf0 | 2203 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2204 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2205 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2206 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2207 | |
2208 | /* | |
2209 | * Sanity check | |
2210 | */ | |
2211 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2212 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2213 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2214 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2215 | printk("could not set ID!\n"); |
2216 | else | |
2217 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2218 | } | |
2219 | } | |
54168ed7 | 2220 | #endif |
1da177e4 | 2221 | |
7ce0bcfd | 2222 | int no_timer_check __initdata; |
8542b200 ZA |
2223 | |
2224 | static int __init notimercheck(char *s) | |
2225 | { | |
2226 | no_timer_check = 1; | |
2227 | return 1; | |
2228 | } | |
2229 | __setup("no_timer_check", notimercheck); | |
2230 | ||
1da177e4 LT |
2231 | /* |
2232 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2233 | * about the timer IRQ. We do the following to work around the situation: | |
2234 | * | |
2235 | * - timer IRQ defaults to IO-APIC IRQ | |
2236 | * - if this function detects that timer IRQs are defunct, then we fall | |
2237 | * back to ISA timer IRQs | |
2238 | */ | |
f0a7a5c9 | 2239 | static int __init timer_irq_works(void) |
1da177e4 LT |
2240 | { |
2241 | unsigned long t1 = jiffies; | |
4aae0702 | 2242 | unsigned long flags; |
1da177e4 | 2243 | |
8542b200 ZA |
2244 | if (no_timer_check) |
2245 | return 1; | |
2246 | ||
4aae0702 | 2247 | local_save_flags(flags); |
1da177e4 LT |
2248 | local_irq_enable(); |
2249 | /* Let ten ticks pass... */ | |
2250 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2251 | local_irq_restore(flags); |
1da177e4 LT |
2252 | |
2253 | /* | |
2254 | * Expect a few ticks at least, to be sure some possible | |
2255 | * glue logic does not lock up after one or two first | |
2256 | * ticks in a non-ExtINT mode. Also the local APIC | |
2257 | * might have cached one ExtINT interrupt. Finally, at | |
2258 | * least one tick may be lost due to delays. | |
2259 | */ | |
54168ed7 IM |
2260 | |
2261 | /* jiffies wrap? */ | |
1d16b53e | 2262 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2263 | return 1; |
1da177e4 LT |
2264 | return 0; |
2265 | } | |
2266 | ||
2267 | /* | |
2268 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2269 | * number of pending IRQ events unhandled. These cases are very rare, | |
2270 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2271 | * better to do it this way as thus we do not have to be aware of | |
2272 | * 'pending' interrupts in the IRQ path, except at this point. | |
2273 | */ | |
2274 | /* | |
2275 | * Edge triggered needs to resend any interrupt | |
2276 | * that was delayed but this is now handled in the device | |
2277 | * independent code. | |
2278 | */ | |
2279 | ||
2280 | /* | |
2281 | * Starting up a edge-triggered IO-APIC interrupt is | |
2282 | * nasty - we need to make sure that we get the edge. | |
2283 | * If it is already asserted for some reason, we need | |
2284 | * return 1 to indicate that is was pending. | |
2285 | * | |
2286 | * This is not complete - we should be able to fake | |
2287 | * an edge even if it isn't on the 8259A... | |
2288 | */ | |
54168ed7 | 2289 | |
f5b9ed7a | 2290 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2291 | { |
2292 | int was_pending = 0; | |
2293 | unsigned long flags; | |
0b8f1efa | 2294 | struct irq_cfg *cfg; |
1da177e4 LT |
2295 | |
2296 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2297 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2298 | disable_8259A_irq(irq); |
2299 | if (i8259A_irq_pending(irq)) | |
2300 | was_pending = 1; | |
2301 | } | |
0b8f1efa | 2302 | cfg = irq_cfg(irq); |
3145e941 | 2303 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2304 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2305 | ||
2306 | return was_pending; | |
2307 | } | |
2308 | ||
54168ed7 | 2309 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2310 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2311 | { |
54168ed7 IM |
2312 | |
2313 | struct irq_cfg *cfg = irq_cfg(irq); | |
2314 | unsigned long flags; | |
2315 | ||
2316 | spin_lock_irqsave(&vector_lock, flags); | |
dac5f412 | 2317 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2318 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2319 | |
2320 | return 1; | |
2321 | } | |
54168ed7 IM |
2322 | #else |
2323 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2324 | { |
dac5f412 | 2325 | apic->send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2326 | |
d6c88a50 | 2327 | return 1; |
54168ed7 IM |
2328 | } |
2329 | #endif | |
497c9a19 | 2330 | |
54168ed7 IM |
2331 | /* |
2332 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2333 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2334 | * handled with the level-triggered descriptor, but that one has slightly | |
2335 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2336 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2337 | * races. | |
2338 | */ | |
497c9a19 | 2339 | |
54168ed7 | 2340 | #ifdef CONFIG_SMP |
497c9a19 | 2341 | |
54168ed7 | 2342 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2343 | |
54168ed7 IM |
2344 | /* |
2345 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2346 | * | |
0280f7c4 SS |
2347 | * For both level and edge triggered, irq migration is a simple atomic |
2348 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2349 | * |
0280f7c4 SS |
2350 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2351 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2352 | * Real vector that is used for interrupting cpu will be coming from | |
2353 | * the interrupt-remapping table entry. | |
54168ed7 | 2354 | */ |
d5dedd45 | 2355 | static int |
e7986739 | 2356 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2357 | { |
54168ed7 | 2358 | struct irq_cfg *cfg; |
54168ed7 | 2359 | struct irte irte; |
54168ed7 | 2360 | unsigned int dest; |
3145e941 | 2361 | unsigned int irq; |
d5dedd45 | 2362 | int ret = -1; |
497c9a19 | 2363 | |
22f65d31 | 2364 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2365 | return ret; |
497c9a19 | 2366 | |
3145e941 | 2367 | irq = desc->irq; |
54168ed7 | 2368 | if (get_irte(irq, &irte)) |
d5dedd45 | 2369 | return ret; |
497c9a19 | 2370 | |
3145e941 YL |
2371 | cfg = desc->chip_data; |
2372 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2373 | return ret; |
54168ed7 | 2374 | |
debccb3e | 2375 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2376 | |
54168ed7 IM |
2377 | irte.vector = cfg->vector; |
2378 | irte.dest_id = IRTE_DEST(dest); | |
2379 | ||
2380 | /* | |
2381 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2382 | */ | |
2383 | modify_irte(irq, &irte); | |
2384 | ||
22f65d31 MT |
2385 | if (cfg->move_in_progress) |
2386 | send_cleanup_vector(cfg); | |
54168ed7 | 2387 | |
7f7ace0c | 2388 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2389 | |
2390 | return 0; | |
54168ed7 IM |
2391 | } |
2392 | ||
54168ed7 IM |
2393 | /* |
2394 | * Migrates the IRQ destination in the process context. | |
2395 | */ | |
d5dedd45 | 2396 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2397 | const struct cpumask *mask) |
54168ed7 | 2398 | { |
d5dedd45 | 2399 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2400 | } |
d5dedd45 | 2401 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2402 | const struct cpumask *mask) |
3145e941 YL |
2403 | { |
2404 | struct irq_desc *desc = irq_to_desc(irq); | |
2405 | ||
d5dedd45 | 2406 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2407 | } |
29b61be6 | 2408 | #else |
d5dedd45 | 2409 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2410 | const struct cpumask *mask) |
2411 | { | |
d5dedd45 | 2412 | return 0; |
29b61be6 | 2413 | } |
54168ed7 IM |
2414 | #endif |
2415 | ||
2416 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2417 | { | |
2418 | unsigned vector, me; | |
8f2466f4 | 2419 | |
54168ed7 | 2420 | ack_APIC_irq(); |
54168ed7 | 2421 | exit_idle(); |
54168ed7 IM |
2422 | irq_enter(); |
2423 | ||
2424 | me = smp_processor_id(); | |
2425 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2426 | unsigned int irq; | |
68a8ca59 | 2427 | unsigned int irr; |
54168ed7 IM |
2428 | struct irq_desc *desc; |
2429 | struct irq_cfg *cfg; | |
2430 | irq = __get_cpu_var(vector_irq)[vector]; | |
2431 | ||
0b8f1efa YL |
2432 | if (irq == -1) |
2433 | continue; | |
2434 | ||
54168ed7 IM |
2435 | desc = irq_to_desc(irq); |
2436 | if (!desc) | |
2437 | continue; | |
2438 | ||
2439 | cfg = irq_cfg(irq); | |
2440 | spin_lock(&desc->lock); | |
2441 | if (!cfg->move_cleanup_count) | |
2442 | goto unlock; | |
2443 | ||
22f65d31 | 2444 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2445 | goto unlock; |
2446 | ||
68a8ca59 SS |
2447 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2448 | /* | |
2449 | * Check if the vector that needs to be cleanedup is | |
2450 | * registered at the cpu's IRR. If so, then this is not | |
2451 | * the best time to clean it up. Lets clean it up in the | |
2452 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2453 | * to myself. | |
2454 | */ | |
2455 | if (irr & (1 << (vector % 32))) { | |
2456 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2457 | goto unlock; | |
2458 | } | |
54168ed7 IM |
2459 | __get_cpu_var(vector_irq)[vector] = -1; |
2460 | cfg->move_cleanup_count--; | |
2461 | unlock: | |
2462 | spin_unlock(&desc->lock); | |
2463 | } | |
2464 | ||
2465 | irq_exit(); | |
2466 | } | |
2467 | ||
3145e941 | 2468 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2469 | { |
3145e941 YL |
2470 | struct irq_desc *desc = *descp; |
2471 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2472 | unsigned vector, me; |
2473 | ||
fcef5911 | 2474 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2475 | return; |
2476 | ||
2477 | vector = ~get_irq_regs()->orig_ax; | |
2478 | me = smp_processor_id(); | |
10b888d6 | 2479 | |
fcef5911 | 2480 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2481 | send_cleanup_vector(cfg); |
497c9a19 YL |
2482 | } |
2483 | #else | |
3145e941 | 2484 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2485 | #endif |
3145e941 | 2486 | |
0280f7c4 SS |
2487 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2488 | { | |
2489 | int apic, pin; | |
2490 | struct irq_pin_list *entry; | |
2491 | ||
2492 | entry = cfg->irq_2_pin; | |
2493 | for (;;) { | |
2494 | ||
2495 | if (!entry) | |
2496 | break; | |
2497 | ||
2498 | apic = entry->apic; | |
2499 | pin = entry->pin; | |
2500 | io_apic_eoi(apic, pin); | |
2501 | entry = entry->next; | |
2502 | } | |
2503 | } | |
2504 | ||
2505 | static void | |
2506 | eoi_ioapic_irq(struct irq_desc *desc) | |
2507 | { | |
2508 | struct irq_cfg *cfg; | |
2509 | unsigned long flags; | |
2510 | unsigned int irq; | |
2511 | ||
2512 | irq = desc->irq; | |
2513 | cfg = desc->chip_data; | |
2514 | ||
2515 | spin_lock_irqsave(&ioapic_lock, flags); | |
2516 | __eoi_ioapic_irq(irq, cfg); | |
2517 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2518 | } | |
2519 | ||
746cddd3 | 2520 | #ifdef CONFIG_X86_X2APIC |
54168ed7 IM |
2521 | static void ack_x2apic_level(unsigned int irq) |
2522 | { | |
0280f7c4 | 2523 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 | 2524 | ack_x2APIC_irq(); |
0280f7c4 | 2525 | eoi_ioapic_irq(desc); |
54168ed7 IM |
2526 | } |
2527 | ||
2528 | static void ack_x2apic_edge(unsigned int irq) | |
2529 | { | |
2530 | ack_x2APIC_irq(); | |
2531 | } | |
2532 | #endif | |
497c9a19 | 2533 | |
1d025192 YL |
2534 | static void ack_apic_edge(unsigned int irq) |
2535 | { | |
3145e941 YL |
2536 | struct irq_desc *desc = irq_to_desc(irq); |
2537 | ||
2538 | irq_complete_move(&desc); | |
1d025192 YL |
2539 | move_native_irq(irq); |
2540 | ack_APIC_irq(); | |
2541 | } | |
2542 | ||
3eb2cce8 | 2543 | atomic_t irq_mis_count; |
3eb2cce8 | 2544 | |
047c8fdb YL |
2545 | static void ack_apic_level(unsigned int irq) |
2546 | { | |
3145e941 YL |
2547 | struct irq_desc *desc = irq_to_desc(irq); |
2548 | ||
3eb2cce8 YL |
2549 | #ifdef CONFIG_X86_32 |
2550 | unsigned long v; | |
2551 | int i; | |
2552 | #endif | |
3145e941 | 2553 | struct irq_cfg *cfg; |
54168ed7 | 2554 | int do_unmask_irq = 0; |
047c8fdb | 2555 | |
3145e941 | 2556 | irq_complete_move(&desc); |
047c8fdb | 2557 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2558 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2559 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2560 | do_unmask_irq = 1; |
3145e941 | 2561 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2562 | } |
047c8fdb YL |
2563 | #endif |
2564 | ||
3eb2cce8 YL |
2565 | #ifdef CONFIG_X86_32 |
2566 | /* | |
2567 | * It appears there is an erratum which affects at least version 0x11 | |
2568 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2569 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2570 | * erroneously delivered as edge-triggered one but the respective IRR | |
2571 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2572 | * message but it will never arrive and further interrupts are blocked | |
2573 | * from the source. The exact reason is so far unknown, but the | |
2574 | * phenomenon was observed when two consecutive interrupt requests | |
2575 | * from a given source get delivered to the same CPU and the source is | |
2576 | * temporarily disabled in between. | |
2577 | * | |
2578 | * A workaround is to simulate an EOI message manually. We achieve it | |
2579 | * by setting the trigger mode to edge and then to level when the edge | |
2580 | * trigger mode gets detected in the TMR of a local APIC for a | |
2581 | * level-triggered interrupt. We mask the source for the time of the | |
2582 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2583 | * The idea is from Manfred Spraul. --macro | |
2584 | */ | |
3145e941 YL |
2585 | cfg = desc->chip_data; |
2586 | i = cfg->vector; | |
3eb2cce8 YL |
2587 | |
2588 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2589 | #endif | |
2590 | ||
54168ed7 IM |
2591 | /* |
2592 | * We must acknowledge the irq before we move it or the acknowledge will | |
2593 | * not propagate properly. | |
2594 | */ | |
2595 | ack_APIC_irq(); | |
2596 | ||
746cddd3 WH |
2597 | if (irq_remapped(irq)) |
2598 | eoi_ioapic_irq(desc); | |
2599 | ||
54168ed7 IM |
2600 | /* Now we can move and renable the irq */ |
2601 | if (unlikely(do_unmask_irq)) { | |
2602 | /* Only migrate the irq if the ack has been received. | |
2603 | * | |
2604 | * On rare occasions the broadcast level triggered ack gets | |
2605 | * delayed going to ioapics, and if we reprogram the | |
2606 | * vector while Remote IRR is still set the irq will never | |
2607 | * fire again. | |
2608 | * | |
2609 | * To prevent this scenario we read the Remote IRR bit | |
2610 | * of the ioapic. This has two effects. | |
2611 | * - On any sane system the read of the ioapic will | |
2612 | * flush writes (and acks) going to the ioapic from | |
2613 | * this cpu. | |
2614 | * - We get to see if the ACK has actually been delivered. | |
2615 | * | |
2616 | * Based on failed experiments of reprogramming the | |
2617 | * ioapic entry from outside of irq context starting | |
2618 | * with masking the ioapic entry and then polling until | |
2619 | * Remote IRR was clear before reprogramming the | |
2620 | * ioapic I don't trust the Remote IRR bit to be | |
2621 | * completey accurate. | |
2622 | * | |
2623 | * However there appears to be no other way to plug | |
2624 | * this race, so if the Remote IRR bit is not | |
2625 | * accurate and is causing problems then it is a hardware bug | |
2626 | * and you can go talk to the chipset vendor about it. | |
2627 | */ | |
3145e941 YL |
2628 | cfg = desc->chip_data; |
2629 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2630 | move_masked_irq(irq); |
3145e941 | 2631 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2632 | } |
1d025192 | 2633 | |
3eb2cce8 | 2634 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2635 | if (!(v & (1 << (i & 0x1f)))) { |
2636 | atomic_inc(&irq_mis_count); | |
2637 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2638 | __mask_and_edge_IO_APIC_irq(cfg); |
2639 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2640 | spin_unlock(&ioapic_lock); |
2641 | } | |
047c8fdb | 2642 | #endif |
3eb2cce8 | 2643 | } |
1d025192 | 2644 | |
d0b03bd1 HW |
2645 | #ifdef CONFIG_INTR_REMAP |
2646 | static void ir_ack_apic_edge(unsigned int irq) | |
2647 | { | |
2648 | #ifdef CONFIG_X86_X2APIC | |
2649 | if (x2apic_enabled()) | |
2650 | return ack_x2apic_edge(irq); | |
2651 | #endif | |
2652 | return ack_apic_edge(irq); | |
2653 | } | |
2654 | ||
2655 | static void ir_ack_apic_level(unsigned int irq) | |
2656 | { | |
2657 | #ifdef CONFIG_X86_X2APIC | |
2658 | if (x2apic_enabled()) | |
2659 | return ack_x2apic_level(irq); | |
2660 | #endif | |
2661 | return ack_apic_level(irq); | |
2662 | } | |
2663 | #endif /* CONFIG_INTR_REMAP */ | |
2664 | ||
f5b9ed7a | 2665 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2666 | .name = "IO-APIC", |
2667 | .startup = startup_ioapic_irq, | |
2668 | .mask = mask_IO_APIC_irq, | |
2669 | .unmask = unmask_IO_APIC_irq, | |
2670 | .ack = ack_apic_edge, | |
2671 | .eoi = ack_apic_level, | |
54d5d424 | 2672 | #ifdef CONFIG_SMP |
d6c88a50 | 2673 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2674 | #endif |
ace80ab7 | 2675 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2676 | }; |
2677 | ||
54168ed7 | 2678 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2679 | .name = "IR-IO-APIC", |
2680 | .startup = startup_ioapic_irq, | |
2681 | .mask = mask_IO_APIC_irq, | |
2682 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2683 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2684 | .ack = ir_ack_apic_edge, |
2685 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2686 | #ifdef CONFIG_SMP |
d6c88a50 | 2687 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2688 | #endif |
54168ed7 IM |
2689 | #endif |
2690 | .retrigger = ioapic_retrigger_irq, | |
2691 | }; | |
1da177e4 LT |
2692 | |
2693 | static inline void init_IO_APIC_traps(void) | |
2694 | { | |
2695 | int irq; | |
08678b08 | 2696 | struct irq_desc *desc; |
da51a821 | 2697 | struct irq_cfg *cfg; |
1da177e4 LT |
2698 | |
2699 | /* | |
2700 | * NOTE! The local APIC isn't very good at handling | |
2701 | * multiple interrupts at the same interrupt level. | |
2702 | * As the interrupt level is determined by taking the | |
2703 | * vector number and shifting that right by 4, we | |
2704 | * want to spread these out a bit so that they don't | |
2705 | * all fall in the same interrupt level. | |
2706 | * | |
2707 | * Also, we've got to be careful not to trash gate | |
2708 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2709 | */ | |
0b8f1efa | 2710 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2711 | cfg = desc->chip_data; |
2712 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2713 | /* |
2714 | * Hmm.. We don't have an entry for this, | |
2715 | * so default to an old-fashioned 8259 | |
2716 | * interrupt if we can.. | |
2717 | */ | |
99d093d1 | 2718 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2719 | make_8259A_irq(irq); |
0b8f1efa | 2720 | else |
1da177e4 | 2721 | /* Strange. Oh, well.. */ |
08678b08 | 2722 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2723 | } |
2724 | } | |
2725 | } | |
2726 | ||
f5b9ed7a IM |
2727 | /* |
2728 | * The local APIC irq-chip implementation: | |
2729 | */ | |
1da177e4 | 2730 | |
36062448 | 2731 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2732 | { |
2733 | unsigned long v; | |
2734 | ||
2735 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2736 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2737 | } |
2738 | ||
36062448 | 2739 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2740 | { |
f5b9ed7a | 2741 | unsigned long v; |
1da177e4 | 2742 | |
f5b9ed7a | 2743 | v = apic_read(APIC_LVT0); |
593f4a78 | 2744 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2745 | } |
1da177e4 | 2746 | |
3145e941 | 2747 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2748 | { |
2749 | ack_APIC_irq(); | |
2750 | } | |
2751 | ||
f5b9ed7a | 2752 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2753 | .name = "local-APIC", |
f5b9ed7a IM |
2754 | .mask = mask_lapic_irq, |
2755 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2756 | .ack = ack_lapic_irq, |
1da177e4 LT |
2757 | }; |
2758 | ||
3145e941 | 2759 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2760 | { |
08678b08 | 2761 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2762 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2763 | "edge"); | |
c88ac1df MR |
2764 | } |
2765 | ||
e9427101 | 2766 | static void __init setup_nmi(void) |
1da177e4 LT |
2767 | { |
2768 | /* | |
36062448 | 2769 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2770 | * We put the 8259A master into AEOI mode and |
2771 | * unmask on all local APICs LVT0 as NMI. | |
2772 | * | |
2773 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2774 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2775 | * the NMI handler or the timer interrupt. | |
36062448 | 2776 | */ |
1da177e4 LT |
2777 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2778 | ||
e9427101 | 2779 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2780 | |
2781 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2782 | } | |
2783 | ||
2784 | /* | |
2785 | * This looks a bit hackish but it's about the only one way of sending | |
2786 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2787 | * not support the ExtINT mode, unfortunately. We need to send these | |
2788 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2789 | * 8259A interrupt line asserted until INTA. --macro | |
2790 | */ | |
28acf285 | 2791 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2792 | { |
fcfd636a | 2793 | int apic, pin, i; |
1da177e4 LT |
2794 | struct IO_APIC_route_entry entry0, entry1; |
2795 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2796 | |
fcfd636a | 2797 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2798 | if (pin == -1) { |
2799 | WARN_ON_ONCE(1); | |
2800 | return; | |
2801 | } | |
fcfd636a | 2802 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2803 | if (apic == -1) { |
2804 | WARN_ON_ONCE(1); | |
1da177e4 | 2805 | return; |
956fb531 | 2806 | } |
1da177e4 | 2807 | |
cf4c6a2f | 2808 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2809 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2810 | |
2811 | memset(&entry1, 0, sizeof(entry1)); | |
2812 | ||
2813 | entry1.dest_mode = 0; /* physical delivery */ | |
2814 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2815 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2816 | entry1.delivery_mode = dest_ExtINT; |
2817 | entry1.polarity = entry0.polarity; | |
2818 | entry1.trigger = 0; | |
2819 | entry1.vector = 0; | |
2820 | ||
cf4c6a2f | 2821 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2822 | |
2823 | save_control = CMOS_READ(RTC_CONTROL); | |
2824 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2825 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2826 | RTC_FREQ_SELECT); | |
2827 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2828 | ||
2829 | i = 100; | |
2830 | while (i-- > 0) { | |
2831 | mdelay(10); | |
2832 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2833 | i -= 10; | |
2834 | } | |
2835 | ||
2836 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2837 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2838 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2839 | |
cf4c6a2f | 2840 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2841 | } |
2842 | ||
efa2559f | 2843 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2844 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2845 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2846 | { |
2847 | disable_timer_pin_1 = 1; | |
2848 | return 0; | |
2849 | } | |
54168ed7 | 2850 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2851 | |
2852 | int timer_through_8259 __initdata; | |
2853 | ||
1da177e4 LT |
2854 | /* |
2855 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2856 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2857 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2858 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2859 | * |
2860 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2861 | */ |
8542b200 | 2862 | static inline void __init check_timer(void) |
1da177e4 | 2863 | { |
3145e941 YL |
2864 | struct irq_desc *desc = irq_to_desc(0); |
2865 | struct irq_cfg *cfg = desc->chip_data; | |
2866 | int cpu = boot_cpu_id; | |
fcfd636a | 2867 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2868 | unsigned long flags; |
047c8fdb | 2869 | int no_pin1 = 0; |
4aae0702 IM |
2870 | |
2871 | local_irq_save(flags); | |
d4d25dec | 2872 | |
1da177e4 LT |
2873 | /* |
2874 | * get/set the timer IRQ vector: | |
2875 | */ | |
2876 | disable_8259A_irq(0); | |
fe402e1f | 2877 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2878 | |
2879 | /* | |
d11d5794 MR |
2880 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2881 | * wire has to be disabled in the local APIC. Also | |
2882 | * timer interrupts need to be acknowledged manually in | |
2883 | * the 8259A for the i82489DX when using the NMI | |
2884 | * watchdog as that APIC treats NMIs as level-triggered. | |
2885 | * The AEOI mode will finish them in the 8259A | |
2886 | * automatically. | |
1da177e4 | 2887 | */ |
593f4a78 | 2888 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2889 | init_8259A(1); |
54168ed7 | 2890 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2891 | { |
2892 | unsigned int ver; | |
2893 | ||
2894 | ver = apic_read(APIC_LVR); | |
2895 | ver = GET_APIC_VERSION(ver); | |
2896 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2897 | } | |
54168ed7 | 2898 | #endif |
1da177e4 | 2899 | |
fcfd636a EB |
2900 | pin1 = find_isa_irq_pin(0, mp_INT); |
2901 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2902 | pin2 = ioapic_i8259.pin; | |
2903 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2904 | |
49a66a0b MR |
2905 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2906 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2907 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2908 | |
691874fa MR |
2909 | /* |
2910 | * Some BIOS writers are clueless and report the ExtINTA | |
2911 | * I/O APIC input from the cascaded 8259A as the timer | |
2912 | * interrupt input. So just in case, if only one pin | |
2913 | * was found above, try it both directly and through the | |
2914 | * 8259A. | |
2915 | */ | |
2916 | if (pin1 == -1) { | |
54168ed7 IM |
2917 | if (intr_remapping_enabled) |
2918 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2919 | pin1 = pin2; |
2920 | apic1 = apic2; | |
2921 | no_pin1 = 1; | |
2922 | } else if (pin2 == -1) { | |
2923 | pin2 = pin1; | |
2924 | apic2 = apic1; | |
2925 | } | |
2926 | ||
1da177e4 LT |
2927 | if (pin1 != -1) { |
2928 | /* | |
2929 | * Ok, does IRQ0 through the IOAPIC work? | |
2930 | */ | |
691874fa | 2931 | if (no_pin1) { |
3145e941 | 2932 | add_pin_to_irq_cpu(cfg, cpu, apic1, pin1); |
497c9a19 | 2933 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2934 | } else { |
2935 | /* for edge trigger, setup_IO_APIC_irq already | |
2936 | * leave it unmasked. | |
2937 | * so only need to unmask if it is level-trigger | |
2938 | * do we really have level trigger timer? | |
2939 | */ | |
2940 | int idx; | |
2941 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2942 | if (idx != -1 && irq_trigger(idx)) | |
2943 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 2944 | } |
1da177e4 LT |
2945 | if (timer_irq_works()) { |
2946 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2947 | setup_nmi(); |
2948 | enable_8259A_irq(0); | |
1da177e4 | 2949 | } |
66759a01 CE |
2950 | if (disable_timer_pin_1 > 0) |
2951 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2952 | goto out; |
1da177e4 | 2953 | } |
54168ed7 IM |
2954 | if (intr_remapping_enabled) |
2955 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2956 | local_irq_disable(); |
fcfd636a | 2957 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2958 | if (!no_pin1) |
49a66a0b MR |
2959 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2960 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2961 | |
49a66a0b MR |
2962 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2963 | "(IRQ0) through the 8259A ...\n"); | |
2964 | apic_printk(APIC_QUIET, KERN_INFO | |
2965 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2966 | /* |
2967 | * legacy devices should be connected to IO APIC #0 | |
2968 | */ | |
3145e941 | 2969 | replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2); |
497c9a19 | 2970 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
ecd29476 | 2971 | enable_8259A_irq(0); |
1da177e4 | 2972 | if (timer_irq_works()) { |
49a66a0b | 2973 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2974 | timer_through_8259 = 1; |
1da177e4 | 2975 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2976 | disable_8259A_irq(0); |
1da177e4 | 2977 | setup_nmi(); |
60134ebe | 2978 | enable_8259A_irq(0); |
1da177e4 | 2979 | } |
4aae0702 | 2980 | goto out; |
1da177e4 LT |
2981 | } |
2982 | /* | |
2983 | * Cleanup, just in case ... | |
2984 | */ | |
f72dccac | 2985 | local_irq_disable(); |
ecd29476 | 2986 | disable_8259A_irq(0); |
fcfd636a | 2987 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2988 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2989 | } |
1da177e4 LT |
2990 | |
2991 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2992 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2993 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2994 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2995 | } |
54168ed7 | 2996 | #ifdef CONFIG_X86_32 |
d11d5794 | 2997 | timer_ack = 0; |
54168ed7 | 2998 | #endif |
1da177e4 | 2999 | |
49a66a0b MR |
3000 | apic_printk(APIC_QUIET, KERN_INFO |
3001 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3002 | |
3145e941 | 3003 | lapic_register_intr(0, desc); |
497c9a19 | 3004 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
3005 | enable_8259A_irq(0); |
3006 | ||
3007 | if (timer_irq_works()) { | |
49a66a0b | 3008 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3009 | goto out; |
1da177e4 | 3010 | } |
f72dccac | 3011 | local_irq_disable(); |
e67465f1 | 3012 | disable_8259A_irq(0); |
497c9a19 | 3013 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3014 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3015 | |
49a66a0b MR |
3016 | apic_printk(APIC_QUIET, KERN_INFO |
3017 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3018 | |
1da177e4 LT |
3019 | init_8259A(0); |
3020 | make_8259A_irq(0); | |
593f4a78 | 3021 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3022 | |
3023 | unlock_ExtINT_logic(); | |
3024 | ||
3025 | if (timer_irq_works()) { | |
49a66a0b | 3026 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3027 | goto out; |
1da177e4 | 3028 | } |
f72dccac | 3029 | local_irq_disable(); |
49a66a0b | 3030 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3031 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3032 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3033 | out: |
3034 | local_irq_restore(flags); | |
1da177e4 LT |
3035 | } |
3036 | ||
3037 | /* | |
af174783 MR |
3038 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3039 | * to devices. However there may be an I/O APIC pin available for | |
3040 | * this interrupt regardless. The pin may be left unconnected, but | |
3041 | * typically it will be reused as an ExtINT cascade interrupt for | |
3042 | * the master 8259A. In the MPS case such a pin will normally be | |
3043 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3044 | * there is no provision for ExtINT interrupts, and in the absence | |
3045 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3046 | * interrupt, that is edge-triggered and unmasked by default. We | |
3047 | * used to do this, but it caused problems on some systems because | |
3048 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3049 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3050 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3051 | * the I/O APIC in all cases now. No actual device should request | |
3052 | * it anyway. --macro | |
1da177e4 LT |
3053 | */ |
3054 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
3055 | ||
3056 | void __init setup_IO_APIC(void) | |
3057 | { | |
54168ed7 | 3058 | |
54168ed7 IM |
3059 | /* |
3060 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3061 | */ | |
1da177e4 | 3062 | |
af174783 | 3063 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3064 | |
54168ed7 | 3065 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3066 | /* |
54168ed7 IM |
3067 | * Set up IO-APIC IRQ routing. |
3068 | */ | |
3069 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3070 | if (!acpi_ioapic) |
3071 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3072 | #endif |
1da177e4 LT |
3073 | sync_Arb_IDs(); |
3074 | setup_IO_APIC_irqs(); | |
3075 | init_IO_APIC_traps(); | |
1e4c85f9 | 3076 | check_timer(); |
1da177e4 LT |
3077 | } |
3078 | ||
3079 | /* | |
54168ed7 IM |
3080 | * Called after all the initialization is done. If we didnt find any |
3081 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3082 | */ |
36062448 | 3083 | |
1da177e4 LT |
3084 | static int __init io_apic_bug_finalize(void) |
3085 | { | |
d6c88a50 TG |
3086 | if (sis_apic_bug == -1) |
3087 | sis_apic_bug = 0; | |
3088 | return 0; | |
1da177e4 LT |
3089 | } |
3090 | ||
3091 | late_initcall(io_apic_bug_finalize); | |
3092 | ||
3093 | struct sysfs_ioapic_data { | |
3094 | struct sys_device dev; | |
3095 | struct IO_APIC_route_entry entry[0]; | |
3096 | }; | |
54168ed7 | 3097 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3098 | |
438510f6 | 3099 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3100 | { |
3101 | struct IO_APIC_route_entry *entry; | |
3102 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3103 | int i; |
36062448 | 3104 | |
1da177e4 LT |
3105 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3106 | entry = data->entry; | |
54168ed7 IM |
3107 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3108 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3109 | |
3110 | return 0; | |
3111 | } | |
3112 | ||
3113 | static int ioapic_resume(struct sys_device *dev) | |
3114 | { | |
3115 | struct IO_APIC_route_entry *entry; | |
3116 | struct sysfs_ioapic_data *data; | |
3117 | unsigned long flags; | |
3118 | union IO_APIC_reg_00 reg_00; | |
3119 | int i; | |
36062448 | 3120 | |
1da177e4 LT |
3121 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3122 | entry = data->entry; | |
3123 | ||
3124 | spin_lock_irqsave(&ioapic_lock, flags); | |
3125 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3126 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3127 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3128 | io_apic_write(dev->id, 0, reg_00.raw); |
3129 | } | |
1da177e4 | 3130 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3131 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3132 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3133 | |
3134 | return 0; | |
3135 | } | |
3136 | ||
3137 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3138 | .name = "ioapic", |
1da177e4 LT |
3139 | .suspend = ioapic_suspend, |
3140 | .resume = ioapic_resume, | |
3141 | }; | |
3142 | ||
3143 | static int __init ioapic_init_sysfs(void) | |
3144 | { | |
54168ed7 IM |
3145 | struct sys_device * dev; |
3146 | int i, size, error; | |
1da177e4 LT |
3147 | |
3148 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3149 | if (error) | |
3150 | return error; | |
3151 | ||
54168ed7 | 3152 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3153 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3154 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3155 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3156 | if (!mp_ioapic_data[i]) { |
3157 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3158 | continue; | |
3159 | } | |
1da177e4 | 3160 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3161 | dev->id = i; |
1da177e4 LT |
3162 | dev->cls = &ioapic_sysdev_class; |
3163 | error = sysdev_register(dev); | |
3164 | if (error) { | |
3165 | kfree(mp_ioapic_data[i]); | |
3166 | mp_ioapic_data[i] = NULL; | |
3167 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3168 | continue; | |
3169 | } | |
3170 | } | |
3171 | ||
3172 | return 0; | |
3173 | } | |
3174 | ||
3175 | device_initcall(ioapic_init_sysfs); | |
3176 | ||
abcaa2b8 | 3177 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
3fc471ed | 3178 | /* |
95d77884 | 3179 | * Dynamic irq allocate and deallocation |
3fc471ed | 3180 | */ |
199751d7 | 3181 | unsigned int create_irq_nr(unsigned int irq_want) |
3fc471ed | 3182 | { |
ace80ab7 | 3183 | /* Allocate an unused irq */ |
54168ed7 IM |
3184 | unsigned int irq; |
3185 | unsigned int new; | |
3fc471ed | 3186 | unsigned long flags; |
0b8f1efa YL |
3187 | struct irq_cfg *cfg_new = NULL; |
3188 | int cpu = boot_cpu_id; | |
3189 | struct irq_desc *desc_new = NULL; | |
199751d7 YL |
3190 | |
3191 | irq = 0; | |
abcaa2b8 YL |
3192 | if (irq_want < nr_irqs_gsi) |
3193 | irq_want = nr_irqs_gsi; | |
3194 | ||
ace80ab7 | 3195 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3196 | for (new = irq_want; new < nr_irqs; new++) { |
0b8f1efa YL |
3197 | desc_new = irq_to_desc_alloc_cpu(new, cpu); |
3198 | if (!desc_new) { | |
3199 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3200 | continue; |
0b8f1efa YL |
3201 | } |
3202 | cfg_new = desc_new->chip_data; | |
3203 | ||
3204 | if (cfg_new->vector != 0) | |
ace80ab7 | 3205 | continue; |
fe402e1f | 3206 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3207 | irq = new; |
3208 | break; | |
3209 | } | |
3210 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3211 | |
199751d7 | 3212 | if (irq > 0) { |
3fc471ed | 3213 | dynamic_irq_init(irq); |
0b8f1efa YL |
3214 | /* restore it, in case dynamic_irq_init clear it */ |
3215 | if (desc_new) | |
3216 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3217 | } |
3218 | return irq; | |
3219 | } | |
3220 | ||
199751d7 YL |
3221 | int create_irq(void) |
3222 | { | |
be5d5350 | 3223 | unsigned int irq_want; |
54168ed7 IM |
3224 | int irq; |
3225 | ||
be5d5350 YL |
3226 | irq_want = nr_irqs_gsi; |
3227 | irq = create_irq_nr(irq_want); | |
54168ed7 IM |
3228 | |
3229 | if (irq == 0) | |
3230 | irq = -1; | |
3231 | ||
3232 | return irq; | |
199751d7 YL |
3233 | } |
3234 | ||
3fc471ed EB |
3235 | void destroy_irq(unsigned int irq) |
3236 | { | |
3237 | unsigned long flags; | |
0b8f1efa YL |
3238 | struct irq_cfg *cfg; |
3239 | struct irq_desc *desc; | |
3fc471ed | 3240 | |
0b8f1efa YL |
3241 | /* store it, in case dynamic_irq_cleanup clear it */ |
3242 | desc = irq_to_desc(irq); | |
3243 | cfg = desc->chip_data; | |
3fc471ed | 3244 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3245 | /* connect back irq_cfg */ |
3246 | if (desc) | |
3247 | desc->chip_data = cfg; | |
3fc471ed | 3248 | |
54168ed7 | 3249 | free_irte(irq); |
3fc471ed | 3250 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3251 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3252 | spin_unlock_irqrestore(&vector_lock, flags); |
3253 | } | |
3fc471ed | 3254 | |
2d3fcc1c | 3255 | /* |
27b46d76 | 3256 | * MSI message composition |
2d3fcc1c EB |
3257 | */ |
3258 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3259 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3260 | { |
497c9a19 YL |
3261 | struct irq_cfg *cfg; |
3262 | int err; | |
2d3fcc1c EB |
3263 | unsigned dest; |
3264 | ||
f1182638 JB |
3265 | if (disable_apic) |
3266 | return -ENXIO; | |
3267 | ||
3145e941 | 3268 | cfg = irq_cfg(irq); |
fe402e1f | 3269 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3270 | if (err) |
3271 | return err; | |
2d3fcc1c | 3272 | |
debccb3e | 3273 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3274 | |
54168ed7 IM |
3275 | if (irq_remapped(irq)) { |
3276 | struct irte irte; | |
3277 | int ir_index; | |
3278 | u16 sub_handle; | |
3279 | ||
3280 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3281 | BUG_ON(ir_index == -1); | |
3282 | ||
3283 | memset (&irte, 0, sizeof(irte)); | |
3284 | ||
3285 | irte.present = 1; | |
9b5bc8dc | 3286 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3287 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3288 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3289 | irte.vector = cfg->vector; |
3290 | irte.dest_id = IRTE_DEST(dest); | |
3291 | ||
3292 | modify_irte(irq, &irte); | |
3293 | ||
3294 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3295 | msg->data = sub_handle; | |
3296 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3297 | MSI_ADDR_IR_SHV | | |
3298 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3299 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3300 | } else { |
9d783ba0 SS |
3301 | if (x2apic_enabled()) |
3302 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3303 | MSI_ADDR_EXT_DEST_ID(dest); | |
3304 | else | |
3305 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3306 | ||
54168ed7 IM |
3307 | msg->address_lo = |
3308 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3309 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3310 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3311 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3312 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3313 | MSI_ADDR_REDIRECTION_CPU: |
3314 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3315 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3316 | |
54168ed7 IM |
3317 | msg->data = |
3318 | MSI_DATA_TRIGGER_EDGE | | |
3319 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3320 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3321 | MSI_DATA_DELIVERY_FIXED: |
3322 | MSI_DATA_DELIVERY_LOWPRI) | | |
3323 | MSI_DATA_VECTOR(cfg->vector); | |
3324 | } | |
497c9a19 | 3325 | return err; |
2d3fcc1c EB |
3326 | } |
3327 | ||
3b7d1921 | 3328 | #ifdef CONFIG_SMP |
d5dedd45 | 3329 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3330 | { |
3145e941 | 3331 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3332 | struct irq_cfg *cfg; |
3b7d1921 EB |
3333 | struct msi_msg msg; |
3334 | unsigned int dest; | |
3b7d1921 | 3335 | |
22f65d31 MT |
3336 | dest = set_desc_affinity(desc, mask); |
3337 | if (dest == BAD_APICID) | |
d5dedd45 | 3338 | return -1; |
2d3fcc1c | 3339 | |
3145e941 | 3340 | cfg = desc->chip_data; |
2d3fcc1c | 3341 | |
3145e941 | 3342 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3343 | |
3344 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3345 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3346 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3347 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3348 | ||
3145e941 | 3349 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3350 | |
3351 | return 0; | |
2d3fcc1c | 3352 | } |
54168ed7 IM |
3353 | #ifdef CONFIG_INTR_REMAP |
3354 | /* | |
3355 | * Migrate the MSI irq to another cpumask. This migration is | |
3356 | * done in the process context using interrupt-remapping hardware. | |
3357 | */ | |
d5dedd45 | 3358 | static int |
e7986739 | 3359 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3360 | { |
3145e941 | 3361 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3362 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3363 | unsigned int dest; |
54168ed7 | 3364 | struct irte irte; |
54168ed7 IM |
3365 | |
3366 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3367 | return -1; |
54168ed7 | 3368 | |
22f65d31 MT |
3369 | dest = set_desc_affinity(desc, mask); |
3370 | if (dest == BAD_APICID) | |
d5dedd45 | 3371 | return -1; |
54168ed7 | 3372 | |
54168ed7 IM |
3373 | irte.vector = cfg->vector; |
3374 | irte.dest_id = IRTE_DEST(dest); | |
3375 | ||
3376 | /* | |
3377 | * atomically update the IRTE with the new destination and vector. | |
3378 | */ | |
3379 | modify_irte(irq, &irte); | |
3380 | ||
3381 | /* | |
3382 | * After this point, all the interrupts will start arriving | |
3383 | * at the new destination. So, time to cleanup the previous | |
3384 | * vector allocation. | |
3385 | */ | |
22f65d31 MT |
3386 | if (cfg->move_in_progress) |
3387 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3388 | |
3389 | return 0; | |
54168ed7 | 3390 | } |
3145e941 | 3391 | |
54168ed7 | 3392 | #endif |
3b7d1921 | 3393 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3394 | |
3b7d1921 EB |
3395 | /* |
3396 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3397 | * which implement the MSI or MSI-X Capability Structure. | |
3398 | */ | |
3399 | static struct irq_chip msi_chip = { | |
3400 | .name = "PCI-MSI", | |
3401 | .unmask = unmask_msi_irq, | |
3402 | .mask = mask_msi_irq, | |
1d025192 | 3403 | .ack = ack_apic_edge, |
3b7d1921 EB |
3404 | #ifdef CONFIG_SMP |
3405 | .set_affinity = set_msi_irq_affinity, | |
3406 | #endif | |
3407 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3408 | }; |
3409 | ||
54168ed7 IM |
3410 | static struct irq_chip msi_ir_chip = { |
3411 | .name = "IR-PCI-MSI", | |
3412 | .unmask = unmask_msi_irq, | |
3413 | .mask = mask_msi_irq, | |
a1e38ca5 | 3414 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3415 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3416 | #ifdef CONFIG_SMP |
3417 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3418 | #endif |
54168ed7 IM |
3419 | #endif |
3420 | .retrigger = ioapic_retrigger_irq, | |
3421 | }; | |
3422 | ||
3423 | /* | |
3424 | * Map the PCI dev to the corresponding remapping hardware unit | |
3425 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3426 | * in it. | |
3427 | */ | |
3428 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3429 | { | |
3430 | struct intel_iommu *iommu; | |
3431 | int index; | |
3432 | ||
3433 | iommu = map_dev_to_ir(dev); | |
3434 | if (!iommu) { | |
3435 | printk(KERN_ERR | |
3436 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3437 | return -ENOENT; | |
3438 | } | |
3439 | ||
3440 | index = alloc_irte(iommu, irq, nvec); | |
3441 | if (index < 0) { | |
3442 | printk(KERN_ERR | |
3443 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3444 | pci_name(dev)); |
54168ed7 IM |
3445 | return -ENOSPC; |
3446 | } | |
3447 | return index; | |
3448 | } | |
1d025192 | 3449 | |
3145e941 | 3450 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3451 | { |
3452 | int ret; | |
3453 | struct msi_msg msg; | |
3454 | ||
3455 | ret = msi_compose_msg(dev, irq, &msg); | |
3456 | if (ret < 0) | |
3457 | return ret; | |
3458 | ||
3145e941 | 3459 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3460 | write_msi_msg(irq, &msg); |
3461 | ||
54168ed7 IM |
3462 | if (irq_remapped(irq)) { |
3463 | struct irq_desc *desc = irq_to_desc(irq); | |
3464 | /* | |
3465 | * irq migration in process context | |
3466 | */ | |
3467 | desc->status |= IRQ_MOVE_PCNTXT; | |
3468 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3469 | } else | |
54168ed7 | 3470 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3471 | |
c81bba49 YL |
3472 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3473 | ||
1d025192 YL |
3474 | return 0; |
3475 | } | |
3476 | ||
047c8fdb YL |
3477 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3478 | { | |
54168ed7 IM |
3479 | unsigned int irq; |
3480 | int ret, sub_handle; | |
0b8f1efa | 3481 | struct msi_desc *msidesc; |
54168ed7 | 3482 | unsigned int irq_want; |
1cc18521 | 3483 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3484 | int index = 0; |
54168ed7 | 3485 | |
1c8d7b0a MW |
3486 | /* x86 doesn't support multiple MSI yet */ |
3487 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3488 | return 1; | |
3489 | ||
be5d5350 | 3490 | irq_want = nr_irqs_gsi; |
54168ed7 | 3491 | sub_handle = 0; |
0b8f1efa YL |
3492 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
3493 | irq = create_irq_nr(irq_want); | |
54168ed7 IM |
3494 | if (irq == 0) |
3495 | return -1; | |
f1ee5548 | 3496 | irq_want = irq + 1; |
54168ed7 IM |
3497 | if (!intr_remapping_enabled) |
3498 | goto no_ir; | |
3499 | ||
3500 | if (!sub_handle) { | |
3501 | /* | |
3502 | * allocate the consecutive block of IRTE's | |
3503 | * for 'nvec' | |
3504 | */ | |
3505 | index = msi_alloc_irte(dev, irq, nvec); | |
3506 | if (index < 0) { | |
3507 | ret = index; | |
3508 | goto error; | |
3509 | } | |
3510 | } else { | |
3511 | iommu = map_dev_to_ir(dev); | |
3512 | if (!iommu) { | |
3513 | ret = -ENOENT; | |
3514 | goto error; | |
3515 | } | |
3516 | /* | |
3517 | * setup the mapping between the irq and the IRTE | |
3518 | * base index, the sub_handle pointing to the | |
3519 | * appropriate interrupt remap table entry. | |
3520 | */ | |
3521 | set_irte_irq(irq, iommu, index, sub_handle); | |
3522 | } | |
3523 | no_ir: | |
0b8f1efa | 3524 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3525 | if (ret < 0) |
3526 | goto error; | |
3527 | sub_handle++; | |
3528 | } | |
3529 | return 0; | |
047c8fdb YL |
3530 | |
3531 | error: | |
54168ed7 IM |
3532 | destroy_irq(irq); |
3533 | return ret; | |
047c8fdb YL |
3534 | } |
3535 | ||
3b7d1921 EB |
3536 | void arch_teardown_msi_irq(unsigned int irq) |
3537 | { | |
f7feaca7 | 3538 | destroy_irq(irq); |
3b7d1921 EB |
3539 | } |
3540 | ||
9d783ba0 | 3541 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3542 | #ifdef CONFIG_SMP |
d5dedd45 | 3543 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3544 | { |
3145e941 | 3545 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3546 | struct irq_cfg *cfg; |
3547 | struct msi_msg msg; | |
3548 | unsigned int dest; | |
54168ed7 | 3549 | |
22f65d31 MT |
3550 | dest = set_desc_affinity(desc, mask); |
3551 | if (dest == BAD_APICID) | |
d5dedd45 | 3552 | return -1; |
54168ed7 | 3553 | |
3145e941 | 3554 | cfg = desc->chip_data; |
54168ed7 IM |
3555 | |
3556 | dmar_msi_read(irq, &msg); | |
3557 | ||
3558 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3559 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3560 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3561 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3562 | ||
3563 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3564 | |
3565 | return 0; | |
54168ed7 | 3566 | } |
3145e941 | 3567 | |
54168ed7 IM |
3568 | #endif /* CONFIG_SMP */ |
3569 | ||
3570 | struct irq_chip dmar_msi_type = { | |
3571 | .name = "DMAR_MSI", | |
3572 | .unmask = dmar_msi_unmask, | |
3573 | .mask = dmar_msi_mask, | |
3574 | .ack = ack_apic_edge, | |
3575 | #ifdef CONFIG_SMP | |
3576 | .set_affinity = dmar_msi_set_affinity, | |
3577 | #endif | |
3578 | .retrigger = ioapic_retrigger_irq, | |
3579 | }; | |
3580 | ||
3581 | int arch_setup_dmar_msi(unsigned int irq) | |
3582 | { | |
3583 | int ret; | |
3584 | struct msi_msg msg; | |
2d3fcc1c | 3585 | |
54168ed7 IM |
3586 | ret = msi_compose_msg(NULL, irq, &msg); |
3587 | if (ret < 0) | |
3588 | return ret; | |
3589 | dmar_msi_write(irq, &msg); | |
3590 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3591 | "edge"); | |
3592 | return 0; | |
3593 | } | |
3594 | #endif | |
3595 | ||
58ac1e76 | 3596 | #ifdef CONFIG_HPET_TIMER |
3597 | ||
3598 | #ifdef CONFIG_SMP | |
d5dedd45 | 3599 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3600 | { |
3145e941 | 3601 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3602 | struct irq_cfg *cfg; |
58ac1e76 | 3603 | struct msi_msg msg; |
3604 | unsigned int dest; | |
58ac1e76 | 3605 | |
22f65d31 MT |
3606 | dest = set_desc_affinity(desc, mask); |
3607 | if (dest == BAD_APICID) | |
d5dedd45 | 3608 | return -1; |
58ac1e76 | 3609 | |
3145e941 | 3610 | cfg = desc->chip_data; |
58ac1e76 | 3611 | |
3612 | hpet_msi_read(irq, &msg); | |
3613 | ||
3614 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3615 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3616 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3617 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3618 | ||
3619 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3620 | |
3621 | return 0; | |
58ac1e76 | 3622 | } |
3145e941 | 3623 | |
58ac1e76 | 3624 | #endif /* CONFIG_SMP */ |
3625 | ||
1cc18521 | 3626 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3627 | .name = "HPET_MSI", |
3628 | .unmask = hpet_msi_unmask, | |
3629 | .mask = hpet_msi_mask, | |
3630 | .ack = ack_apic_edge, | |
3631 | #ifdef CONFIG_SMP | |
3632 | .set_affinity = hpet_msi_set_affinity, | |
3633 | #endif | |
3634 | .retrigger = ioapic_retrigger_irq, | |
3635 | }; | |
3636 | ||
3637 | int arch_setup_hpet_msi(unsigned int irq) | |
3638 | { | |
3639 | int ret; | |
3640 | struct msi_msg msg; | |
6ec3cfec | 3641 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3642 | |
3643 | ret = msi_compose_msg(NULL, irq, &msg); | |
3644 | if (ret < 0) | |
3645 | return ret; | |
3646 | ||
3647 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3648 | desc->status |= IRQ_MOVE_PCNTXT; |
58ac1e76 | 3649 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, |
3650 | "edge"); | |
c81bba49 | 3651 | |
58ac1e76 | 3652 | return 0; |
3653 | } | |
3654 | #endif | |
3655 | ||
54168ed7 | 3656 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3657 | /* |
3658 | * Hypertransport interrupt support | |
3659 | */ | |
3660 | #ifdef CONFIG_HT_IRQ | |
3661 | ||
3662 | #ifdef CONFIG_SMP | |
3663 | ||
497c9a19 | 3664 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3665 | { |
ec68307c EB |
3666 | struct ht_irq_msg msg; |
3667 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3668 | |
497c9a19 | 3669 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3670 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3671 | |
497c9a19 | 3672 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3673 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3674 | |
ec68307c | 3675 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3676 | } |
3677 | ||
d5dedd45 | 3678 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3679 | { |
3145e941 | 3680 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3681 | struct irq_cfg *cfg; |
8b955b0d | 3682 | unsigned int dest; |
8b955b0d | 3683 | |
22f65d31 MT |
3684 | dest = set_desc_affinity(desc, mask); |
3685 | if (dest == BAD_APICID) | |
d5dedd45 | 3686 | return -1; |
8b955b0d | 3687 | |
3145e941 | 3688 | cfg = desc->chip_data; |
8b955b0d | 3689 | |
497c9a19 | 3690 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3691 | |
3692 | return 0; | |
8b955b0d | 3693 | } |
3145e941 | 3694 | |
8b955b0d EB |
3695 | #endif |
3696 | ||
c37e108d | 3697 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3698 | .name = "PCI-HT", |
3699 | .mask = mask_ht_irq, | |
3700 | .unmask = unmask_ht_irq, | |
1d025192 | 3701 | .ack = ack_apic_edge, |
8b955b0d EB |
3702 | #ifdef CONFIG_SMP |
3703 | .set_affinity = set_ht_irq_affinity, | |
3704 | #endif | |
3705 | .retrigger = ioapic_retrigger_irq, | |
3706 | }; | |
3707 | ||
3708 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3709 | { | |
497c9a19 YL |
3710 | struct irq_cfg *cfg; |
3711 | int err; | |
8b955b0d | 3712 | |
f1182638 JB |
3713 | if (disable_apic) |
3714 | return -ENXIO; | |
3715 | ||
3145e941 | 3716 | cfg = irq_cfg(irq); |
fe402e1f | 3717 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3718 | if (!err) { |
ec68307c | 3719 | struct ht_irq_msg msg; |
8b955b0d | 3720 | unsigned dest; |
8b955b0d | 3721 | |
debccb3e IM |
3722 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3723 | apic->target_cpus()); | |
8b955b0d | 3724 | |
ec68307c | 3725 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3726 | |
ec68307c EB |
3727 | msg.address_lo = |
3728 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3729 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3730 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3731 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3732 | HT_IRQ_LOW_DM_PHYSICAL : |
3733 | HT_IRQ_LOW_DM_LOGICAL) | | |
3734 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3735 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3736 | HT_IRQ_LOW_MT_FIXED : |
3737 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3738 | HT_IRQ_LOW_IRQ_MASKED; | |
3739 | ||
ec68307c | 3740 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3741 | |
a460e745 IM |
3742 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3743 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3744 | |
3745 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3746 | } |
497c9a19 | 3747 | return err; |
8b955b0d EB |
3748 | } |
3749 | #endif /* CONFIG_HT_IRQ */ | |
3750 | ||
03b48632 | 3751 | #ifdef CONFIG_X86_UV |
4173a0e7 DN |
3752 | /* |
3753 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3754 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3755 | */ | |
3756 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3757 | unsigned long mmr_offset) | |
3758 | { | |
22f65d31 | 3759 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3760 | struct irq_cfg *cfg; |
3761 | int mmr_pnode; | |
3762 | unsigned long mmr_value; | |
3763 | struct uv_IO_APIC_route_entry *entry; | |
3764 | unsigned long flags; | |
3765 | int err; | |
3766 | ||
3145e941 YL |
3767 | cfg = irq_cfg(irq); |
3768 | ||
e7986739 | 3769 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3770 | if (err != 0) |
3771 | return err; | |
3772 | ||
3773 | spin_lock_irqsave(&vector_lock, flags); | |
3774 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3775 | irq_name); | |
3776 | spin_unlock_irqrestore(&vector_lock, flags); | |
3777 | ||
4173a0e7 DN |
3778 | mmr_value = 0; |
3779 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3780 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3781 | ||
3782 | entry->vector = cfg->vector; | |
9b5bc8dc IM |
3783 | entry->delivery_mode = apic->irq_delivery_mode; |
3784 | entry->dest_mode = apic->irq_dest_mode; | |
4173a0e7 DN |
3785 | entry->polarity = 0; |
3786 | entry->trigger = 0; | |
3787 | entry->mask = 0; | |
debccb3e | 3788 | entry->dest = apic->cpu_mask_to_apicid(eligible_cpu); |
4173a0e7 DN |
3789 | |
3790 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3791 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3792 | ||
3793 | return irq; | |
3794 | } | |
3795 | ||
3796 | /* | |
3797 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3798 | * longer allowed to be sent. | |
3799 | */ | |
3800 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3801 | { | |
3802 | unsigned long mmr_value; | |
3803 | struct uv_IO_APIC_route_entry *entry; | |
3804 | int mmr_pnode; | |
3805 | ||
3806 | mmr_value = 0; | |
3807 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3808 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3809 | ||
3810 | entry->mask = 1; | |
3811 | ||
3812 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3813 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3814 | } | |
3815 | #endif /* CONFIG_X86_64 */ | |
3816 | ||
9d6a4d08 YL |
3817 | int __init io_apic_get_redir_entries (int ioapic) |
3818 | { | |
3819 | union IO_APIC_reg_01 reg_01; | |
3820 | unsigned long flags; | |
3821 | ||
3822 | spin_lock_irqsave(&ioapic_lock, flags); | |
3823 | reg_01.raw = io_apic_read(ioapic, 1); | |
3824 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3825 | ||
3826 | return reg_01.bits.entries; | |
3827 | } | |
3828 | ||
be5d5350 | 3829 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3830 | { |
be5d5350 YL |
3831 | int nr = 0; |
3832 | ||
cc6c5006 YL |
3833 | nr = acpi_probe_gsi(); |
3834 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3835 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3836 | } else { |
3837 | /* for acpi=off or acpi is not compiled in */ | |
3838 | int idx; | |
3839 | ||
3840 | nr = 0; | |
3841 | for (idx = 0; idx < nr_ioapics; idx++) | |
3842 | nr += io_apic_get_redir_entries(idx) + 1; | |
3843 | ||
3844 | if (nr > nr_irqs_gsi) | |
3845 | nr_irqs_gsi = nr; | |
3846 | } | |
3847 | ||
3848 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3849 | } |
3850 | ||
4a046d17 YL |
3851 | #ifdef CONFIG_SPARSE_IRQ |
3852 | int __init arch_probe_nr_irqs(void) | |
3853 | { | |
3854 | int nr; | |
3855 | ||
f1ee5548 YL |
3856 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3857 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3858 | |
f1ee5548 YL |
3859 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3860 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3861 | /* | |
3862 | * for MSI and HT dyn irq | |
3863 | */ | |
3864 | nr += nr_irqs_gsi * 16; | |
3865 | #endif | |
3866 | if (nr < nr_irqs) | |
4a046d17 YL |
3867 | nr_irqs = nr; |
3868 | ||
3869 | return 0; | |
3870 | } | |
3871 | #endif | |
3872 | ||
1da177e4 | 3873 | /* -------------------------------------------------------------------------- |
54168ed7 | 3874 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3875 | -------------------------------------------------------------------------- */ |
3876 | ||
888ba6c6 | 3877 | #ifdef CONFIG_ACPI |
1da177e4 | 3878 | |
54168ed7 | 3879 | #ifdef CONFIG_X86_32 |
36062448 | 3880 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3881 | { |
3882 | union IO_APIC_reg_00 reg_00; | |
3883 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3884 | physid_mask_t tmp; | |
3885 | unsigned long flags; | |
3886 | int i = 0; | |
3887 | ||
3888 | /* | |
36062448 PC |
3889 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3890 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3891 | * supports up to 16 on one shared APIC bus. |
36062448 | 3892 | * |
1da177e4 LT |
3893 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3894 | * advantage of new APIC bus architecture. | |
3895 | */ | |
3896 | ||
3897 | if (physids_empty(apic_id_map)) | |
d190cb87 | 3898 | apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
3899 | |
3900 | spin_lock_irqsave(&ioapic_lock, flags); | |
3901 | reg_00.raw = io_apic_read(ioapic, 0); | |
3902 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3903 | ||
3904 | if (apic_id >= get_physical_broadcast()) { | |
3905 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3906 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3907 | apic_id = reg_00.bits.ID; | |
3908 | } | |
3909 | ||
3910 | /* | |
36062448 | 3911 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3912 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3913 | */ | |
d1d7cae8 | 3914 | if (apic->check_apicid_used(apic_id_map, apic_id)) { |
1da177e4 LT |
3915 | |
3916 | for (i = 0; i < get_physical_broadcast(); i++) { | |
d1d7cae8 | 3917 | if (!apic->check_apicid_used(apic_id_map, i)) |
1da177e4 LT |
3918 | break; |
3919 | } | |
3920 | ||
3921 | if (i == get_physical_broadcast()) | |
3922 | panic("Max apic_id exceeded!\n"); | |
3923 | ||
3924 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3925 | "trying %d\n", ioapic, apic_id, i); | |
3926 | ||
3927 | apic_id = i; | |
36062448 | 3928 | } |
1da177e4 | 3929 | |
8058714a | 3930 | tmp = apic->apicid_to_cpu_present(apic_id); |
1da177e4 LT |
3931 | physids_or(apic_id_map, apic_id_map, tmp); |
3932 | ||
3933 | if (reg_00.bits.ID != apic_id) { | |
3934 | reg_00.bits.ID = apic_id; | |
3935 | ||
3936 | spin_lock_irqsave(&ioapic_lock, flags); | |
3937 | io_apic_write(ioapic, 0, reg_00.raw); | |
3938 | reg_00.raw = io_apic_read(ioapic, 0); | |
3939 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3940 | ||
3941 | /* Sanity check */ | |
6070f9ec AD |
3942 | if (reg_00.bits.ID != apic_id) { |
3943 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3944 | return -1; | |
3945 | } | |
1da177e4 LT |
3946 | } |
3947 | ||
3948 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3949 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3950 | ||
3951 | return apic_id; | |
3952 | } | |
3953 | ||
36062448 | 3954 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3955 | { |
3956 | union IO_APIC_reg_01 reg_01; | |
3957 | unsigned long flags; | |
3958 | ||
3959 | spin_lock_irqsave(&ioapic_lock, flags); | |
3960 | reg_01.raw = io_apic_read(ioapic, 1); | |
3961 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3962 | ||
3963 | return reg_01.bits.version; | |
3964 | } | |
54168ed7 | 3965 | #endif |
1da177e4 | 3966 | |
54168ed7 | 3967 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 3968 | { |
0b8f1efa YL |
3969 | struct irq_desc *desc; |
3970 | struct irq_cfg *cfg; | |
3971 | int cpu = boot_cpu_id; | |
3972 | ||
1da177e4 | 3973 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3974 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
3975 | ioapic); |
3976 | return -EINVAL; | |
3977 | } | |
3978 | ||
0b8f1efa YL |
3979 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
3980 | if (!desc) { | |
3981 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3982 | return 0; | |
3983 | } | |
3984 | ||
1da177e4 LT |
3985 | /* |
3986 | * IRQs < 16 are already in the irq_2_pin[] map | |
3987 | */ | |
99d093d1 | 3988 | if (irq >= NR_IRQS_LEGACY) { |
0b8f1efa | 3989 | cfg = desc->chip_data; |
3145e941 | 3990 | add_pin_to_irq_cpu(cfg, cpu, ioapic, pin); |
0b8f1efa | 3991 | } |
1da177e4 | 3992 | |
3145e941 | 3993 | setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity); |
1da177e4 LT |
3994 | |
3995 | return 0; | |
3996 | } | |
3997 | ||
54168ed7 | 3998 | |
61fd47e0 SL |
3999 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
4000 | { | |
4001 | int i; | |
4002 | ||
4003 | if (skip_ioapic_setup) | |
4004 | return -1; | |
4005 | ||
4006 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
4007 | if (mp_irqs[i].irqtype == mp_INT && |
4008 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
4009 | break; |
4010 | if (i >= mp_irq_entries) | |
4011 | return -1; | |
4012 | ||
4013 | *trigger = irq_trigger(i); | |
4014 | *polarity = irq_polarity(i); | |
4015 | return 0; | |
4016 | } | |
4017 | ||
888ba6c6 | 4018 | #endif /* CONFIG_ACPI */ |
1a3f239d | 4019 | |
497c9a19 YL |
4020 | /* |
4021 | * This function currently is only a helper for the i386 smp boot process where | |
4022 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4023 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4024 | */ |
4025 | #ifdef CONFIG_SMP | |
4026 | void __init setup_ioapic_dest(void) | |
4027 | { | |
4028 | int pin, ioapic, irq, irq_entry; | |
6c2e9403 | 4029 | struct irq_desc *desc; |
497c9a19 | 4030 | struct irq_cfg *cfg; |
22f65d31 | 4031 | const struct cpumask *mask; |
497c9a19 YL |
4032 | |
4033 | if (skip_ioapic_setup == 1) | |
4034 | return; | |
4035 | ||
4036 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
4037 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
4038 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4039 | if (irq_entry == -1) | |
4040 | continue; | |
4041 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
4042 | ||
4043 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
4044 | * when you have too many devices, because at that time only boot | |
4045 | * cpu is online. | |
4046 | */ | |
0b8f1efa YL |
4047 | desc = irq_to_desc(irq); |
4048 | cfg = desc->chip_data; | |
6c2e9403 | 4049 | if (!cfg->vector) { |
3145e941 | 4050 | setup_IO_APIC_irq(ioapic, pin, irq, desc, |
497c9a19 YL |
4051 | irq_trigger(irq_entry), |
4052 | irq_polarity(irq_entry)); | |
6c2e9403 TG |
4053 | continue; |
4054 | ||
4055 | } | |
4056 | ||
4057 | /* | |
4058 | * Honour affinities which have been set in early boot | |
4059 | */ | |
6c2e9403 TG |
4060 | if (desc->status & |
4061 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
7f7ace0c | 4062 | mask = desc->affinity; |
6c2e9403 | 4063 | else |
fe402e1f | 4064 | mask = apic->target_cpus(); |
6c2e9403 | 4065 | |
6c2e9403 | 4066 | if (intr_remapping_enabled) |
3145e941 | 4067 | set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 4068 | else |
3145e941 | 4069 | set_ioapic_affinity_irq_desc(desc, mask); |
497c9a19 YL |
4070 | } |
4071 | ||
4072 | } | |
4073 | } | |
4074 | #endif | |
4075 | ||
54168ed7 IM |
4076 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4077 | ||
4078 | static struct resource *ioapic_resources; | |
4079 | ||
4080 | static struct resource * __init ioapic_setup_resources(void) | |
4081 | { | |
4082 | unsigned long n; | |
4083 | struct resource *res; | |
4084 | char *mem; | |
4085 | int i; | |
4086 | ||
4087 | if (nr_ioapics <= 0) | |
4088 | return NULL; | |
4089 | ||
4090 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4091 | n *= nr_ioapics; | |
4092 | ||
4093 | mem = alloc_bootmem(n); | |
4094 | res = (void *)mem; | |
4095 | ||
4096 | if (mem != NULL) { | |
4097 | mem += sizeof(struct resource) * nr_ioapics; | |
4098 | ||
4099 | for (i = 0; i < nr_ioapics; i++) { | |
4100 | res[i].name = mem; | |
4101 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4102 | sprintf(mem, "IOAPIC %u", i); | |
4103 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4104 | } | |
4105 | } | |
4106 | ||
4107 | ioapic_resources = res; | |
4108 | ||
4109 | return res; | |
4110 | } | |
54168ed7 | 4111 | |
f3294a33 YL |
4112 | void __init ioapic_init_mappings(void) |
4113 | { | |
4114 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4115 | struct resource *ioapic_res; |
d6c88a50 | 4116 | int i; |
f3294a33 | 4117 | |
54168ed7 | 4118 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4119 | for (i = 0; i < nr_ioapics; i++) { |
4120 | if (smp_found_config) { | |
b5ba7e6d | 4121 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4122 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4123 | if (!ioapic_phys) { |
4124 | printk(KERN_ERR | |
4125 | "WARNING: bogus zero IO-APIC " | |
4126 | "address found in MPTABLE, " | |
4127 | "disabling IO/APIC support!\n"); | |
4128 | smp_found_config = 0; | |
4129 | skip_ioapic_setup = 1; | |
4130 | goto fake_ioapic_page; | |
4131 | } | |
54168ed7 | 4132 | #endif |
f3294a33 | 4133 | } else { |
54168ed7 | 4134 | #ifdef CONFIG_X86_32 |
f3294a33 | 4135 | fake_ioapic_page: |
54168ed7 | 4136 | #endif |
f3294a33 | 4137 | ioapic_phys = (unsigned long) |
54168ed7 | 4138 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4139 | ioapic_phys = __pa(ioapic_phys); |
4140 | } | |
4141 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4142 | apic_printk(APIC_VERBOSE, |
4143 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4144 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4145 | idx++; |
54168ed7 | 4146 | |
54168ed7 IM |
4147 | if (ioapic_res != NULL) { |
4148 | ioapic_res->start = ioapic_phys; | |
4149 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4150 | ioapic_res++; | |
4151 | } | |
f3294a33 YL |
4152 | } |
4153 | } | |
4154 | ||
54168ed7 IM |
4155 | static int __init ioapic_insert_resources(void) |
4156 | { | |
4157 | int i; | |
4158 | struct resource *r = ioapic_resources; | |
4159 | ||
4160 | if (!r) { | |
04c93ce4 BZ |
4161 | if (nr_ioapics > 0) { |
4162 | printk(KERN_ERR | |
4163 | "IO APIC resources couldn't be allocated.\n"); | |
4164 | return -1; | |
4165 | } | |
4166 | return 0; | |
54168ed7 IM |
4167 | } |
4168 | ||
4169 | for (i = 0; i < nr_ioapics; i++) { | |
4170 | insert_resource(&iomem_resource, r); | |
4171 | r++; | |
4172 | } | |
4173 | ||
4174 | return 0; | |
4175 | } | |
4176 | ||
4177 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4178 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4179 | late_initcall(ioapic_insert_resources); |