Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Written by: Patricia Gaughen, IBM Corporation | |
3 | * | |
4 | * Copyright (C) 2002, IBM Corp. | |
cb81eaed | 5 | * Copyright (C) 2009, Red Hat, Inc., Ingo Molnar |
1da177e4 | 6 | * |
4f179d12 | 7 | * All rights reserved. |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
17 | * NON INFRINGEMENT. See the GNU General Public License for more | |
18 | * details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | * | |
24 | * Send feedback to <gone@us.ibm.com> | |
25 | */ | |
4f179d12 | 26 | #include <linux/nodemask.h> |
cb81eaed | 27 | #include <linux/topology.h> |
1da177e4 | 28 | #include <linux/bootmem.h> |
a9ce6bc1 | 29 | #include <linux/memblock.h> |
36afc3af IM |
30 | #include <linux/threads.h> |
31 | #include <linux/cpumask.h> | |
32 | #include <linux/kernel.h> | |
1da177e4 LT |
33 | #include <linux/mmzone.h> |
34 | #include <linux/module.h> | |
36afc3af IM |
35 | #include <linux/string.h> |
36 | #include <linux/init.h> | |
37 | #include <linux/numa.h> | |
38 | #include <linux/smp.h> | |
cb81eaed | 39 | #include <linux/io.h> |
4f179d12 IM |
40 | #include <linux/mm.h> |
41 | ||
e1474e2d | 42 | #include <asm/processor.h> |
36afc3af IM |
43 | #include <asm/fixmap.h> |
44 | #include <asm/mpspec.h> | |
4f179d12 | 45 | #include <asm/numaq.h> |
64898a8b | 46 | #include <asm/setup.h> |
36afc3af | 47 | #include <asm/apic.h> |
4f179d12 | 48 | #include <asm/e820.h> |
36afc3af | 49 | #include <asm/ipi.h> |
1da177e4 | 50 | |
cb81eaed IM |
51 | int found_numaq; |
52 | ||
53 | /* | |
54 | * Have to match translation table entries to main table entries by counter | |
55 | * hence the mpc_record variable .... can't see a less disgusting way of | |
56 | * doing this .... | |
57 | */ | |
58 | struct mpc_trans { | |
59 | unsigned char mpc_type; | |
60 | unsigned char trans_len; | |
61 | unsigned char trans_type; | |
62 | unsigned char trans_quad; | |
63 | unsigned char trans_global; | |
64 | unsigned char trans_local; | |
65 | unsigned short trans_reserved; | |
66 | }; | |
67 | ||
cb81eaed IM |
68 | static int mpc_record; |
69 | ||
b6122b38 | 70 | static struct mpc_trans *translation_table[MAX_MPC_ENTRY]; |
cb81eaed IM |
71 | |
72 | int mp_bus_id_to_node[MAX_MP_BUSSES]; | |
73 | int mp_bus_id_to_local[MAX_MP_BUSSES]; | |
74 | int quad_local_to_mp_bus_id[NR_CPUS/4][4]; | |
75 | ||
76 | ||
36afc3af IM |
77 | static inline void numaq_register_node(int node, struct sys_cfg_data *scd) |
78 | { | |
79 | struct eachquadmem *eq = scd->eq + node; | |
299a180a TH |
80 | u64 start = (u64)(eq->hi_shrd_mem_start - eq->priv_mem_size) << 20; |
81 | u64 end = (u64)(eq->hi_shrd_mem_start + eq->hi_shrd_mem_size) << 20; | |
82 | int ret; | |
36afc3af | 83 | |
299a180a TH |
84 | node_set(node, numa_nodes_parsed); |
85 | ret = numa_add_memblk(node, start, end); | |
86 | BUG_ON(ret < 0); | |
36afc3af | 87 | } |
1da177e4 LT |
88 | |
89 | /* | |
90 | * Function: smp_dump_qct() | |
91 | * | |
92 | * Description: gets memory layout from the quad config table. This | |
299a180a | 93 | * function also updates numa_nodes_parsed with the nodes (quads) present. |
1da177e4 LT |
94 | */ |
95 | static void __init smp_dump_qct(void) | |
96 | { | |
36afc3af | 97 | struct sys_cfg_data *scd; |
1da177e4 | 98 | int node; |
36afc3af IM |
99 | |
100 | scd = (void *)__va(SYS_CFG_DATA_PRIV_ADDR); | |
1da177e4 | 101 | |
1da177e4 | 102 | for_each_node(node) { |
36afc3af IM |
103 | if (scd->quads_present31_0 & (1 << node)) |
104 | numaq_register_node(node, scd); | |
1da177e4 LT |
105 | } |
106 | } | |
107 | ||
148f9bb8 | 108 | void numaq_tsc_disable(void) |
64898a8b YL |
109 | { |
110 | if (!found_numaq) | |
111 | return; | |
112 | ||
113 | if (num_online_nodes() > 1) { | |
114 | printk(KERN_DEBUG "NUMAQ: disabling TSC\n"); | |
115 | setup_clear_cpu_cap(X86_FEATURE_TSC); | |
116 | } | |
117 | } | |
118 | ||
845b3944 | 119 | static void __init numaq_tsc_init(void) |
63b5d7af YL |
120 | { |
121 | numaq_tsc_disable(); | |
63b5d7af YL |
122 | } |
123 | ||
64898a8b YL |
124 | static inline int generate_logical_apicid(int quad, int phys_apicid) |
125 | { | |
126 | return (quad << 4) + (phys_apicid ? phys_apicid << 1 : 1); | |
127 | } | |
128 | ||
129 | /* x86_quirks member */ | |
f4f21b71 | 130 | static int mpc_apic_id(struct mpc_cpu *m) |
64898a8b YL |
131 | { |
132 | int quad = translation_table[mpc_record]->trans_quad; | |
c4563826 | 133 | int logical_apicid = generate_logical_apicid(quad, m->apicid); |
64898a8b | 134 | |
36afc3af IM |
135 | printk(KERN_DEBUG |
136 | "Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n", | |
137 | m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8, | |
138 | (m->cpufeature & CPU_MODEL_MASK) >> 4, | |
139 | m->apicver, quad, logical_apicid); | |
140 | ||
64898a8b YL |
141 | return logical_apicid; |
142 | } | |
143 | ||
64898a8b | 144 | /* x86_quirks member */ |
00fb8606 | 145 | static void mpc_oem_bus_info(struct mpc_bus *m, char *name) |
64898a8b YL |
146 | { |
147 | int quad = translation_table[mpc_record]->trans_quad; | |
148 | int local = translation_table[mpc_record]->trans_local; | |
149 | ||
d4c715fa JSR |
150 | mp_bus_id_to_node[m->busid] = quad; |
151 | mp_bus_id_to_local[m->busid] = local; | |
36afc3af IM |
152 | |
153 | printk(KERN_INFO "Bus #%d is %s (node %d)\n", m->busid, name, quad); | |
64898a8b YL |
154 | } |
155 | ||
64898a8b | 156 | /* x86_quirks member */ |
00fb8606 | 157 | static void mpc_oem_pci_bus(struct mpc_bus *m) |
64898a8b YL |
158 | { |
159 | int quad = translation_table[mpc_record]->trans_quad; | |
160 | int local = translation_table[mpc_record]->trans_local; | |
161 | ||
d4c715fa | 162 | quad_local_to_mp_bus_id[quad][local] = m->busid; |
64898a8b YL |
163 | } |
164 | ||
f4848472 TG |
165 | /* |
166 | * Called from mpparse code. | |
167 | * mode = 0: prescan | |
168 | * mode = 1: one mpc entry scanned | |
169 | */ | |
170 | static void numaq_mpc_record(unsigned int mode) | |
171 | { | |
172 | if (!mode) | |
173 | mpc_record = 0; | |
174 | else | |
175 | mpc_record++; | |
176 | } | |
177 | ||
36afc3af | 178 | static void __init MP_translation_info(struct mpc_trans *m) |
64898a8b YL |
179 | { |
180 | printk(KERN_INFO | |
cb81eaed | 181 | "Translation: record %d, type %d, quad %d, global %d, local %d\n", |
64898a8b YL |
182 | mpc_record, m->trans_type, m->trans_quad, m->trans_global, |
183 | m->trans_local); | |
184 | ||
185 | if (mpc_record >= MAX_MPC_ENTRY) | |
186 | printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n"); | |
187 | else | |
36afc3af IM |
188 | translation_table[mpc_record] = m; /* stash this for later */ |
189 | ||
64898a8b YL |
190 | if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad)) |
191 | node_set_online(m->trans_quad); | |
192 | } | |
193 | ||
194 | static int __init mpf_checksum(unsigned char *mp, int len) | |
195 | { | |
196 | int sum = 0; | |
197 | ||
198 | while (len--) | |
199 | sum += *mp++; | |
200 | ||
201 | return sum & 0xFF; | |
202 | } | |
203 | ||
204 | /* | |
205 | * Read/parse the MPC oem tables | |
206 | */ | |
72302142 | 207 | static void __init smp_read_mpc_oem(struct mpc_table *mpc) |
64898a8b | 208 | { |
72302142 | 209 | struct mpc_oemtable *oemtable = (void *)(long)mpc->oemptr; |
64898a8b YL |
210 | int count = sizeof(*oemtable); /* the header size */ |
211 | unsigned char *oemptr = ((unsigned char *)oemtable) + count; | |
212 | ||
213 | mpc_record = 0; | |
36afc3af | 214 | printk(KERN_INFO |
3235dc3f | 215 | "Found an OEM MPC table at %8p - parsing it...\n", oemtable); |
36afc3af | 216 | |
a1d0272a | 217 | if (memcmp(oemtable->signature, MPC_OEM_SIGNATURE, 4)) { |
64898a8b YL |
218 | printk(KERN_WARNING |
219 | "SMP mpc oemtable: bad signature [%c%c%c%c]!\n", | |
a1d0272a JSR |
220 | oemtable->signature[0], oemtable->signature[1], |
221 | oemtable->signature[2], oemtable->signature[3]); | |
64898a8b YL |
222 | return; |
223 | } | |
36afc3af | 224 | |
a1d0272a | 225 | if (mpf_checksum((unsigned char *)oemtable, oemtable->length)) { |
64898a8b YL |
226 | printk(KERN_WARNING "SMP oem mptable: checksum error!\n"); |
227 | return; | |
228 | } | |
36afc3af | 229 | |
a1d0272a | 230 | while (count < oemtable->length) { |
64898a8b YL |
231 | switch (*oemptr) { |
232 | case MP_TRANSLATION: | |
233 | { | |
36afc3af IM |
234 | struct mpc_trans *m = (void *)oemptr; |
235 | ||
64898a8b YL |
236 | MP_translation_info(m); |
237 | oemptr += sizeof(*m); | |
238 | count += sizeof(*m); | |
239 | ++mpc_record; | |
240 | break; | |
241 | } | |
242 | default: | |
36afc3af IM |
243 | printk(KERN_WARNING |
244 | "Unrecognised OEM table entry type! - %d\n", | |
245 | (int)*oemptr); | |
246 | return; | |
64898a8b YL |
247 | } |
248 | } | |
249 | } | |
250 | ||
ab530e1f YL |
251 | static __init void early_check_numaq(void) |
252 | { | |
ab530e1f YL |
253 | /* |
254 | * get boot-time SMP configuration: | |
255 | */ | |
256 | if (smp_found_config) | |
257 | early_get_smp_config(); | |
64898a8b | 258 | |
f4848472 | 259 | if (found_numaq) { |
f4848472 | 260 | x86_init.mpparse.mpc_record = numaq_mpc_record; |
de934103 | 261 | x86_init.mpparse.setup_ioapic_ids = x86_init_noop; |
fd6c6661 | 262 | x86_init.mpparse.mpc_apic_id = mpc_apic_id; |
72302142 | 263 | x86_init.mpparse.smp_read_mpc_oem = smp_read_mpc_oem; |
52fdb568 | 264 | x86_init.mpparse.mpc_oem_pci_bus = mpc_oem_pci_bus; |
90e1c696 | 265 | x86_init.mpparse.mpc_oem_bus_info = mpc_oem_bus_info; |
845b3944 | 266 | x86_init.timers.tsc_pre_init = numaq_tsc_init; |
b72d0db9 | 267 | x86_init.pci.init = pci_numaq_init; |
f4848472 | 268 | } |
ab530e1f YL |
269 | } |
270 | ||
299a180a | 271 | int __init numaq_numa_init(void) |
1da177e4 | 272 | { |
ab530e1f YL |
273 | early_check_numaq(); |
274 | if (!found_numaq) | |
299a180a | 275 | return -ENOENT; |
1da177e4 | 276 | smp_dump_qct(); |
36afc3af | 277 | |
299a180a | 278 | return 0; |
1da177e4 | 279 | } |
61b90b7c | 280 | |
61b90b7c IM |
281 | #define NUMAQ_APIC_DFR_VALUE (APIC_DFR_CLUSTER) |
282 | ||
283 | static inline unsigned int numaq_get_apic_id(unsigned long x) | |
284 | { | |
285 | return (x >> 24) & 0x0F; | |
286 | } | |
287 | ||
61b90b7c IM |
288 | static inline void numaq_send_IPI_mask(const struct cpumask *mask, int vector) |
289 | { | |
43f39890 | 290 | default_send_IPI_mask_sequence_logical(mask, vector); |
61b90b7c IM |
291 | } |
292 | ||
293 | static inline void numaq_send_IPI_allbutself(int vector) | |
294 | { | |
43f39890 | 295 | default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector); |
61b90b7c IM |
296 | } |
297 | ||
298 | static inline void numaq_send_IPI_all(int vector) | |
299 | { | |
300 | numaq_send_IPI_mask(cpu_online_mask, vector); | |
301 | } | |
302 | ||
36afc3af IM |
303 | #define NUMAQ_TRAMPOLINE_PHYS_LOW (0x8) |
304 | #define NUMAQ_TRAMPOLINE_PHYS_HIGH (0xa) | |
61b90b7c IM |
305 | |
306 | /* | |
307 | * Because we use NMIs rather than the INIT-STARTUP sequence to | |
308 | * bootstrap the CPUs, the APIC may be in a weird state. Kick it: | |
309 | */ | |
310 | static inline void numaq_smp_callin_clear_local_apic(void) | |
311 | { | |
312 | clear_local_APIC(); | |
313 | } | |
314 | ||
73e907de | 315 | static inline const struct cpumask *numaq_target_cpus(void) |
61b90b7c | 316 | { |
101aaca1 | 317 | return cpu_all_mask; |
61b90b7c IM |
318 | } |
319 | ||
7abc0753 | 320 | static unsigned long numaq_check_apicid_used(physid_mask_t *map, int apicid) |
61b90b7c | 321 | { |
7abc0753 | 322 | return physid_isset(apicid, *map); |
61b90b7c IM |
323 | } |
324 | ||
325 | static inline unsigned long numaq_check_apicid_present(int bit) | |
326 | { | |
327 | return physid_isset(bit, phys_cpu_present_map); | |
328 | } | |
329 | ||
61b90b7c IM |
330 | static inline int numaq_apic_id_registered(void) |
331 | { | |
332 | return 1; | |
333 | } | |
334 | ||
335 | static inline void numaq_init_apic_ldr(void) | |
336 | { | |
337 | /* Already done in NUMA-Q firmware */ | |
338 | } | |
339 | ||
340 | static inline void numaq_setup_apic_routing(void) | |
341 | { | |
cb81eaed IM |
342 | printk(KERN_INFO |
343 | "Enabling APIC mode: NUMA-Q. Using %d I/O APICs\n", | |
344 | nr_ioapics); | |
61b90b7c IM |
345 | } |
346 | ||
347 | /* | |
348 | * Skip adding the timer int on secondary nodes, which causes | |
349 | * a small but painful rift in the time-space continuum. | |
350 | */ | |
351 | static inline int numaq_multi_timer_check(int apic, int irq) | |
352 | { | |
353 | return apic != 0 && irq == 0; | |
354 | } | |
355 | ||
7abc0753 | 356 | static inline void numaq_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) |
61b90b7c IM |
357 | { |
358 | /* We don't have a good way to do this yet - hack */ | |
7abc0753 | 359 | return physids_promote(0xFUL, retmap); |
61b90b7c IM |
360 | } |
361 | ||
61b90b7c IM |
362 | /* |
363 | * Supporting over 60 cpus on NUMA-Q requires a locality-dependent | |
364 | * cpu to APIC ID relation to properly interact with the intelligent | |
365 | * mode of the cluster controller. | |
366 | */ | |
367 | static inline int numaq_cpu_present_to_apicid(int mps_cpu) | |
368 | { | |
369 | if (mps_cpu < 60) | |
370 | return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3)); | |
371 | else | |
372 | return BAD_APICID; | |
373 | } | |
374 | ||
36afc3af | 375 | static inline int numaq_apicid_to_node(int logical_apicid) |
61b90b7c IM |
376 | { |
377 | return logical_apicid >> 4; | |
378 | } | |
379 | ||
89e5dc21 TH |
380 | static int numaq_numa_cpu_node(int cpu) |
381 | { | |
382 | int logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); | |
383 | ||
384 | if (logical_apicid != BAD_APICID) | |
385 | return numaq_apicid_to_node(logical_apicid); | |
386 | return NUMA_NO_NODE; | |
387 | } | |
388 | ||
7abc0753 | 389 | static void numaq_apicid_to_cpu_present(int logical_apicid, physid_mask_t *retmap) |
61b90b7c IM |
390 | { |
391 | int node = numaq_apicid_to_node(logical_apicid); | |
392 | int cpu = __ffs(logical_apicid & 0xf); | |
393 | ||
7abc0753 | 394 | physid_set_mask_of_physid(cpu + 4*node, retmap); |
61b90b7c IM |
395 | } |
396 | ||
4f179d12 IM |
397 | /* Where the IO area was mapped on multiquad, always 0 otherwise */ |
398 | void *xquad_portio; | |
61b90b7c | 399 | |
e11dadab | 400 | static inline int numaq_check_phys_apicid_present(int phys_apicid) |
61b90b7c IM |
401 | { |
402 | return 1; | |
403 | } | |
404 | ||
405 | /* | |
406 | * We use physical apicids here, not logical, so just return the default | |
407 | * physical broadcast to stop people from breaking us | |
408 | */ | |
ff164324 | 409 | static int |
61b90b7c | 410 | numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
411 | const struct cpumask *andmask, |
412 | unsigned int *apicid) | |
61b90b7c | 413 | { |
ff164324 AG |
414 | *apicid = 0x0F; |
415 | return 0; | |
61b90b7c IM |
416 | } |
417 | ||
418 | /* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */ | |
419 | static inline int numaq_phys_pkg_id(int cpuid_apic, int index_msb) | |
420 | { | |
421 | return cpuid_apic >> index_msb; | |
422 | } | |
36afc3af IM |
423 | |
424 | static int | |
cb81eaed | 425 | numaq_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid) |
61b90b7c | 426 | { |
cb81eaed IM |
427 | if (strncmp(oem, "IBM NUMA", 8)) |
428 | printk(KERN_ERR "Warning! Not a NUMA-Q system!\n"); | |
429 | else | |
430 | found_numaq = 1; | |
431 | ||
61b90b7c IM |
432 | return found_numaq; |
433 | } | |
434 | ||
435 | static int probe_numaq(void) | |
436 | { | |
437 | /* already know from get_memcfg_numaq() */ | |
438 | return found_numaq; | |
439 | } | |
440 | ||
61b90b7c IM |
441 | static void numaq_setup_portio_remap(void) |
442 | { | |
443 | int num_quads = num_online_nodes(); | |
444 | ||
445 | if (num_quads <= 1) | |
4f179d12 | 446 | return; |
61b90b7c | 447 | |
cb81eaed IM |
448 | printk(KERN_INFO |
449 | "Remapping cross-quad port I/O for %d quads\n", num_quads); | |
450 | ||
61b90b7c | 451 | xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD); |
cb81eaed IM |
452 | |
453 | printk(KERN_INFO | |
454 | "xquad_portio vaddr 0x%08lx, len %08lx\n", | |
61b90b7c IM |
455 | (u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD); |
456 | } | |
457 | ||
1a8880a1 SS |
458 | /* Use __refdata to keep false positive warning calm. */ |
459 | static struct apic __refdata apic_numaq = { | |
61b90b7c IM |
460 | |
461 | .name = "NUMAQ", | |
462 | .probe = probe_numaq, | |
463 | .acpi_madt_oem_check = NULL, | |
fa63030e | 464 | .apic_id_valid = default_apic_id_valid, |
61b90b7c IM |
465 | .apic_id_registered = numaq_apic_id_registered, |
466 | ||
467 | .irq_delivery_mode = dest_LowestPrio, | |
468 | /* physical delivery on LOCAL quad: */ | |
469 | .irq_dest_mode = 0, | |
470 | ||
471 | .target_cpus = numaq_target_cpus, | |
472 | .disable_esr = 1, | |
473 | .dest_logical = APIC_DEST_LOGICAL, | |
474 | .check_apicid_used = numaq_check_apicid_used, | |
475 | .check_apicid_present = numaq_check_apicid_present, | |
476 | ||
9d8e1066 | 477 | .vector_allocation_domain = flat_vector_allocation_domain, |
61b90b7c IM |
478 | .init_apic_ldr = numaq_init_apic_ldr, |
479 | ||
480 | .ioapic_phys_id_map = numaq_ioapic_phys_id_map, | |
481 | .setup_apic_routing = numaq_setup_apic_routing, | |
482 | .multi_timer_check = numaq_multi_timer_check, | |
61b90b7c IM |
483 | .cpu_present_to_apicid = numaq_cpu_present_to_apicid, |
484 | .apicid_to_cpu_present = numaq_apicid_to_cpu_present, | |
485 | .setup_portio_remap = numaq_setup_portio_remap, | |
486 | .check_phys_apicid_present = numaq_check_phys_apicid_present, | |
487 | .enable_apic_mode = NULL, | |
488 | .phys_pkg_id = numaq_phys_pkg_id, | |
cb81eaed | 489 | .mps_oem_check = numaq_mps_oem_check, |
61b90b7c IM |
490 | |
491 | .get_apic_id = numaq_get_apic_id, | |
492 | .set_apic_id = NULL, | |
493 | .apic_id_mask = 0x0F << 24, | |
494 | ||
61b90b7c IM |
495 | .cpu_mask_to_apicid_and = numaq_cpu_mask_to_apicid_and, |
496 | ||
497 | .send_IPI_mask = numaq_send_IPI_mask, | |
498 | .send_IPI_mask_allbutself = NULL, | |
499 | .send_IPI_allbutself = numaq_send_IPI_allbutself, | |
500 | .send_IPI_all = numaq_send_IPI_all, | |
6b64ee02 | 501 | .send_IPI_self = default_send_IPI_self, |
61b90b7c | 502 | |
1f5bcabf | 503 | .wakeup_secondary_cpu = wakeup_secondary_cpu_via_nmi, |
61b90b7c IM |
504 | .trampoline_phys_low = NUMAQ_TRAMPOLINE_PHYS_LOW, |
505 | .trampoline_phys_high = NUMAQ_TRAMPOLINE_PHYS_HIGH, | |
506 | ||
507 | /* We don't do anything here because we use NMI's to boot instead */ | |
508 | .wait_for_init_deassert = NULL, | |
509 | ||
510 | .smp_callin_clear_local_apic = numaq_smp_callin_clear_local_apic, | |
61b90b7c | 511 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
512 | |
513 | .read = native_apic_mem_read, | |
514 | .write = native_apic_mem_write, | |
2a43195d | 515 | .eoi_write = native_apic_mem_write, |
c1eeb2de YL |
516 | .icr_read = native_apic_icr_read, |
517 | .icr_write = native_apic_icr_write, | |
518 | .wait_icr_idle = native_apic_wait_icr_idle, | |
519 | .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, | |
acb8bc09 TH |
520 | |
521 | .x86_32_early_logical_apicid = noop_x86_32_early_logical_apicid, | |
89e5dc21 | 522 | .x86_32_numa_cpu_node = numaq_numa_cpu_node, |
61b90b7c | 523 | }; |
107e0e0c SS |
524 | |
525 | apic_driver(apic_numaq); |