Commit | Line | Data |
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1da177e4 | 1 | /* |
835c34a1 | 2 | * IBM Summit-Specific Code |
1da177e4 LT |
3 | * |
4 | * Written By: Matthew Dobson, IBM Corporation | |
5 | * | |
6 | * Copyright (c) 2003 IBM Corp. | |
7 | * | |
8 | * All rights reserved. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or (at | |
13 | * your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
18 | * NON INFRINGEMENT. See the GNU General Public License for more | |
19 | * details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * Send feedback to <colpatch@us.ibm.com> | |
26 | * | |
27 | */ | |
28 | ||
c767a54b JP |
29 | #define pr_fmt(fmt) "summit: %s: " fmt, __func__ |
30 | ||
1da177e4 | 31 | #include <linux/mm.h> |
1da177e4 | 32 | #include <asm/io.h> |
356fa0c6 | 33 | #include <asm/bios_ebda.h> |
b11b867f IM |
34 | |
35 | /* | |
36 | * APIC driver for the IBM "Summit" chipset. | |
37 | */ | |
b11b867f IM |
38 | #include <linux/threads.h> |
39 | #include <linux/cpumask.h> | |
40 | #include <asm/mpspec.h> | |
41 | #include <asm/apic.h> | |
42 | #include <asm/smp.h> | |
b11b867f IM |
43 | #include <asm/fixmap.h> |
44 | #include <asm/apicdef.h> | |
43f39890 | 45 | #include <asm/ipi.h> |
b11b867f IM |
46 | #include <linux/kernel.h> |
47 | #include <linux/string.h> | |
b11b867f IM |
48 | #include <linux/gfp.h> |
49 | #include <linux/smp.h> | |
50 | ||
b5f26d05 | 51 | static unsigned summit_get_apic_id(unsigned long x) |
b11b867f IM |
52 | { |
53 | return (x >> 24) & 0xFF; | |
54 | } | |
55 | ||
70ba2b6a | 56 | static inline void summit_send_IPI_mask(const struct cpumask *mask, int vector) |
b11b867f | 57 | { |
43f39890 | 58 | default_send_IPI_mask_sequence_logical(mask, vector); |
b11b867f IM |
59 | } |
60 | ||
b5f26d05 | 61 | static void summit_send_IPI_allbutself(int vector) |
b11b867f | 62 | { |
70ba2b6a | 63 | default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector); |
b11b867f IM |
64 | } |
65 | ||
b5f26d05 | 66 | static void summit_send_IPI_all(int vector) |
b11b867f | 67 | { |
70ba2b6a | 68 | summit_send_IPI_mask(cpu_online_mask, vector); |
b11b867f IM |
69 | } |
70 | ||
71 | #include <asm/tsc.h> | |
72 | ||
73 | extern int use_cyclone; | |
74 | ||
75 | #ifdef CONFIG_X86_SUMMIT_NUMA | |
2fcb1f1f | 76 | static void setup_summit(void); |
b11b867f | 77 | #else |
2fcb1f1f | 78 | static inline void setup_summit(void) {} |
b11b867f IM |
79 | #endif |
80 | ||
b5f26d05 JS |
81 | static int summit_mps_oem_check(struct mpc_table *mpc, char *oem, |
82 | char *productid) | |
b11b867f IM |
83 | { |
84 | if (!strncmp(oem, "IBM ENSW", 8) && | |
85 | (!strncmp(productid, "VIGIL SMP", 9) | |
86 | || !strncmp(productid, "EXA", 3) | |
87 | || !strncmp(productid, "RUTHLESS SMP", 12))){ | |
88 | mark_tsc_unstable("Summit based system"); | |
89 | use_cyclone = 1; /*enable cyclone-timer*/ | |
90 | setup_summit(); | |
91 | return 1; | |
92 | } | |
93 | return 0; | |
94 | } | |
95 | ||
96 | /* Hook from generic ACPI tables.c */ | |
b5f26d05 | 97 | static int summit_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
b11b867f IM |
98 | { |
99 | if (!strncmp(oem_id, "IBM", 3) && | |
100 | (!strncmp(oem_table_id, "SERVIGIL", 8) | |
101 | || !strncmp(oem_table_id, "EXA", 3))){ | |
102 | mark_tsc_unstable("Summit based system"); | |
103 | use_cyclone = 1; /*enable cyclone-timer*/ | |
104 | setup_summit(); | |
105 | return 1; | |
106 | } | |
107 | return 0; | |
108 | } | |
109 | ||
110 | struct rio_table_hdr { | |
111 | unsigned char version; /* Version number of this data structure */ | |
112 | /* Version 3 adds chassis_num & WP_index */ | |
113 | unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil) */ | |
114 | unsigned char num_rio_dev; /* # of RIO I/O devices (Cyclones and Winnipegs) */ | |
115 | } __attribute__((packed)); | |
116 | ||
117 | struct scal_detail { | |
118 | unsigned char node_id; /* Scalability Node ID */ | |
119 | unsigned long CBAR; /* Address of 1MB register space */ | |
120 | unsigned char port0node; /* Node ID port connected to: 0xFF=None */ | |
121 | unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
122 | unsigned char port1node; /* Node ID port connected to: 0xFF = None */ | |
123 | unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
124 | unsigned char port2node; /* Node ID port connected to: 0xFF = None */ | |
125 | unsigned char port2port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
126 | unsigned char chassis_num; /* 1 based Chassis number (1 = boot node) */ | |
127 | } __attribute__((packed)); | |
128 | ||
129 | struct rio_detail { | |
130 | unsigned char node_id; /* RIO Node ID */ | |
131 | unsigned long BBAR; /* Address of 1MB register space */ | |
132 | unsigned char type; /* Type of device */ | |
133 | unsigned char owner_id; /* For WPEG: Node ID of Cyclone that owns this WPEG*/ | |
134 | /* For CYC: Node ID of Twister that owns this CYC */ | |
135 | unsigned char port0node; /* Node ID port connected to: 0xFF=None */ | |
136 | unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
137 | unsigned char port1node; /* Node ID port connected to: 0xFF=None */ | |
138 | unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
139 | unsigned char first_slot; /* For WPEG: Lowest slot number below this WPEG */ | |
140 | /* For CYC: 0 */ | |
141 | unsigned char status; /* For WPEG: Bit 0 = 1 : the XAPIC is used */ | |
142 | /* = 0 : the XAPIC is not used, ie:*/ | |
143 | /* ints fwded to another XAPIC */ | |
144 | /* Bits1:7 Reserved */ | |
145 | /* For CYC: Bits0:7 Reserved */ | |
146 | unsigned char WP_index; /* For WPEG: WPEG instance index - lower ones have */ | |
147 | /* lower slot numbers/PCI bus numbers */ | |
148 | /* For CYC: No meaning */ | |
149 | unsigned char chassis_num; /* 1 based Chassis number */ | |
150 | /* For LookOut WPEGs this field indicates the */ | |
151 | /* Expansion Chassis #, enumerated from Boot */ | |
152 | /* Node WPEG external port, then Boot Node CYC */ | |
153 | /* external port, then Next Vigil chassis WPEG */ | |
154 | /* external port, etc. */ | |
155 | /* Shared Lookouts have only 1 chassis number (the */ | |
156 | /* first one assigned) */ | |
157 | } __attribute__((packed)); | |
158 | ||
159 | ||
160 | typedef enum { | |
161 | CompatTwister = 0, /* Compatibility Twister */ | |
162 | AltTwister = 1, /* Alternate Twister of internal 8-way */ | |
163 | CompatCyclone = 2, /* Compatibility Cyclone */ | |
164 | AltCyclone = 3, /* Alternate Cyclone of internal 8-way */ | |
165 | CompatWPEG = 4, /* Compatibility WPEG */ | |
166 | AltWPEG = 5, /* Second Planar WPEG */ | |
167 | LookOutAWPEG = 6, /* LookOut WPEG */ | |
168 | LookOutBWPEG = 7, /* LookOut WPEG */ | |
169 | } node_type; | |
170 | ||
171 | static inline int is_WPEG(struct rio_detail *rio){ | |
172 | return (rio->type == CompatWPEG || rio->type == AltWPEG || | |
173 | rio->type == LookOutAWPEG || rio->type == LookOutBWPEG); | |
174 | } | |
175 | ||
b11b867f IM |
176 | #define SUMMIT_APIC_DFR_VALUE (APIC_DFR_CLUSTER) |
177 | ||
73e907de | 178 | static const struct cpumask *summit_target_cpus(void) |
b11b867f IM |
179 | { |
180 | /* CPU_MASK_ALL (0xff) has undefined behaviour with | |
181 | * dest_LowestPrio mode logical clustered apic interrupt routing | |
182 | * Just start on cpu 0. IRQ balancing will spread load | |
183 | */ | |
4f062896 | 184 | return cpumask_of(0); |
b11b867f IM |
185 | } |
186 | ||
7abc0753 | 187 | static unsigned long summit_check_apicid_used(physid_mask_t *map, int apicid) |
b11b867f IM |
188 | { |
189 | return 0; | |
190 | } | |
191 | ||
192 | /* we don't use the phys_cpu_present_map to indicate apicid presence */ | |
b5f26d05 | 193 | static unsigned long summit_check_apicid_present(int bit) |
b11b867f IM |
194 | { |
195 | return 1; | |
196 | } | |
197 | ||
3b39d937 | 198 | static int summit_early_logical_apicid(int cpu) |
b11b867f | 199 | { |
b11b867f | 200 | int count = 0; |
3b39d937 | 201 | u8 my_id = early_per_cpu(x86_cpu_to_apicid, cpu); |
b9e0d1aa | 202 | u8 my_cluster = APIC_CLUSTER(my_id); |
b11b867f IM |
203 | #ifdef CONFIG_SMP |
204 | u8 lid; | |
205 | int i; | |
206 | ||
207 | /* Create logical APIC IDs by counting CPUs already in cluster. */ | |
208 | for (count = 0, i = nr_cpu_ids; --i >= 0; ) { | |
4c321ff8 | 209 | lid = early_per_cpu(x86_cpu_to_logical_apicid, i); |
b9e0d1aa | 210 | if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster) |
b11b867f IM |
211 | ++count; |
212 | } | |
213 | #endif | |
214 | /* We only have a 4 wide bitmap in cluster mode. If a deranged | |
215 | * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */ | |
216 | BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT); | |
3b39d937 TH |
217 | return my_cluster | (1UL << count); |
218 | } | |
219 | ||
220 | static void summit_init_apic_ldr(void) | |
221 | { | |
222 | int cpu = smp_processor_id(); | |
223 | unsigned long id = early_per_cpu(x86_cpu_to_logical_apicid, cpu); | |
224 | unsigned long val; | |
225 | ||
b11b867f IM |
226 | apic_write(APIC_DFR, SUMMIT_APIC_DFR_VALUE); |
227 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
228 | val |= SET_APIC_LOGICAL_ID(id); | |
229 | apic_write(APIC_LDR, val); | |
230 | } | |
231 | ||
b5f26d05 | 232 | static int summit_apic_id_registered(void) |
b11b867f IM |
233 | { |
234 | return 1; | |
235 | } | |
236 | ||
b5f26d05 | 237 | static void summit_setup_apic_routing(void) |
b11b867f | 238 | { |
c767a54b JP |
239 | pr_info("Enabling APIC mode: Summit. Using %d I/O APICs\n", |
240 | nr_ioapics); | |
b11b867f IM |
241 | } |
242 | ||
b5f26d05 | 243 | static int summit_cpu_present_to_apicid(int mps_cpu) |
b11b867f IM |
244 | { |
245 | if (mps_cpu < nr_cpu_ids) | |
246 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); | |
247 | else | |
248 | return BAD_APICID; | |
249 | } | |
250 | ||
7abc0753 | 251 | static void summit_ioapic_phys_id_map(physid_mask_t *phys_id_map, physid_mask_t *retmap) |
b11b867f IM |
252 | { |
253 | /* For clustered we don't have a good way to do this yet - hack */ | |
7abc0753 | 254 | physids_promote(0x0FL, retmap); |
b11b867f IM |
255 | } |
256 | ||
7abc0753 | 257 | static void summit_apicid_to_cpu_present(int apicid, physid_mask_t *retmap) |
b11b867f | 258 | { |
7abc0753 | 259 | physid_set_mask_of_physid(0, retmap); |
b11b867f IM |
260 | } |
261 | ||
e11dadab | 262 | static int summit_check_phys_apicid_present(int physical_apicid) |
b11b867f IM |
263 | { |
264 | return 1; | |
265 | } | |
266 | ||
a5a39156 | 267 | static inline int |
ff164324 | 268 | summit_cpu_mask_to_apicid(const struct cpumask *cpumask, unsigned int *dest_id) |
b11b867f | 269 | { |
fae176d6 | 270 | unsigned int round = 0; |
ea3807ea | 271 | unsigned int cpu, apicid = 0; |
b11b867f | 272 | |
b11b867f | 273 | /* |
10b614ea | 274 | * The cpus in the mask must all be on the apic cluster. |
b11b867f | 275 | */ |
4988a40c | 276 | for_each_cpu_and(cpu, cpumask, cpu_online_mask) { |
7632611f | 277 | int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
b11b867f | 278 | |
fae176d6 | 279 | if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) { |
c767a54b | 280 | pr_err("Not a valid mask!\n"); |
ff164324 | 281 | return -EINVAL; |
b11b867f | 282 | } |
fae176d6 JS |
283 | apicid |= new_apicid; |
284 | round++; | |
b11b867f | 285 | } |
214e270b AG |
286 | if (!round) |
287 | return -EINVAL; | |
ff164324 AG |
288 | *dest_id = apicid; |
289 | return 0; | |
b11b867f IM |
290 | } |
291 | ||
ff164324 AG |
292 | static int |
293 | summit_cpu_mask_to_apicid_and(const struct cpumask *inmask, | |
294 | const struct cpumask *andmask, | |
295 | unsigned int *apicid) | |
b11b867f | 296 | { |
b11b867f | 297 | cpumask_var_t cpumask; |
49ad3fd4 | 298 | *apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0); |
b11b867f IM |
299 | |
300 | if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC)) | |
ff164324 | 301 | return 0; |
b11b867f IM |
302 | |
303 | cpumask_and(cpumask, inmask, andmask); | |
ff164324 | 304 | summit_cpu_mask_to_apicid(cpumask, apicid); |
b11b867f IM |
305 | |
306 | free_cpumask_var(cpumask); | |
307 | ||
ff164324 | 308 | return 0; |
b11b867f IM |
309 | } |
310 | ||
311 | /* | |
312 | * cpuid returns the value latched in the HW at reset, not the APIC ID | |
313 | * register's value. For any box whose BIOS changes APIC IDs, like | |
314 | * clustered APIC systems, we must use hard_smp_processor_id. | |
315 | * | |
316 | * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID. | |
317 | */ | |
b5f26d05 | 318 | static int summit_phys_pkg_id(int cpuid_apic, int index_msb) |
b11b867f IM |
319 | { |
320 | return hard_smp_processor_id() >> index_msb; | |
321 | } | |
322 | ||
323 | static int probe_summit(void) | |
324 | { | |
325 | /* probed later in mptable/ACPI hooks */ | |
326 | return 0; | |
327 | } | |
328 | ||
7c20dcc5 | 329 | #ifdef CONFIG_X86_SUMMIT_NUMA |
2fcb1f1f JS |
330 | static struct rio_table_hdr *rio_table_hdr; |
331 | static struct scal_detail *scal_devs[MAX_NUMNODES]; | |
332 | static struct rio_detail *rio_devs[MAX_NUMNODES*4]; | |
1da177e4 | 333 | |
d49c4288 | 334 | #ifndef CONFIG_X86_NUMAQ |
2fcb1f1f | 335 | static int mp_bus_id_to_node[MAX_MP_BUSSES]; |
d49c4288 | 336 | #endif |
037cab07 | 337 | |
2fcb1f1f | 338 | static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus) |
1da177e4 LT |
339 | { |
340 | int twister = 0, node = 0; | |
341 | int i, bus, num_buses; | |
342 | ||
60e11746 PC |
343 | for (i = 0; i < rio_table_hdr->num_rio_dev; i++) { |
344 | if (rio_devs[i]->node_id == rio_devs[wpeg_num]->owner_id) { | |
1da177e4 LT |
345 | twister = rio_devs[i]->owner_id; |
346 | break; | |
347 | } | |
348 | } | |
60e11746 | 349 | if (i == rio_table_hdr->num_rio_dev) { |
c767a54b | 350 | pr_err("Couldn't find owner Cyclone for Winnipeg!\n"); |
1da177e4 LT |
351 | return last_bus; |
352 | } | |
353 | ||
60e11746 PC |
354 | for (i = 0; i < rio_table_hdr->num_scal_dev; i++) { |
355 | if (scal_devs[i]->node_id == twister) { | |
1da177e4 LT |
356 | node = scal_devs[i]->node_id; |
357 | break; | |
358 | } | |
359 | } | |
60e11746 | 360 | if (i == rio_table_hdr->num_scal_dev) { |
c767a54b | 361 | pr_err("Couldn't find owner Twister for Cyclone!\n"); |
1da177e4 LT |
362 | return last_bus; |
363 | } | |
364 | ||
60e11746 | 365 | switch (rio_devs[wpeg_num]->type) { |
1da177e4 | 366 | case CompatWPEG: |
60e11746 PC |
367 | /* |
368 | * The Compatibility Winnipeg controls the 2 legacy buses, | |
1da177e4 LT |
369 | * the 66MHz PCI bus [2 slots] and the 2 "extra" buses in case |
370 | * a PCI-PCI bridge card is used in either slot: total 5 buses. | |
371 | */ | |
372 | num_buses = 5; | |
373 | break; | |
374 | case AltWPEG: | |
60e11746 PC |
375 | /* |
376 | * The Alternate Winnipeg controls the 2 133MHz buses [1 slot | |
1da177e4 LT |
377 | * each], their 2 "extra" buses, the 100MHz bus [2 slots] and |
378 | * the "extra" buses for each of those slots: total 7 buses. | |
379 | */ | |
380 | num_buses = 7; | |
381 | break; | |
382 | case LookOutAWPEG: | |
383 | case LookOutBWPEG: | |
60e11746 PC |
384 | /* |
385 | * A Lookout Winnipeg controls 3 100MHz buses [2 slots each] | |
1da177e4 LT |
386 | * & the "extra" buses for each of those slots: total 9 buses. |
387 | */ | |
388 | num_buses = 9; | |
389 | break; | |
390 | default: | |
c767a54b | 391 | pr_info("Unsupported Winnipeg type!\n"); |
1da177e4 LT |
392 | return last_bus; |
393 | } | |
394 | ||
60e11746 | 395 | for (bus = last_bus; bus < last_bus + num_buses; bus++) |
1da177e4 LT |
396 | mp_bus_id_to_node[bus] = node; |
397 | return bus; | |
398 | } | |
399 | ||
2fcb1f1f | 400 | static int build_detail_arrays(void) |
1da177e4 LT |
401 | { |
402 | unsigned long ptr; | |
403 | int i, scal_detail_size, rio_detail_size; | |
404 | ||
60e11746 | 405 | if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) { |
c767a54b JP |
406 | pr_warn("MAX_NUMNODES too low! Defined as %d, but system has %d nodes\n", |
407 | MAX_NUMNODES, rio_table_hdr->num_scal_dev); | |
1da177e4 LT |
408 | return 0; |
409 | } | |
410 | ||
60e11746 | 411 | switch (rio_table_hdr->version) { |
1da177e4 | 412 | default: |
c767a54b JP |
413 | pr_warn("Invalid Rio Grande Table Version: %d\n", |
414 | rio_table_hdr->version); | |
1da177e4 LT |
415 | return 0; |
416 | case 2: | |
417 | scal_detail_size = 11; | |
418 | rio_detail_size = 13; | |
419 | break; | |
420 | case 3: | |
421 | scal_detail_size = 12; | |
422 | rio_detail_size = 15; | |
423 | break; | |
424 | } | |
425 | ||
426 | ptr = (unsigned long)rio_table_hdr + 3; | |
60e11746 | 427 | for (i = 0; i < rio_table_hdr->num_scal_dev; i++, ptr += scal_detail_size) |
1da177e4 LT |
428 | scal_devs[i] = (struct scal_detail *)ptr; |
429 | ||
60e11746 | 430 | for (i = 0; i < rio_table_hdr->num_rio_dev; i++, ptr += rio_detail_size) |
1da177e4 LT |
431 | rio_devs[i] = (struct rio_detail *)ptr; |
432 | ||
433 | return 1; | |
434 | } | |
435 | ||
2fcb1f1f | 436 | void setup_summit(void) |
1da177e4 LT |
437 | { |
438 | unsigned long ptr; | |
439 | unsigned short offset; | |
440 | int i, next_wpeg, next_bus = 0; | |
441 | ||
442 | /* The pointer to the EBDA is stored in the word @ phys 0x40E(40:0E) */ | |
356fa0c6 AM |
443 | ptr = get_bios_ebda(); |
444 | ptr = (unsigned long)phys_to_virt(ptr); | |
1da177e4 LT |
445 | |
446 | rio_table_hdr = NULL; | |
447 | offset = 0x180; | |
60e11746 | 448 | while (offset) { |
1da177e4 | 449 | /* The block id is stored in the 2nd word */ |
60e11746 | 450 | if (*((unsigned short *)(ptr + offset + 2)) == 0x4752) { |
1da177e4 LT |
451 | /* set the pointer past the offset & block id */ |
452 | rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); | |
453 | break; | |
454 | } | |
455 | /* The next offset is stored in the 1st word. 0 means no more */ | |
456 | offset = *((unsigned short *)(ptr + offset)); | |
457 | } | |
60e11746 | 458 | if (!rio_table_hdr) { |
c767a54b | 459 | pr_err("Unable to locate Rio Grande Table in EBDA - bailing!\n"); |
1da177e4 LT |
460 | return; |
461 | } | |
462 | ||
463 | if (!build_detail_arrays()) | |
464 | return; | |
465 | ||
466 | /* The first Winnipeg we're looking for has an index of 0 */ | |
467 | next_wpeg = 0; | |
468 | do { | |
60e11746 PC |
469 | for (i = 0; i < rio_table_hdr->num_rio_dev; i++) { |
470 | if (is_WPEG(rio_devs[i]) && rio_devs[i]->WP_index == next_wpeg) { | |
1da177e4 LT |
471 | /* It's the Winnipeg we're looking for! */ |
472 | next_bus = setup_pci_node_map_for_wpeg(i, next_bus); | |
473 | next_wpeg++; | |
474 | break; | |
475 | } | |
476 | } | |
477 | /* | |
478 | * If we go through all Rio devices and don't find one with | |
479 | * the next index, it means we've found all the Winnipegs, | |
480 | * and thus all the PCI buses. | |
481 | */ | |
482 | if (i == rio_table_hdr->num_rio_dev) | |
483 | next_wpeg = 0; | |
484 | } while (next_wpeg != 0); | |
485 | } | |
7c20dcc5 | 486 | #endif |
b11b867f | 487 | |
1a8880a1 | 488 | static struct apic apic_summit = { |
b11b867f IM |
489 | |
490 | .name = "summit", | |
491 | .probe = probe_summit, | |
492 | .acpi_madt_oem_check = summit_acpi_madt_oem_check, | |
fa63030e | 493 | .apic_id_valid = default_apic_id_valid, |
b11b867f IM |
494 | .apic_id_registered = summit_apic_id_registered, |
495 | ||
496 | .irq_delivery_mode = dest_LowestPrio, | |
497 | /* logical delivery broadcast to all CPUs: */ | |
498 | .irq_dest_mode = 1, | |
499 | ||
500 | .target_cpus = summit_target_cpus, | |
501 | .disable_esr = 1, | |
502 | .dest_logical = APIC_DEST_LOGICAL, | |
503 | .check_apicid_used = summit_check_apicid_used, | |
504 | .check_apicid_present = summit_check_apicid_present, | |
505 | ||
9d8e1066 | 506 | .vector_allocation_domain = flat_vector_allocation_domain, |
b11b867f IM |
507 | .init_apic_ldr = summit_init_apic_ldr, |
508 | ||
509 | .ioapic_phys_id_map = summit_ioapic_phys_id_map, | |
510 | .setup_apic_routing = summit_setup_apic_routing, | |
511 | .multi_timer_check = NULL, | |
b11b867f IM |
512 | .cpu_present_to_apicid = summit_cpu_present_to_apicid, |
513 | .apicid_to_cpu_present = summit_apicid_to_cpu_present, | |
514 | .setup_portio_remap = NULL, | |
515 | .check_phys_apicid_present = summit_check_phys_apicid_present, | |
516 | .enable_apic_mode = NULL, | |
517 | .phys_pkg_id = summit_phys_pkg_id, | |
518 | .mps_oem_check = summit_mps_oem_check, | |
519 | ||
520 | .get_apic_id = summit_get_apic_id, | |
521 | .set_apic_id = NULL, | |
522 | .apic_id_mask = 0xFF << 24, | |
523 | ||
b11b867f IM |
524 | .cpu_mask_to_apicid_and = summit_cpu_mask_to_apicid_and, |
525 | ||
526 | .send_IPI_mask = summit_send_IPI_mask, | |
527 | .send_IPI_mask_allbutself = NULL, | |
528 | .send_IPI_allbutself = summit_send_IPI_allbutself, | |
529 | .send_IPI_all = summit_send_IPI_all, | |
6b64ee02 | 530 | .send_IPI_self = default_send_IPI_self, |
b11b867f | 531 | |
b11b867f IM |
532 | .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, |
533 | .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, | |
534 | ||
465822cf | 535 | .wait_for_init_deassert = true, |
b11b867f | 536 | .smp_callin_clear_local_apic = NULL, |
b11b867f | 537 | .inquire_remote_apic = default_inquire_remote_apic, |
c1eeb2de YL |
538 | |
539 | .read = native_apic_mem_read, | |
540 | .write = native_apic_mem_write, | |
2a43195d | 541 | .eoi_write = native_apic_mem_write, |
c1eeb2de YL |
542 | .icr_read = native_apic_icr_read, |
543 | .icr_write = native_apic_icr_write, | |
544 | .wait_icr_idle = native_apic_wait_icr_idle, | |
545 | .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, | |
acb8bc09 | 546 | |
3b39d937 | 547 | .x86_32_early_logical_apicid = summit_early_logical_apicid, |
b11b867f | 548 | }; |
107e0e0c SS |
549 | |
550 | apic_driver(apic_summit); |