Commit | Line | Data |
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74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/compiler.h> | |
74afab7a | 16 | #include <linux/slab.h> |
d746d1eb | 17 | #include <asm/irqdomain.h> |
74afab7a JL |
18 | #include <asm/hw_irq.h> |
19 | #include <asm/apic.h> | |
20 | #include <asm/i8259.h> | |
21 | #include <asm/desc.h> | |
22 | #include <asm/irq_remapping.h> | |
23 | ||
7f3262ed JL |
24 | struct apic_chip_data { |
25 | struct irq_cfg cfg; | |
26 | cpumask_var_t domain; | |
27 | cpumask_var_t old_domain; | |
28 | u8 move_in_progress : 1; | |
29 | }; | |
30 | ||
b5dc8e6c | 31 | struct irq_domain *x86_vector_domain; |
c8f3e518 | 32 | EXPORT_SYMBOL_GPL(x86_vector_domain); |
74afab7a | 33 | static DEFINE_RAW_SPINLOCK(vector_lock); |
3716fd27 | 34 | static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask; |
b5dc8e6c | 35 | static struct irq_chip lapic_controller; |
13315320 | 36 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed | 37 | static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; |
13315320 | 38 | #endif |
74afab7a JL |
39 | |
40 | void lock_vector_lock(void) | |
41 | { | |
42 | /* Used to the online set of cpus does not change | |
43 | * during assign_irq_vector. | |
44 | */ | |
45 | raw_spin_lock(&vector_lock); | |
46 | } | |
47 | ||
48 | void unlock_vector_lock(void) | |
49 | { | |
50 | raw_spin_unlock(&vector_lock); | |
51 | } | |
52 | ||
7f3262ed | 53 | static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data) |
74afab7a | 54 | { |
b5dc8e6c JL |
55 | if (!irq_data) |
56 | return NULL; | |
57 | ||
58 | while (irq_data->parent_data) | |
59 | irq_data = irq_data->parent_data; | |
60 | ||
74afab7a JL |
61 | return irq_data->chip_data; |
62 | } | |
63 | ||
7f3262ed JL |
64 | struct irq_cfg *irqd_cfg(struct irq_data *irq_data) |
65 | { | |
66 | struct apic_chip_data *data = apic_chip_data(irq_data); | |
67 | ||
68 | return data ? &data->cfg : NULL; | |
69 | } | |
c8f3e518 | 70 | EXPORT_SYMBOL_GPL(irqd_cfg); |
7f3262ed JL |
71 | |
72 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 73 | { |
7f3262ed JL |
74 | return irqd_cfg(irq_get_irq_data(irq)); |
75 | } | |
74afab7a | 76 | |
7f3262ed JL |
77 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
78 | { | |
79 | struct apic_chip_data *data; | |
80 | ||
81 | data = kzalloc_node(sizeof(*data), GFP_KERNEL, node); | |
82 | if (!data) | |
74afab7a | 83 | return NULL; |
7f3262ed JL |
84 | if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node)) |
85 | goto out_data; | |
86 | if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node)) | |
74afab7a | 87 | goto out_domain; |
7f3262ed | 88 | return data; |
74afab7a | 89 | out_domain: |
7f3262ed JL |
90 | free_cpumask_var(data->domain); |
91 | out_data: | |
92 | kfree(data); | |
74afab7a JL |
93 | return NULL; |
94 | } | |
95 | ||
7f3262ed | 96 | static void free_apic_chip_data(struct apic_chip_data *data) |
74afab7a | 97 | { |
7f3262ed JL |
98 | if (data) { |
99 | free_cpumask_var(data->domain); | |
100 | free_cpumask_var(data->old_domain); | |
101 | kfree(data); | |
b5dc8e6c | 102 | } |
74afab7a JL |
103 | } |
104 | ||
7f3262ed JL |
105 | static int __assign_irq_vector(int irq, struct apic_chip_data *d, |
106 | const struct cpumask *mask) | |
74afab7a JL |
107 | { |
108 | /* | |
109 | * NOTE! The local APIC isn't very good at handling | |
110 | * multiple interrupts at the same interrupt level. | |
111 | * As the interrupt level is determined by taking the | |
112 | * vector number and shifting that right by 4, we | |
113 | * want to spread these out a bit so that they don't | |
114 | * all fall in the same interrupt level. | |
115 | * | |
116 | * Also, we've got to be careful not to trash gate | |
117 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
118 | */ | |
119 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
120 | static int current_offset = VECTOR_OFFSET_START % 16; | |
ab25ac02 | 121 | int cpu, vector; |
74afab7a | 122 | |
98229aa3 TG |
123 | /* |
124 | * If there is still a move in progress or the previous move has not | |
125 | * been cleaned up completely, tell the caller to come back later. | |
126 | */ | |
127 | if (d->move_in_progress || | |
128 | cpumask_intersects(d->old_domain, cpu_online_mask)) | |
74afab7a JL |
129 | return -EBUSY; |
130 | ||
74afab7a | 131 | /* Only try and allocate irqs on cpus that are present */ |
7f3262ed | 132 | cpumask_clear(d->old_domain); |
8a580f70 | 133 | cpumask_clear(searched_cpumask); |
74afab7a JL |
134 | cpu = cpumask_first_and(mask, cpu_online_mask); |
135 | while (cpu < nr_cpu_ids) { | |
ab25ac02 | 136 | int new_cpu, offset; |
74afab7a | 137 | |
3716fd27 | 138 | /* Get the possible target cpus for @mask/@cpu from the apic */ |
f7fa7aee | 139 | apic->vector_allocation_domain(cpu, vector_cpumask, mask); |
74afab7a | 140 | |
3716fd27 TG |
141 | /* |
142 | * Clear the offline cpus from @vector_cpumask for searching | |
143 | * and verify whether the result overlaps with @mask. If true, | |
144 | * then the call to apic->cpu_mask_to_apicid_and() will | |
145 | * succeed as well. If not, no point in trying to find a | |
146 | * vector in this mask. | |
147 | */ | |
148 | cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask); | |
149 | if (!cpumask_intersects(vector_searchmask, mask)) | |
150 | goto next_cpu; | |
151 | ||
f7fa7aee | 152 | if (cpumask_subset(vector_cpumask, d->domain)) { |
f7fa7aee | 153 | if (cpumask_equal(vector_cpumask, d->domain)) |
433cbd57 | 154 | goto success; |
74afab7a | 155 | /* |
ab25ac02 TG |
156 | * Mark the cpus which are not longer in the mask for |
157 | * cleanup. | |
74afab7a | 158 | */ |
ab25ac02 TG |
159 | cpumask_andnot(d->old_domain, d->domain, vector_cpumask); |
160 | vector = d->cfg.vector; | |
161 | goto update; | |
74afab7a JL |
162 | } |
163 | ||
164 | vector = current_vector; | |
165 | offset = current_offset; | |
166 | next: | |
167 | vector += 16; | |
168 | if (vector >= first_system_vector) { | |
169 | offset = (offset + 1) % 16; | |
170 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
171 | } | |
172 | ||
95ffeb4b TG |
173 | /* If the search wrapped around, try the next cpu */ |
174 | if (unlikely(current_vector == vector)) | |
175 | goto next_cpu; | |
74afab7a JL |
176 | |
177 | if (test_bit(vector, used_vectors)) | |
178 | goto next; | |
179 | ||
3716fd27 | 180 | for_each_cpu(new_cpu, vector_searchmask) { |
a782a7e4 | 181 | if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) |
74afab7a JL |
182 | goto next; |
183 | } | |
184 | /* Found one! */ | |
185 | current_vector = vector; | |
186 | current_offset = offset; | |
ab25ac02 TG |
187 | /* Schedule the old vector for cleanup on all cpus */ |
188 | if (d->cfg.vector) | |
7f3262ed | 189 | cpumask_copy(d->old_domain, d->domain); |
3716fd27 | 190 | for_each_cpu(new_cpu, vector_searchmask) |
a782a7e4 | 191 | per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); |
ab25ac02 | 192 | goto update; |
95ffeb4b TG |
193 | |
194 | next_cpu: | |
195 | /* | |
196 | * We exclude the current @vector_cpumask from the requested | |
197 | * @mask and try again with the next online cpu in the | |
198 | * result. We cannot modify @mask, so we use @vector_cpumask | |
199 | * as a temporary buffer here as it will be reassigned when | |
200 | * calling apic->vector_allocation_domain() above. | |
201 | */ | |
202 | cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask); | |
203 | cpumask_andnot(vector_cpumask, mask, searched_cpumask); | |
204 | cpu = cpumask_first_and(vector_cpumask, cpu_online_mask); | |
205 | continue; | |
74afab7a | 206 | } |
433cbd57 | 207 | return -ENOSPC; |
74afab7a | 208 | |
ab25ac02 | 209 | update: |
847667ef TG |
210 | /* |
211 | * Exclude offline cpus from the cleanup mask and set the | |
212 | * move_in_progress flag when the result is not empty. | |
213 | */ | |
214 | cpumask_and(d->old_domain, d->old_domain, cpu_online_mask); | |
215 | d->move_in_progress = !cpumask_empty(d->old_domain); | |
551adc60 | 216 | d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0; |
ab25ac02 TG |
217 | d->cfg.vector = vector; |
218 | cpumask_copy(d->domain, vector_cpumask); | |
433cbd57 | 219 | success: |
3716fd27 TG |
220 | /* |
221 | * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail | |
222 | * as we already established, that mask & d->domain & cpu_online_mask | |
223 | * is not empty. | |
224 | */ | |
225 | BUG_ON(apic->cpu_mask_to_apicid_and(mask, d->domain, | |
226 | &d->cfg.dest_apicid)); | |
227 | return 0; | |
74afab7a JL |
228 | } |
229 | ||
7f3262ed | 230 | static int assign_irq_vector(int irq, struct apic_chip_data *data, |
f970510c | 231 | const struct cpumask *mask) |
74afab7a JL |
232 | { |
233 | int err; | |
234 | unsigned long flags; | |
235 | ||
236 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed | 237 | err = __assign_irq_vector(irq, data, mask); |
74afab7a JL |
238 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
239 | return err; | |
240 | } | |
241 | ||
486ca539 JL |
242 | static int assign_irq_vector_policy(int irq, int node, |
243 | struct apic_chip_data *data, | |
244 | struct irq_alloc_info *info) | |
245 | { | |
246 | if (info && info->mask) | |
247 | return assign_irq_vector(irq, data, info->mask); | |
248 | if (node != NUMA_NO_NODE && | |
249 | assign_irq_vector(irq, data, cpumask_of_node(node)) == 0) | |
250 | return 0; | |
251 | return assign_irq_vector(irq, data, apic->target_cpus()); | |
252 | } | |
253 | ||
7f3262ed | 254 | static void clear_irq_vector(int irq, struct apic_chip_data *data) |
74afab7a | 255 | { |
a782a7e4 | 256 | struct irq_desc *desc; |
a782a7e4 | 257 | int cpu, vector; |
74afab7a | 258 | |
1bdb8970 KB |
259 | if (!data->cfg.vector) |
260 | return; | |
74afab7a | 261 | |
7f3262ed JL |
262 | vector = data->cfg.vector; |
263 | for_each_cpu_and(cpu, data->domain, cpu_online_mask) | |
7276c6a2 | 264 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a | 265 | |
7f3262ed JL |
266 | data->cfg.vector = 0; |
267 | cpumask_clear(data->domain); | |
74afab7a | 268 | |
98229aa3 TG |
269 | /* |
270 | * If move is in progress or the old_domain mask is not empty, | |
271 | * i.e. the cleanup IPI has not been processed yet, we need to remove | |
272 | * the old references to desc from all cpus vector tables. | |
273 | */ | |
274 | if (!data->move_in_progress && cpumask_empty(data->old_domain)) | |
74afab7a | 275 | return; |
74afab7a | 276 | |
a782a7e4 | 277 | desc = irq_to_desc(irq); |
7f3262ed | 278 | for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) { |
74afab7a JL |
279 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
280 | vector++) { | |
a782a7e4 | 281 | if (per_cpu(vector_irq, cpu)[vector] != desc) |
74afab7a | 282 | continue; |
7276c6a2 | 283 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a JL |
284 | break; |
285 | } | |
286 | } | |
7f3262ed | 287 | data->move_in_progress = 0; |
74afab7a JL |
288 | } |
289 | ||
b5dc8e6c JL |
290 | void init_irq_alloc_info(struct irq_alloc_info *info, |
291 | const struct cpumask *mask) | |
292 | { | |
293 | memset(info, 0, sizeof(*info)); | |
294 | info->mask = mask; | |
295 | } | |
296 | ||
297 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
298 | { | |
299 | if (src) | |
300 | *dst = *src; | |
301 | else | |
302 | memset(dst, 0, sizeof(*dst)); | |
303 | } | |
304 | ||
b5dc8e6c JL |
305 | static void x86_vector_free_irqs(struct irq_domain *domain, |
306 | unsigned int virq, unsigned int nr_irqs) | |
307 | { | |
111abeba | 308 | struct apic_chip_data *apic_data; |
b5dc8e6c | 309 | struct irq_data *irq_data; |
111abeba | 310 | unsigned long flags; |
b5dc8e6c JL |
311 | int i; |
312 | ||
313 | for (i = 0; i < nr_irqs; i++) { | |
314 | irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i); | |
315 | if (irq_data && irq_data->chip_data) { | |
111abeba | 316 | raw_spin_lock_irqsave(&vector_lock, flags); |
b5dc8e6c | 317 | clear_irq_vector(virq + i, irq_data->chip_data); |
111abeba JL |
318 | apic_data = irq_data->chip_data; |
319 | irq_domain_reset_irq_data(irq_data); | |
320 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
321 | free_apic_chip_data(apic_data); | |
13315320 JL |
322 | #ifdef CONFIG_X86_IO_APIC |
323 | if (virq + i < nr_legacy_irqs()) | |
7f3262ed | 324 | legacy_irq_data[virq + i] = NULL; |
13315320 | 325 | #endif |
b5dc8e6c JL |
326 | } |
327 | } | |
328 | } | |
329 | ||
330 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, | |
331 | unsigned int nr_irqs, void *arg) | |
332 | { | |
333 | struct irq_alloc_info *info = arg; | |
7f3262ed | 334 | struct apic_chip_data *data; |
b5dc8e6c | 335 | struct irq_data *irq_data; |
5f2dbbc5 | 336 | int i, err, node; |
b5dc8e6c JL |
337 | |
338 | if (disable_apic) | |
339 | return -ENXIO; | |
340 | ||
341 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
342 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
343 | return -ENOSYS; | |
344 | ||
b5dc8e6c JL |
345 | for (i = 0; i < nr_irqs; i++) { |
346 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
347 | BUG_ON(!irq_data); | |
5f2dbbc5 | 348 | node = irq_data_get_node(irq_data); |
13315320 | 349 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed JL |
350 | if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) |
351 | data = legacy_irq_data[virq + i]; | |
13315320 JL |
352 | else |
353 | #endif | |
5f2dbbc5 | 354 | data = alloc_apic_chip_data(node); |
7f3262ed | 355 | if (!data) { |
b5dc8e6c JL |
356 | err = -ENOMEM; |
357 | goto error; | |
358 | } | |
359 | ||
360 | irq_data->chip = &lapic_controller; | |
7f3262ed | 361 | irq_data->chip_data = data; |
b5dc8e6c | 362 | irq_data->hwirq = virq + i; |
43af9872 | 363 | err = assign_irq_vector_policy(virq + i, node, data, info); |
b5dc8e6c JL |
364 | if (err) |
365 | goto error; | |
366 | } | |
367 | ||
368 | return 0; | |
369 | ||
370 | error: | |
371 | x86_vector_free_irqs(domain, virq, i + 1); | |
372 | return err; | |
373 | } | |
374 | ||
eb18cf55 TG |
375 | static const struct irq_domain_ops x86_vector_domain_ops = { |
376 | .alloc = x86_vector_alloc_irqs, | |
377 | .free = x86_vector_free_irqs, | |
b5dc8e6c JL |
378 | }; |
379 | ||
11d686e9 JL |
380 | int __init arch_probe_nr_irqs(void) |
381 | { | |
382 | int nr; | |
383 | ||
384 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
385 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
386 | ||
387 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
388 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
389 | /* | |
390 | * for MSI and HT dyn irq | |
391 | */ | |
392 | if (gsi_top <= NR_IRQS_LEGACY) | |
393 | nr += 8 * nr_cpu_ids; | |
394 | else | |
395 | nr += gsi_top * 16; | |
396 | #endif | |
397 | if (nr < nr_irqs) | |
398 | nr_irqs = nr; | |
399 | ||
8c058b0b VK |
400 | /* |
401 | * We don't know if PIC is present at this point so we need to do | |
402 | * probe() to get the right number of legacy IRQs. | |
403 | */ | |
404 | return legacy_pic->probe(); | |
11d686e9 JL |
405 | } |
406 | ||
13315320 JL |
407 | #ifdef CONFIG_X86_IO_APIC |
408 | static void init_legacy_irqs(void) | |
409 | { | |
410 | int i, node = cpu_to_node(0); | |
7f3262ed | 411 | struct apic_chip_data *data; |
13315320 JL |
412 | |
413 | /* | |
414 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
191a6635 | 415 | * ISA_IRQ_VECTOR(i) for all cpu's. |
13315320 JL |
416 | */ |
417 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
7f3262ed JL |
418 | data = legacy_irq_data[i] = alloc_apic_chip_data(node); |
419 | BUG_ON(!data); | |
191a6635 IM |
420 | |
421 | data->cfg.vector = ISA_IRQ_VECTOR(i); | |
7f3262ed JL |
422 | cpumask_setall(data->domain); |
423 | irq_set_chip_data(i, data); | |
13315320 JL |
424 | } |
425 | } | |
426 | #else | |
427 | static void init_legacy_irqs(void) { } | |
428 | #endif | |
429 | ||
11d686e9 JL |
430 | int __init arch_early_irq_init(void) |
431 | { | |
13315320 JL |
432 | init_legacy_irqs(); |
433 | ||
b5dc8e6c JL |
434 | x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops, |
435 | NULL); | |
436 | BUG_ON(x86_vector_domain == NULL); | |
437 | irq_set_default_host(x86_vector_domain); | |
438 | ||
52f518a3 | 439 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 440 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 441 | |
f7fa7aee | 442 | BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); |
3716fd27 | 443 | BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); |
8a580f70 | 444 | BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL)); |
f7fa7aee | 445 | |
11d686e9 JL |
446 | return arch_early_ioapic_init(); |
447 | } | |
448 | ||
a782a7e4 | 449 | /* Initialize vector_irq on a new cpu */ |
74afab7a JL |
450 | static void __setup_vector_irq(int cpu) |
451 | { | |
7f3262ed | 452 | struct apic_chip_data *data; |
a782a7e4 TG |
453 | struct irq_desc *desc; |
454 | int irq, vector; | |
74afab7a | 455 | |
74afab7a | 456 | /* Mark the inuse vectors */ |
a782a7e4 TG |
457 | for_each_irq_desc(irq, desc) { |
458 | struct irq_data *idata = irq_desc_get_irq_data(desc); | |
74afab7a | 459 | |
a782a7e4 TG |
460 | data = apic_chip_data(idata); |
461 | if (!data || !cpumask_test_cpu(cpu, data->domain)) | |
74afab7a | 462 | continue; |
7f3262ed | 463 | vector = data->cfg.vector; |
a782a7e4 | 464 | per_cpu(vector_irq, cpu)[vector] = desc; |
74afab7a JL |
465 | } |
466 | /* Mark the free vectors */ | |
467 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
a782a7e4 TG |
468 | desc = per_cpu(vector_irq, cpu)[vector]; |
469 | if (IS_ERR_OR_NULL(desc)) | |
74afab7a JL |
470 | continue; |
471 | ||
a782a7e4 | 472 | data = apic_chip_data(irq_desc_get_irq_data(desc)); |
7f3262ed | 473 | if (!cpumask_test_cpu(cpu, data->domain)) |
7276c6a2 | 474 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a | 475 | } |
74afab7a JL |
476 | } |
477 | ||
478 | /* | |
5a3f75e3 | 479 | * Setup the vector to irq mappings. Must be called with vector_lock held. |
74afab7a JL |
480 | */ |
481 | void setup_vector_irq(int cpu) | |
482 | { | |
483 | int irq; | |
484 | ||
5a3f75e3 | 485 | lockdep_assert_held(&vector_lock); |
74afab7a JL |
486 | /* |
487 | * On most of the platforms, legacy PIC delivers the interrupts on the | |
488 | * boot cpu. But there are certain platforms where PIC interrupts are | |
489 | * delivered to multiple cpu's. If the legacy IRQ is handled by the | |
490 | * legacy PIC, for the new cpu that is coming online, setup the static | |
491 | * legacy vector to irq mapping: | |
492 | */ | |
493 | for (irq = 0; irq < nr_legacy_irqs(); irq++) | |
a782a7e4 | 494 | per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq); |
74afab7a JL |
495 | |
496 | __setup_vector_irq(cpu); | |
497 | } | |
498 | ||
7f3262ed | 499 | static int apic_retrigger_irq(struct irq_data *irq_data) |
74afab7a | 500 | { |
7f3262ed | 501 | struct apic_chip_data *data = apic_chip_data(irq_data); |
74afab7a JL |
502 | unsigned long flags; |
503 | int cpu; | |
504 | ||
505 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed JL |
506 | cpu = cpumask_first_and(data->domain, cpu_online_mask); |
507 | apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector); | |
74afab7a JL |
508 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
509 | ||
510 | return 1; | |
511 | } | |
512 | ||
513 | void apic_ack_edge(struct irq_data *data) | |
514 | { | |
a9786091 | 515 | irq_complete_move(irqd_cfg(data)); |
74afab7a JL |
516 | irq_move_irq(data); |
517 | ack_APIC_irq(); | |
518 | } | |
519 | ||
68f9f440 JL |
520 | static int apic_set_affinity(struct irq_data *irq_data, |
521 | const struct cpumask *dest, bool force) | |
b5dc8e6c | 522 | { |
7f3262ed | 523 | struct apic_chip_data *data = irq_data->chip_data; |
b5dc8e6c JL |
524 | int err, irq = irq_data->irq; |
525 | ||
526 | if (!config_enabled(CONFIG_SMP)) | |
527 | return -EPERM; | |
528 | ||
529 | if (!cpumask_intersects(dest, cpu_online_mask)) | |
530 | return -EINVAL; | |
531 | ||
7f3262ed | 532 | err = assign_irq_vector(irq, data, dest); |
3716fd27 | 533 | return err ? err : IRQ_SET_MASK_OK; |
b5dc8e6c JL |
534 | } |
535 | ||
536 | static struct irq_chip lapic_controller = { | |
537 | .irq_ack = apic_ack_edge, | |
68f9f440 | 538 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
539 | .irq_retrigger = apic_retrigger_irq, |
540 | }; | |
541 | ||
74afab7a | 542 | #ifdef CONFIG_SMP |
7f3262ed | 543 | static void __send_cleanup_vector(struct apic_chip_data *data) |
74afab7a | 544 | { |
c1684f50 | 545 | raw_spin_lock(&vector_lock); |
5da0c121 | 546 | cpumask_and(data->old_domain, data->old_domain, cpu_online_mask); |
c1684f50 | 547 | data->move_in_progress = 0; |
5da0c121 TG |
548 | if (!cpumask_empty(data->old_domain)) |
549 | apic->send_IPI_mask(data->old_domain, IRQ_MOVE_CLEANUP_VECTOR); | |
c1684f50 | 550 | raw_spin_unlock(&vector_lock); |
74afab7a JL |
551 | } |
552 | ||
c6c2002b JL |
553 | void send_cleanup_vector(struct irq_cfg *cfg) |
554 | { | |
7f3262ed JL |
555 | struct apic_chip_data *data; |
556 | ||
557 | data = container_of(cfg, struct apic_chip_data, cfg); | |
558 | if (data->move_in_progress) | |
559 | __send_cleanup_vector(data); | |
c6c2002b JL |
560 | } |
561 | ||
74afab7a JL |
562 | asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) |
563 | { | |
564 | unsigned vector, me; | |
565 | ||
6af7faf6 | 566 | entering_ack_irq(); |
74afab7a | 567 | |
df54c493 TG |
568 | /* Prevent vectors vanishing under us */ |
569 | raw_spin_lock(&vector_lock); | |
570 | ||
74afab7a JL |
571 | me = smp_processor_id(); |
572 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
7f3262ed | 573 | struct apic_chip_data *data; |
a782a7e4 TG |
574 | struct irq_desc *desc; |
575 | unsigned int irr; | |
74afab7a | 576 | |
df54c493 | 577 | retry: |
a782a7e4 TG |
578 | desc = __this_cpu_read(vector_irq[vector]); |
579 | if (IS_ERR_OR_NULL(desc)) | |
74afab7a JL |
580 | continue; |
581 | ||
df54c493 TG |
582 | if (!raw_spin_trylock(&desc->lock)) { |
583 | raw_spin_unlock(&vector_lock); | |
584 | cpu_relax(); | |
585 | raw_spin_lock(&vector_lock); | |
586 | goto retry; | |
587 | } | |
74afab7a | 588 | |
a782a7e4 | 589 | data = apic_chip_data(irq_desc_get_irq_data(desc)); |
7f3262ed | 590 | if (!data) |
df54c493 | 591 | goto unlock; |
74afab7a JL |
592 | |
593 | /* | |
98229aa3 TG |
594 | * Nothing to cleanup if irq migration is in progress |
595 | * or this cpu is not set in the cleanup mask. | |
74afab7a | 596 | */ |
98229aa3 TG |
597 | if (data->move_in_progress || |
598 | !cpumask_test_cpu(me, data->old_domain)) | |
74afab7a JL |
599 | goto unlock; |
600 | ||
98229aa3 TG |
601 | /* |
602 | * We have two cases to handle here: | |
603 | * 1) vector is unchanged but the target mask got reduced | |
604 | * 2) vector and the target mask has changed | |
605 | * | |
606 | * #1 is obvious, but in #2 we have two vectors with the same | |
607 | * irq descriptor: the old and the new vector. So we need to | |
608 | * make sure that we only cleanup the old vector. The new | |
609 | * vector has the current @vector number in the config and | |
610 | * this cpu is part of the target mask. We better leave that | |
611 | * one alone. | |
612 | */ | |
7f3262ed JL |
613 | if (vector == data->cfg.vector && |
614 | cpumask_test_cpu(me, data->domain)) | |
74afab7a JL |
615 | goto unlock; |
616 | ||
617 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
618 | /* | |
619 | * Check if the vector that needs to be cleanedup is | |
620 | * registered at the cpu's IRR. If so, then this is not | |
621 | * the best time to clean it up. Lets clean it up in the | |
622 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
623 | * to myself. | |
624 | */ | |
625 | if (irr & (1 << (vector % 32))) { | |
626 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
627 | goto unlock; | |
628 | } | |
7276c6a2 | 629 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
98229aa3 | 630 | cpumask_clear_cpu(me, data->old_domain); |
74afab7a JL |
631 | unlock: |
632 | raw_spin_unlock(&desc->lock); | |
633 | } | |
634 | ||
df54c493 TG |
635 | raw_spin_unlock(&vector_lock); |
636 | ||
6af7faf6 | 637 | exiting_irq(); |
74afab7a JL |
638 | } |
639 | ||
640 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) | |
641 | { | |
642 | unsigned me; | |
7f3262ed | 643 | struct apic_chip_data *data; |
74afab7a | 644 | |
7f3262ed JL |
645 | data = container_of(cfg, struct apic_chip_data, cfg); |
646 | if (likely(!data->move_in_progress)) | |
74afab7a JL |
647 | return; |
648 | ||
649 | me = smp_processor_id(); | |
7f3262ed JL |
650 | if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain)) |
651 | __send_cleanup_vector(data); | |
74afab7a JL |
652 | } |
653 | ||
654 | void irq_complete_move(struct irq_cfg *cfg) | |
655 | { | |
656 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
657 | } | |
658 | ||
90a2282e | 659 | /* |
551adc60 | 660 | * Called from fixup_irqs() with @desc->lock held and interrupts disabled. |
90a2282e TG |
661 | */ |
662 | void irq_force_complete_move(struct irq_desc *desc) | |
74afab7a | 663 | { |
90a2282e TG |
664 | struct irq_data *irqdata = irq_desc_get_irq_data(desc); |
665 | struct apic_chip_data *data = apic_chip_data(irqdata); | |
666 | struct irq_cfg *cfg = data ? &data->cfg : NULL; | |
551adc60 | 667 | unsigned int cpu; |
56d7d2f4 TG |
668 | |
669 | if (!cfg) | |
670 | return; | |
74afab7a | 671 | |
56d7d2f4 | 672 | /* |
98229aa3 TG |
673 | * This is tricky. If the cleanup of @data->old_domain has not been |
674 | * done yet, then the following setaffinity call will fail with | |
675 | * -EBUSY. This can leave the interrupt in a stale state. | |
676 | * | |
551adc60 TG |
677 | * All CPUs are stuck in stop machine with interrupts disabled so |
678 | * calling __irq_complete_move() would be completely pointless. | |
56d7d2f4 TG |
679 | */ |
680 | raw_spin_lock(&vector_lock); | |
551adc60 TG |
681 | /* |
682 | * Clean out all offline cpus (including the outgoing one) from the | |
683 | * old_domain mask. | |
684 | */ | |
98229aa3 | 685 | cpumask_and(data->old_domain, data->old_domain, cpu_online_mask); |
551adc60 TG |
686 | |
687 | /* | |
688 | * If move_in_progress is cleared and the old_domain mask is empty, | |
689 | * then there is nothing to cleanup. fixup_irqs() will take care of | |
690 | * the stale vectors on the outgoing cpu. | |
691 | */ | |
692 | if (!data->move_in_progress && cpumask_empty(data->old_domain)) { | |
98229aa3 | 693 | raw_spin_unlock(&vector_lock); |
551adc60 TG |
694 | return; |
695 | } | |
696 | ||
697 | /* | |
698 | * 1) The interrupt is in move_in_progress state. That means that we | |
699 | * have not seen an interrupt since the io_apic was reprogrammed to | |
700 | * the new vector. | |
701 | * | |
702 | * 2) The interrupt has fired on the new vector, but the cleanup IPIs | |
703 | * have not been processed yet. | |
704 | */ | |
705 | if (data->move_in_progress) { | |
98229aa3 | 706 | /* |
551adc60 TG |
707 | * In theory there is a race: |
708 | * | |
709 | * set_ioapic(new_vector) <-- Interrupt is raised before update | |
710 | * is effective, i.e. it's raised on | |
711 | * the old vector. | |
712 | * | |
713 | * So if the target cpu cannot handle that interrupt before | |
714 | * the old vector is cleaned up, we get a spurious interrupt | |
715 | * and in the worst case the ioapic irq line becomes stale. | |
716 | * | |
717 | * But in case of cpu hotplug this should be a non issue | |
718 | * because if the affinity update happens right before all | |
719 | * cpus rendevouz in stop machine, there is no way that the | |
720 | * interrupt can be blocked on the target cpu because all cpus | |
721 | * loops first with interrupts enabled in stop machine, so the | |
722 | * old vector is not yet cleaned up when the interrupt fires. | |
723 | * | |
724 | * So the only way to run into this issue is if the delivery | |
725 | * of the interrupt on the apic/system bus would be delayed | |
726 | * beyond the point where the target cpu disables interrupts | |
727 | * in stop machine. I doubt that it can happen, but at least | |
728 | * there is a theroretical chance. Virtualization might be | |
729 | * able to expose this, but AFAICT the IOAPIC emulation is not | |
730 | * as stupid as the real hardware. | |
731 | * | |
732 | * Anyway, there is nothing we can do about that at this point | |
733 | * w/o refactoring the whole fixup_irq() business completely. | |
734 | * We print at least the irq number and the old vector number, | |
735 | * so we have the necessary information when a problem in that | |
736 | * area arises. | |
98229aa3 | 737 | */ |
551adc60 TG |
738 | pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", |
739 | irqdata->irq, cfg->old_vector); | |
98229aa3 | 740 | } |
551adc60 TG |
741 | /* |
742 | * If old_domain is not empty, then other cpus still have the irq | |
743 | * descriptor set in their vector array. Clean it up. | |
744 | */ | |
745 | for_each_cpu(cpu, data->old_domain) | |
746 | per_cpu(vector_irq, cpu)[cfg->old_vector] = VECTOR_UNUSED; | |
747 | ||
748 | /* Cleanup the left overs of the (half finished) move */ | |
749 | cpumask_clear(data->old_domain); | |
750 | data->move_in_progress = 0; | |
56d7d2f4 | 751 | raw_spin_unlock(&vector_lock); |
74afab7a | 752 | } |
74afab7a JL |
753 | #endif |
754 | ||
74afab7a JL |
755 | static void __init print_APIC_field(int base) |
756 | { | |
757 | int i; | |
758 | ||
759 | printk(KERN_DEBUG); | |
760 | ||
761 | for (i = 0; i < 8; i++) | |
762 | pr_cont("%08x", apic_read(base + i*0x10)); | |
763 | ||
764 | pr_cont("\n"); | |
765 | } | |
766 | ||
767 | static void __init print_local_APIC(void *dummy) | |
768 | { | |
769 | unsigned int i, v, ver, maxlvt; | |
770 | u64 icr; | |
771 | ||
849d3569 JL |
772 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
773 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 774 | v = apic_read(APIC_ID); |
849d3569 | 775 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 776 | v = apic_read(APIC_LVR); |
849d3569 | 777 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
778 | ver = GET_APIC_VERSION(v); |
779 | maxlvt = lapic_get_maxlvt(); | |
780 | ||
781 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 782 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
783 | |
784 | /* !82489DX */ | |
785 | if (APIC_INTEGRATED(ver)) { | |
786 | if (!APIC_XAPIC(ver)) { | |
787 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
788 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
789 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
790 | } |
791 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 792 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
793 | } |
794 | ||
795 | /* | |
796 | * Remote read supported only in the 82489DX and local APIC for | |
797 | * Pentium processors. | |
798 | */ | |
799 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
800 | v = apic_read(APIC_RRR); | |
849d3569 | 801 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
802 | } |
803 | ||
804 | v = apic_read(APIC_LDR); | |
849d3569 | 805 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
806 | if (!x2apic_enabled()) { |
807 | v = apic_read(APIC_DFR); | |
849d3569 | 808 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
809 | } |
810 | v = apic_read(APIC_SPIV); | |
849d3569 | 811 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 812 | |
849d3569 | 813 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 814 | print_APIC_field(APIC_ISR); |
849d3569 | 815 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 816 | print_APIC_field(APIC_TMR); |
849d3569 | 817 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
818 | print_APIC_field(APIC_IRR); |
819 | ||
820 | /* !82489DX */ | |
821 | if (APIC_INTEGRATED(ver)) { | |
822 | /* Due to the Pentium erratum 3AP. */ | |
823 | if (maxlvt > 3) | |
824 | apic_write(APIC_ESR, 0); | |
825 | ||
826 | v = apic_read(APIC_ESR); | |
849d3569 | 827 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
828 | } |
829 | ||
830 | icr = apic_icr_read(); | |
849d3569 JL |
831 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
832 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
833 | |
834 | v = apic_read(APIC_LVTT); | |
849d3569 | 835 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
836 | |
837 | if (maxlvt > 3) { | |
838 | /* PC is LVT#4. */ | |
839 | v = apic_read(APIC_LVTPC); | |
849d3569 | 840 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
841 | } |
842 | v = apic_read(APIC_LVT0); | |
849d3569 | 843 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 844 | v = apic_read(APIC_LVT1); |
849d3569 | 845 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
846 | |
847 | if (maxlvt > 2) { | |
848 | /* ERR is LVT#3. */ | |
849 | v = apic_read(APIC_LVTERR); | |
849d3569 | 850 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
851 | } |
852 | ||
853 | v = apic_read(APIC_TMICT); | |
849d3569 | 854 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 855 | v = apic_read(APIC_TMCCT); |
849d3569 | 856 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 857 | v = apic_read(APIC_TDCR); |
849d3569 | 858 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
859 | |
860 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
861 | v = apic_read(APIC_EFEAT); | |
862 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 863 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 864 | v = apic_read(APIC_ECTRL); |
849d3569 | 865 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
866 | for (i = 0; i < maxlvt; i++) { |
867 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 868 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
869 | } |
870 | } | |
871 | pr_cont("\n"); | |
872 | } | |
873 | ||
874 | static void __init print_local_APICs(int maxcpu) | |
875 | { | |
876 | int cpu; | |
877 | ||
878 | if (!maxcpu) | |
879 | return; | |
880 | ||
881 | preempt_disable(); | |
882 | for_each_online_cpu(cpu) { | |
883 | if (cpu >= maxcpu) | |
884 | break; | |
885 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
886 | } | |
887 | preempt_enable(); | |
888 | } | |
889 | ||
890 | static void __init print_PIC(void) | |
891 | { | |
892 | unsigned int v; | |
893 | unsigned long flags; | |
894 | ||
895 | if (!nr_legacy_irqs()) | |
896 | return; | |
897 | ||
849d3569 | 898 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
899 | |
900 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
901 | ||
902 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 903 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
904 | |
905 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 906 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
907 | |
908 | outb(0x0b, 0xa0); | |
909 | outb(0x0b, 0x20); | |
910 | v = inb(0xa0) << 8 | inb(0x20); | |
911 | outb(0x0a, 0xa0); | |
912 | outb(0x0a, 0x20); | |
913 | ||
914 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
915 | ||
849d3569 | 916 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
917 | |
918 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 919 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
920 | } |
921 | ||
922 | static int show_lapic __initdata = 1; | |
923 | static __init int setup_show_lapic(char *arg) | |
924 | { | |
925 | int num = -1; | |
926 | ||
927 | if (strcmp(arg, "all") == 0) { | |
928 | show_lapic = CONFIG_NR_CPUS; | |
929 | } else { | |
930 | get_option(&arg, &num); | |
931 | if (num >= 0) | |
932 | show_lapic = num; | |
933 | } | |
934 | ||
935 | return 1; | |
936 | } | |
937 | __setup("show_lapic=", setup_show_lapic); | |
938 | ||
939 | static int __init print_ICs(void) | |
940 | { | |
941 | if (apic_verbosity == APIC_QUIET) | |
942 | return 0; | |
943 | ||
944 | print_PIC(); | |
945 | ||
946 | /* don't print out if apic is not there */ | |
947 | if (!cpu_has_apic && !apic_from_smp_config()) | |
948 | return 0; | |
949 | ||
950 | print_local_APICs(show_lapic); | |
951 | print_IO_APICs(); | |
952 | ||
953 | return 0; | |
954 | } | |
955 | ||
956 | late_initcall(print_ICs); |