Commit | Line | Data |
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12a67cf6 SS |
1 | #include <linux/threads.h> |
2 | #include <linux/cpumask.h> | |
3 | #include <linux/string.h> | |
4 | #include <linux/kernel.h> | |
5 | #include <linux/ctype.h> | |
6 | #include <linux/init.h> | |
1b9b89e7 | 7 | #include <linux/dmar.h> |
9d0fa6c5 | 8 | #include <linux/cpu.h> |
1b9b89e7 | 9 | |
12a67cf6 | 10 | #include <asm/smp.h> |
79deb8e5 | 11 | #include <asm/x2apic.h> |
12a67cf6 | 12 | |
2de1f33e | 13 | static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid); |
a39d1f3f | 14 | static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster); |
9d0fa6c5 | 15 | static DEFINE_PER_CPU(cpumask_var_t, ipi_mask); |
12a67cf6 | 16 | |
2caa3715 | 17 | static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 18 | { |
ef1f87aa | 19 | return x2apic_enabled(); |
1b9b89e7 YL |
20 | } |
21 | ||
a39d1f3f CG |
22 | static inline u32 x2apic_cluster(int cpu) |
23 | { | |
24 | return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16; | |
25 | } | |
26 | ||
a27d0b5e SS |
27 | static void |
28 | __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest) | |
12a67cf6 | 29 | { |
9d0fa6c5 CG |
30 | struct cpumask *cpus_in_cluster_ptr; |
31 | struct cpumask *ipi_mask_ptr; | |
32 | unsigned int cpu, this_cpu; | |
dac5f412 | 33 | unsigned long flags; |
9d0fa6c5 | 34 | u32 dest; |
12a67cf6 | 35 | |
ce4e240c SS |
36 | x2apic_wrmsr_fence(); |
37 | ||
12a67cf6 | 38 | local_irq_save(flags); |
a27d0b5e SS |
39 | |
40 | this_cpu = smp_processor_id(); | |
9d0fa6c5 CG |
41 | |
42 | /* | |
43 | * We are to modify mask, so we need an own copy | |
44 | * and be sure it's manipulated with irq off. | |
45 | */ | |
46 | ipi_mask_ptr = __raw_get_cpu_var(ipi_mask); | |
47 | cpumask_copy(ipi_mask_ptr, mask); | |
48 | ||
49 | /* | |
50 | * The idea is to send one IPI per cluster. | |
51 | */ | |
52 | for_each_cpu(cpu, ipi_mask_ptr) { | |
53 | unsigned long i; | |
54 | ||
55 | cpus_in_cluster_ptr = per_cpu(cpus_in_cluster, cpu); | |
56 | dest = 0; | |
57 | ||
58 | /* Collect cpus in cluster. */ | |
59 | for_each_cpu_and(i, ipi_mask_ptr, cpus_in_cluster_ptr) { | |
60 | if (apic_dest == APIC_DEST_ALLINC || i != this_cpu) | |
61 | dest |= per_cpu(x86_cpu_to_logical_apicid, i); | |
62 | } | |
63 | ||
64 | if (!dest) | |
a27d0b5e | 65 | continue; |
9d0fa6c5 CG |
66 | |
67 | __x2apic_send_IPI_dest(dest, vector, apic->dest_logical); | |
68 | /* | |
69 | * Cluster sibling cpus should be discared now so | |
70 | * we would not send IPI them second time. | |
71 | */ | |
72 | cpumask_andnot(ipi_mask_ptr, ipi_mask_ptr, cpus_in_cluster_ptr); | |
dac5f412 | 73 | } |
a27d0b5e | 74 | |
12a67cf6 SS |
75 | local_irq_restore(flags); |
76 | } | |
77 | ||
a27d0b5e SS |
78 | static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) |
79 | { | |
80 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC); | |
81 | } | |
82 | ||
dac5f412 | 83 | static void |
49d0c7a0 | 84 | x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
12a67cf6 | 85 | { |
a27d0b5e | 86 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); |
e7986739 | 87 | } |
12a67cf6 | 88 | |
e7986739 MT |
89 | static void x2apic_send_IPI_allbutself(int vector) |
90 | { | |
a27d0b5e | 91 | __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT); |
12a67cf6 SS |
92 | } |
93 | ||
94 | static void x2apic_send_IPI_all(int vector) | |
95 | { | |
a27d0b5e | 96 | __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC); |
12a67cf6 SS |
97 | } |
98 | ||
ff164324 | 99 | static int |
debccb3e | 100 | x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
101 | const struct cpumask *andmask, |
102 | unsigned int *apicid) | |
95d313cf | 103 | { |
0b8255e6 SS |
104 | u32 dest = 0; |
105 | u16 cluster; | |
106 | int i; | |
95d313cf | 107 | |
0b8255e6 SS |
108 | for_each_cpu_and(i, cpumask, andmask) { |
109 | if (!cpumask_test_cpu(i, cpu_online_mask)) | |
110 | continue; | |
111 | dest = per_cpu(x86_cpu_to_logical_apicid, i); | |
112 | cluster = x2apic_cluster(i); | |
113 | break; | |
debccb3e IM |
114 | } |
115 | ||
0b8255e6 | 116 | if (!dest) |
ff164324 | 117 | return -EINVAL; |
0b8255e6 SS |
118 | |
119 | for_each_cpu_and(i, cpumask, andmask) { | |
120 | if (!cpumask_test_cpu(i, cpu_online_mask)) | |
121 | continue; | |
122 | if (cluster != x2apic_cluster(i)) | |
123 | continue; | |
124 | dest |= per_cpu(x86_cpu_to_logical_apicid, i); | |
125 | } | |
126 | ||
ff164324 AG |
127 | *apicid = dest; |
128 | ||
129 | return 0; | |
95d313cf MT |
130 | } |
131 | ||
12a67cf6 | 132 | static void init_x2apic_ldr(void) |
a39d1f3f CG |
133 | { |
134 | unsigned int this_cpu = smp_processor_id(); | |
135 | unsigned int cpu; | |
136 | ||
137 | per_cpu(x86_cpu_to_logical_apicid, this_cpu) = apic_read(APIC_LDR); | |
138 | ||
139 | __cpu_set(this_cpu, per_cpu(cpus_in_cluster, this_cpu)); | |
140 | for_each_online_cpu(cpu) { | |
141 | if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu)) | |
142 | continue; | |
143 | __cpu_set(this_cpu, per_cpu(cpus_in_cluster, cpu)); | |
144 | __cpu_set(cpu, per_cpu(cpus_in_cluster, this_cpu)); | |
145 | } | |
146 | } | |
147 | ||
148 | /* | |
149 | * At CPU state changes, update the x2apic cluster sibling info. | |
150 | */ | |
151 | static int __cpuinit | |
152 | update_clusterinfo(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
153 | { | |
154 | unsigned int this_cpu = (unsigned long)hcpu; | |
155 | unsigned int cpu; | |
156 | int err = 0; | |
157 | ||
158 | switch (action) { | |
159 | case CPU_UP_PREPARE: | |
160 | if (!zalloc_cpumask_var(&per_cpu(cpus_in_cluster, this_cpu), | |
161 | GFP_KERNEL)) { | |
162 | err = -ENOMEM; | |
9d0fa6c5 CG |
163 | } else if (!zalloc_cpumask_var(&per_cpu(ipi_mask, this_cpu), |
164 | GFP_KERNEL)) { | |
165 | free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu)); | |
166 | err = -ENOMEM; | |
a39d1f3f CG |
167 | } |
168 | break; | |
169 | case CPU_UP_CANCELED: | |
170 | case CPU_UP_CANCELED_FROZEN: | |
171 | case CPU_DEAD: | |
172 | for_each_online_cpu(cpu) { | |
173 | if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu)) | |
174 | continue; | |
175 | __cpu_clear(this_cpu, per_cpu(cpus_in_cluster, cpu)); | |
176 | __cpu_clear(cpu, per_cpu(cpus_in_cluster, this_cpu)); | |
177 | } | |
178 | free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu)); | |
9d0fa6c5 | 179 | free_cpumask_var(per_cpu(ipi_mask, this_cpu)); |
a39d1f3f CG |
180 | break; |
181 | } | |
182 | ||
183 | return notifier_from_errno(err); | |
184 | } | |
185 | ||
186 | static struct notifier_block __refdata x2apic_cpu_notifier = { | |
187 | .notifier_call = update_clusterinfo, | |
188 | }; | |
189 | ||
190 | static int x2apic_init_cpu_notifier(void) | |
12a67cf6 SS |
191 | { |
192 | int cpu = smp_processor_id(); | |
193 | ||
a39d1f3f | 194 | zalloc_cpumask_var(&per_cpu(cpus_in_cluster, cpu), GFP_KERNEL); |
9d0fa6c5 | 195 | zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL); |
a39d1f3f | 196 | |
9d0fa6c5 | 197 | BUG_ON(!per_cpu(cpus_in_cluster, cpu) || !per_cpu(ipi_mask, cpu)); |
a39d1f3f CG |
198 | |
199 | __cpu_set(cpu, per_cpu(cpus_in_cluster, cpu)); | |
200 | register_hotcpu_notifier(&x2apic_cpu_notifier); | |
201 | return 1; | |
12a67cf6 SS |
202 | } |
203 | ||
9ebd680b SS |
204 | static int x2apic_cluster_probe(void) |
205 | { | |
a39d1f3f CG |
206 | if (x2apic_mode) |
207 | return x2apic_init_cpu_notifier(); | |
208 | else | |
209 | return 0; | |
9ebd680b SS |
210 | } |
211 | ||
d872818d SS |
212 | static const struct cpumask *x2apic_cluster_target_cpus(void) |
213 | { | |
214 | return cpu_all_mask; | |
215 | } | |
216 | ||
0b8255e6 SS |
217 | /* |
218 | * Each x2apic cluster is an allocation domain. | |
219 | */ | |
1ac322d0 SS |
220 | static void cluster_vector_allocation_domain(int cpu, struct cpumask *retmask, |
221 | const struct cpumask *mask) | |
0b8255e6 | 222 | { |
d872818d SS |
223 | /* |
224 | * To minimize vector pressure, default case of boot, device bringup | |
225 | * etc will use a single cpu for the interrupt destination. | |
226 | * | |
227 | * On explicit migration requests coming from irqbalance etc, | |
228 | * interrupts will be routed to the x2apic cluster (cluster-id | |
229 | * derived from the first cpu in the mask) members specified | |
230 | * in the mask. | |
231 | */ | |
232 | if (mask == x2apic_cluster_target_cpus()) | |
233 | cpumask_copy(retmask, cpumask_of(cpu)); | |
234 | else | |
235 | cpumask_and(retmask, mask, per_cpu(cpus_in_cluster, cpu)); | |
0b8255e6 SS |
236 | } |
237 | ||
1a8880a1 | 238 | static struct apic apic_x2apic_cluster = { |
504a3c3a IM |
239 | |
240 | .name = "cluster x2apic", | |
9ebd680b | 241 | .probe = x2apic_cluster_probe, |
504a3c3a | 242 | .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, |
b7157acf | 243 | .apic_id_valid = x2apic_apic_id_valid, |
504a3c3a IM |
244 | .apic_id_registered = x2apic_apic_id_registered, |
245 | ||
f8987a10 | 246 | .irq_delivery_mode = dest_LowestPrio, |
0b06e734 | 247 | .irq_dest_mode = 1, /* logical */ |
504a3c3a | 248 | |
d872818d | 249 | .target_cpus = x2apic_cluster_target_cpus, |
08125d3e | 250 | .disable_esr = 0, |
bdb1a9b6 | 251 | .dest_logical = APIC_DEST_LOGICAL, |
504a3c3a IM |
252 | .check_apicid_used = NULL, |
253 | .check_apicid_present = NULL, | |
254 | ||
0b8255e6 | 255 | .vector_allocation_domain = cluster_vector_allocation_domain, |
504a3c3a IM |
256 | .init_apic_ldr = init_x2apic_ldr, |
257 | ||
258 | .ioapic_phys_id_map = NULL, | |
259 | .setup_apic_routing = NULL, | |
260 | .multi_timer_check = NULL, | |
a21769a4 | 261 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
504a3c3a IM |
262 | .apicid_to_cpu_present = NULL, |
263 | .setup_portio_remap = NULL, | |
a27a6210 | 264 | .check_phys_apicid_present = default_check_phys_apicid_present, |
504a3c3a | 265 | .enable_apic_mode = NULL, |
79deb8e5 | 266 | .phys_pkg_id = x2apic_phys_pkg_id, |
504a3c3a IM |
267 | .mps_oem_check = NULL, |
268 | ||
79deb8e5 CG |
269 | .get_apic_id = x2apic_get_apic_id, |
270 | .set_apic_id = x2apic_set_apic_id, | |
504a3c3a IM |
271 | .apic_id_mask = 0xFFFFFFFFu, |
272 | ||
504a3c3a IM |
273 | .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and, |
274 | ||
275 | .send_IPI_mask = x2apic_send_IPI_mask, | |
276 | .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself, | |
277 | .send_IPI_allbutself = x2apic_send_IPI_allbutself, | |
278 | .send_IPI_all = x2apic_send_IPI_all, | |
279 | .send_IPI_self = x2apic_send_IPI_self, | |
280 | ||
abfa584c IM |
281 | .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, |
282 | .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, | |
504a3c3a IM |
283 | .wait_for_init_deassert = NULL, |
284 | .smp_callin_clear_local_apic = NULL, | |
504a3c3a | 285 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
286 | |
287 | .read = native_apic_msr_read, | |
288 | .write = native_apic_msr_write, | |
0ab711ae | 289 | .eoi_write = native_apic_msr_eoi_write, |
c1eeb2de YL |
290 | .icr_read = native_x2apic_icr_read, |
291 | .icr_write = native_x2apic_icr_write, | |
292 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
293 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
12a67cf6 | 294 | }; |
107e0e0c SS |
295 | |
296 | apic_driver(apic_x2apic_cluster); |