Commit | Line | Data |
---|---|---|
ac23d4ee JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV APIC functions (note: not an Intel compatible APIC) | |
7 | * | |
c8f730b1 | 8 | * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved. |
ac23d4ee | 9 | */ |
ac23d4ee | 10 | #include <linux/cpumask.h> |
0b1da1c8 IM |
11 | #include <linux/hardirq.h> |
12 | #include <linux/proc_fs.h> | |
13 | #include <linux/threads.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
ac23d4ee | 16 | #include <linux/string.h> |
ac23d4ee | 17 | #include <linux/ctype.h> |
ac23d4ee | 18 | #include <linux/sched.h> |
7f1baa06 | 19 | #include <linux/timer.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
0b1da1c8 IM |
21 | #include <linux/cpu.h> |
22 | #include <linux/init.h> | |
27229ca6 | 23 | #include <linux/io.h> |
841582ea | 24 | #include <linux/pci.h> |
78c06176 | 25 | #include <linux/kdebug.h> |
0b1da1c8 | 26 | |
ac23d4ee JS |
27 | #include <asm/uv/uv_mmrs.h> |
28 | #include <asm/uv/uv_hub.h> | |
0b1da1c8 IM |
29 | #include <asm/current.h> |
30 | #include <asm/pgtable.h> | |
7019cc2d | 31 | #include <asm/uv/bios.h> |
0b1da1c8 IM |
32 | #include <asm/uv/uv.h> |
33 | #include <asm/apic.h> | |
34 | #include <asm/ipi.h> | |
35 | #include <asm/smp.h> | |
fd12a0d6 | 36 | #include <asm/x86_init.h> |
ac23d4ee | 37 | |
510b3725 YL |
38 | DEFINE_PER_CPU(int, x2apic_extra_bits); |
39 | ||
841582ea MT |
40 | #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args) |
41 | ||
1b9b89e7 | 42 | static enum uv_system_type uv_system_type; |
fd12a0d6 | 43 | static u64 gru_start_paddr, gru_end_paddr; |
c8f730b1 | 44 | static union uvh_apicid uvh_apicid; |
7a1110e8 JS |
45 | int uv_min_hub_revision_id; |
46 | EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); | |
78c06176 | 47 | static DEFINE_SPINLOCK(uv_nmi_lock); |
fd12a0d6 | 48 | |
eb41c8be | 49 | static inline bool is_GRU_range(u64 start, u64 end) |
fd12a0d6 | 50 | { |
ccef0864 | 51 | return start >= gru_start_paddr && end <= gru_end_paddr; |
fd12a0d6 JS |
52 | } |
53 | ||
eb41c8be | 54 | static bool uv_is_untracked_pat_range(u64 start, u64 end) |
fd12a0d6 JS |
55 | { |
56 | return is_ISA_range(start, end) || is_GRU_range(start, end); | |
57 | } | |
1b9b89e7 | 58 | |
27229ca6 JS |
59 | static int early_get_nodeid(void) |
60 | { | |
61 | union uvh_node_id_u node_id; | |
62 | unsigned long *mmr; | |
63 | ||
64 | mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr)); | |
65 | node_id.v = *mmr; | |
66 | early_iounmap(mmr, sizeof(*mmr)); | |
7a1110e8 JS |
67 | |
68 | /* Currently, all blades have same revision number */ | |
69 | uv_min_hub_revision_id = node_id.s.revision; | |
70 | ||
27229ca6 JS |
71 | return node_id.s.node_id; |
72 | } | |
73 | ||
0520bd84 | 74 | static void __init early_get_apic_pnode_shift(void) |
c8f730b1 RA |
75 | { |
76 | unsigned long *mmr; | |
77 | ||
78 | mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_APICID, sizeof(*mmr)); | |
79 | uvh_apicid.v = *mmr; | |
80 | early_iounmap(mmr, sizeof(*mmr)); | |
81 | if (!uvh_apicid.v) | |
82 | /* | |
83 | * Old bios, use default value | |
84 | */ | |
85 | uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT; | |
c8f730b1 RA |
86 | } |
87 | ||
52459ab9 | 88 | static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 89 | { |
1d2c867c RA |
90 | int nodeid; |
91 | ||
1b9b89e7 | 92 | if (!strcmp(oem_id, "SGI")) { |
1d2c867c | 93 | nodeid = early_get_nodeid(); |
0520bd84 | 94 | early_get_apic_pnode_shift(); |
fd12a0d6 | 95 | x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; |
78c06176 | 96 | x86_platform.nmi_init = uv_nmi_init; |
1b9b89e7 YL |
97 | if (!strcmp(oem_table_id, "UVL")) |
98 | uv_system_type = UV_LEGACY_APIC; | |
99 | else if (!strcmp(oem_table_id, "UVX")) | |
100 | uv_system_type = UV_X2APIC; | |
101 | else if (!strcmp(oem_table_id, "UVH")) { | |
27229ca6 | 102 | __get_cpu_var(x2apic_extra_bits) = |
0520bd84 | 103 | nodeid << (uvh_apicid.s.pnode_shift - 1); |
1b9b89e7 YL |
104 | uv_system_type = UV_NON_UNIQUE_APIC; |
105 | return 1; | |
106 | } | |
107 | } | |
108 | return 0; | |
109 | } | |
110 | ||
111 | enum uv_system_type get_uv_system_type(void) | |
112 | { | |
113 | return uv_system_type; | |
114 | } | |
115 | ||
116 | int is_uv_system(void) | |
117 | { | |
118 | return uv_system_type != UV_NONE; | |
119 | } | |
8067794b | 120 | EXPORT_SYMBOL_GPL(is_uv_system); |
1b9b89e7 | 121 | |
ac23d4ee JS |
122 | DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
123 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); | |
124 | ||
125 | struct uv_blade_info *uv_blade_info; | |
126 | EXPORT_SYMBOL_GPL(uv_blade_info); | |
127 | ||
128 | short *uv_node_to_blade; | |
129 | EXPORT_SYMBOL_GPL(uv_node_to_blade); | |
130 | ||
131 | short *uv_cpu_to_blade; | |
132 | EXPORT_SYMBOL_GPL(uv_cpu_to_blade); | |
133 | ||
134 | short uv_possible_blades; | |
135 | EXPORT_SYMBOL_GPL(uv_possible_blades); | |
136 | ||
7019cc2d RA |
137 | unsigned long sn_rtc_cycles_per_second; |
138 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | |
139 | ||
bcda016e | 140 | static const struct cpumask *uv_target_cpus(void) |
ac23d4ee | 141 | { |
8447b360 | 142 | return cpu_online_mask; |
ac23d4ee JS |
143 | } |
144 | ||
bcda016e | 145 | static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask) |
ac23d4ee | 146 | { |
bcda016e MT |
147 | cpumask_clear(retmask); |
148 | cpumask_set_cpu(cpu, retmask); | |
ac23d4ee JS |
149 | } |
150 | ||
667c5296 | 151 | static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) |
ac23d4ee | 152 | { |
0b1da1c8 | 153 | #ifdef CONFIG_SMP |
ac23d4ee | 154 | unsigned long val; |
9f5314fb | 155 | int pnode; |
ac23d4ee | 156 | |
9f5314fb | 157 | pnode = uv_apicid_to_pnode(phys_apicid); |
ac23d4ee JS |
158 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
159 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 160 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 161 | APIC_DM_INIT; |
9f5314fb | 162 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
34d05591 JS |
163 | mdelay(10); |
164 | ||
165 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | | |
166 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 167 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 168 | APIC_DM_STARTUP; |
9f5314fb | 169 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
2b6163bf YL |
170 | |
171 | atomic_set(&init_deasserted, 1); | |
0b1da1c8 | 172 | #endif |
ac23d4ee JS |
173 | return 0; |
174 | } | |
175 | ||
176 | static void uv_send_IPI_one(int cpu, int vector) | |
177 | { | |
66666e50 | 178 | unsigned long apicid; |
9f5314fb | 179 | int pnode; |
ac23d4ee | 180 | |
1e0b5d00 | 181 | apicid = per_cpu(x86_cpu_to_apicid, cpu); |
9f5314fb | 182 | pnode = uv_apicid_to_pnode(apicid); |
66666e50 | 183 | uv_hub_send_ipi(pnode, apicid, vector); |
ac23d4ee JS |
184 | } |
185 | ||
bcda016e | 186 | static void uv_send_IPI_mask(const struct cpumask *mask, int vector) |
ac23d4ee JS |
187 | { |
188 | unsigned int cpu; | |
189 | ||
bcda016e | 190 | for_each_cpu(cpu, mask) |
e7986739 MT |
191 | uv_send_IPI_one(cpu, vector); |
192 | } | |
193 | ||
bcda016e | 194 | static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
e7986739 | 195 | { |
e7986739 | 196 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 197 | unsigned int cpu; |
e7986739 | 198 | |
dac5f412 | 199 | for_each_cpu(cpu, mask) { |
e7986739 | 200 | if (cpu != this_cpu) |
ac23d4ee | 201 | uv_send_IPI_one(cpu, vector); |
dac5f412 | 202 | } |
ac23d4ee JS |
203 | } |
204 | ||
205 | static void uv_send_IPI_allbutself(int vector) | |
206 | { | |
e7986739 | 207 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 208 | unsigned int cpu; |
ac23d4ee | 209 | |
dac5f412 | 210 | for_each_online_cpu(cpu) { |
e7986739 MT |
211 | if (cpu != this_cpu) |
212 | uv_send_IPI_one(cpu, vector); | |
dac5f412 | 213 | } |
ac23d4ee JS |
214 | } |
215 | ||
216 | static void uv_send_IPI_all(int vector) | |
217 | { | |
bcda016e | 218 | uv_send_IPI_mask(cpu_online_mask, vector); |
ac23d4ee JS |
219 | } |
220 | ||
221 | static int uv_apic_id_registered(void) | |
222 | { | |
223 | return 1; | |
224 | } | |
225 | ||
277d1f58 | 226 | static void uv_init_apic_ldr(void) |
5c520a67 SS |
227 | { |
228 | } | |
229 | ||
bcda016e | 230 | static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask) |
ac23d4ee | 231 | { |
ac23d4ee JS |
232 | /* |
233 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
234 | * May as well be the first. | |
235 | */ | |
debccb3e IM |
236 | int cpu = cpumask_first(cpumask); |
237 | ||
247bc6ca | 238 | if ((unsigned)cpu < nr_cpu_ids) |
ac23d4ee JS |
239 | return per_cpu(x86_cpu_to_apicid, cpu); |
240 | else | |
241 | return BAD_APICID; | |
242 | } | |
243 | ||
debccb3e IM |
244 | static unsigned int |
245 | uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | |
246 | const struct cpumask *andmask) | |
95d313cf MT |
247 | { |
248 | int cpu; | |
249 | ||
250 | /* | |
251 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
252 | * May as well be the first. | |
253 | */ | |
debccb3e | 254 | for_each_cpu_and(cpu, cpumask, andmask) { |
a775a38b MT |
255 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
256 | break; | |
debccb3e | 257 | } |
18374d89 | 258 | return per_cpu(x86_cpu_to_apicid, cpu); |
95d313cf MT |
259 | } |
260 | ||
ca6c8ed4 | 261 | static unsigned int x2apic_get_apic_id(unsigned long x) |
0c81c746 SS |
262 | { |
263 | unsigned int id; | |
264 | ||
265 | WARN_ON(preemptible() && num_online_cpus() > 1); | |
f910a9dc | 266 | id = x | __get_cpu_var(x2apic_extra_bits); |
0c81c746 SS |
267 | |
268 | return id; | |
269 | } | |
270 | ||
1b9b89e7 | 271 | static unsigned long set_apic_id(unsigned int id) |
f910a9dc YL |
272 | { |
273 | unsigned long x; | |
274 | ||
275 | /* maskout x2apic_extra_bits ? */ | |
276 | x = id; | |
277 | return x; | |
278 | } | |
279 | ||
280 | static unsigned int uv_read_apic_id(void) | |
281 | { | |
282 | ||
ca6c8ed4 | 283 | return x2apic_get_apic_id(apic_read(APIC_ID)); |
f910a9dc YL |
284 | } |
285 | ||
d4c9a9f3 | 286 | static int uv_phys_pkg_id(int initial_apicid, int index_msb) |
ac23d4ee | 287 | { |
0c81c746 | 288 | return uv_read_apic_id() >> index_msb; |
ac23d4ee JS |
289 | } |
290 | ||
ac23d4ee JS |
291 | static void uv_send_IPI_self(int vector) |
292 | { | |
293 | apic_write(APIC_SELF_IPI, vector); | |
294 | } | |
ac23d4ee | 295 | |
52459ab9 | 296 | struct apic __refdata apic_x2apic_uv_x = { |
c7967329 IM |
297 | |
298 | .name = "UV large system", | |
299 | .probe = NULL, | |
300 | .acpi_madt_oem_check = uv_acpi_madt_oem_check, | |
301 | .apic_id_registered = uv_apic_id_registered, | |
302 | ||
f8987a10 | 303 | .irq_delivery_mode = dest_Fixed, |
c5997fa8 | 304 | .irq_dest_mode = 0, /* physical */ |
c7967329 IM |
305 | |
306 | .target_cpus = uv_target_cpus, | |
08125d3e | 307 | .disable_esr = 0, |
bdb1a9b6 | 308 | .dest_logical = APIC_DEST_LOGICAL, |
c7967329 IM |
309 | .check_apicid_used = NULL, |
310 | .check_apicid_present = NULL, | |
311 | ||
c7967329 IM |
312 | .vector_allocation_domain = uv_vector_allocation_domain, |
313 | .init_apic_ldr = uv_init_apic_ldr, | |
314 | ||
315 | .ioapic_phys_id_map = NULL, | |
316 | .setup_apic_routing = NULL, | |
317 | .multi_timer_check = NULL, | |
318 | .apicid_to_node = NULL, | |
319 | .cpu_to_logical_apicid = NULL, | |
a21769a4 | 320 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
c7967329 IM |
321 | .apicid_to_cpu_present = NULL, |
322 | .setup_portio_remap = NULL, | |
a27a6210 | 323 | .check_phys_apicid_present = default_check_phys_apicid_present, |
c7967329 | 324 | .enable_apic_mode = NULL, |
d4c9a9f3 | 325 | .phys_pkg_id = uv_phys_pkg_id, |
c7967329 IM |
326 | .mps_oem_check = NULL, |
327 | ||
ca6c8ed4 | 328 | .get_apic_id = x2apic_get_apic_id, |
c7967329 IM |
329 | .set_apic_id = set_apic_id, |
330 | .apic_id_mask = 0xFFFFFFFFu, | |
331 | ||
332 | .cpu_mask_to_apicid = uv_cpu_mask_to_apicid, | |
333 | .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, | |
334 | ||
335 | .send_IPI_mask = uv_send_IPI_mask, | |
336 | .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, | |
337 | .send_IPI_allbutself = uv_send_IPI_allbutself, | |
338 | .send_IPI_all = uv_send_IPI_all, | |
339 | .send_IPI_self = uv_send_IPI_self, | |
340 | ||
1f5bcabf | 341 | .wakeup_secondary_cpu = uv_wakeup_secondary, |
abfa584c IM |
342 | .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, |
343 | .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, | |
c7967329 IM |
344 | .wait_for_init_deassert = NULL, |
345 | .smp_callin_clear_local_apic = NULL, | |
c7967329 | 346 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
347 | |
348 | .read = native_apic_msr_read, | |
349 | .write = native_apic_msr_write, | |
350 | .icr_read = native_x2apic_icr_read, | |
351 | .icr_write = native_x2apic_icr_write, | |
352 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
353 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
ac23d4ee JS |
354 | }; |
355 | ||
9f5314fb | 356 | static __cpuinit void set_x2apic_extra_bits(int pnode) |
ac23d4ee | 357 | { |
9f5314fb | 358 | __get_cpu_var(x2apic_extra_bits) = (pnode << 6); |
ac23d4ee JS |
359 | } |
360 | ||
361 | /* | |
362 | * Called on boot cpu. | |
363 | */ | |
9f5314fb JS |
364 | static __init int boot_pnode_to_blade(int pnode) |
365 | { | |
366 | int blade; | |
367 | ||
368 | for (blade = 0; blade < uv_num_possible_blades(); blade++) | |
369 | if (pnode == uv_blade_info[blade].pnode) | |
370 | return blade; | |
371 | BUG(); | |
372 | } | |
373 | ||
374 | struct redir_addr { | |
375 | unsigned long redirect; | |
376 | unsigned long alias; | |
377 | }; | |
378 | ||
379 | #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT | |
380 | ||
381 | static __initdata struct redir_addr redir_addrs[] = { | |
62b0cfc2 JS |
382 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR}, |
383 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR}, | |
384 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR}, | |
9f5314fb JS |
385 | }; |
386 | ||
387 | static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) | |
388 | { | |
62b0cfc2 | 389 | union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; |
9f5314fb JS |
390 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; |
391 | int i; | |
392 | ||
393 | for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) { | |
394 | alias.v = uv_read_local_mmr(redir_addrs[i].alias); | |
036ed8ba | 395 | if (alias.s.enable && alias.s.base == 0) { |
9f5314fb JS |
396 | *size = (1UL << alias.s.m_alias); |
397 | redirect.v = uv_read_local_mmr(redir_addrs[i].redirect); | |
398 | *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; | |
399 | return; | |
400 | } | |
401 | } | |
036ed8ba | 402 | *base = *size = 0; |
9f5314fb JS |
403 | } |
404 | ||
83f5d894 JS |
405 | enum map_type {map_wb, map_uc}; |
406 | ||
fcfbb2b5 MT |
407 | static __init void map_high(char *id, unsigned long base, int pshift, |
408 | int bshift, int max_pnode, enum map_type map_type) | |
83f5d894 JS |
409 | { |
410 | unsigned long bytes, paddr; | |
411 | ||
fcfbb2b5 MT |
412 | paddr = base << pshift; |
413 | bytes = (1UL << bshift) * (max_pnode + 1); | |
83f5d894 | 414 | printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, |
0b1da1c8 | 415 | paddr + bytes); |
83f5d894 JS |
416 | if (map_type == map_uc) |
417 | init_extra_mapping_uc(paddr, bytes); | |
418 | else | |
419 | init_extra_mapping_wb(paddr, bytes); | |
420 | ||
421 | } | |
422 | static __init void map_gru_high(int max_pnode) | |
423 | { | |
424 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
425 | int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
426 | ||
427 | gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); | |
fd12a0d6 | 428 | if (gru.s.enable) { |
fcfbb2b5 | 429 | map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb); |
fd12a0d6 JS |
430 | gru_start_paddr = ((u64)gru.s.base << shift); |
431 | gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); | |
432 | ||
433 | } | |
83f5d894 JS |
434 | } |
435 | ||
daf7b9c9 JS |
436 | static __init void map_mmr_high(int max_pnode) |
437 | { | |
438 | union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; | |
439 | int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
440 | ||
441 | mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); | |
442 | if (mmr.s.enable) | |
fcfbb2b5 | 443 | map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); |
daf7b9c9 JS |
444 | } |
445 | ||
83f5d894 JS |
446 | static __init void map_mmioh_high(int max_pnode) |
447 | { | |
448 | union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; | |
449 | int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
450 | ||
451 | mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); | |
452 | if (mmioh.s.enable) | |
fcfbb2b5 MT |
453 | map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io, |
454 | max_pnode, map_uc); | |
83f5d894 JS |
455 | } |
456 | ||
918bc960 JS |
457 | static __init void map_low_mmrs(void) |
458 | { | |
459 | init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); | |
460 | init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); | |
461 | } | |
462 | ||
7019cc2d RA |
463 | static __init void uv_rtc_init(void) |
464 | { | |
922402f1 RA |
465 | long status; |
466 | u64 ticks_per_sec; | |
7019cc2d | 467 | |
922402f1 RA |
468 | status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, |
469 | &ticks_per_sec); | |
470 | if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { | |
7019cc2d RA |
471 | printk(KERN_WARNING |
472 | "unable to determine platform RTC clock frequency, " | |
473 | "guessing.\n"); | |
474 | /* BIOS gives wrong value for clock freq. so guess */ | |
475 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; | |
476 | } else | |
477 | sn_rtc_cycles_per_second = ticks_per_sec; | |
478 | } | |
479 | ||
7f1baa06 MT |
480 | /* |
481 | * percpu heartbeat timer | |
482 | */ | |
483 | static void uv_heartbeat(unsigned long ignored) | |
484 | { | |
485 | struct timer_list *timer = &uv_hub_info->scir.timer; | |
486 | unsigned char bits = uv_hub_info->scir.state; | |
487 | ||
488 | /* flip heartbeat bit */ | |
489 | bits ^= SCIR_CPU_HEARTBEAT; | |
490 | ||
69a72a0e MT |
491 | /* is this cpu idle? */ |
492 | if (idle_cpu(raw_smp_processor_id())) | |
7f1baa06 MT |
493 | bits &= ~SCIR_CPU_ACTIVITY; |
494 | else | |
495 | bits |= SCIR_CPU_ACTIVITY; | |
496 | ||
497 | /* update system controller interface reg */ | |
498 | uv_set_scir_bits(bits); | |
499 | ||
500 | /* enable next timer period */ | |
5c333864 | 501 | mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL); |
7f1baa06 MT |
502 | } |
503 | ||
504 | static void __cpuinit uv_heartbeat_enable(int cpu) | |
505 | { | |
99659a92 | 506 | while (!uv_cpu_hub_info(cpu)->scir.enabled) { |
7f1baa06 MT |
507 | struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; |
508 | ||
509 | uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); | |
510 | setup_timer(timer, uv_heartbeat, cpu); | |
511 | timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; | |
512 | add_timer_on(timer, cpu); | |
513 | uv_cpu_hub_info(cpu)->scir.enabled = 1; | |
7f1baa06 | 514 | |
99659a92 RK |
515 | /* also ensure that boot cpu is enabled */ |
516 | cpu = 0; | |
517 | } | |
7f1baa06 MT |
518 | } |
519 | ||
77be80e4 | 520 | #ifdef CONFIG_HOTPLUG_CPU |
7f1baa06 MT |
521 | static void __cpuinit uv_heartbeat_disable(int cpu) |
522 | { | |
523 | if (uv_cpu_hub_info(cpu)->scir.enabled) { | |
524 | uv_cpu_hub_info(cpu)->scir.enabled = 0; | |
525 | del_timer(&uv_cpu_hub_info(cpu)->scir.timer); | |
526 | } | |
527 | uv_set_cpu_scir_bits(cpu, 0xff); | |
528 | } | |
529 | ||
7f1baa06 MT |
530 | /* |
531 | * cpu hotplug notifier | |
532 | */ | |
533 | static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self, | |
534 | unsigned long action, void *hcpu) | |
535 | { | |
536 | long cpu = (long)hcpu; | |
537 | ||
538 | switch (action) { | |
539 | case CPU_ONLINE: | |
540 | uv_heartbeat_enable(cpu); | |
541 | break; | |
542 | case CPU_DOWN_PREPARE: | |
543 | uv_heartbeat_disable(cpu); | |
544 | break; | |
545 | default: | |
546 | break; | |
547 | } | |
548 | return NOTIFY_OK; | |
549 | } | |
550 | ||
551 | static __init void uv_scir_register_cpu_notifier(void) | |
552 | { | |
553 | hotcpu_notifier(uv_scir_cpu_notify, 0); | |
554 | } | |
555 | ||
556 | #else /* !CONFIG_HOTPLUG_CPU */ | |
557 | ||
558 | static __init void uv_scir_register_cpu_notifier(void) | |
559 | { | |
560 | } | |
561 | ||
562 | static __init int uv_init_heartbeat(void) | |
563 | { | |
564 | int cpu; | |
565 | ||
566 | if (is_uv_system()) | |
567 | for_each_online_cpu(cpu) | |
568 | uv_heartbeat_enable(cpu); | |
569 | return 0; | |
570 | } | |
571 | ||
572 | late_initcall(uv_init_heartbeat); | |
573 | ||
574 | #endif /* !CONFIG_HOTPLUG_CPU */ | |
575 | ||
841582ea MT |
576 | /* Direct Legacy VGA I/O traffic to designated IOH */ |
577 | int uv_set_vga_state(struct pci_dev *pdev, bool decode, | |
578 | unsigned int command_bits, bool change_bridge) | |
579 | { | |
580 | int domain, bus, rc; | |
581 | ||
582 | PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n", | |
583 | pdev->devfn, decode, command_bits, change_bridge); | |
584 | ||
585 | if (!change_bridge) | |
586 | return 0; | |
587 | ||
588 | if ((command_bits & PCI_COMMAND_IO) == 0) | |
589 | return 0; | |
590 | ||
591 | domain = pci_domain_nr(pdev->bus); | |
592 | bus = pdev->bus->number; | |
593 | ||
594 | rc = uv_bios_set_legacy_vga_target(decode, domain, bus); | |
595 | PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc); | |
596 | ||
597 | return rc; | |
598 | } | |
599 | ||
8da077d6 JS |
600 | /* |
601 | * Called on each cpu to initialize the per_cpu UV data area. | |
0b1da1c8 | 602 | * FIXME: hotplug not supported yet |
8da077d6 JS |
603 | */ |
604 | void __cpuinit uv_cpu_init(void) | |
605 | { | |
606 | /* CPU 0 initilization will be done via uv_system_init. */ | |
607 | if (!uv_blade_info) | |
608 | return; | |
609 | ||
610 | uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; | |
611 | ||
612 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) | |
613 | set_x2apic_extra_bits(uv_hub_info->pnode); | |
614 | } | |
615 | ||
78c06176 RA |
616 | /* |
617 | * When NMI is received, print a stack trace. | |
618 | */ | |
619 | int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data) | |
620 | { | |
621 | if (reason != DIE_NMI_IPI) | |
622 | return NOTIFY_OK; | |
5edd19af CW |
623 | |
624 | if (in_crash_kexec) | |
625 | /* do nothing if entering the crash kernel */ | |
626 | return NOTIFY_OK; | |
78c06176 RA |
627 | /* |
628 | * Use a lock so only one cpu prints at a time | |
629 | * to prevent intermixed output. | |
630 | */ | |
631 | spin_lock(&uv_nmi_lock); | |
632 | pr_info("NMI stack dump cpu %u:\n", smp_processor_id()); | |
633 | dump_stack(); | |
634 | spin_unlock(&uv_nmi_lock); | |
635 | ||
636 | return NOTIFY_STOP; | |
637 | } | |
638 | ||
639 | static struct notifier_block uv_dump_stack_nmi_nb = { | |
640 | .notifier_call = uv_handle_nmi | |
641 | }; | |
642 | ||
643 | void uv_register_nmi_notifier(void) | |
644 | { | |
645 | if (register_die_notifier(&uv_dump_stack_nmi_nb)) | |
646 | printk(KERN_WARNING "UV NMI handler failed to register\n"); | |
647 | } | |
648 | ||
649 | void uv_nmi_init(void) | |
650 | { | |
651 | unsigned int value; | |
652 | ||
653 | /* | |
654 | * Unmask NMI on all cpus | |
655 | */ | |
656 | value = apic_read(APIC_LVT1) | APIC_DM_NMI; | |
657 | value &= ~APIC_LVT_MASKED; | |
658 | apic_write(APIC_LVT1, value); | |
659 | } | |
c4bd1fda MS |
660 | |
661 | void __init uv_system_init(void) | |
ac23d4ee | 662 | { |
62b0cfc2 | 663 | union uvh_rh_gam_config_mmr_u m_n_config; |
9f5314fb JS |
664 | union uvh_node_id_u node_id; |
665 | unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size; | |
666 | int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val; | |
c4ed3f04 | 667 | int gnode_extra, max_pnode = 0; |
6a891a24 JS |
668 | unsigned long mmr_base, present, paddr; |
669 | unsigned short pnode_mask; | |
ac23d4ee | 670 | |
918bc960 JS |
671 | map_low_mmrs(); |
672 | ||
62b0cfc2 | 673 | m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR ); |
9f5314fb JS |
674 | m_val = m_n_config.s.m_skt; |
675 | n_val = m_n_config.s.n_skt; | |
ac23d4ee JS |
676 | mmr_base = |
677 | uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & | |
678 | ~UV_MMR_ENABLE; | |
c4ed3f04 JS |
679 | pnode_mask = (1 << n_val) - 1; |
680 | node_id.v = uv_read_local_mmr(UVH_NODE_ID); | |
681 | gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1; | |
682 | gnode_upper = ((unsigned long)gnode_extra << m_val); | |
683 | printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n", | |
684 | n_val, m_val, gnode_upper, gnode_extra); | |
685 | ||
ac23d4ee JS |
686 | printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base); |
687 | ||
9f5314fb JS |
688 | for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) |
689 | uv_possible_blades += | |
690 | hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8)); | |
ac23d4ee JS |
691 | printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades()); |
692 | ||
693 | bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); | |
ef020ab0 | 694 | uv_blade_info = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 695 | BUG_ON(!uv_blade_info); |
6c7184b7 JS |
696 | for (blade = 0; blade < uv_num_possible_blades(); blade++) |
697 | uv_blade_info[blade].memory_nid = -1; | |
ac23d4ee | 698 | |
9f5314fb JS |
699 | get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); |
700 | ||
ac23d4ee | 701 | bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); |
ef020ab0 | 702 | uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 703 | BUG_ON(!uv_node_to_blade); |
ac23d4ee JS |
704 | memset(uv_node_to_blade, 255, bytes); |
705 | ||
706 | bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); | |
ef020ab0 | 707 | uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 708 | BUG_ON(!uv_cpu_to_blade); |
ac23d4ee JS |
709 | memset(uv_cpu_to_blade, 255, bytes); |
710 | ||
9f5314fb JS |
711 | blade = 0; |
712 | for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { | |
713 | present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); | |
714 | for (j = 0; j < 64; j++) { | |
715 | if (!test_bit(j, &present)) | |
716 | continue; | |
36ac4b98 JS |
717 | pnode = (i * 64 + j); |
718 | uv_blade_info[blade].pnode = pnode; | |
9f5314fb | 719 | uv_blade_info[blade].nr_possible_cpus = 0; |
ac23d4ee | 720 | uv_blade_info[blade].nr_online_cpus = 0; |
36ac4b98 | 721 | max_pnode = max(pnode, max_pnode); |
9f5314fb | 722 | blade++; |
ac23d4ee | 723 | } |
9f5314fb | 724 | } |
ac23d4ee | 725 | |
7f594232 | 726 | uv_bios_init(); |
b76365a1 RA |
727 | uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, |
728 | &sn_region_size, &system_serial_number); | |
7019cc2d RA |
729 | uv_rtc_init(); |
730 | ||
9f5314fb | 731 | for_each_present_cpu(cpu) { |
39d30770 MT |
732 | int apicid = per_cpu(x86_cpu_to_apicid, cpu); |
733 | ||
9f5314fb | 734 | nid = cpu_to_node(cpu); |
c8f730b1 RA |
735 | /* |
736 | * apic_pnode_shift must be set before calling uv_apicid_to_pnode(); | |
737 | */ | |
738 | uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift; | |
39d30770 | 739 | pnode = uv_apicid_to_pnode(apicid); |
9f5314fb JS |
740 | blade = boot_pnode_to_blade(pnode); |
741 | lcpu = uv_blade_info[blade].nr_possible_cpus; | |
742 | uv_blade_info[blade].nr_possible_cpus++; | |
743 | ||
6c7184b7 JS |
744 | /* Any node on the blade, else will contain -1. */ |
745 | uv_blade_info[blade].memory_nid = nid; | |
746 | ||
9f5314fb | 747 | uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; |
189f67c4 | 748 | uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size; |
9f5314fb | 749 | uv_cpu_hub_info(cpu)->m_val = m_val; |
036ed8ba | 750 | uv_cpu_hub_info(cpu)->n_val = n_val; |
ac23d4ee JS |
751 | uv_cpu_hub_info(cpu)->numa_blade_id = blade; |
752 | uv_cpu_hub_info(cpu)->blade_processor_id = lcpu; | |
9f5314fb | 753 | uv_cpu_hub_info(cpu)->pnode = pnode; |
6a891a24 | 754 | uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask; |
036ed8ba | 755 | uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1; |
9f5314fb | 756 | uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper; |
c4ed3f04 | 757 | uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra; |
ac23d4ee | 758 | uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; |
b0f20989 | 759 | uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id; |
39d30770 | 760 | uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid); |
ac23d4ee JS |
761 | uv_node_to_blade[nid] = blade; |
762 | uv_cpu_to_blade[cpu] = blade; | |
ac23d4ee | 763 | } |
83f5d894 | 764 | |
6a891a24 JS |
765 | /* Add blade/pnode info for nodes without cpus */ |
766 | for_each_online_node(nid) { | |
767 | if (uv_node_to_blade[nid] >= 0) | |
768 | continue; | |
769 | paddr = node_start_pfn(nid) << PAGE_SHIFT; | |
fc61e663 | 770 | paddr = uv_soc_phys_ram_to_gpa(paddr); |
6a891a24 JS |
771 | pnode = (paddr >> m_val) & pnode_mask; |
772 | blade = boot_pnode_to_blade(pnode); | |
773 | uv_node_to_blade[nid] = blade; | |
774 | } | |
775 | ||
83f5d894 | 776 | map_gru_high(max_pnode); |
daf7b9c9 | 777 | map_mmr_high(max_pnode); |
83f5d894 | 778 | map_mmioh_high(max_pnode); |
ac23d4ee | 779 | |
8da077d6 | 780 | uv_cpu_init(); |
7f1baa06 | 781 | uv_scir_register_cpu_notifier(); |
78c06176 | 782 | uv_register_nmi_notifier(); |
a3d732f9 | 783 | proc_mkdir("sgi_uv", NULL); |
841582ea MT |
784 | |
785 | /* register Legacy VGA I/O redirection handler */ | |
786 | pci_register_set_vga_state(uv_set_vga_state); | |
ac23d4ee | 787 | } |