Commit | Line | Data |
---|---|---|
ac23d4ee JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV APIC functions (note: not an Intel compatible APIC) | |
7 | * | |
5f40f7d9 | 8 | * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. |
ac23d4ee | 9 | */ |
ac23d4ee | 10 | #include <linux/cpumask.h> |
0b1da1c8 IM |
11 | #include <linux/hardirq.h> |
12 | #include <linux/proc_fs.h> | |
13 | #include <linux/threads.h> | |
14 | #include <linux/kernel.h> | |
186f4360 | 15 | #include <linux/export.h> |
ac23d4ee | 16 | #include <linux/string.h> |
ac23d4ee | 17 | #include <linux/ctype.h> |
ac23d4ee | 18 | #include <linux/sched.h> |
7f1baa06 | 19 | #include <linux/timer.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
0b1da1c8 IM |
21 | #include <linux/cpu.h> |
22 | #include <linux/init.h> | |
27229ca6 | 23 | #include <linux/io.h> |
841582ea | 24 | #include <linux/pci.h> |
78c06176 | 25 | #include <linux/kdebug.h> |
ca444564 | 26 | #include <linux/delay.h> |
818987e9 | 27 | #include <linux/crash_dump.h> |
1b3a5d02 | 28 | #include <linux/reboot.h> |
0b1da1c8 | 29 | |
ac23d4ee JS |
30 | #include <asm/uv/uv_mmrs.h> |
31 | #include <asm/uv/uv_hub.h> | |
0b1da1c8 IM |
32 | #include <asm/current.h> |
33 | #include <asm/pgtable.h> | |
7019cc2d | 34 | #include <asm/uv/bios.h> |
0b1da1c8 IM |
35 | #include <asm/uv/uv.h> |
36 | #include <asm/apic.h> | |
37 | #include <asm/ipi.h> | |
38 | #include <asm/smp.h> | |
fd12a0d6 | 39 | #include <asm/x86_init.h> |
1d44e828 JS |
40 | #include <asm/nmi.h> |
41 | ||
510b3725 YL |
42 | DEFINE_PER_CPU(int, x2apic_extra_bits); |
43 | ||
841582ea MT |
44 | #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args) |
45 | ||
1b9b89e7 | 46 | static enum uv_system_type uv_system_type; |
fd12a0d6 | 47 | static u64 gru_start_paddr, gru_end_paddr; |
879d5ad0 DS |
48 | static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr; |
49 | static u64 gru_dist_lmask, gru_dist_umask; | |
c8f730b1 | 50 | static union uvh_apicid uvh_apicid; |
405422d8 MT |
51 | |
52 | /* info derived from CPUID */ | |
53 | static struct { | |
54 | unsigned int apicid_shift; | |
55 | unsigned int apicid_mask; | |
56 | unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */ | |
57 | unsigned int pnode_mask; | |
58 | unsigned int gpa_shift; | |
59 | } uv_cpuid; | |
60 | ||
7a1110e8 JS |
61 | int uv_min_hub_revision_id; |
62 | EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); | |
8191c9f6 DS |
63 | unsigned int uv_apicid_hibits; |
64 | EXPORT_SYMBOL_GPL(uv_apicid_hibits); | |
fd12a0d6 | 65 | |
1a8880a1 | 66 | static struct apic apic_x2apic_uv_x; |
3edcf2ff | 67 | static struct uv_hub_info_s uv_hub_info_node0; |
1a8880a1 | 68 | |
7563421b MT |
69 | /* Set this to use hardware error handler instead of kernel panic */ |
70 | static int disable_uv_undefined_panic = 1; | |
71 | unsigned long uv_undefined(char *str) | |
72 | { | |
73 | if (likely(!disable_uv_undefined_panic)) | |
74 | panic("UV: error: undefined MMR: %s\n", str); | |
75 | else | |
76 | pr_crit("UV: error: undefined MMR: %s\n", str); | |
77 | return ~0ul; /* cause a machine fault */ | |
78 | } | |
79 | EXPORT_SYMBOL(uv_undefined); | |
80 | ||
e6810413 JS |
81 | static unsigned long __init uv_early_read_mmr(unsigned long addr) |
82 | { | |
83 | unsigned long val, *mmr; | |
84 | ||
85 | mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); | |
86 | val = *mmr; | |
87 | early_iounmap(mmr, sizeof(*mmr)); | |
88 | return val; | |
89 | } | |
90 | ||
eb41c8be | 91 | static inline bool is_GRU_range(u64 start, u64 end) |
fd12a0d6 | 92 | { |
879d5ad0 DS |
93 | if (gru_dist_base) { |
94 | u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */ | |
95 | u64 sl = start & gru_dist_lmask; /* base offset bits */ | |
96 | u64 eu = end & gru_dist_umask; | |
97 | u64 el = end & gru_dist_lmask; | |
98 | ||
99 | /* Must reside completely within a single GRU range */ | |
100 | return (sl == gru_dist_base && el == gru_dist_base && | |
101 | su >= gru_first_node_paddr && | |
102 | su <= gru_last_node_paddr && | |
103 | eu == su); | |
104 | } else { | |
105 | return start >= gru_start_paddr && end <= gru_end_paddr; | |
106 | } | |
fd12a0d6 JS |
107 | } |
108 | ||
eb41c8be | 109 | static bool uv_is_untracked_pat_range(u64 start, u64 end) |
fd12a0d6 JS |
110 | { |
111 | return is_ISA_range(start, end) || is_GRU_range(start, end); | |
112 | } | |
1b9b89e7 | 113 | |
d8850ba4 | 114 | static int __init early_get_pnodeid(void) |
27229ca6 JS |
115 | { |
116 | union uvh_node_id_u node_id; | |
d8850ba4 JS |
117 | union uvh_rh_gam_config_mmr_u m_n_config; |
118 | int pnode; | |
7a1110e8 JS |
119 | |
120 | /* Currently, all blades have same revision number */ | |
e6810413 | 121 | node_id.v = uv_early_read_mmr(UVH_NODE_ID); |
d8850ba4 | 122 | m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); |
7a1110e8 JS |
123 | uv_min_hub_revision_id = node_id.s.revision; |
124 | ||
b15cc4a1 MT |
125 | switch (node_id.s.part_number) { |
126 | case UV2_HUB_PART_NUMBER: | |
127 | case UV2_HUB_PART_NUMBER_X: | |
b495e039 | 128 | uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; |
b15cc4a1 MT |
129 | break; |
130 | case UV3_HUB_PART_NUMBER: | |
131 | case UV3_HUB_PART_NUMBER_X: | |
dd3c9c4b | 132 | uv_min_hub_revision_id += UV3_HUB_REVISION_BASE; |
b15cc4a1 | 133 | break; |
a0ec83f3 MT |
134 | case UV4_HUB_PART_NUMBER: |
135 | uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1; | |
136 | break; | |
b15cc4a1 | 137 | } |
2a919596 JS |
138 | |
139 | uv_hub_info->hub_revision = uv_min_hub_revision_id; | |
405422d8 MT |
140 | uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1; |
141 | pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask; | |
142 | uv_cpuid.gpa_shift = 46; /* default unless changed */ | |
143 | ||
144 | pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n", | |
145 | node_id.s.revision, node_id.s.part_number, node_id.s.node_id, | |
146 | m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode); | |
d8850ba4 | 147 | return pnode; |
27229ca6 JS |
148 | } |
149 | ||
405422d8 MT |
150 | /* [copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */ |
151 | #define SMT_LEVEL 0 /* leaf 0xb SMT level */ | |
152 | #define INVALID_TYPE 0 /* leaf 0xb sub-leaf types */ | |
153 | #define SMT_TYPE 1 | |
154 | #define CORE_TYPE 2 | |
155 | #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff) | |
156 | #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) | |
157 | ||
158 | static void set_x2apic_bits(void) | |
159 | { | |
160 | unsigned int eax, ebx, ecx, edx, sub_index; | |
161 | unsigned int sid_shift; | |
162 | ||
163 | cpuid(0, &eax, &ebx, &ecx, &edx); | |
164 | if (eax < 0xb) { | |
165 | pr_info("UV: CPU does not have CPUID.11\n"); | |
166 | return; | |
167 | } | |
168 | cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); | |
169 | if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) { | |
170 | pr_info("UV: CPUID.11 not implemented\n"); | |
171 | return; | |
172 | } | |
173 | sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); | |
174 | sub_index = 1; | |
175 | do { | |
176 | cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx); | |
177 | if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) { | |
178 | sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); | |
179 | break; | |
180 | } | |
181 | sub_index++; | |
182 | } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE); | |
183 | uv_cpuid.apicid_shift = 0; | |
184 | uv_cpuid.apicid_mask = (~(-1 << sid_shift)); | |
185 | uv_cpuid.socketid_shift = sid_shift; | |
186 | } | |
187 | ||
188 | static void __init early_get_apic_socketid_shift(void) | |
c8f730b1 | 189 | { |
405422d8 MT |
190 | if (is_uv2_hub() || is_uv3_hub()) |
191 | uvh_apicid.v = uv_early_read_mmr(UVH_APICID); | |
192 | ||
193 | set_x2apic_bits(); | |
194 | ||
195 | pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", | |
196 | uv_cpuid.apicid_shift, uv_cpuid.apicid_mask); | |
197 | pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", | |
198 | uv_cpuid.socketid_shift, uv_cpuid.pnode_mask); | |
c8f730b1 RA |
199 | } |
200 | ||
8191c9f6 DS |
201 | /* |
202 | * Add an extra bit as dictated by bios to the destination apicid of | |
203 | * interrupts potentially passing through the UV HUB. This prevents | |
204 | * a deadlock between interrupts and IO port operations. | |
205 | */ | |
206 | static void __init uv_set_apicid_hibit(void) | |
207 | { | |
2a919596 | 208 | union uv1h_lb_target_physical_apic_id_mask_u apicid_mask; |
8191c9f6 | 209 | |
2a919596 JS |
210 | if (is_uv1_hub()) { |
211 | apicid_mask.v = | |
212 | uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK); | |
213 | uv_apicid_hibits = | |
214 | apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK; | |
215 | } | |
8191c9f6 DS |
216 | } |
217 | ||
52459ab9 | 218 | static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 219 | { |
379b97e2 MT |
220 | int pnodeid; |
221 | int uv_apic; | |
1d2c867c | 222 | |
7a4e0170 MT |
223 | if (strncmp(oem_id, "SGI", 3) != 0) |
224 | return 0; | |
225 | ||
5a52e8f8 MT |
226 | if (numa_off) { |
227 | pr_err("UV: NUMA is off, disabling UV support\n"); | |
228 | return 0; | |
229 | } | |
230 | ||
3edcf2ff MT |
231 | /* Setup early hub type field in uv_hub_info for Node 0 */ |
232 | uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0; | |
233 | ||
379b97e2 MT |
234 | /* |
235 | * Determine UV arch type. | |
236 | * SGI: UV100/1000 | |
237 | * SGI2: UV2000/3000 | |
238 | * SGI3: UV300 (truncated to 4 chars because of different varieties) | |
a0ec83f3 | 239 | * SGI4: UV400 (truncated to 4 chars because of different varieties) |
379b97e2 MT |
240 | */ |
241 | uv_hub_info->hub_revision = | |
a0ec83f3 | 242 | !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE : |
379b97e2 MT |
243 | !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE : |
244 | !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE : | |
245 | !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0; | |
246 | ||
247 | if (uv_hub_info->hub_revision == 0) | |
248 | goto badbios; | |
249 | ||
250 | pnodeid = early_get_pnodeid(); | |
405422d8 | 251 | early_get_apic_socketid_shift(); |
379b97e2 MT |
252 | x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; |
253 | x86_platform.nmi_init = uv_nmi_init; | |
254 | ||
255 | if (!strcmp(oem_table_id, "UVX")) { /* most common */ | |
256 | uv_system_type = UV_X2APIC; | |
257 | uv_apic = 0; | |
258 | ||
259 | } else if (!strcmp(oem_table_id, "UVH")) { /* only UV1 systems */ | |
260 | uv_system_type = UV_NON_UNIQUE_APIC; | |
261 | __this_cpu_write(x2apic_extra_bits, | |
262 | pnodeid << uvh_apicid.s.pnode_shift); | |
263 | uv_set_apicid_hibit(); | |
264 | uv_apic = 1; | |
265 | ||
266 | } else if (!strcmp(oem_table_id, "UVL")) { /* only used for */ | |
267 | uv_system_type = UV_LEGACY_APIC; /* very small systems */ | |
268 | uv_apic = 0; | |
269 | ||
270 | } else { | |
271 | goto badbios; | |
1b9b89e7 | 272 | } |
379b97e2 MT |
273 | |
274 | pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", | |
275 | oem_id, oem_table_id, uv_system_type, | |
276 | uv_min_hub_revision_id, uv_apic); | |
277 | ||
278 | return uv_apic; | |
279 | ||
280 | badbios: | |
281 | pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id); | |
282 | pr_err("Current BIOS not supported, update kernel and/or BIOS\n"); | |
283 | BUG(); | |
1b9b89e7 YL |
284 | } |
285 | ||
286 | enum uv_system_type get_uv_system_type(void) | |
287 | { | |
288 | return uv_system_type; | |
289 | } | |
290 | ||
291 | int is_uv_system(void) | |
292 | { | |
293 | return uv_system_type != UV_NONE; | |
294 | } | |
8067794b | 295 | EXPORT_SYMBOL_GPL(is_uv_system); |
1b9b89e7 | 296 | |
3edcf2ff MT |
297 | void **__uv_hub_info_list; |
298 | EXPORT_SYMBOL_GPL(__uv_hub_info_list); | |
ac23d4ee | 299 | |
0045ddd2 MT |
300 | DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); |
301 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info); | |
302 | ||
ac23d4ee JS |
303 | short uv_possible_blades; |
304 | EXPORT_SYMBOL_GPL(uv_possible_blades); | |
305 | ||
7019cc2d RA |
306 | unsigned long sn_rtc_cycles_per_second; |
307 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | |
308 | ||
1de329c1 | 309 | /* the following values are used for the per node hub info struct */ |
906f3b20 | 310 | static __initdata unsigned short *_node_to_pnode; |
1de329c1 MT |
311 | static __initdata unsigned short _min_socket, _max_socket; |
312 | static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len; | |
313 | static __initdata struct uv_gam_range_entry *uv_gre_table; | |
314 | static __initdata struct uv_gam_parameters *uv_gp_table; | |
6e27b91c MT |
315 | static __initdata unsigned short *_socket_to_node; |
316 | static __initdata unsigned short *_socket_to_pnode; | |
317 | static __initdata unsigned short *_pnode_to_socket; | |
c85375cd | 318 | static __initdata struct uv_gam_range_s *_gr_table; |
1de329c1 | 319 | #define SOCK_EMPTY ((unsigned short)~0) |
906f3b20 | 320 | |
3edcf2ff MT |
321 | extern int uv_hub_info_version(void) |
322 | { | |
323 | return UV_HUB_INFO_VERSION; | |
324 | } | |
325 | EXPORT_SYMBOL(uv_hub_info_version); | |
326 | ||
c85375cd MT |
327 | /* Build GAM range lookup table */ |
328 | static __init void build_uv_gr_table(void) | |
329 | { | |
330 | struct uv_gam_range_entry *gre = uv_gre_table; | |
331 | struct uv_gam_range_s *grt; | |
332 | unsigned long last_limit = 0, ram_limit = 0; | |
054f621f | 333 | int bytes, i, sid, lsid = -1, indx = 0, lindx = -1; |
c85375cd MT |
334 | |
335 | if (!gre) | |
336 | return; | |
337 | ||
338 | bytes = _gr_table_len * sizeof(struct uv_gam_range_s); | |
339 | grt = kzalloc(bytes, GFP_KERNEL); | |
340 | BUG_ON(!grt); | |
341 | _gr_table = grt; | |
342 | ||
343 | for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { | |
344 | if (gre->type == UV_GAM_RANGE_TYPE_HOLE) { | |
345 | if (!ram_limit) { /* mark hole between ram/non-ram */ | |
346 | ram_limit = last_limit; | |
347 | last_limit = gre->limit; | |
348 | lsid++; | |
349 | continue; | |
350 | } | |
351 | last_limit = gre->limit; | |
352 | pr_info("UV: extra hole in GAM RE table @%d\n", | |
353 | (int)(gre - uv_gre_table)); | |
354 | continue; | |
355 | } | |
356 | if (_max_socket < gre->sockid) { | |
357 | pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", | |
358 | gre->sockid, _max_socket, | |
359 | (int)(gre - uv_gre_table)); | |
360 | continue; | |
361 | } | |
362 | sid = gre->sockid - _min_socket; | |
363 | if (lsid < sid) { /* new range */ | |
054f621f MT |
364 | grt = &_gr_table[indx]; |
365 | grt->base = lindx; | |
c85375cd MT |
366 | grt->nasid = gre->nasid; |
367 | grt->limit = last_limit = gre->limit; | |
368 | lsid = sid; | |
054f621f | 369 | lindx = indx++; |
c85375cd MT |
370 | continue; |
371 | } | |
372 | if (lsid == sid && !ram_limit) { /* update range */ | |
373 | if (grt->limit == last_limit) { /* .. if contiguous */ | |
374 | grt->limit = last_limit = gre->limit; | |
375 | continue; | |
376 | } | |
377 | } | |
378 | if (!ram_limit) { /* non-contiguous ram range */ | |
379 | grt++; | |
054f621f | 380 | grt->base = lindx; |
c85375cd MT |
381 | grt->nasid = gre->nasid; |
382 | grt->limit = last_limit = gre->limit; | |
383 | continue; | |
384 | } | |
385 | grt++; /* non-contiguous/non-ram */ | |
386 | grt->base = grt - _gr_table; /* base is this entry */ | |
387 | grt->nasid = gre->nasid; | |
388 | grt->limit = last_limit = gre->limit; | |
389 | lsid++; | |
390 | } | |
391 | ||
392 | /* shorten table if possible */ | |
393 | grt++; | |
394 | i = grt - _gr_table; | |
395 | if (i < _gr_table_len) { | |
396 | void *ret; | |
397 | ||
398 | bytes = i * sizeof(struct uv_gam_range_s); | |
399 | ret = krealloc(_gr_table, bytes, GFP_KERNEL); | |
400 | if (ret) { | |
401 | _gr_table = ret; | |
402 | _gr_table_len = i; | |
403 | } | |
404 | } | |
405 | ||
406 | /* display resultant gam range table */ | |
407 | for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) { | |
408 | int gb = grt->base; | |
409 | unsigned long start = gb < 0 ? 0 : | |
410 | (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT; | |
411 | unsigned long end = | |
412 | (unsigned long)grt->limit << UV_GAM_RANGE_SHFT; | |
413 | ||
414 | pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", | |
415 | i, grt->nasid, start, end, gb); | |
416 | } | |
417 | } | |
418 | ||
148f9bb8 | 419 | static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) |
ac23d4ee JS |
420 | { |
421 | unsigned long val; | |
9f5314fb | 422 | int pnode; |
ac23d4ee | 423 | |
9f5314fb | 424 | pnode = uv_apicid_to_pnode(phys_apicid); |
8191c9f6 | 425 | phys_apicid |= uv_apicid_hibits; |
ac23d4ee JS |
426 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
427 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 428 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 429 | APIC_DM_INIT; |
9f5314fb | 430 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
34d05591 JS |
431 | |
432 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | | |
433 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 434 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 435 | APIC_DM_STARTUP; |
9f5314fb | 436 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
2b6163bf | 437 | |
ac23d4ee JS |
438 | return 0; |
439 | } | |
440 | ||
441 | static void uv_send_IPI_one(int cpu, int vector) | |
442 | { | |
66666e50 | 443 | unsigned long apicid; |
9f5314fb | 444 | int pnode; |
ac23d4ee | 445 | |
1e0b5d00 | 446 | apicid = per_cpu(x86_cpu_to_apicid, cpu); |
9f5314fb | 447 | pnode = uv_apicid_to_pnode(apicid); |
66666e50 | 448 | uv_hub_send_ipi(pnode, apicid, vector); |
ac23d4ee JS |
449 | } |
450 | ||
bcda016e | 451 | static void uv_send_IPI_mask(const struct cpumask *mask, int vector) |
ac23d4ee JS |
452 | { |
453 | unsigned int cpu; | |
454 | ||
bcda016e | 455 | for_each_cpu(cpu, mask) |
e7986739 MT |
456 | uv_send_IPI_one(cpu, vector); |
457 | } | |
458 | ||
bcda016e | 459 | static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
e7986739 | 460 | { |
e7986739 | 461 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 462 | unsigned int cpu; |
e7986739 | 463 | |
dac5f412 | 464 | for_each_cpu(cpu, mask) { |
e7986739 | 465 | if (cpu != this_cpu) |
ac23d4ee | 466 | uv_send_IPI_one(cpu, vector); |
dac5f412 | 467 | } |
ac23d4ee JS |
468 | } |
469 | ||
470 | static void uv_send_IPI_allbutself(int vector) | |
471 | { | |
e7986739 | 472 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 473 | unsigned int cpu; |
ac23d4ee | 474 | |
dac5f412 | 475 | for_each_online_cpu(cpu) { |
e7986739 MT |
476 | if (cpu != this_cpu) |
477 | uv_send_IPI_one(cpu, vector); | |
dac5f412 | 478 | } |
ac23d4ee JS |
479 | } |
480 | ||
481 | static void uv_send_IPI_all(int vector) | |
482 | { | |
bcda016e | 483 | uv_send_IPI_mask(cpu_online_mask, vector); |
ac23d4ee JS |
484 | } |
485 | ||
b7157acf SP |
486 | static int uv_apic_id_valid(int apicid) |
487 | { | |
488 | return 1; | |
489 | } | |
490 | ||
ac23d4ee JS |
491 | static int uv_apic_id_registered(void) |
492 | { | |
493 | return 1; | |
494 | } | |
495 | ||
277d1f58 | 496 | static void uv_init_apic_ldr(void) |
5c520a67 SS |
497 | { |
498 | } | |
499 | ||
ff164324 | 500 | static int |
debccb3e | 501 | uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
502 | const struct cpumask *andmask, |
503 | unsigned int *apicid) | |
95d313cf | 504 | { |
ea3807ea | 505 | int unsigned cpu; |
95d313cf MT |
506 | |
507 | /* | |
508 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
509 | * May as well be the first. | |
510 | */ | |
debccb3e | 511 | for_each_cpu_and(cpu, cpumask, andmask) { |
a775a38b MT |
512 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
513 | break; | |
debccb3e | 514 | } |
ff164324 | 515 | |
ea3807ea | 516 | if (likely(cpu < nr_cpu_ids)) { |
a5a39156 AG |
517 | *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; |
518 | return 0; | |
a5a39156 | 519 | } |
ea3807ea AG |
520 | |
521 | return -EINVAL; | |
95d313cf MT |
522 | } |
523 | ||
ca6c8ed4 | 524 | static unsigned int x2apic_get_apic_id(unsigned long x) |
0c81c746 SS |
525 | { |
526 | unsigned int id; | |
527 | ||
528 | WARN_ON(preemptible() && num_online_cpus() > 1); | |
0a3aee0d | 529 | id = x | __this_cpu_read(x2apic_extra_bits); |
0c81c746 SS |
530 | |
531 | return id; | |
532 | } | |
533 | ||
1b9b89e7 | 534 | static unsigned long set_apic_id(unsigned int id) |
f910a9dc YL |
535 | { |
536 | unsigned long x; | |
537 | ||
538 | /* maskout x2apic_extra_bits ? */ | |
539 | x = id; | |
540 | return x; | |
541 | } | |
542 | ||
543 | static unsigned int uv_read_apic_id(void) | |
544 | { | |
ca6c8ed4 | 545 | return x2apic_get_apic_id(apic_read(APIC_ID)); |
f910a9dc YL |
546 | } |
547 | ||
d4c9a9f3 | 548 | static int uv_phys_pkg_id(int initial_apicid, int index_msb) |
ac23d4ee | 549 | { |
0c81c746 | 550 | return uv_read_apic_id() >> index_msb; |
ac23d4ee JS |
551 | } |
552 | ||
ac23d4ee JS |
553 | static void uv_send_IPI_self(int vector) |
554 | { | |
555 | apic_write(APIC_SELF_IPI, vector); | |
556 | } | |
ac23d4ee | 557 | |
9ebd680b SS |
558 | static int uv_probe(void) |
559 | { | |
560 | return apic == &apic_x2apic_uv_x; | |
561 | } | |
562 | ||
1a8880a1 | 563 | static struct apic __refdata apic_x2apic_uv_x = { |
c7967329 IM |
564 | |
565 | .name = "UV large system", | |
9ebd680b | 566 | .probe = uv_probe, |
c7967329 | 567 | .acpi_madt_oem_check = uv_acpi_madt_oem_check, |
b7157acf | 568 | .apic_id_valid = uv_apic_id_valid, |
c7967329 IM |
569 | .apic_id_registered = uv_apic_id_registered, |
570 | ||
f8987a10 | 571 | .irq_delivery_mode = dest_Fixed, |
c5997fa8 | 572 | .irq_dest_mode = 0, /* physical */ |
c7967329 | 573 | |
bf721d3a | 574 | .target_cpus = online_target_cpus, |
08125d3e | 575 | .disable_esr = 0, |
bdb1a9b6 | 576 | .dest_logical = APIC_DEST_LOGICAL, |
c7967329 | 577 | .check_apicid_used = NULL, |
c7967329 | 578 | |
9d8e1066 | 579 | .vector_allocation_domain = default_vector_allocation_domain, |
c7967329 IM |
580 | .init_apic_ldr = uv_init_apic_ldr, |
581 | ||
582 | .ioapic_phys_id_map = NULL, | |
583 | .setup_apic_routing = NULL, | |
a21769a4 | 584 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
c7967329 | 585 | .apicid_to_cpu_present = NULL, |
a27a6210 | 586 | .check_phys_apicid_present = default_check_phys_apicid_present, |
d4c9a9f3 | 587 | .phys_pkg_id = uv_phys_pkg_id, |
c7967329 | 588 | |
ca6c8ed4 | 589 | .get_apic_id = x2apic_get_apic_id, |
c7967329 | 590 | .set_apic_id = set_apic_id, |
c7967329 | 591 | |
c7967329 IM |
592 | .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, |
593 | ||
8642ea95 | 594 | .send_IPI = uv_send_IPI_one, |
c7967329 IM |
595 | .send_IPI_mask = uv_send_IPI_mask, |
596 | .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, | |
597 | .send_IPI_allbutself = uv_send_IPI_allbutself, | |
598 | .send_IPI_all = uv_send_IPI_all, | |
599 | .send_IPI_self = uv_send_IPI_self, | |
600 | ||
1f5bcabf | 601 | .wakeup_secondary_cpu = uv_wakeup_secondary, |
c7967329 | 602 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
603 | |
604 | .read = native_apic_msr_read, | |
605 | .write = native_apic_msr_write, | |
0ab711ae | 606 | .eoi_write = native_apic_msr_eoi_write, |
c1eeb2de YL |
607 | .icr_read = native_x2apic_icr_read, |
608 | .icr_write = native_x2apic_icr_write, | |
609 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
610 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
ac23d4ee JS |
611 | }; |
612 | ||
148f9bb8 | 613 | static void set_x2apic_extra_bits(int pnode) |
ac23d4ee | 614 | { |
16ee8db6 | 615 | __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); |
ac23d4ee JS |
616 | } |
617 | ||
c443c03d | 618 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 |
9f5314fb JS |
619 | #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT |
620 | ||
9f5314fb JS |
621 | static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) |
622 | { | |
62b0cfc2 | 623 | union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; |
9f5314fb | 624 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; |
c443c03d MT |
625 | unsigned long m_redirect; |
626 | unsigned long m_overlay; | |
9f5314fb JS |
627 | int i; |
628 | ||
c443c03d MT |
629 | for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) { |
630 | switch (i) { | |
631 | case 0: | |
632 | m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR; | |
633 | m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR; | |
634 | break; | |
635 | case 1: | |
636 | m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR; | |
637 | m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR; | |
638 | break; | |
639 | case 2: | |
640 | m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR; | |
641 | m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR; | |
642 | break; | |
643 | } | |
644 | alias.v = uv_read_local_mmr(m_overlay); | |
036ed8ba | 645 | if (alias.s.enable && alias.s.base == 0) { |
9f5314fb | 646 | *size = (1UL << alias.s.m_alias); |
c443c03d MT |
647 | redirect.v = uv_read_local_mmr(m_redirect); |
648 | *base = (unsigned long)redirect.s.dest_base | |
649 | << DEST_SHIFT; | |
9f5314fb JS |
650 | return; |
651 | } | |
652 | } | |
036ed8ba | 653 | *base = *size = 0; |
9f5314fb JS |
654 | } |
655 | ||
83f5d894 JS |
656 | enum map_type {map_wb, map_uc}; |
657 | ||
fcfbb2b5 MT |
658 | static __init void map_high(char *id, unsigned long base, int pshift, |
659 | int bshift, int max_pnode, enum map_type map_type) | |
83f5d894 JS |
660 | { |
661 | unsigned long bytes, paddr; | |
662 | ||
fcfbb2b5 MT |
663 | paddr = base << pshift; |
664 | bytes = (1UL << bshift) * (max_pnode + 1); | |
b15cc4a1 MT |
665 | if (!paddr) { |
666 | pr_info("UV: Map %s_HI base address NULL\n", id); | |
667 | return; | |
668 | } | |
879d5ad0 | 669 | pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes); |
83f5d894 JS |
670 | if (map_type == map_uc) |
671 | init_extra_mapping_uc(paddr, bytes); | |
672 | else | |
673 | init_extra_mapping_wb(paddr, bytes); | |
83f5d894 | 674 | } |
b15cc4a1 | 675 | |
879d5ad0 DS |
676 | static __init void map_gru_distributed(unsigned long c) |
677 | { | |
678 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
679 | u64 paddr; | |
680 | unsigned long bytes; | |
681 | int nid; | |
682 | ||
683 | gru.v = c; | |
684 | /* only base bits 42:28 relevant in dist mode */ | |
685 | gru_dist_base = gru.v & 0x000007fff0000000UL; | |
686 | if (!gru_dist_base) { | |
687 | pr_info("UV: Map GRU_DIST base address NULL\n"); | |
688 | return; | |
689 | } | |
690 | bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
691 | gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1); | |
692 | gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1); | |
693 | gru_dist_base &= gru_dist_lmask; /* Clear bits above M */ | |
694 | for_each_online_node(nid) { | |
695 | paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) | | |
696 | gru_dist_base; | |
697 | init_extra_mapping_wb(paddr, bytes); | |
698 | gru_first_node_paddr = min(paddr, gru_first_node_paddr); | |
699 | gru_last_node_paddr = max(paddr, gru_last_node_paddr); | |
700 | } | |
701 | /* Save upper (63:M) bits of address only for is_GRU_range */ | |
702 | gru_first_node_paddr &= gru_dist_umask; | |
703 | gru_last_node_paddr &= gru_dist_umask; | |
704 | pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n", | |
705 | gru_dist_base, gru_first_node_paddr, gru_last_node_paddr); | |
706 | } | |
707 | ||
83f5d894 JS |
708 | static __init void map_gru_high(int max_pnode) |
709 | { | |
710 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
711 | int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
c443c03d MT |
712 | unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK; |
713 | unsigned long base; | |
83f5d894 JS |
714 | |
715 | gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); | |
879d5ad0 | 716 | if (!gru.s.enable) { |
b15cc4a1 | 717 | pr_info("UV: GRU disabled\n"); |
879d5ad0 DS |
718 | return; |
719 | } | |
720 | ||
721 | if (is_uv3_hub() && gru.s3.mode) { | |
722 | map_gru_distributed(gru.v); | |
723 | return; | |
fd12a0d6 | 724 | } |
c443c03d MT |
725 | base = (gru.v & mask) >> shift; |
726 | map_high("GRU", base, shift, shift, max_pnode, map_wb); | |
727 | gru_start_paddr = ((u64)base << shift); | |
879d5ad0 | 728 | gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); |
83f5d894 JS |
729 | } |
730 | ||
daf7b9c9 JS |
731 | static __init void map_mmr_high(int max_pnode) |
732 | { | |
733 | union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; | |
734 | int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
735 | ||
736 | mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); | |
737 | if (mmr.s.enable) | |
fcfbb2b5 | 738 | map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); |
b15cc4a1 MT |
739 | else |
740 | pr_info("UV: MMR disabled\n"); | |
741 | } | |
742 | ||
743 | /* | |
744 | * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY | |
745 | * and REDIRECT MMR regs are exactly the same on UV3. | |
746 | */ | |
747 | struct mmioh_config { | |
748 | unsigned long overlay; | |
749 | unsigned long redirect; | |
750 | char *id; | |
751 | }; | |
752 | ||
753 | static __initdata struct mmioh_config mmiohs[] = { | |
754 | { | |
755 | UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR, | |
756 | UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR, | |
757 | "MMIOH0" | |
758 | }, | |
759 | { | |
760 | UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR, | |
761 | UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR, | |
762 | "MMIOH1" | |
763 | }, | |
764 | }; | |
765 | ||
a2f28e69 | 766 | /* UV3 & UV4 have identical MMIOH overlay configs */ |
b15cc4a1 MT |
767 | static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode) |
768 | { | |
769 | union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay; | |
770 | unsigned long mmr; | |
771 | unsigned long base; | |
772 | int i, n, shift, m_io, max_io; | |
773 | int nasid, lnasid, fi, li; | |
774 | char *id; | |
775 | ||
776 | id = mmiohs[index].id; | |
777 | overlay.v = uv_read_local_mmr(mmiohs[index].overlay); | |
778 | pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n", | |
779 | id, overlay.v, overlay.s3.base, overlay.s3.m_io); | |
780 | if (!overlay.s3.enable) { | |
781 | pr_info("UV: %s disabled\n", id); | |
782 | return; | |
783 | } | |
784 | ||
785 | shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT; | |
786 | base = (unsigned long)overlay.s3.base; | |
787 | m_io = overlay.s3.m_io; | |
788 | mmr = mmiohs[index].redirect; | |
789 | n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH; | |
790 | min_pnode *= 2; /* convert to NASID */ | |
791 | max_pnode *= 2; | |
792 | max_io = lnasid = fi = li = -1; | |
793 | ||
794 | for (i = 0; i < n; i++) { | |
795 | union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect; | |
796 | ||
797 | redirect.v = uv_read_local_mmr(mmr + i * 8); | |
798 | nasid = redirect.s3.nasid; | |
799 | if (nasid < min_pnode || max_pnode < nasid) | |
800 | nasid = -1; /* invalid NASID */ | |
801 | ||
802 | if (nasid == lnasid) { | |
803 | li = i; | |
804 | if (i != n-1) /* last entry check */ | |
805 | continue; | |
806 | } | |
807 | ||
808 | /* check if we have a cached (or last) redirect to print */ | |
809 | if (lnasid != -1 || (i == n-1 && nasid != -1)) { | |
810 | unsigned long addr1, addr2; | |
811 | int f, l; | |
812 | ||
813 | if (lnasid == -1) { | |
814 | f = l = i; | |
815 | lnasid = nasid; | |
816 | } else { | |
817 | f = fi; | |
818 | l = li; | |
819 | } | |
820 | addr1 = (base << shift) + | |
821 | f * (unsigned long)(1 << m_io); | |
822 | addr2 = (base << shift) + | |
823 | (l + 1) * (unsigned long)(1 << m_io); | |
824 | pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", | |
825 | id, fi, li, lnasid, addr1, addr2); | |
826 | if (max_io < l) | |
827 | max_io = l; | |
828 | } | |
829 | fi = li = i; | |
830 | lnasid = nasid; | |
831 | } | |
832 | ||
833 | pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", | |
834 | id, base, shift, m_io, max_io); | |
835 | ||
836 | if (max_io >= 0) | |
837 | map_high(id, base, shift, m_io, max_io, map_uc); | |
daf7b9c9 JS |
838 | } |
839 | ||
b15cc4a1 | 840 | static __init void map_mmioh_high(int min_pnode, int max_pnode) |
83f5d894 JS |
841 | { |
842 | union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; | |
b15cc4a1 MT |
843 | unsigned long mmr, base; |
844 | int shift, enable, m_io, n_io; | |
83f5d894 | 845 | |
a2f28e69 | 846 | if (is_uv3_hub() || is_uv4_hub()) { |
b15cc4a1 MT |
847 | /* Map both MMIOH Regions */ |
848 | map_mmioh_high_uv3(0, min_pnode, max_pnode); | |
849 | map_mmioh_high_uv3(1, min_pnode, max_pnode); | |
850 | return; | |
2a919596 | 851 | } |
b15cc4a1 MT |
852 | |
853 | if (is_uv1_hub()) { | |
854 | mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; | |
855 | shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
856 | mmioh.v = uv_read_local_mmr(mmr); | |
857 | enable = !!mmioh.s1.enable; | |
858 | base = mmioh.s1.base; | |
859 | m_io = mmioh.s1.m_io; | |
860 | n_io = mmioh.s1.n_io; | |
861 | } else if (is_uv2_hub()) { | |
862 | mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; | |
2a919596 | 863 | shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; |
b15cc4a1 MT |
864 | mmioh.v = uv_read_local_mmr(mmr); |
865 | enable = !!mmioh.s2.enable; | |
866 | base = mmioh.s2.base; | |
867 | m_io = mmioh.s2.m_io; | |
868 | n_io = mmioh.s2.n_io; | |
869 | } else | |
870 | return; | |
871 | ||
872 | if (enable) { | |
873 | max_pnode &= (1 << n_io) - 1; | |
874 | pr_info( | |
875 | "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", | |
876 | base, shift, m_io, n_io, max_pnode); | |
877 | map_high("MMIOH", base, shift, m_io, max_pnode, map_uc); | |
878 | } else { | |
879 | pr_info("UV: MMIOH disabled\n"); | |
2a919596 | 880 | } |
83f5d894 JS |
881 | } |
882 | ||
918bc960 JS |
883 | static __init void map_low_mmrs(void) |
884 | { | |
885 | init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); | |
886 | init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); | |
887 | } | |
888 | ||
7019cc2d RA |
889 | static __init void uv_rtc_init(void) |
890 | { | |
922402f1 RA |
891 | long status; |
892 | u64 ticks_per_sec; | |
7019cc2d | 893 | |
922402f1 RA |
894 | status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, |
895 | &ticks_per_sec); | |
896 | if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { | |
7019cc2d RA |
897 | printk(KERN_WARNING |
898 | "unable to determine platform RTC clock frequency, " | |
899 | "guessing.\n"); | |
900 | /* BIOS gives wrong value for clock freq. so guess */ | |
901 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; | |
902 | } else | |
903 | sn_rtc_cycles_per_second = ticks_per_sec; | |
904 | } | |
905 | ||
7f1baa06 MT |
906 | /* |
907 | * percpu heartbeat timer | |
908 | */ | |
909 | static void uv_heartbeat(unsigned long ignored) | |
910 | { | |
d38bb135 MT |
911 | struct timer_list *timer = &uv_scir_info->timer; |
912 | unsigned char bits = uv_scir_info->state; | |
7f1baa06 MT |
913 | |
914 | /* flip heartbeat bit */ | |
915 | bits ^= SCIR_CPU_HEARTBEAT; | |
916 | ||
69a72a0e MT |
917 | /* is this cpu idle? */ |
918 | if (idle_cpu(raw_smp_processor_id())) | |
7f1baa06 MT |
919 | bits &= ~SCIR_CPU_ACTIVITY; |
920 | else | |
921 | bits |= SCIR_CPU_ACTIVITY; | |
922 | ||
923 | /* update system controller interface reg */ | |
924 | uv_set_scir_bits(bits); | |
925 | ||
926 | /* enable next timer period */ | |
920a4a70 | 927 | mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL); |
7f1baa06 MT |
928 | } |
929 | ||
148f9bb8 | 930 | static void uv_heartbeat_enable(int cpu) |
7f1baa06 | 931 | { |
d38bb135 MT |
932 | while (!uv_cpu_scir_info(cpu)->enabled) { |
933 | struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer; | |
7f1baa06 MT |
934 | |
935 | uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); | |
920a4a70 | 936 | setup_pinned_timer(timer, uv_heartbeat, cpu); |
7f1baa06 MT |
937 | timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; |
938 | add_timer_on(timer, cpu); | |
d38bb135 | 939 | uv_cpu_scir_info(cpu)->enabled = 1; |
7f1baa06 | 940 | |
99659a92 RK |
941 | /* also ensure that boot cpu is enabled */ |
942 | cpu = 0; | |
943 | } | |
7f1baa06 MT |
944 | } |
945 | ||
77be80e4 | 946 | #ifdef CONFIG_HOTPLUG_CPU |
148f9bb8 | 947 | static void uv_heartbeat_disable(int cpu) |
7f1baa06 | 948 | { |
d38bb135 MT |
949 | if (uv_cpu_scir_info(cpu)->enabled) { |
950 | uv_cpu_scir_info(cpu)->enabled = 0; | |
951 | del_timer(&uv_cpu_scir_info(cpu)->timer); | |
7f1baa06 MT |
952 | } |
953 | uv_set_cpu_scir_bits(cpu, 0xff); | |
954 | } | |
955 | ||
7f1baa06 MT |
956 | /* |
957 | * cpu hotplug notifier | |
958 | */ | |
148f9bb8 PG |
959 | static int uv_scir_cpu_notify(struct notifier_block *self, unsigned long action, |
960 | void *hcpu) | |
7f1baa06 MT |
961 | { |
962 | long cpu = (long)hcpu; | |
963 | ||
f47ab81a TG |
964 | switch (action & ~CPU_TASKS_FROZEN) { |
965 | case CPU_DOWN_FAILED: | |
7f1baa06 MT |
966 | case CPU_ONLINE: |
967 | uv_heartbeat_enable(cpu); | |
968 | break; | |
969 | case CPU_DOWN_PREPARE: | |
970 | uv_heartbeat_disable(cpu); | |
971 | break; | |
972 | default: | |
973 | break; | |
974 | } | |
975 | return NOTIFY_OK; | |
976 | } | |
977 | ||
978 | static __init void uv_scir_register_cpu_notifier(void) | |
979 | { | |
980 | hotcpu_notifier(uv_scir_cpu_notify, 0); | |
981 | } | |
982 | ||
983 | #else /* !CONFIG_HOTPLUG_CPU */ | |
984 | ||
985 | static __init void uv_scir_register_cpu_notifier(void) | |
986 | { | |
987 | } | |
988 | ||
989 | static __init int uv_init_heartbeat(void) | |
990 | { | |
991 | int cpu; | |
992 | ||
993 | if (is_uv_system()) | |
994 | for_each_online_cpu(cpu) | |
995 | uv_heartbeat_enable(cpu); | |
996 | return 0; | |
997 | } | |
998 | ||
999 | late_initcall(uv_init_heartbeat); | |
1000 | ||
1001 | #endif /* !CONFIG_HOTPLUG_CPU */ | |
1002 | ||
841582ea MT |
1003 | /* Direct Legacy VGA I/O traffic to designated IOH */ |
1004 | int uv_set_vga_state(struct pci_dev *pdev, bool decode, | |
7ad35cf2 | 1005 | unsigned int command_bits, u32 flags) |
841582ea MT |
1006 | { |
1007 | int domain, bus, rc; | |
1008 | ||
7ad35cf2 DA |
1009 | PR_DEVEL("devfn %x decode %d cmd %x flags %d\n", |
1010 | pdev->devfn, decode, command_bits, flags); | |
841582ea | 1011 | |
7ad35cf2 | 1012 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
841582ea MT |
1013 | return 0; |
1014 | ||
1015 | if ((command_bits & PCI_COMMAND_IO) == 0) | |
1016 | return 0; | |
1017 | ||
1018 | domain = pci_domain_nr(pdev->bus); | |
1019 | bus = pdev->bus->number; | |
1020 | ||
1021 | rc = uv_bios_set_legacy_vga_target(decode, domain, bus); | |
1022 | PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc); | |
1023 | ||
1024 | return rc; | |
1025 | } | |
1026 | ||
8da077d6 JS |
1027 | /* |
1028 | * Called on each cpu to initialize the per_cpu UV data area. | |
0b1da1c8 | 1029 | * FIXME: hotplug not supported yet |
8da077d6 | 1030 | */ |
148f9bb8 | 1031 | void uv_cpu_init(void) |
8da077d6 | 1032 | { |
6a6256f9 | 1033 | /* CPU 0 initialization will be done via uv_system_init. */ |
906f3b20 | 1034 | if (smp_processor_id() == 0) |
8da077d6 JS |
1035 | return; |
1036 | ||
906f3b20 | 1037 | uv_hub_info->nr_online_cpus++; |
8da077d6 JS |
1038 | |
1039 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) | |
1040 | set_x2apic_extra_bits(uv_hub_info->pnode); | |
1041 | } | |
1042 | ||
c443c03d MT |
1043 | struct mn { |
1044 | unsigned char m_val; | |
1045 | unsigned char n_val; | |
1046 | unsigned char m_shift; | |
1047 | unsigned char n_lshift; | |
1048 | }; | |
1049 | ||
1050 | static void get_mn(struct mn *mnp) | |
ac23d4ee | 1051 | { |
c443c03d MT |
1052 | union uvh_rh_gam_config_mmr_u m_n_config; |
1053 | union uv3h_gr0_gam_gr_config_u m_gr_config; | |
1054 | ||
1055 | m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR); | |
1056 | mnp->n_val = m_n_config.s.n_skt; | |
1057 | if (is_uv4_hub()) { | |
1058 | mnp->m_val = 0; | |
1059 | mnp->n_lshift = 0; | |
1060 | } else if (is_uv3_hub()) { | |
1061 | mnp->m_val = m_n_config.s3.m_skt; | |
1062 | m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG); | |
1063 | mnp->n_lshift = m_gr_config.s3.m_skt; | |
1064 | } else if (is_uv2_hub()) { | |
1065 | mnp->m_val = m_n_config.s2.m_skt; | |
1066 | mnp->n_lshift = mnp->m_val == 40 ? 40 : 39; | |
1067 | } else if (is_uv1_hub()) { | |
1068 | mnp->m_val = m_n_config.s1.m_skt; | |
1069 | mnp->n_lshift = mnp->m_val; | |
1070 | } | |
1071 | mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; | |
1072 | } | |
1073 | ||
1074 | void __init uv_init_hub_info(struct uv_hub_info_s *hub_info) | |
1075 | { | |
1076 | struct mn mn = {0}; /* avoid unitialized warnings */ | |
9f5314fb | 1077 | union uvh_node_id_u node_id; |
c443c03d MT |
1078 | |
1079 | get_mn(&mn); | |
1080 | hub_info->m_val = mn.m_val; | |
1081 | hub_info->n_val = mn.n_val; | |
1082 | hub_info->m_shift = mn.m_shift; | |
405422d8 | 1083 | hub_info->n_lshift = mn.n_lshift ? mn.n_lshift : 0; |
c443c03d MT |
1084 | |
1085 | hub_info->hub_revision = uv_hub_info->hub_revision; | |
405422d8 | 1086 | hub_info->pnode_mask = uv_cpuid.pnode_mask; |
1de329c1 | 1087 | hub_info->min_pnode = _min_pnode; |
6e27b91c MT |
1088 | hub_info->min_socket = _min_socket; |
1089 | hub_info->pnode_to_socket = _pnode_to_socket; | |
1090 | hub_info->socket_to_node = _socket_to_node; | |
1091 | hub_info->socket_to_pnode = _socket_to_pnode; | |
c85375cd MT |
1092 | hub_info->gr_table_len = _gr_table_len; |
1093 | hub_info->gr_table = _gr_table; | |
405422d8 MT |
1094 | hub_info->gpa_mask = mn.m_val ? |
1095 | (1UL << (mn.m_val + mn.n_val)) - 1 : | |
1096 | (1UL << uv_cpuid.gpa_shift) - 1; | |
c443c03d MT |
1097 | |
1098 | node_id.v = uv_read_local_mmr(UVH_NODE_ID); | |
1099 | hub_info->gnode_extra = | |
1100 | (node_id.s.node_id & ~((1 << mn.n_val) - 1)) >> 1; | |
1101 | ||
1102 | hub_info->gnode_upper = | |
1103 | ((unsigned long)hub_info->gnode_extra << mn.m_val); | |
1104 | ||
1de329c1 MT |
1105 | if (uv_gp_table) { |
1106 | hub_info->global_mmr_base = uv_gp_table->mmr_base; | |
1107 | hub_info->global_mmr_shift = uv_gp_table->mmr_shift; | |
1108 | hub_info->global_gru_base = uv_gp_table->gru_base; | |
1109 | hub_info->global_gru_shift = uv_gp_table->gru_shift; | |
1110 | hub_info->gpa_shift = uv_gp_table->gpa_shift; | |
1111 | hub_info->gpa_mask = (1UL << hub_info->gpa_shift) - 1; | |
1112 | } else { | |
1113 | hub_info->global_mmr_base = | |
1114 | uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & | |
1115 | ~UV_MMR_ENABLE; | |
1116 | hub_info->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT; | |
1117 | } | |
c443c03d MT |
1118 | |
1119 | get_lowmem_redirect( | |
1120 | &hub_info->lowmem_remap_base, &hub_info->lowmem_remap_top); | |
1121 | ||
405422d8 | 1122 | hub_info->apic_pnode_shift = uv_cpuid.socketid_shift; |
c443c03d MT |
1123 | |
1124 | /* show system specific info */ | |
1125 | pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", | |
1126 | hub_info->n_val, hub_info->m_val, | |
1127 | hub_info->m_shift, hub_info->n_lshift); | |
1128 | ||
1de329c1 MT |
1129 | pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", |
1130 | hub_info->gpa_mask, hub_info->gpa_shift, | |
1131 | hub_info->pnode_mask, hub_info->apic_pnode_shift); | |
1132 | ||
1133 | pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", | |
1134 | hub_info->global_mmr_base, hub_info->global_mmr_shift, | |
1135 | hub_info->global_gru_base, hub_info->global_gru_shift); | |
c443c03d MT |
1136 | |
1137 | pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", | |
1138 | hub_info->gnode_upper, hub_info->gnode_extra); | |
1de329c1 MT |
1139 | } |
1140 | ||
1141 | static void __init decode_gam_params(unsigned long ptr) | |
1142 | { | |
1143 | uv_gp_table = (struct uv_gam_parameters *)ptr; | |
1144 | ||
1145 | pr_info("UV: GAM Params...\n"); | |
1146 | pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n", | |
1147 | uv_gp_table->mmr_base, uv_gp_table->mmr_shift, | |
1148 | uv_gp_table->gru_base, uv_gp_table->gru_shift, | |
1149 | uv_gp_table->gpa_shift); | |
1150 | } | |
1151 | ||
1152 | static void __init decode_gam_rng_tbl(unsigned long ptr) | |
1153 | { | |
1154 | struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr; | |
1155 | unsigned long lgre = 0; | |
1156 | int index = 0; | |
1157 | int sock_min = 999999, pnode_min = 99999; | |
1158 | int sock_max = -1, pnode_max = -1; | |
1159 | ||
1160 | uv_gre_table = gre; | |
1161 | for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { | |
1162 | if (!index) { | |
1163 | pr_info("UV: GAM Range Table...\n"); | |
22ac2bca | 1164 | pr_info("UV: # %20s %14s %5s %4s %5s %3s %2s\n", |
1de329c1 | 1165 | "Range", "", "Size", "Type", "NASID", |
22ac2bca | 1166 | "SID", "PN"); |
1de329c1 MT |
1167 | } |
1168 | pr_info( | |
22ac2bca | 1169 | "UV: %2d: 0x%014lx-0x%014lx %5luG %3d %04x %02x %02x\n", |
1de329c1 MT |
1170 | index++, |
1171 | (unsigned long)lgre << UV_GAM_RANGE_SHFT, | |
1172 | (unsigned long)gre->limit << UV_GAM_RANGE_SHFT, | |
1173 | ((unsigned long)(gre->limit - lgre)) >> | |
1174 | (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */ | |
22ac2bca | 1175 | gre->type, gre->nasid, gre->sockid, gre->pnode); |
1de329c1 MT |
1176 | |
1177 | lgre = gre->limit; | |
1178 | if (sock_min > gre->sockid) | |
1179 | sock_min = gre->sockid; | |
1180 | if (sock_max < gre->sockid) | |
1181 | sock_max = gre->sockid; | |
1182 | if (pnode_min > gre->pnode) | |
1183 | pnode_min = gre->pnode; | |
1184 | if (pnode_max < gre->pnode) | |
1185 | pnode_max = gre->pnode; | |
1186 | } | |
1de329c1 MT |
1187 | _min_socket = sock_min; |
1188 | _max_socket = sock_max; | |
1189 | _min_pnode = pnode_min; | |
1190 | _max_pnode = pnode_max; | |
1191 | _gr_table_len = index; | |
1192 | pr_info( | |
1193 | "UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", | |
1194 | index, _min_socket, _max_socket, _min_pnode, _max_pnode); | |
1195 | } | |
1196 | ||
1197 | static void __init decode_uv_systab(void) | |
1198 | { | |
1199 | struct uv_systab *st; | |
1200 | int i; | |
1201 | ||
1202 | st = uv_systab; | |
1203 | if ((!st || st->revision < UV_SYSTAB_VERSION_UV4) && !is_uv4_hub()) | |
1204 | return; | |
1205 | if (st->revision != UV_SYSTAB_VERSION_UV4_LATEST) { | |
1206 | pr_crit( | |
1207 | "UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", | |
1208 | st->revision, UV_SYSTAB_VERSION_UV4_LATEST); | |
1209 | BUG(); | |
1210 | } | |
c443c03d | 1211 | |
1de329c1 MT |
1212 | for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { |
1213 | unsigned long ptr = st->entry[i].offset; | |
c443c03d | 1214 | |
1de329c1 MT |
1215 | if (!ptr) |
1216 | continue; | |
1217 | ||
1218 | ptr = ptr + (unsigned long)st; | |
1219 | ||
1220 | switch (st->entry[i].type) { | |
1221 | case UV_SYSTAB_TYPE_GAM_PARAMS: | |
1222 | decode_gam_params(ptr); | |
1223 | break; | |
1224 | ||
1225 | case UV_SYSTAB_TYPE_GAM_RNG_TBL: | |
1226 | decode_gam_rng_tbl(ptr); | |
1227 | break; | |
1228 | } | |
1229 | } | |
c443c03d MT |
1230 | } |
1231 | ||
906f3b20 MT |
1232 | /* |
1233 | * Setup physical blade translations from UVH_NODE_PRESENT_TABLE | |
1234 | * .. NB: UVH_NODE_PRESENT_TABLE is going away, | |
1235 | * .. being replaced by GAM Range Table | |
1236 | */ | |
1237 | static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info) | |
1238 | { | |
f68376fc | 1239 | int i, uv_pb = 0; |
906f3b20 MT |
1240 | |
1241 | pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH); | |
1242 | for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { | |
1243 | unsigned long np; | |
1244 | ||
1245 | np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); | |
1246 | if (np) | |
1247 | pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np); | |
1248 | ||
1249 | uv_pb += hweight64(np); | |
1250 | } | |
1251 | if (uv_possible_blades != uv_pb) | |
1252 | uv_possible_blades = uv_pb; | |
906f3b20 MT |
1253 | } |
1254 | ||
6e27b91c MT |
1255 | static void __init build_socket_tables(void) |
1256 | { | |
1257 | struct uv_gam_range_entry *gre = uv_gre_table; | |
1258 | int num, nump; | |
1259 | int cpu, i, lnid; | |
1260 | int minsock = _min_socket; | |
1261 | int maxsock = _max_socket; | |
1262 | int minpnode = _min_pnode; | |
1263 | int maxpnode = _max_pnode; | |
1264 | size_t bytes; | |
1265 | ||
1266 | if (!gre) { | |
1267 | if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) { | |
1268 | pr_info("UV: No UVsystab socket table, ignoring\n"); | |
1269 | return; /* not required */ | |
1270 | } | |
1271 | pr_crit( | |
1272 | "UV: Error: UVsystab address translations not available!\n"); | |
1273 | BUG(); | |
1274 | } | |
1275 | ||
1276 | /* build socket id -> node id, pnode */ | |
1277 | num = maxsock - minsock + 1; | |
1278 | bytes = num * sizeof(_socket_to_node[0]); | |
1279 | _socket_to_node = kmalloc(bytes, GFP_KERNEL); | |
1280 | _socket_to_pnode = kmalloc(bytes, GFP_KERNEL); | |
1281 | ||
1282 | nump = maxpnode - minpnode + 1; | |
1283 | bytes = nump * sizeof(_pnode_to_socket[0]); | |
1284 | _pnode_to_socket = kmalloc(bytes, GFP_KERNEL); | |
1285 | BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket); | |
1286 | ||
1287 | for (i = 0; i < num; i++) | |
1288 | _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY; | |
1289 | ||
1290 | for (i = 0; i < nump; i++) | |
1291 | _pnode_to_socket[i] = SOCK_EMPTY; | |
1292 | ||
1293 | /* fill in pnode/node/addr conversion list values */ | |
22ac2bca | 1294 | pr_info("UV: GAM Building socket/pnode conversion tables\n"); |
6e27b91c MT |
1295 | for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { |
1296 | if (gre->type == UV_GAM_RANGE_TYPE_HOLE) | |
1297 | continue; | |
1298 | i = gre->sockid - minsock; | |
1299 | if (_socket_to_pnode[i] != SOCK_EMPTY) | |
1300 | continue; /* duplicate */ | |
1301 | _socket_to_pnode[i] = gre->pnode; | |
6e27b91c MT |
1302 | |
1303 | i = gre->pnode - minpnode; | |
1304 | _pnode_to_socket[i] = gre->sockid; | |
1305 | ||
1306 | pr_info( | |
22ac2bca | 1307 | "UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n", |
6e27b91c MT |
1308 | gre->sockid, gre->type, gre->nasid, |
1309 | _socket_to_pnode[gre->sockid - minsock], | |
6e27b91c MT |
1310 | _pnode_to_socket[gre->pnode - minpnode]); |
1311 | } | |
1312 | ||
22ac2bca | 1313 | /* Set socket -> node values */ |
6e27b91c MT |
1314 | lnid = -1; |
1315 | for_each_present_cpu(cpu) { | |
1316 | int nid = cpu_to_node(cpu); | |
1317 | int apicid, sockid; | |
1318 | ||
1319 | if (lnid == nid) | |
1320 | continue; | |
1321 | lnid = nid; | |
1322 | apicid = per_cpu(x86_cpu_to_apicid, cpu); | |
1323 | sockid = apicid >> uv_cpuid.socketid_shift; | |
22ac2bca MT |
1324 | _socket_to_node[sockid - minsock] = nid; |
1325 | pr_info("UV: sid:%02x: apicid:%04x node:%2d\n", | |
1326 | sockid, apicid, nid); | |
6e27b91c MT |
1327 | } |
1328 | ||
1329 | /* Setup physical blade to pnode translation from GAM Range Table */ | |
1330 | bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]); | |
1331 | _node_to_pnode = kmalloc(bytes, GFP_KERNEL); | |
1332 | BUG_ON(!_node_to_pnode); | |
1333 | ||
1334 | for (lnid = 0; lnid < num_possible_nodes(); lnid++) { | |
1335 | unsigned short sockid; | |
1336 | ||
1337 | for (sockid = minsock; sockid <= maxsock; sockid++) { | |
1338 | if (lnid == _socket_to_node[sockid - minsock]) { | |
1339 | _node_to_pnode[lnid] = | |
1340 | _socket_to_pnode[sockid - minsock]; | |
1341 | break; | |
1342 | } | |
1343 | } | |
1344 | if (sockid > maxsock) { | |
1345 | pr_err("UV: socket for node %d not found!\n", lnid); | |
1346 | BUG(); | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | /* | |
1351 | * If socket id == pnode or socket id == node for all nodes, | |
1352 | * system runs faster by removing corresponding conversion table. | |
1353 | */ | |
1354 | pr_info("UV: Checking socket->node/pnode for identity maps\n"); | |
1355 | if (minsock == 0) { | |
1356 | for (i = 0; i < num; i++) | |
1357 | if (_socket_to_node[i] == SOCK_EMPTY || | |
1358 | i != _socket_to_node[i]) | |
1359 | break; | |
1360 | if (i >= num) { | |
1361 | kfree(_socket_to_node); | |
1362 | _socket_to_node = NULL; | |
1363 | pr_info("UV: 1:1 socket_to_node table removed\n"); | |
1364 | } | |
1365 | } | |
1366 | if (minsock == minpnode) { | |
1367 | for (i = 0; i < num; i++) | |
1368 | if (_socket_to_pnode[i] != SOCK_EMPTY && | |
1369 | _socket_to_pnode[i] != i + minpnode) | |
1370 | break; | |
1371 | if (i >= num) { | |
1372 | kfree(_socket_to_pnode); | |
1373 | _socket_to_pnode = NULL; | |
1374 | pr_info("UV: 1:1 socket_to_pnode table removed\n"); | |
1375 | } | |
1376 | } | |
1377 | } | |
1378 | ||
c443c03d MT |
1379 | void __init uv_system_init(void) |
1380 | { | |
1381 | struct uv_hub_info_s hub_info = {0}; | |
906f3b20 MT |
1382 | int bytes, cpu, nodeid; |
1383 | unsigned short min_pnode = 9999, max_pnode = 0; | |
a0ec83f3 MT |
1384 | char *hub = is_uv4_hub() ? "UV400" : |
1385 | is_uv3_hub() ? "UV300" : | |
1386 | is_uv2_hub() ? "UV2000/3000" : | |
1387 | is_uv1_hub() ? "UV100/1000" : NULL; | |
ac23d4ee | 1388 | |
1912c7af MT |
1389 | if (!hub) { |
1390 | pr_err("UV: Unknown/unsupported UV hub\n"); | |
1391 | return; | |
1392 | } | |
b15cc4a1 | 1393 | pr_info("UV: Found %s hub\n", hub); |
d394f2d9 | 1394 | |
3cd0b535 | 1395 | map_low_mmrs(); |
918bc960 | 1396 | |
1de329c1 MT |
1397 | uv_bios_init(); /* get uv_systab for decoding */ |
1398 | decode_uv_systab(); | |
6e27b91c | 1399 | build_socket_tables(); |
c85375cd | 1400 | build_uv_gr_table(); |
c443c03d | 1401 | uv_init_hub_info(&hub_info); |
906f3b20 MT |
1402 | uv_possible_blades = num_possible_nodes(); |
1403 | if (!_node_to_pnode) | |
1404 | boot_init_possible_blades(&hub_info); | |
da517a08 JS |
1405 | |
1406 | /* uv_num_possible_blades() is really the hub count */ | |
0045ddd2 MT |
1407 | pr_info("UV: Found %d hubs, %d nodes, %d cpus\n", |
1408 | uv_num_possible_blades(), | |
1409 | num_possible_nodes(), | |
1410 | num_possible_cpus()); | |
ac23d4ee | 1411 | |
b76365a1 RA |
1412 | uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, |
1413 | &sn_region_size, &system_serial_number); | |
c443c03d | 1414 | hub_info.coherency_domain_number = sn_coherency_id; |
7019cc2d RA |
1415 | uv_rtc_init(); |
1416 | ||
906f3b20 MT |
1417 | bytes = sizeof(void *) * uv_num_possible_blades(); |
1418 | __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL); | |
1419 | BUG_ON(!__uv_hub_info_list); | |
39d30770 | 1420 | |
906f3b20 MT |
1421 | bytes = sizeof(struct uv_hub_info_s); |
1422 | for_each_node(nodeid) { | |
1423 | struct uv_hub_info_s *new_hub; | |
906f3b20 MT |
1424 | |
1425 | if (__uv_hub_info_list[nodeid]) { | |
1426 | pr_err("UV: Node %d UV HUB already initialized!?\n", | |
1427 | nodeid); | |
1428 | BUG(); | |
3edcf2ff | 1429 | } |
9f5314fb | 1430 | |
906f3b20 MT |
1431 | /* Allocate new per hub info list */ |
1432 | new_hub = (nodeid == 0) ? | |
1433 | &uv_hub_info_node0 : | |
1434 | kzalloc_node(bytes, GFP_KERNEL, nodeid); | |
1435 | BUG_ON(!new_hub); | |
1436 | __uv_hub_info_list[nodeid] = new_hub; | |
1437 | new_hub = uv_hub_info_list(nodeid); | |
1438 | BUG_ON(!new_hub); | |
1439 | *new_hub = hub_info; | |
1440 | ||
f68376fc DS |
1441 | /* Use information from GAM table if available */ |
1442 | if (_node_to_pnode) | |
1443 | new_hub->pnode = _node_to_pnode[nodeid]; | |
1444 | else /* Fill in during cpu loop */ | |
1445 | new_hub->pnode = 0xffff; | |
906f3b20 MT |
1446 | new_hub->numa_blade_id = uv_node_to_blade_id(nodeid); |
1447 | new_hub->memory_nid = -1; | |
1448 | new_hub->nr_possible_cpus = 0; | |
1449 | new_hub->nr_online_cpus = 0; | |
1450 | } | |
6c7184b7 | 1451 | |
906f3b20 MT |
1452 | /* Initialize per cpu info */ |
1453 | for_each_possible_cpu(cpu) { | |
1454 | int apicid = per_cpu(x86_cpu_to_apicid, cpu); | |
f68376fc DS |
1455 | int numa_node_id; |
1456 | unsigned short pnode; | |
0045ddd2 | 1457 | |
906f3b20 | 1458 | nodeid = cpu_to_node(cpu); |
f68376fc DS |
1459 | numa_node_id = numa_cpu_node(cpu); |
1460 | pnode = uv_apicid_to_pnode(apicid); | |
1461 | ||
3edcf2ff | 1462 | uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid); |
3edcf2ff | 1463 | uv_cpu_info_per(cpu)->blade_cpu_id = |
906f3b20 MT |
1464 | uv_cpu_hub_info(cpu)->nr_possible_cpus++; |
1465 | if (uv_cpu_hub_info(cpu)->memory_nid == -1) | |
1466 | uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu); | |
f68376fc DS |
1467 | if (nodeid != numa_node_id && /* init memoryless node */ |
1468 | uv_hub_info_list(numa_node_id)->pnode == 0xffff) | |
1469 | uv_hub_info_list(numa_node_id)->pnode = pnode; | |
1470 | else if (uv_cpu_hub_info(cpu)->pnode == 0xffff) | |
1471 | uv_cpu_hub_info(cpu)->pnode = pnode; | |
906f3b20 | 1472 | uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid); |
ac23d4ee | 1473 | } |
83f5d894 | 1474 | |
906f3b20 | 1475 | for_each_node(nodeid) { |
f68376fc DS |
1476 | unsigned short pnode = uv_hub_info_list(nodeid)->pnode; |
1477 | ||
1478 | /* Add pnode info for pre-GAM list nodes without cpus */ | |
1479 | if (pnode == 0xffff) { | |
1480 | unsigned long paddr; | |
1481 | ||
1482 | paddr = node_start_pfn(nodeid) << PAGE_SHIFT; | |
1483 | pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); | |
1484 | uv_hub_info_list(nodeid)->pnode = pnode; | |
1485 | } | |
1486 | min_pnode = min(pnode, min_pnode); | |
1487 | max_pnode = max(pnode, max_pnode); | |
906f3b20 MT |
1488 | pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n", |
1489 | nodeid, | |
1490 | uv_hub_info_list(nodeid)->pnode, | |
1491 | uv_hub_info_list(nodeid)->nr_possible_cpus); | |
6a891a24 JS |
1492 | } |
1493 | ||
906f3b20 | 1494 | pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode); |
83f5d894 | 1495 | map_gru_high(max_pnode); |
daf7b9c9 | 1496 | map_mmr_high(max_pnode); |
b15cc4a1 | 1497 | map_mmioh_high(min_pnode, max_pnode); |
ac23d4ee | 1498 | |
0d12ef0c | 1499 | uv_nmi_setup(); |
8da077d6 | 1500 | uv_cpu_init(); |
7f1baa06 | 1501 | uv_scir_register_cpu_notifier(); |
a3d732f9 | 1502 | proc_mkdir("sgi_uv", NULL); |
841582ea MT |
1503 | |
1504 | /* register Legacy VGA I/O redirection handler */ | |
1505 | pci_register_set_vga_state(uv_set_vga_state); | |
818987e9 CW |
1506 | |
1507 | /* | |
1508 | * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as | |
1509 | * EFI is not enabled in the kdump kernel. | |
1510 | */ | |
1511 | if (is_kdump_kernel()) | |
1512 | reboot_type = BOOT_ACPI; | |
ac23d4ee | 1513 | } |
107e0e0c SS |
1514 | |
1515 | apic_driver(apic_x2apic_uv_x); |