Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
773763df | 27 | #include <linux/cpu.h> |
ba7eda4c | 28 | #include <linux/clockchips.h> |
70a20025 | 29 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 30 | #include <linux/module.h> |
773763df | 31 | #include <linux/dmi.h> |
6e1cb38a | 32 | #include <linux/dmar.h> |
bcbc4f20 | 33 | #include <linux/ftrace.h> |
e423e33e JSR |
34 | #include <linux/smp.h> |
35 | #include <linux/nmi.h> | |
36 | #include <linux/timex.h> | |
1da177e4 LT |
37 | |
38 | #include <asm/atomic.h> | |
1da177e4 LT |
39 | #include <asm/mtrr.h> |
40 | #include <asm/mpspec.h> | |
efa2559f | 41 | #include <asm/desc.h> |
773763df | 42 | #include <asm/arch_hooks.h> |
e83a5fdc | 43 | #include <asm/hpet.h> |
1da177e4 | 44 | #include <asm/pgalloc.h> |
773763df | 45 | #include <asm/i8253.h> |
95833c83 | 46 | #include <asm/idle.h> |
73dea47f | 47 | #include <asm/proto.h> |
2c8c0e6b | 48 | #include <asm/apic.h> |
6e1cb38a | 49 | #include <asm/i8259.h> |
2bc13797 | 50 | #include <asm/smp.h> |
1da177e4 | 51 | |
dd46e3ca | 52 | #include <mach_apic.h> |
773763df YL |
53 | #include <mach_apicdef.h> |
54 | #include <mach_ipi.h> | |
5af5573e | 55 | |
80e5609c CG |
56 | /* |
57 | * Sanity check | |
58 | */ | |
59 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | |
60 | # error SPURIOUS_APIC_VECTOR definition error | |
61 | #endif | |
62 | ||
b3c51170 YL |
63 | #ifdef CONFIG_X86_32 |
64 | /* | |
65 | * Knob to control our willingness to enable the local APIC. | |
66 | * | |
67 | * +1=force-enable | |
68 | */ | |
69 | static int force_enable_local_apic; | |
70 | /* | |
71 | * APIC command line parameters | |
72 | */ | |
73 | static int __init parse_lapic(char *arg) | |
74 | { | |
75 | force_enable_local_apic = 1; | |
76 | return 0; | |
77 | } | |
78 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
79 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
80 | static int enabled_via_apicbase; | |
81 | ||
b3c51170 YL |
82 | #endif |
83 | ||
84 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 85 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
86 | static __init int setup_apicpmtimer(char *s) |
87 | { | |
88 | apic_calibrate_pmtmr = 1; | |
89 | notsc_setup(NULL); | |
90 | return 0; | |
91 | } | |
92 | __setup("apicpmtimer", setup_apicpmtimer); | |
93 | #endif | |
94 | ||
49899eac YL |
95 | #ifdef CONFIG_X86_64 |
96 | #define HAVE_X2APIC | |
97 | #endif | |
98 | ||
99 | #ifdef HAVE_X2APIC | |
89027d35 | 100 | int x2apic; |
6e1cb38a | 101 | /* x2apic enabled before OS handover */ |
b6b301aa JS |
102 | static int x2apic_preenabled; |
103 | static int disable_x2apic; | |
49899eac YL |
104 | static __init int setup_nox2apic(char *str) |
105 | { | |
106 | disable_x2apic = 1; | |
107 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
108 | return 0; | |
109 | } | |
110 | early_param("nox2apic", setup_nox2apic); | |
111 | #endif | |
1da177e4 | 112 | |
b3c51170 YL |
113 | unsigned long mp_lapic_addr; |
114 | int disable_apic; | |
115 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
116 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 117 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
118 | int local_apic_timer_c2_ok; |
119 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
120 | ||
efa2559f YL |
121 | int first_system_vector = 0xfe; |
122 | ||
e83a5fdc HS |
123 | /* |
124 | * Debug level, exported for io_apic.c | |
125 | */ | |
baa13188 | 126 | unsigned int apic_verbosity; |
e83a5fdc | 127 | |
89c38c28 CG |
128 | int pic_mode; |
129 | ||
bab4b27c AS |
130 | /* Have we found an MP table */ |
131 | int smp_found_config; | |
132 | ||
39928722 AD |
133 | static struct resource lapic_resource = { |
134 | .name = "Local APIC", | |
135 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
136 | }; | |
137 | ||
d03030e9 TG |
138 | static unsigned int calibration_result; |
139 | ||
ba7eda4c TG |
140 | static int lapic_next_event(unsigned long delta, |
141 | struct clock_event_device *evt); | |
142 | static void lapic_timer_setup(enum clock_event_mode mode, | |
143 | struct clock_event_device *evt); | |
9628937d | 144 | static void lapic_timer_broadcast(const struct cpumask *mask); |
0e078e2f | 145 | static void apic_pm_activate(void); |
ba7eda4c | 146 | |
274cfe59 CG |
147 | /* |
148 | * The local apic timer can be used for any function which is CPU local. | |
149 | */ | |
ba7eda4c TG |
150 | static struct clock_event_device lapic_clockevent = { |
151 | .name = "lapic", | |
152 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
153 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
154 | .shift = 32, | |
155 | .set_mode = lapic_timer_setup, | |
156 | .set_next_event = lapic_next_event, | |
157 | .broadcast = lapic_timer_broadcast, | |
158 | .rating = 100, | |
159 | .irq = -1, | |
160 | }; | |
161 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
162 | ||
d3432896 AK |
163 | static unsigned long apic_phys; |
164 | ||
0e078e2f TG |
165 | /* |
166 | * Get the LAPIC version | |
167 | */ | |
168 | static inline int lapic_get_version(void) | |
ba7eda4c | 169 | { |
0e078e2f | 170 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
171 | } |
172 | ||
0e078e2f | 173 | /* |
9c803869 | 174 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
175 | */ |
176 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 177 | { |
9c803869 | 178 | #ifdef CONFIG_X86_64 |
0e078e2f | 179 | return 1; |
9c803869 CG |
180 | #else |
181 | return APIC_INTEGRATED(lapic_get_version()); | |
182 | #endif | |
ba7eda4c TG |
183 | } |
184 | ||
185 | /* | |
0e078e2f | 186 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 187 | */ |
0e078e2f | 188 | static int modern_apic(void) |
ba7eda4c | 189 | { |
0e078e2f TG |
190 | /* AMD systems use old APIC versions, so check the CPU */ |
191 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
192 | boot_cpu_data.x86 >= 0xf) | |
193 | return 1; | |
194 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
195 | } |
196 | ||
274cfe59 CG |
197 | /* |
198 | * Paravirt kernels also might be using these below ops. So we still | |
199 | * use generic apic_read()/apic_write(), which might be pointing to different | |
200 | * ops in PARAVIRT case. | |
201 | */ | |
1b374e4d | 202 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
203 | { |
204 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
205 | cpu_relax(); | |
206 | } | |
207 | ||
1b374e4d | 208 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 209 | { |
3c6bb07a | 210 | u32 send_status; |
8339e9fb FLV |
211 | int timeout; |
212 | ||
213 | timeout = 0; | |
214 | do { | |
215 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
216 | if (!send_status) | |
217 | break; | |
218 | udelay(100); | |
219 | } while (timeout++ < 1000); | |
220 | ||
221 | return send_status; | |
222 | } | |
223 | ||
1b374e4d SS |
224 | void xapic_icr_write(u32 low, u32 id) |
225 | { | |
ed4e5ec1 | 226 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
227 | apic_write(APIC_ICR, low); |
228 | } | |
229 | ||
ec8c842a | 230 | static u64 xapic_icr_read(void) |
1b374e4d SS |
231 | { |
232 | u32 icr1, icr2; | |
233 | ||
234 | icr2 = apic_read(APIC_ICR2); | |
235 | icr1 = apic_read(APIC_ICR); | |
236 | ||
cf9768d7 | 237 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
238 | } |
239 | ||
240 | static struct apic_ops xapic_ops = { | |
241 | .read = native_apic_mem_read, | |
242 | .write = native_apic_mem_write, | |
1b374e4d SS |
243 | .icr_read = xapic_icr_read, |
244 | .icr_write = xapic_icr_write, | |
245 | .wait_icr_idle = xapic_wait_icr_idle, | |
246 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
247 | }; | |
248 | ||
249 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
250 | EXPORT_SYMBOL_GPL(apic_ops); |
251 | ||
49899eac | 252 | #ifdef HAVE_X2APIC |
13c88fb5 SS |
253 | static void x2apic_wait_icr_idle(void) |
254 | { | |
255 | /* no need to wait for icr idle in x2apic */ | |
256 | return; | |
257 | } | |
258 | ||
259 | static u32 safe_x2apic_wait_icr_idle(void) | |
260 | { | |
261 | /* no need to wait for icr idle in x2apic */ | |
262 | return 0; | |
263 | } | |
264 | ||
265 | void x2apic_icr_write(u32 low, u32 id) | |
266 | { | |
267 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
268 | } | |
269 | ||
ec8c842a | 270 | static u64 x2apic_icr_read(void) |
13c88fb5 SS |
271 | { |
272 | unsigned long val; | |
273 | ||
274 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
275 | return val; | |
276 | } | |
277 | ||
278 | static struct apic_ops x2apic_ops = { | |
279 | .read = native_apic_msr_read, | |
280 | .write = native_apic_msr_write, | |
13c88fb5 SS |
281 | .icr_read = x2apic_icr_read, |
282 | .icr_write = x2apic_icr_write, | |
283 | .wait_icr_idle = x2apic_wait_icr_idle, | |
284 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
285 | }; | |
49899eac | 286 | #endif |
13c88fb5 | 287 | |
0e078e2f TG |
288 | /** |
289 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
290 | */ | |
e9427101 | 291 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 292 | { |
11a8e778 | 293 | unsigned int v; |
6935d1f9 TG |
294 | |
295 | /* unmask and set to NMI */ | |
296 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
297 | |
298 | /* Level triggered for 82489DX (32bit mode) */ | |
299 | if (!lapic_is_integrated()) | |
300 | v |= APIC_LVT_LEVEL_TRIGGER; | |
301 | ||
11a8e778 | 302 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
303 | } |
304 | ||
7c37e48b CG |
305 | #ifdef CONFIG_X86_32 |
306 | /** | |
307 | * get_physical_broadcast - Get number of physical broadcast IDs | |
308 | */ | |
309 | int get_physical_broadcast(void) | |
310 | { | |
311 | return modern_apic() ? 0xff : 0xf; | |
312 | } | |
313 | #endif | |
314 | ||
0e078e2f TG |
315 | /** |
316 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
317 | */ | |
37e650c7 | 318 | int lapic_get_maxlvt(void) |
1da177e4 | 319 | { |
36a028de | 320 | unsigned int v; |
1da177e4 LT |
321 | |
322 | v = apic_read(APIC_LVR); | |
36a028de CG |
323 | /* |
324 | * - we always have APIC integrated on 64bit mode | |
325 | * - 82489DXs do not report # of LVT entries | |
326 | */ | |
327 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
328 | } |
329 | ||
274cfe59 CG |
330 | /* |
331 | * Local APIC timer | |
332 | */ | |
333 | ||
c40aaec6 | 334 | /* Clock divisor */ |
c40aaec6 | 335 | #define APIC_DIVISOR 16 |
f07f4f90 | 336 | |
0e078e2f TG |
337 | /* |
338 | * This function sets up the local APIC timer, with a timeout of | |
339 | * 'clocks' APIC bus clock. During calibration we actually call | |
340 | * this function twice on the boot CPU, once with a bogus timeout | |
341 | * value, second time for real. The other (noncalibrating) CPUs | |
342 | * call this function only once, with the real, calibrated value. | |
343 | * | |
344 | * We do reads before writes even if unnecessary, to get around the | |
345 | * P5 APIC double write bug. | |
346 | */ | |
0e078e2f | 347 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 348 | { |
0e078e2f | 349 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 350 | |
0e078e2f TG |
351 | lvtt_value = LOCAL_TIMER_VECTOR; |
352 | if (!oneshot) | |
353 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
354 | if (!lapic_is_integrated()) |
355 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
356 | ||
0e078e2f TG |
357 | if (!irqen) |
358 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 359 | |
0e078e2f | 360 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
361 | |
362 | /* | |
0e078e2f | 363 | * Divide PICLK by 16 |
1da177e4 | 364 | */ |
0e078e2f | 365 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
366 | apic_write(APIC_TDCR, |
367 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
368 | APIC_TDR_DIV_16); | |
0e078e2f TG |
369 | |
370 | if (!oneshot) | |
f07f4f90 | 371 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
372 | } |
373 | ||
0e078e2f | 374 | /* |
7b83dae7 RR |
375 | * Setup extended LVT, AMD specific (K8, family 10h) |
376 | * | |
377 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
378 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
379 | * |
380 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
381 | * enables the vector. See also the BKDGs. | |
0e078e2f | 382 | */ |
7b83dae7 RR |
383 | |
384 | #define APIC_EILVT_LVTOFF_MCE 0 | |
385 | #define APIC_EILVT_LVTOFF_IBS 1 | |
386 | ||
387 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 388 | { |
7b83dae7 | 389 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 390 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 391 | |
0e078e2f | 392 | apic_write(reg, v); |
1da177e4 LT |
393 | } |
394 | ||
7b83dae7 RR |
395 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
396 | { | |
397 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
398 | return APIC_EILVT_LVTOFF_MCE; | |
399 | } | |
400 | ||
401 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
402 | { | |
403 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
404 | return APIC_EILVT_LVTOFF_IBS; | |
405 | } | |
6aa360e6 | 406 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 407 | |
0e078e2f TG |
408 | /* |
409 | * Program the next event, relative to now | |
410 | */ | |
411 | static int lapic_next_event(unsigned long delta, | |
412 | struct clock_event_device *evt) | |
1da177e4 | 413 | { |
0e078e2f TG |
414 | apic_write(APIC_TMICT, delta); |
415 | return 0; | |
1da177e4 LT |
416 | } |
417 | ||
0e078e2f TG |
418 | /* |
419 | * Setup the lapic timer in periodic or oneshot mode | |
420 | */ | |
421 | static void lapic_timer_setup(enum clock_event_mode mode, | |
422 | struct clock_event_device *evt) | |
9b7711f0 HS |
423 | { |
424 | unsigned long flags; | |
0e078e2f | 425 | unsigned int v; |
9b7711f0 | 426 | |
0e078e2f TG |
427 | /* Lapic used as dummy for broadcast ? */ |
428 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
429 | return; |
430 | ||
431 | local_irq_save(flags); | |
432 | ||
0e078e2f TG |
433 | switch (mode) { |
434 | case CLOCK_EVT_MODE_PERIODIC: | |
435 | case CLOCK_EVT_MODE_ONESHOT: | |
436 | __setup_APIC_LVTT(calibration_result, | |
437 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
438 | break; | |
439 | case CLOCK_EVT_MODE_UNUSED: | |
440 | case CLOCK_EVT_MODE_SHUTDOWN: | |
441 | v = apic_read(APIC_LVTT); | |
442 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
443 | apic_write(APIC_LVTT, v); | |
a98f8fd2 | 444 | apic_write(APIC_TMICT, 0xffffffff); |
0e078e2f TG |
445 | break; |
446 | case CLOCK_EVT_MODE_RESUME: | |
447 | /* Nothing to do here */ | |
448 | break; | |
449 | } | |
9b7711f0 HS |
450 | |
451 | local_irq_restore(flags); | |
452 | } | |
453 | ||
1da177e4 | 454 | /* |
0e078e2f | 455 | * Local APIC timer broadcast function |
1da177e4 | 456 | */ |
9628937d | 457 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 458 | { |
0e078e2f TG |
459 | #ifdef CONFIG_SMP |
460 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
461 | #endif | |
462 | } | |
1da177e4 | 463 | |
0e078e2f TG |
464 | /* |
465 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
466 | * of the boot CPU and register the clock event in the framework. | |
467 | */ | |
db4b5525 | 468 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
469 | { |
470 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 471 | |
0e078e2f | 472 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 473 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 474 | |
0e078e2f TG |
475 | clockevents_register_device(levt); |
476 | } | |
1da177e4 | 477 | |
2f04fa88 YL |
478 | /* |
479 | * In this functions we calibrate APIC bus clocks to the external timer. | |
480 | * | |
481 | * We want to do the calibration only once since we want to have local timer | |
482 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
483 | * frequency. | |
484 | * | |
485 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
486 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
487 | * readout is broken, so it never gets out of the wait loop again. This was | |
488 | * also reported by others. | |
489 | * | |
490 | * Monitoring the jiffies value is inaccurate and the clockevents | |
491 | * infrastructure allows us to do a simple substitution of the interrupt | |
492 | * handler. | |
493 | * | |
494 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
495 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
496 | * back to normal later in the boot process). | |
497 | */ | |
498 | ||
499 | #define LAPIC_CAL_LOOPS (HZ/10) | |
500 | ||
501 | static __initdata int lapic_cal_loops = -1; | |
502 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
503 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
504 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
505 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
506 | ||
507 | /* | |
508 | * Temporary interrupt handler. | |
509 | */ | |
510 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
511 | { | |
512 | unsigned long long tsc = 0; | |
513 | long tapic = apic_read(APIC_TMCCT); | |
514 | unsigned long pm = acpi_pm_read_early(); | |
515 | ||
516 | if (cpu_has_tsc) | |
517 | rdtscll(tsc); | |
518 | ||
519 | switch (lapic_cal_loops++) { | |
520 | case 0: | |
521 | lapic_cal_t1 = tapic; | |
522 | lapic_cal_tsc1 = tsc; | |
523 | lapic_cal_pm1 = pm; | |
524 | lapic_cal_j1 = jiffies; | |
525 | break; | |
526 | ||
527 | case LAPIC_CAL_LOOPS: | |
528 | lapic_cal_t2 = tapic; | |
529 | lapic_cal_tsc2 = tsc; | |
530 | if (pm < lapic_cal_pm1) | |
531 | pm += ACPI_PM_OVRRUN; | |
532 | lapic_cal_pm2 = pm; | |
533 | lapic_cal_j2 = jiffies; | |
534 | break; | |
535 | } | |
536 | } | |
537 | ||
754ef0cd YI |
538 | static int __init |
539 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
540 | { |
541 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
542 | const long pm_thresh = pm_100ms / 100; | |
543 | unsigned long mult; | |
544 | u64 res; | |
545 | ||
546 | #ifndef CONFIG_X86_PM_TIMER | |
547 | return -1; | |
548 | #endif | |
549 | ||
550 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
551 | ||
552 | /* Check, if the PM timer is available */ | |
553 | if (!deltapm) | |
554 | return -1; | |
555 | ||
556 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
557 | ||
558 | if (deltapm > (pm_100ms - pm_thresh) && | |
559 | deltapm < (pm_100ms + pm_thresh)) { | |
560 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
754ef0cd YI |
561 | return 0; |
562 | } | |
563 | ||
564 | res = (((u64)deltapm) * mult) >> 22; | |
565 | do_div(res, 1000000); | |
566 | pr_warning("APIC calibration not consistent " | |
567 | "with PM Timer: %ldms instead of 100ms\n",(long)res); | |
568 | ||
569 | /* Correct the lapic counter value */ | |
570 | res = (((u64)(*delta)) * pm_100ms); | |
571 | do_div(res, deltapm); | |
572 | pr_info("APIC delta adjusted to PM-Timer: " | |
573 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
574 | *delta = (long)res; | |
575 | ||
576 | /* Correct the tsc counter value */ | |
577 | if (cpu_has_tsc) { | |
578 | res = (((u64)(*deltatsc)) * pm_100ms); | |
b189892d | 579 | do_div(res, deltapm); |
754ef0cd YI |
580 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
581 | "PM-Timer: %lu (%ld) \n", | |
582 | (unsigned long)res, *deltatsc); | |
583 | *deltatsc = (long)res; | |
b189892d CG |
584 | } |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
2f04fa88 YL |
589 | static int __init calibrate_APIC_clock(void) |
590 | { | |
591 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
592 | void (*real_handler)(struct clock_event_device *dev); |
593 | unsigned long deltaj; | |
754ef0cd | 594 | long delta, deltatsc; |
2f04fa88 YL |
595 | int pm_referenced = 0; |
596 | ||
597 | local_irq_disable(); | |
598 | ||
599 | /* Replace the global interrupt handler */ | |
600 | real_handler = global_clock_event->event_handler; | |
601 | global_clock_event->event_handler = lapic_cal_handler; | |
602 | ||
603 | /* | |
81608f3c | 604 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
605 | * can underflow in the 100ms detection time frame |
606 | */ | |
81608f3c | 607 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
608 | |
609 | /* Let the interrupts run */ | |
610 | local_irq_enable(); | |
611 | ||
612 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
613 | cpu_relax(); | |
614 | ||
615 | local_irq_disable(); | |
616 | ||
617 | /* Restore the real event handler */ | |
618 | global_clock_event->event_handler = real_handler; | |
619 | ||
620 | /* Build delta t1-t2 as apic timer counts down */ | |
621 | delta = lapic_cal_t1 - lapic_cal_t2; | |
622 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
623 | ||
754ef0cd YI |
624 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
625 | ||
b189892d CG |
626 | /* we trust the PM based calibration if possible */ |
627 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 628 | &delta, &deltatsc); |
2f04fa88 YL |
629 | |
630 | /* Calculate the scaled math multiplication factor */ | |
631 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
632 | lapic_clockevent.shift); | |
633 | lapic_clockevent.max_delta_ns = | |
634 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
635 | lapic_clockevent.min_delta_ns = | |
636 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
637 | ||
638 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; | |
639 | ||
640 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
641 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); | |
642 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", | |
643 | calibration_result); | |
644 | ||
645 | if (cpu_has_tsc) { | |
2f04fa88 YL |
646 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
647 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
648 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
649 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
650 | } |
651 | ||
652 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
653 | "%u.%04u MHz.\n", | |
654 | calibration_result / (1000000 / HZ), | |
655 | calibration_result % (1000000 / HZ)); | |
656 | ||
657 | /* | |
658 | * Do a sanity check on the APIC calibration result | |
659 | */ | |
660 | if (calibration_result < (1000000 / HZ)) { | |
661 | local_irq_enable(); | |
ba21ebb6 | 662 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
663 | return -1; |
664 | } | |
665 | ||
666 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
667 | ||
b189892d CG |
668 | /* |
669 | * PM timer calibration failed or not turned on | |
670 | * so lets try APIC timer based calibration | |
671 | */ | |
2f04fa88 YL |
672 | if (!pm_referenced) { |
673 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
674 | ||
675 | /* | |
676 | * Setup the apic timer manually | |
677 | */ | |
678 | levt->event_handler = lapic_cal_handler; | |
679 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
680 | lapic_cal_loops = -1; | |
681 | ||
682 | /* Let the interrupts run */ | |
683 | local_irq_enable(); | |
684 | ||
685 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
686 | cpu_relax(); | |
687 | ||
2f04fa88 YL |
688 | /* Stop the lapic timer */ |
689 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
690 | ||
2f04fa88 YL |
691 | /* Jiffies delta */ |
692 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
693 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
694 | ||
695 | /* Check, if the jiffies result is consistent */ | |
696 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
697 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
698 | else | |
699 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
700 | } else | |
701 | local_irq_enable(); | |
702 | ||
703 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 704 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
705 | return -1; |
706 | } | |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
e83a5fdc HS |
711 | /* |
712 | * Setup the boot APIC | |
713 | * | |
714 | * Calibrate and verify the result. | |
715 | */ | |
0e078e2f TG |
716 | void __init setup_boot_APIC_clock(void) |
717 | { | |
718 | /* | |
274cfe59 CG |
719 | * The local apic timer can be disabled via the kernel |
720 | * commandline or from the CPU detection code. Register the lapic | |
721 | * timer as a dummy clock event source on SMP systems, so the | |
722 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
723 | */ |
724 | if (disable_apic_timer) { | |
ba21ebb6 | 725 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 726 | /* No broadcast on UP ! */ |
9d09951d TG |
727 | if (num_possible_cpus() > 1) { |
728 | lapic_clockevent.mult = 1; | |
0e078e2f | 729 | setup_APIC_timer(); |
9d09951d | 730 | } |
0e078e2f TG |
731 | return; |
732 | } | |
733 | ||
274cfe59 CG |
734 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
735 | "calibrating APIC timer ...\n"); | |
736 | ||
89b3b1f4 | 737 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
738 | /* No broadcast on UP ! */ |
739 | if (num_possible_cpus() > 1) | |
740 | setup_APIC_timer(); | |
741 | return; | |
742 | } | |
743 | ||
0e078e2f TG |
744 | /* |
745 | * If nmi_watchdog is set to IO_APIC, we need the | |
746 | * PIT/HPET going. Otherwise register lapic as a dummy | |
747 | * device. | |
748 | */ | |
749 | if (nmi_watchdog != NMI_IO_APIC) | |
750 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
751 | else | |
ba21ebb6 | 752 | pr_warning("APIC timer registered as dummy," |
116f570e | 753 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 754 | |
274cfe59 | 755 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
756 | setup_APIC_timer(); |
757 | } | |
758 | ||
0e078e2f TG |
759 | void __cpuinit setup_secondary_APIC_clock(void) |
760 | { | |
0e078e2f TG |
761 | setup_APIC_timer(); |
762 | } | |
763 | ||
764 | /* | |
765 | * The guts of the apic timer interrupt | |
766 | */ | |
767 | static void local_apic_timer_interrupt(void) | |
768 | { | |
769 | int cpu = smp_processor_id(); | |
770 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
771 | ||
772 | /* | |
773 | * Normally we should not be here till LAPIC has been initialized but | |
774 | * in some cases like kdump, its possible that there is a pending LAPIC | |
775 | * timer interrupt from previous kernel's context and is delivered in | |
776 | * new kernel the moment interrupts are enabled. | |
777 | * | |
778 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
779 | * its possible that when we get here evt->event_handler is NULL. | |
780 | * Check for event_handler being NULL and discard the interrupt as | |
781 | * spurious. | |
782 | */ | |
783 | if (!evt->event_handler) { | |
ba21ebb6 | 784 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
785 | /* Switch it off */ |
786 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
787 | return; | |
788 | } | |
789 | ||
790 | /* | |
791 | * the NMI deadlock-detector uses this. | |
792 | */ | |
915b0d01 | 793 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
794 | |
795 | evt->event_handler(evt); | |
796 | } | |
797 | ||
798 | /* | |
799 | * Local APIC timer interrupt. This is the most natural way for doing | |
800 | * local interrupts, but local timer interrupts can be emulated by | |
801 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
802 | * | |
803 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
804 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
805 | */ | |
bcbc4f20 | 806 | void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
807 | { |
808 | struct pt_regs *old_regs = set_irq_regs(regs); | |
809 | ||
810 | /* | |
811 | * NOTE! We'd better ACK the irq immediately, | |
812 | * because timer handling can be slow. | |
813 | */ | |
814 | ack_APIC_irq(); | |
815 | /* | |
816 | * update_process_times() expects us to have done irq_enter(). | |
817 | * Besides, if we don't timer interrupts ignore the global | |
818 | * interrupt lock, which is the WrongThing (tm) to do. | |
819 | */ | |
820 | exit_idle(); | |
821 | irq_enter(); | |
822 | local_apic_timer_interrupt(); | |
823 | irq_exit(); | |
274cfe59 | 824 | |
0e078e2f TG |
825 | set_irq_regs(old_regs); |
826 | } | |
827 | ||
828 | int setup_profiling_timer(unsigned int multiplier) | |
829 | { | |
830 | return -EINVAL; | |
831 | } | |
832 | ||
0e078e2f TG |
833 | /* |
834 | * Local APIC start and shutdown | |
835 | */ | |
836 | ||
837 | /** | |
838 | * clear_local_APIC - shutdown the local APIC | |
839 | * | |
840 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
841 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
842 | * leftovers during boot. | |
843 | */ | |
844 | void clear_local_APIC(void) | |
845 | { | |
2584a82d | 846 | int maxlvt; |
0e078e2f TG |
847 | u32 v; |
848 | ||
d3432896 AK |
849 | /* APIC hasn't been mapped yet */ |
850 | if (!apic_phys) | |
851 | return; | |
852 | ||
853 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
854 | /* |
855 | * Masking an LVT entry can trigger a local APIC error | |
856 | * if the vector is zero. Mask LVTERR first to prevent this. | |
857 | */ | |
858 | if (maxlvt >= 3) { | |
859 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
860 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
861 | } | |
862 | /* | |
863 | * Careful: we have to set masks only first to deassert | |
864 | * any level-triggered sources. | |
865 | */ | |
866 | v = apic_read(APIC_LVTT); | |
867 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
868 | v = apic_read(APIC_LVT0); | |
869 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
870 | v = apic_read(APIC_LVT1); | |
871 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
872 | if (maxlvt >= 4) { | |
873 | v = apic_read(APIC_LVTPC); | |
874 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
875 | } | |
876 | ||
6764014b CG |
877 | /* lets not touch this if we didn't frob it */ |
878 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
879 | if (maxlvt >= 5) { | |
880 | v = apic_read(APIC_LVTTHMR); | |
881 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
882 | } | |
883 | #endif | |
0e078e2f TG |
884 | /* |
885 | * Clean APIC state for other OSs: | |
886 | */ | |
887 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
888 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
889 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
890 | if (maxlvt >= 3) | |
891 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
892 | if (maxlvt >= 4) | |
893 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
894 | |
895 | /* Integrated APIC (!82489DX) ? */ | |
896 | if (lapic_is_integrated()) { | |
897 | if (maxlvt > 3) | |
898 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
899 | apic_write(APIC_ESR, 0); | |
900 | apic_read(APIC_ESR); | |
901 | } | |
0e078e2f TG |
902 | } |
903 | ||
904 | /** | |
905 | * disable_local_APIC - clear and disable the local APIC | |
906 | */ | |
907 | void disable_local_APIC(void) | |
908 | { | |
909 | unsigned int value; | |
910 | ||
4a13ad0b JB |
911 | /* APIC hasn't been mapped yet */ |
912 | if (!apic_phys) | |
913 | return; | |
914 | ||
0e078e2f TG |
915 | clear_local_APIC(); |
916 | ||
917 | /* | |
918 | * Disable APIC (implies clearing of registers | |
919 | * for 82489DX!). | |
920 | */ | |
921 | value = apic_read(APIC_SPIV); | |
922 | value &= ~APIC_SPIV_APIC_ENABLED; | |
923 | apic_write(APIC_SPIV, value); | |
990b183e CG |
924 | |
925 | #ifdef CONFIG_X86_32 | |
926 | /* | |
927 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
928 | * restore the disabled state. | |
929 | */ | |
930 | if (enabled_via_apicbase) { | |
931 | unsigned int l, h; | |
932 | ||
933 | rdmsr(MSR_IA32_APICBASE, l, h); | |
934 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
935 | wrmsr(MSR_IA32_APICBASE, l, h); | |
936 | } | |
937 | #endif | |
0e078e2f TG |
938 | } |
939 | ||
fe4024dc CG |
940 | /* |
941 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
942 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
943 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
944 | * for the case where Linux didn't enable the LAPIC. | |
945 | */ | |
0e078e2f TG |
946 | void lapic_shutdown(void) |
947 | { | |
948 | unsigned long flags; | |
949 | ||
950 | if (!cpu_has_apic) | |
951 | return; | |
952 | ||
953 | local_irq_save(flags); | |
954 | ||
fe4024dc CG |
955 | #ifdef CONFIG_X86_32 |
956 | if (!enabled_via_apicbase) | |
957 | clear_local_APIC(); | |
958 | else | |
959 | #endif | |
960 | disable_local_APIC(); | |
961 | ||
0e078e2f TG |
962 | |
963 | local_irq_restore(flags); | |
964 | } | |
965 | ||
966 | /* | |
967 | * This is to verify that we're looking at a real local APIC. | |
968 | * Check these against your board if the CPUs aren't getting | |
969 | * started for no apparent reason. | |
970 | */ | |
971 | int __init verify_local_APIC(void) | |
972 | { | |
973 | unsigned int reg0, reg1; | |
974 | ||
975 | /* | |
976 | * The version register is read-only in a real APIC. | |
977 | */ | |
978 | reg0 = apic_read(APIC_LVR); | |
979 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
980 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
981 | reg1 = apic_read(APIC_LVR); | |
982 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
983 | ||
984 | /* | |
985 | * The two version reads above should print the same | |
986 | * numbers. If the second one is different, then we | |
987 | * poke at a non-APIC. | |
988 | */ | |
989 | if (reg1 != reg0) | |
990 | return 0; | |
991 | ||
992 | /* | |
993 | * Check if the version looks reasonably. | |
994 | */ | |
995 | reg1 = GET_APIC_VERSION(reg0); | |
996 | if (reg1 == 0x00 || reg1 == 0xff) | |
997 | return 0; | |
998 | reg1 = lapic_get_maxlvt(); | |
999 | if (reg1 < 0x02 || reg1 == 0xff) | |
1000 | return 0; | |
1001 | ||
1002 | /* | |
1003 | * The ID register is read/write in a real APIC. | |
1004 | */ | |
2d7a66d0 | 1005 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
1006 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
1007 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 1008 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
1009 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
1010 | apic_write(APIC_ID, reg0); | |
1011 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
1012 | return 0; | |
1013 | ||
1014 | /* | |
1da177e4 LT |
1015 | * The next two are just to see if we have sane values. |
1016 | * They're only really relevant if we're in Virtual Wire | |
1017 | * compatibility mode, but most boxes are anymore. | |
1018 | */ | |
1019 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1020 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1021 | reg1 = apic_read(APIC_LVT1); |
1022 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1023 | ||
1024 | return 1; | |
1025 | } | |
1026 | ||
0e078e2f TG |
1027 | /** |
1028 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1029 | */ | |
1da177e4 LT |
1030 | void __init sync_Arb_IDs(void) |
1031 | { | |
296cb951 CG |
1032 | /* |
1033 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1034 | * needed on AMD. | |
1035 | */ | |
1036 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1037 | return; |
1038 | ||
1039 | /* | |
1040 | * Wait for idle. | |
1041 | */ | |
1042 | apic_wait_icr_idle(); | |
1043 | ||
1044 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1045 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1046 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1047 | } |
1048 | ||
1da177e4 LT |
1049 | /* |
1050 | * An initial setup of the virtual wire mode. | |
1051 | */ | |
1052 | void __init init_bsp_APIC(void) | |
1053 | { | |
11a8e778 | 1054 | unsigned int value; |
1da177e4 LT |
1055 | |
1056 | /* | |
1057 | * Don't do the setup now if we have a SMP BIOS as the | |
1058 | * through-I/O-APIC virtual wire mode might be active. | |
1059 | */ | |
1060 | if (smp_found_config || !cpu_has_apic) | |
1061 | return; | |
1062 | ||
1da177e4 LT |
1063 | /* |
1064 | * Do not trust the local APIC being empty at bootup. | |
1065 | */ | |
1066 | clear_local_APIC(); | |
1067 | ||
1068 | /* | |
1069 | * Enable APIC. | |
1070 | */ | |
1071 | value = apic_read(APIC_SPIV); | |
1072 | value &= ~APIC_VECTOR_MASK; | |
1073 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1074 | |
1075 | #ifdef CONFIG_X86_32 | |
1076 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1077 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1078 | (boot_cpu_data.x86 == 15)) | |
1079 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1080 | else | |
1081 | #endif | |
1082 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1083 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1084 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1085 | |
1086 | /* | |
1087 | * Set up the virtual wire mode. | |
1088 | */ | |
11a8e778 | 1089 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1090 | value = APIC_DM_NMI; |
638c0411 CG |
1091 | if (!lapic_is_integrated()) /* 82489DX */ |
1092 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1093 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1094 | } |
1095 | ||
c43da2f5 CG |
1096 | static void __cpuinit lapic_setup_esr(void) |
1097 | { | |
9df08f10 CG |
1098 | unsigned int oldvalue, value, maxlvt; |
1099 | ||
1100 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1101 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1102 | return; |
1103 | } | |
c43da2f5 | 1104 | |
9df08f10 | 1105 | if (esr_disable) { |
c43da2f5 | 1106 | /* |
9df08f10 CG |
1107 | * Something untraceable is creating bad interrupts on |
1108 | * secondary quads ... for the moment, just leave the | |
1109 | * ESR disabled - we can't do anything useful with the | |
1110 | * errors anyway - mbligh | |
c43da2f5 | 1111 | */ |
ba21ebb6 | 1112 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1113 | return; |
c43da2f5 | 1114 | } |
9df08f10 CG |
1115 | |
1116 | maxlvt = lapic_get_maxlvt(); | |
1117 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1118 | apic_write(APIC_ESR, 0); | |
1119 | oldvalue = apic_read(APIC_ESR); | |
1120 | ||
1121 | /* enables sending errors */ | |
1122 | value = ERROR_APIC_VECTOR; | |
1123 | apic_write(APIC_LVTERR, value); | |
1124 | ||
1125 | /* | |
1126 | * spec says clear errors after enabling vector. | |
1127 | */ | |
1128 | if (maxlvt > 3) | |
1129 | apic_write(APIC_ESR, 0); | |
1130 | value = apic_read(APIC_ESR); | |
1131 | if (value != oldvalue) | |
1132 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1133 | "vector: 0x%08x after: 0x%08x\n", | |
1134 | oldvalue, value); | |
c43da2f5 CG |
1135 | } |
1136 | ||
1137 | ||
0e078e2f TG |
1138 | /** |
1139 | * setup_local_APIC - setup the local APIC | |
1140 | */ | |
1141 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 1142 | { |
739f33b3 | 1143 | unsigned int value; |
da7ed9f9 | 1144 | int i, j; |
1da177e4 | 1145 | |
89c38c28 CG |
1146 | #ifdef CONFIG_X86_32 |
1147 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08ad776e | 1148 | if (lapic_is_integrated() && esr_disable) { |
89c38c28 CG |
1149 | apic_write(APIC_ESR, 0); |
1150 | apic_write(APIC_ESR, 0); | |
1151 | apic_write(APIC_ESR, 0); | |
1152 | apic_write(APIC_ESR, 0); | |
1153 | } | |
1154 | #endif | |
1155 | ||
ac23d4ee | 1156 | preempt_disable(); |
1da177e4 | 1157 | |
1da177e4 LT |
1158 | /* |
1159 | * Double-check whether this APIC is really registered. | |
1160 | * This is meaningless in clustered apic mode, so we skip it. | |
1161 | */ | |
1162 | if (!apic_id_registered()) | |
1163 | BUG(); | |
1164 | ||
1165 | /* | |
1166 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1167 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1168 | * document number 292116). So here it goes... | |
1169 | */ | |
1170 | init_apic_ldr(); | |
1171 | ||
1172 | /* | |
1173 | * Set Task Priority to 'accept all'. We never change this | |
1174 | * later on. | |
1175 | */ | |
1176 | value = apic_read(APIC_TASKPRI); | |
1177 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1178 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1179 | |
da7ed9f9 VG |
1180 | /* |
1181 | * After a crash, we no longer service the interrupts and a pending | |
1182 | * interrupt from previous kernel might still have ISR bit set. | |
1183 | * | |
1184 | * Most probably by now CPU has serviced that pending interrupt and | |
1185 | * it might not have done the ack_APIC_irq() because it thought, | |
1186 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1187 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1188 | * the interrupt. Hence a vector might get locked. It was noticed | |
1189 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1190 | */ | |
1191 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1192 | value = apic_read(APIC_ISR + i*0x10); | |
1193 | for (j = 31; j >= 0; j--) { | |
1194 | if (value & (1<<j)) | |
1195 | ack_APIC_irq(); | |
1196 | } | |
1197 | } | |
1198 | ||
1da177e4 LT |
1199 | /* |
1200 | * Now that we are all set up, enable the APIC | |
1201 | */ | |
1202 | value = apic_read(APIC_SPIV); | |
1203 | value &= ~APIC_VECTOR_MASK; | |
1204 | /* | |
1205 | * Enable APIC | |
1206 | */ | |
1207 | value |= APIC_SPIV_APIC_ENABLED; | |
1208 | ||
89c38c28 CG |
1209 | #ifdef CONFIG_X86_32 |
1210 | /* | |
1211 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1212 | * certain networking cards. If high frequency interrupts are | |
1213 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1214 | * entry is masked/unmasked at a high rate as well then sooner or | |
1215 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1216 | * from the device. If focus CPU is disabled then the hang goes | |
1217 | * away, oh well :-( | |
1218 | * | |
1219 | * [ This bug can be reproduced easily with a level-triggered | |
1220 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1221 | * BX chipset. ] | |
1222 | */ | |
1223 | /* | |
1224 | * Actually disabling the focus CPU check just makes the hang less | |
1225 | * frequent as it makes the interrupt distributon model be more | |
1226 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1227 | * See also the comment in end_level_ioapic_irq(). --macro | |
1228 | */ | |
1229 | ||
1230 | /* | |
1231 | * - enable focus processor (bit==0) | |
1232 | * - 64bit mode always use processor focus | |
1233 | * so no need to set it | |
1234 | */ | |
1235 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1236 | #endif | |
3f14c746 | 1237 | |
1da177e4 LT |
1238 | /* |
1239 | * Set spurious IRQ vector | |
1240 | */ | |
1241 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1242 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1243 | |
1244 | /* | |
1245 | * Set up LVT0, LVT1: | |
1246 | * | |
1247 | * set up through-local-APIC on the BP's LINT0. This is not | |
1248 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1249 | * we delegate interrupts to the 8259A. | |
1250 | */ | |
1251 | /* | |
1252 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1253 | */ | |
1254 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1255 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1256 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1257 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1258 | smp_processor_id()); |
1da177e4 LT |
1259 | } else { |
1260 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1261 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1262 | smp_processor_id()); |
1da177e4 | 1263 | } |
11a8e778 | 1264 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1265 | |
1266 | /* | |
1267 | * only the BP should see the LINT1 NMI signal, obviously. | |
1268 | */ | |
1269 | if (!smp_processor_id()) | |
1270 | value = APIC_DM_NMI; | |
1271 | else | |
1272 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1273 | if (!lapic_is_integrated()) /* 82489DX */ |
1274 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1275 | apic_write(APIC_LVT1, value); |
89c38c28 | 1276 | |
ac23d4ee | 1277 | preempt_enable(); |
739f33b3 | 1278 | } |
1da177e4 | 1279 | |
739f33b3 AK |
1280 | void __cpuinit end_local_APIC_setup(void) |
1281 | { | |
1282 | lapic_setup_esr(); | |
fa6b95fc CG |
1283 | |
1284 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1285 | { |
1286 | unsigned int value; | |
1287 | /* Disable the local apic timer */ | |
1288 | value = apic_read(APIC_LVTT); | |
1289 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1290 | apic_write(APIC_LVTT, value); | |
1291 | } | |
fa6b95fc CG |
1292 | #endif |
1293 | ||
f2802e7f | 1294 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1295 | apic_pm_activate(); |
1da177e4 | 1296 | } |
1da177e4 | 1297 | |
49899eac | 1298 | #ifdef HAVE_X2APIC |
6e1cb38a SS |
1299 | void check_x2apic(void) |
1300 | { | |
1301 | int msr, msr2; | |
1302 | ||
1303 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1304 | ||
1305 | if (msr & X2APIC_ENABLE) { | |
ba21ebb6 | 1306 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
6e1cb38a SS |
1307 | x2apic_preenabled = x2apic = 1; |
1308 | apic_ops = &x2apic_ops; | |
1309 | } | |
1310 | } | |
1311 | ||
1312 | void enable_x2apic(void) | |
1313 | { | |
1314 | int msr, msr2; | |
1315 | ||
1316 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1317 | if (!(msr & X2APIC_ENABLE)) { | |
ba21ebb6 | 1318 | pr_info("Enabling x2apic\n"); |
6e1cb38a SS |
1319 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); |
1320 | } | |
1321 | } | |
1322 | ||
2236d252 | 1323 | void __init enable_IR_x2apic(void) |
6e1cb38a SS |
1324 | { |
1325 | #ifdef CONFIG_INTR_REMAP | |
1326 | int ret; | |
1327 | unsigned long flags; | |
1328 | ||
1329 | if (!cpu_has_x2apic) | |
1330 | return; | |
1331 | ||
1332 | if (!x2apic_preenabled && disable_x2apic) { | |
ba21ebb6 CG |
1333 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1334 | "because of nox2apic\n"); | |
6e1cb38a SS |
1335 | return; |
1336 | } | |
1337 | ||
1338 | if (x2apic_preenabled && disable_x2apic) | |
1339 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1340 | ||
1341 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
ba21ebb6 CG |
1342 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1343 | "because of skipping io-apic setup\n"); | |
6e1cb38a SS |
1344 | return; |
1345 | } | |
1346 | ||
1347 | ret = dmar_table_init(); | |
1348 | if (ret) { | |
ba21ebb6 | 1349 | pr_info("dmar_table_init() failed with %d:\n", ret); |
6e1cb38a SS |
1350 | |
1351 | if (x2apic_preenabled) | |
1352 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1353 | else | |
ba21ebb6 | 1354 | pr_info("Not enabling x2apic,Intr-remapping\n"); |
6e1cb38a SS |
1355 | return; |
1356 | } | |
1357 | ||
1358 | local_irq_save(flags); | |
1359 | mask_8259A(); | |
5ffa4eb2 CG |
1360 | |
1361 | ret = save_mask_IO_APIC_setup(); | |
1362 | if (ret) { | |
ba21ebb6 | 1363 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
5ffa4eb2 CG |
1364 | goto end; |
1365 | } | |
6e1cb38a SS |
1366 | |
1367 | ret = enable_intr_remapping(1); | |
1368 | ||
1369 | if (ret && x2apic_preenabled) { | |
1370 | local_irq_restore(flags); | |
1371 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1372 | } | |
1373 | ||
1374 | if (ret) | |
5ffa4eb2 | 1375 | goto end_restore; |
6e1cb38a SS |
1376 | |
1377 | if (!x2apic) { | |
1378 | x2apic = 1; | |
1379 | apic_ops = &x2apic_ops; | |
1380 | enable_x2apic(); | |
1381 | } | |
5ffa4eb2 CG |
1382 | |
1383 | end_restore: | |
6e1cb38a SS |
1384 | if (ret) |
1385 | /* | |
1386 | * IR enabling failed | |
1387 | */ | |
1388 | restore_IO_APIC_setup(); | |
1389 | else | |
1390 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1391 | ||
5ffa4eb2 | 1392 | end: |
6e1cb38a SS |
1393 | unmask_8259A(); |
1394 | local_irq_restore(flags); | |
1395 | ||
1396 | if (!ret) { | |
1397 | if (!x2apic_preenabled) | |
ba21ebb6 | 1398 | pr_info("Enabled x2apic and interrupt-remapping\n"); |
6e1cb38a | 1399 | else |
ba21ebb6 | 1400 | pr_info("Enabled Interrupt-remapping\n"); |
6e1cb38a | 1401 | } else |
ba21ebb6 | 1402 | pr_err("Failed to enable Interrupt-remapping and x2apic\n"); |
6e1cb38a SS |
1403 | #else |
1404 | if (!cpu_has_x2apic) | |
1405 | return; | |
1406 | ||
1407 | if (x2apic_preenabled) | |
1408 | panic("x2apic enabled prior OS handover," | |
1409 | " enable CONFIG_INTR_REMAP"); | |
1410 | ||
ba21ebb6 CG |
1411 | pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping " |
1412 | " and x2apic\n"); | |
6e1cb38a SS |
1413 | #endif |
1414 | ||
1415 | return; | |
1416 | } | |
49899eac | 1417 | #endif /* HAVE_X2APIC */ |
6e1cb38a | 1418 | |
be7a656f | 1419 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1420 | /* |
1421 | * Detect and enable local APICs on non-SMP boards. | |
1422 | * Original code written by Keir Fraser. | |
1423 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1424 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1425 | */ |
0e078e2f | 1426 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1427 | { |
1428 | if (!cpu_has_apic) { | |
ba21ebb6 | 1429 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1430 | return -1; |
1431 | } | |
1432 | ||
1433 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1434 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1435 | return 0; |
1436 | } | |
be7a656f YL |
1437 | #else |
1438 | /* | |
1439 | * Detect and initialize APIC | |
1440 | */ | |
1441 | static int __init detect_init_APIC(void) | |
1442 | { | |
1443 | u32 h, l, features; | |
1444 | ||
1445 | /* Disabled by kernel option? */ | |
1446 | if (disable_apic) | |
1447 | return -1; | |
1448 | ||
1449 | switch (boot_cpu_data.x86_vendor) { | |
1450 | case X86_VENDOR_AMD: | |
1451 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
1452 | (boot_cpu_data.x86 == 15)) | |
1453 | break; | |
1454 | goto no_apic; | |
1455 | case X86_VENDOR_INTEL: | |
1456 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1457 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1458 | break; | |
1459 | goto no_apic; | |
1460 | default: | |
1461 | goto no_apic; | |
1462 | } | |
1463 | ||
1464 | if (!cpu_has_apic) { | |
1465 | /* | |
1466 | * Over-ride BIOS and try to enable the local APIC only if | |
1467 | * "lapic" specified. | |
1468 | */ | |
1469 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1470 | pr_info("Local APIC disabled by BIOS -- " |
1471 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1472 | return -1; |
1473 | } | |
1474 | /* | |
1475 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1476 | * MSR. This can only be done in software for Intel P6 or later | |
1477 | * and AMD K7 (Model > 1) or later. | |
1478 | */ | |
1479 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1480 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
ba21ebb6 | 1481 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
be7a656f YL |
1482 | l &= ~MSR_IA32_APICBASE_BASE; |
1483 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1484 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1485 | enabled_via_apicbase = 1; | |
1486 | } | |
1487 | } | |
1488 | /* | |
1489 | * The APIC feature bit should now be enabled | |
1490 | * in `cpuid' | |
1491 | */ | |
1492 | features = cpuid_edx(1); | |
1493 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
ba21ebb6 | 1494 | pr_warning("Could not enable APIC!\n"); |
be7a656f YL |
1495 | return -1; |
1496 | } | |
1497 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1498 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1499 | ||
1500 | /* The BIOS may have set up the APIC at some other address */ | |
1501 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1502 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1503 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1504 | ||
ba21ebb6 | 1505 | pr_info("Found and enabled local APIC!\n"); |
be7a656f YL |
1506 | |
1507 | apic_pm_activate(); | |
1508 | ||
1509 | return 0; | |
1510 | ||
1511 | no_apic: | |
ba21ebb6 | 1512 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1513 | return -1; |
1514 | } | |
1515 | #endif | |
1da177e4 | 1516 | |
f28c0ae2 | 1517 | #ifdef CONFIG_X86_64 |
8643f9d0 YL |
1518 | void __init early_init_lapic_mapping(void) |
1519 | { | |
431ee79d | 1520 | unsigned long phys_addr; |
8643f9d0 YL |
1521 | |
1522 | /* | |
1523 | * If no local APIC can be found then go out | |
1524 | * : it means there is no mpatable and MADT | |
1525 | */ | |
1526 | if (!smp_found_config) | |
1527 | return; | |
1528 | ||
431ee79d | 1529 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1530 | |
431ee79d | 1531 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1532 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1533 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1534 | |
1535 | /* | |
1536 | * Fetch the APIC ID of the BSP in case we have a | |
1537 | * default configuration (or the MP table is broken). | |
1538 | */ | |
4c9961d5 | 1539 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 | 1540 | } |
f28c0ae2 | 1541 | #endif |
8643f9d0 | 1542 | |
0e078e2f TG |
1543 | /** |
1544 | * init_apic_mappings - initialize APIC mappings | |
1545 | */ | |
1da177e4 LT |
1546 | void __init init_apic_mappings(void) |
1547 | { | |
49899eac | 1548 | #ifdef HAVE_X2APIC |
6e1cb38a | 1549 | if (x2apic) { |
4c9961d5 | 1550 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1551 | return; |
1552 | } | |
49899eac | 1553 | #endif |
6e1cb38a | 1554 | |
1da177e4 LT |
1555 | /* |
1556 | * If no local APIC can be found then set up a fake all | |
1557 | * zeroes page to simulate the local APIC and another | |
1558 | * one for the IO-APIC. | |
1559 | */ | |
1560 | if (!smp_found_config && detect_init_APIC()) { | |
1561 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1562 | apic_phys = __pa(apic_phys); | |
1563 | } else | |
1564 | apic_phys = mp_lapic_addr; | |
1565 | ||
1566 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
79c09698 | 1567 | apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", |
7ffeeb1e | 1568 | APIC_BASE, apic_phys); |
1da177e4 LT |
1569 | |
1570 | /* | |
1571 | * Fetch the APIC ID of the BSP in case we have a | |
1572 | * default configuration (or the MP table is broken). | |
1573 | */ | |
f28c0ae2 YL |
1574 | if (boot_cpu_physical_apicid == -1U) |
1575 | boot_cpu_physical_apicid = read_apic_id(); | |
1da177e4 LT |
1576 | } |
1577 | ||
1578 | /* | |
0e078e2f TG |
1579 | * This initializes the IO-APIC and APIC hardware if this is |
1580 | * a UP kernel. | |
1da177e4 | 1581 | */ |
1b313f4a CG |
1582 | int apic_version[MAX_APICS]; |
1583 | ||
0e078e2f | 1584 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1585 | { |
fa2bd35a | 1586 | #ifdef CONFIG_X86_64 |
0e078e2f | 1587 | if (disable_apic) { |
ba21ebb6 | 1588 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1589 | return -1; |
1590 | } | |
1591 | if (!cpu_has_apic) { | |
1592 | disable_apic = 1; | |
ba21ebb6 | 1593 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1594 | return -1; |
1595 | } | |
fa2bd35a YL |
1596 | #else |
1597 | if (!smp_found_config && !cpu_has_apic) | |
1598 | return -1; | |
1599 | ||
1600 | /* | |
1601 | * Complain if the BIOS pretends there is one. | |
1602 | */ | |
1603 | if (!cpu_has_apic && | |
1604 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1605 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1606 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1607 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1608 | return -1; | |
1609 | } | |
1610 | #endif | |
1611 | ||
49899eac | 1612 | #ifdef HAVE_X2APIC |
6e1cb38a | 1613 | enable_IR_x2apic(); |
49899eac | 1614 | #endif |
fa2bd35a | 1615 | #ifdef CONFIG_X86_64 |
6e1cb38a | 1616 | setup_apic_routing(); |
fa2bd35a | 1617 | #endif |
6e1cb38a | 1618 | |
0e078e2f | 1619 | verify_local_APIC(); |
b5841765 GC |
1620 | connect_bsp_APIC(); |
1621 | ||
fa2bd35a | 1622 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1623 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1624 | #else |
1625 | /* | |
1626 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1627 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1628 | * might be zero if read from MP tables. Get it from LAPIC. | |
1629 | */ | |
1630 | # ifdef CONFIG_CRASH_DUMP | |
1631 | boot_cpu_physical_apicid = read_apic_id(); | |
1632 | # endif | |
1633 | #endif | |
1634 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1635 | setup_local_APIC(); |
1da177e4 | 1636 | |
fa2bd35a | 1637 | #ifdef CONFIG_X86_64 |
739f33b3 AK |
1638 | /* |
1639 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1640 | * We need clear_IO_APIC before enabling vector on BP | |
1641 | */ | |
1642 | if (!skip_ioapic_setup && nr_ioapics) | |
1643 | enable_IO_APIC(); | |
fa2bd35a | 1644 | #endif |
739f33b3 | 1645 | |
fa2bd35a | 1646 | #ifdef CONFIG_X86_IO_APIC |
acae7d90 | 1647 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
fa2bd35a | 1648 | #endif |
acae7d90 | 1649 | localise_nmi_watchdog(); |
739f33b3 AK |
1650 | end_local_APIC_setup(); |
1651 | ||
fa2bd35a | 1652 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1653 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1654 | setup_IO_APIC(); | |
fa2bd35a | 1655 | # ifdef CONFIG_X86_64 |
0e078e2f TG |
1656 | else |
1657 | nr_ioapics = 0; | |
fa2bd35a YL |
1658 | # endif |
1659 | #endif | |
1660 | ||
1661 | #ifdef CONFIG_X86_64 | |
0e078e2f TG |
1662 | setup_boot_APIC_clock(); |
1663 | check_nmi_watchdog(); | |
fa2bd35a YL |
1664 | #else |
1665 | setup_boot_clock(); | |
1666 | #endif | |
1667 | ||
0e078e2f | 1668 | return 0; |
1da177e4 LT |
1669 | } |
1670 | ||
1671 | /* | |
0e078e2f | 1672 | * Local APIC interrupts |
1da177e4 LT |
1673 | */ |
1674 | ||
0e078e2f TG |
1675 | /* |
1676 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1677 | */ | |
dc1528dd | 1678 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 | 1679 | { |
dc1528dd YL |
1680 | u32 v; |
1681 | ||
0e078e2f TG |
1682 | exit_idle(); |
1683 | irq_enter(); | |
1da177e4 | 1684 | /* |
0e078e2f TG |
1685 | * Check if this really is a spurious interrupt and ACK it |
1686 | * if it is a vectored one. Just in case... | |
1687 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1688 | */ |
0e078e2f TG |
1689 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1690 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1691 | ack_APIC_irq(); | |
c4d58cbd | 1692 | |
915b0d01 HS |
1693 | inc_irq_stat(irq_spurious_count); |
1694 | ||
dc1528dd | 1695 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
ba21ebb6 CG |
1696 | pr_info("spurious APIC interrupt on CPU#%d, " |
1697 | "should never happen.\n", smp_processor_id()); | |
0e078e2f TG |
1698 | irq_exit(); |
1699 | } | |
1da177e4 | 1700 | |
0e078e2f TG |
1701 | /* |
1702 | * This interrupt should never happen with our APIC/SMP architecture | |
1703 | */ | |
dc1528dd | 1704 | void smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1705 | { |
dc1528dd | 1706 | u32 v, v1; |
1da177e4 | 1707 | |
0e078e2f TG |
1708 | exit_idle(); |
1709 | irq_enter(); | |
1710 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1711 | v = apic_read(APIC_ESR); | |
1712 | apic_write(APIC_ESR, 0); | |
1713 | v1 = apic_read(APIC_ESR); | |
1714 | ack_APIC_irq(); | |
1715 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1716 | |
ba21ebb6 CG |
1717 | /* |
1718 | * Here is what the APIC error bits mean: | |
1719 | * 0: Send CS error | |
1720 | * 1: Receive CS error | |
1721 | * 2: Send accept error | |
1722 | * 3: Receive accept error | |
1723 | * 4: Reserved | |
1724 | * 5: Send illegal vector | |
1725 | * 6: Received illegal vector | |
1726 | * 7: Illegal register address | |
1727 | */ | |
1728 | pr_debug("APIC error on CPU%d: %02x(%02x)\n", | |
0e078e2f TG |
1729 | smp_processor_id(), v , v1); |
1730 | irq_exit(); | |
1da177e4 LT |
1731 | } |
1732 | ||
b5841765 | 1733 | /** |
36c9d674 CG |
1734 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1735 | */ | |
b5841765 GC |
1736 | void __init connect_bsp_APIC(void) |
1737 | { | |
36c9d674 CG |
1738 | #ifdef CONFIG_X86_32 |
1739 | if (pic_mode) { | |
1740 | /* | |
1741 | * Do not trust the local APIC being empty at bootup. | |
1742 | */ | |
1743 | clear_local_APIC(); | |
1744 | /* | |
1745 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1746 | * local APIC to INT and NMI lines. | |
1747 | */ | |
1748 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1749 | "enabling APIC mode.\n"); | |
1750 | outb(0x70, 0x22); | |
1751 | outb(0x01, 0x23); | |
1752 | } | |
1753 | #endif | |
b5841765 GC |
1754 | enable_apic_mode(); |
1755 | } | |
1756 | ||
274cfe59 CG |
1757 | /** |
1758 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1759 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1760 | * | |
1761 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1762 | * APIC is disabled. | |
1763 | */ | |
0e078e2f | 1764 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1765 | { |
1b4ee4e4 CG |
1766 | unsigned int value; |
1767 | ||
c177b0bc CG |
1768 | #ifdef CONFIG_X86_32 |
1769 | if (pic_mode) { | |
1770 | /* | |
1771 | * Put the board back into PIC mode (has an effect only on | |
1772 | * certain older boards). Note that APIC interrupts, including | |
1773 | * IPIs, won't work beyond this point! The only exception are | |
1774 | * INIT IPIs. | |
1775 | */ | |
1776 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1777 | "entering PIC mode.\n"); | |
1778 | outb(0x70, 0x22); | |
1779 | outb(0x00, 0x23); | |
1780 | return; | |
1781 | } | |
1782 | #endif | |
1783 | ||
0e078e2f | 1784 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1785 | |
0e078e2f TG |
1786 | /* For the spurious interrupt use vector F, and enable it */ |
1787 | value = apic_read(APIC_SPIV); | |
1788 | value &= ~APIC_VECTOR_MASK; | |
1789 | value |= APIC_SPIV_APIC_ENABLED; | |
1790 | value |= 0xf; | |
1791 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1792 | |
0e078e2f TG |
1793 | if (!virt_wire_setup) { |
1794 | /* | |
1795 | * For LVT0 make it edge triggered, active high, | |
1796 | * external and enabled | |
1797 | */ | |
1798 | value = apic_read(APIC_LVT0); | |
1799 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1800 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1801 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1802 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1803 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1804 | apic_write(APIC_LVT0, value); | |
1805 | } else { | |
1806 | /* Disable LVT0 */ | |
1807 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1808 | } | |
b8ce3359 | 1809 | |
c177b0bc CG |
1810 | /* |
1811 | * For LVT1 make it edge triggered, active high, | |
1812 | * nmi and enabled | |
1813 | */ | |
0e078e2f TG |
1814 | value = apic_read(APIC_LVT1); |
1815 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1816 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1817 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1818 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1819 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1820 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1821 | } |
1822 | ||
be8a5685 AS |
1823 | void __cpuinit generic_processor_info(int apicid, int version) |
1824 | { | |
1825 | int cpu; | |
be8a5685 | 1826 | |
1b313f4a CG |
1827 | /* |
1828 | * Validate version | |
1829 | */ | |
1830 | if (version == 0x0) { | |
ba21ebb6 | 1831 | pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " |
3b11ce7f MT |
1832 | "fixing up to 0x10. (tell your hw vendor)\n", |
1833 | version); | |
1b313f4a | 1834 | version = 0x10; |
be8a5685 | 1835 | } |
1b313f4a | 1836 | apic_version[apicid] = version; |
be8a5685 | 1837 | |
3b11ce7f MT |
1838 | if (num_processors >= nr_cpu_ids) { |
1839 | int max = nr_cpu_ids; | |
1840 | int thiscpu = max + disabled_cpus; | |
1841 | ||
1842 | pr_warning( | |
1843 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
1844 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
1845 | ||
1846 | disabled_cpus++; | |
be8a5685 AS |
1847 | return; |
1848 | } | |
1849 | ||
1850 | num_processors++; | |
3b11ce7f | 1851 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
be8a5685 | 1852 | |
b2b815d8 MT |
1853 | if (version != apic_version[boot_cpu_physical_apicid]) |
1854 | WARN_ONCE(1, | |
1855 | "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", | |
1856 | apic_version[boot_cpu_physical_apicid], cpu, version); | |
1857 | ||
be8a5685 AS |
1858 | physid_set(apicid, phys_cpu_present_map); |
1859 | if (apicid == boot_cpu_physical_apicid) { | |
1860 | /* | |
1861 | * x86_bios_cpu_apicid is required to have processors listed | |
1862 | * in same order as logical cpu numbers. Hence the first | |
1863 | * entry is BSP, and so on. | |
1864 | */ | |
1865 | cpu = 0; | |
1866 | } | |
e0da3364 YL |
1867 | if (apicid > max_physical_apicid) |
1868 | max_physical_apicid = apicid; | |
1869 | ||
1b313f4a CG |
1870 | #ifdef CONFIG_X86_32 |
1871 | /* | |
1872 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1873 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1874 | * before this can be done without some confusion. | |
1875 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1876 | * - Ashok Raj <ashok.raj@intel.com> | |
1877 | */ | |
1878 | if (max_physical_apicid >= 8) { | |
1879 | switch (boot_cpu_data.x86_vendor) { | |
1880 | case X86_VENDOR_INTEL: | |
1881 | if (!APIC_XAPIC(version)) { | |
1882 | def_to_bigsmp = 0; | |
1883 | break; | |
1884 | } | |
1885 | /* If P4 and above fall through */ | |
1886 | case X86_VENDOR_AMD: | |
1887 | def_to_bigsmp = 1; | |
1888 | } | |
1889 | } | |
1890 | #endif | |
1891 | ||
1892 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
be8a5685 | 1893 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1894 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1895 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1896 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1897 | |
1898 | cpu_to_apicid[cpu] = apicid; | |
1899 | bios_cpu_apicid[cpu] = apicid; | |
1900 | } else { | |
1901 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1902 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1903 | } | |
1b313f4a | 1904 | #endif |
be8a5685 | 1905 | |
1de88cd4 MT |
1906 | set_cpu_possible(cpu, true); |
1907 | set_cpu_present(cpu, true); | |
be8a5685 AS |
1908 | } |
1909 | ||
3491998d | 1910 | #ifdef CONFIG_X86_64 |
0c81c746 SS |
1911 | int hard_smp_processor_id(void) |
1912 | { | |
1913 | return read_apic_id(); | |
1914 | } | |
3491998d | 1915 | #endif |
0c81c746 | 1916 | |
89039b37 | 1917 | /* |
0e078e2f | 1918 | * Power management |
89039b37 | 1919 | */ |
0e078e2f TG |
1920 | #ifdef CONFIG_PM |
1921 | ||
1922 | static struct { | |
274cfe59 CG |
1923 | /* |
1924 | * 'active' is true if the local APIC was enabled by us and | |
1925 | * not the BIOS; this signifies that we are also responsible | |
1926 | * for disabling it before entering apm/acpi suspend | |
1927 | */ | |
0e078e2f TG |
1928 | int active; |
1929 | /* r/w apic fields */ | |
1930 | unsigned int apic_id; | |
1931 | unsigned int apic_taskpri; | |
1932 | unsigned int apic_ldr; | |
1933 | unsigned int apic_dfr; | |
1934 | unsigned int apic_spiv; | |
1935 | unsigned int apic_lvtt; | |
1936 | unsigned int apic_lvtpc; | |
1937 | unsigned int apic_lvt0; | |
1938 | unsigned int apic_lvt1; | |
1939 | unsigned int apic_lvterr; | |
1940 | unsigned int apic_tmict; | |
1941 | unsigned int apic_tdcr; | |
1942 | unsigned int apic_thmr; | |
1943 | } apic_pm_state; | |
1944 | ||
1945 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1946 | { | |
1947 | unsigned long flags; | |
1948 | int maxlvt; | |
89039b37 | 1949 | |
0e078e2f TG |
1950 | if (!apic_pm_state.active) |
1951 | return 0; | |
89039b37 | 1952 | |
0e078e2f | 1953 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1954 | |
2d7a66d0 | 1955 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1956 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1957 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1958 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1959 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1960 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1961 | if (maxlvt >= 4) | |
1962 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1963 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1964 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1965 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1966 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1967 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1968 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1969 | if (maxlvt >= 5) |
1970 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1971 | #endif | |
24968cfd | 1972 | |
0e078e2f TG |
1973 | local_irq_save(flags); |
1974 | disable_local_APIC(); | |
1975 | local_irq_restore(flags); | |
1976 | return 0; | |
1da177e4 LT |
1977 | } |
1978 | ||
0e078e2f | 1979 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1980 | { |
0e078e2f TG |
1981 | unsigned int l, h; |
1982 | unsigned long flags; | |
1983 | int maxlvt; | |
1da177e4 | 1984 | |
0e078e2f TG |
1985 | if (!apic_pm_state.active) |
1986 | return 0; | |
89b831ef | 1987 | |
0e078e2f | 1988 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1989 | |
0e078e2f | 1990 | local_irq_save(flags); |
92206c90 | 1991 | |
49899eac | 1992 | #ifdef HAVE_X2APIC |
92206c90 CG |
1993 | if (x2apic) |
1994 | enable_x2apic(); | |
1995 | else | |
1996 | #endif | |
d5e629a6 | 1997 | { |
92206c90 CG |
1998 | /* |
1999 | * Make sure the APICBASE points to the right address | |
2000 | * | |
2001 | * FIXME! This will be wrong if we ever support suspend on | |
2002 | * SMP! We'll need to do this as part of the CPU restore! | |
2003 | */ | |
6e1cb38a SS |
2004 | rdmsr(MSR_IA32_APICBASE, l, h); |
2005 | l &= ~MSR_IA32_APICBASE_BASE; | |
2006 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2007 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 2008 | } |
6e1cb38a | 2009 | |
0e078e2f TG |
2010 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2011 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2012 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2013 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2014 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2015 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2016 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2017 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 2018 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2019 | if (maxlvt >= 5) |
2020 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2021 | #endif | |
2022 | if (maxlvt >= 4) | |
2023 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2024 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2025 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2026 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2027 | apic_write(APIC_ESR, 0); | |
2028 | apic_read(APIC_ESR); | |
2029 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2030 | apic_write(APIC_ESR, 0); | |
2031 | apic_read(APIC_ESR); | |
92206c90 | 2032 | |
0e078e2f | 2033 | local_irq_restore(flags); |
92206c90 | 2034 | |
0e078e2f TG |
2035 | return 0; |
2036 | } | |
b8ce3359 | 2037 | |
274cfe59 CG |
2038 | /* |
2039 | * This device has no shutdown method - fully functioning local APICs | |
2040 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2041 | */ | |
2042 | ||
0e078e2f TG |
2043 | static struct sysdev_class lapic_sysclass = { |
2044 | .name = "lapic", | |
2045 | .resume = lapic_resume, | |
2046 | .suspend = lapic_suspend, | |
2047 | }; | |
b8ce3359 | 2048 | |
0e078e2f | 2049 | static struct sys_device device_lapic = { |
e83a5fdc HS |
2050 | .id = 0, |
2051 | .cls = &lapic_sysclass, | |
0e078e2f | 2052 | }; |
b8ce3359 | 2053 | |
0e078e2f TG |
2054 | static void __cpuinit apic_pm_activate(void) |
2055 | { | |
2056 | apic_pm_state.active = 1; | |
1da177e4 LT |
2057 | } |
2058 | ||
0e078e2f | 2059 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2060 | { |
0e078e2f | 2061 | int error; |
e83a5fdc | 2062 | |
0e078e2f TG |
2063 | if (!cpu_has_apic) |
2064 | return 0; | |
2065 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 2066 | |
0e078e2f TG |
2067 | error = sysdev_class_register(&lapic_sysclass); |
2068 | if (!error) | |
2069 | error = sysdev_register(&device_lapic); | |
2070 | return error; | |
1da177e4 | 2071 | } |
0e078e2f TG |
2072 | device_initcall(init_lapic_sysfs); |
2073 | ||
2074 | #else /* CONFIG_PM */ | |
2075 | ||
2076 | static void apic_pm_activate(void) { } | |
2077 | ||
2078 | #endif /* CONFIG_PM */ | |
1da177e4 | 2079 | |
f28c0ae2 | 2080 | #ifdef CONFIG_X86_64 |
1da177e4 | 2081 | /* |
f8bf3c65 | 2082 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
2083 | * |
2084 | * Thus far, the major user of this is IBM's Summit2 series: | |
2085 | * | |
637029c6 | 2086 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
2087 | * multi-chassis. Use available data to take a good guess. |
2088 | * If in doubt, go HPET. | |
2089 | */ | |
f8bf3c65 | 2090 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
2091 | { |
2092 | int i, clusters, zeros; | |
2093 | unsigned id; | |
322850af | 2094 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2095 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2096 | ||
322850af YL |
2097 | /* |
2098 | * there is not this kind of box with AMD CPU yet. | |
2099 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
2100 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 2101 | * vsmp box still need checking... |
322850af | 2102 | */ |
1cb68487 | 2103 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
2104 | return 0; |
2105 | ||
23ca4bba | 2106 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2107 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 | 2108 | |
168ef543 | 2109 | for (i = 0; i < nr_cpu_ids; i++) { |
e8c10ef9 | 2110 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2111 | if (bios_cpu_apicid) { |
2112 | id = bios_cpu_apicid[i]; | |
e423e33e | 2113 | } else if (i < nr_cpu_ids) { |
e8c10ef9 | 2114 | if (cpu_present(i)) |
2115 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2116 | else | |
2117 | continue; | |
e423e33e | 2118 | } else |
e8c10ef9 | 2119 | break; |
2120 | ||
1da177e4 LT |
2121 | if (id != BAD_APICID) |
2122 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2123 | } | |
2124 | ||
2125 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2126 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2127 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2128 | * Since clusters are allocated sequentially, count zeros only if | |
2129 | * they are bounded by ones. | |
1da177e4 LT |
2130 | */ |
2131 | clusters = 0; | |
2132 | zeros = 0; | |
2133 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2134 | if (test_bit(i, clustermap)) { | |
2135 | clusters += 1 + zeros; | |
2136 | zeros = 0; | |
2137 | } else | |
2138 | ++zeros; | |
2139 | } | |
2140 | ||
1cb68487 RT |
2141 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2142 | * not guaranteed to be synced between boards | |
2143 | */ | |
2144 | if (is_vsmp_box() && clusters > 1) | |
2145 | return 1; | |
2146 | ||
1da177e4 | 2147 | /* |
f8bf3c65 | 2148 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
2149 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
2150 | * out, but AFAIK this will work even for them. | |
2151 | */ | |
2152 | return (clusters > 2); | |
2153 | } | |
f28c0ae2 | 2154 | #endif |
1da177e4 LT |
2155 | |
2156 | /* | |
0e078e2f | 2157 | * APIC command line parameters |
1da177e4 | 2158 | */ |
789fa735 | 2159 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2160 | { |
1da177e4 | 2161 | disable_apic = 1; |
9175fc06 | 2162 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2163 | return 0; |
2164 | } | |
2165 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2166 | |
2c8c0e6b | 2167 | /* same as disableapic, for compatibility */ |
789fa735 | 2168 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2169 | { |
789fa735 | 2170 | return setup_disableapic(arg); |
6935d1f9 | 2171 | } |
2c8c0e6b | 2172 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2173 | |
2e7c2838 LT |
2174 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2175 | { | |
2176 | local_apic_timer_c2_ok = 1; | |
2177 | return 0; | |
2178 | } | |
2179 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2180 | ||
36fef094 | 2181 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2182 | { |
1da177e4 | 2183 | disable_apic_timer = 1; |
36fef094 | 2184 | return 0; |
6935d1f9 | 2185 | } |
36fef094 CG |
2186 | early_param("noapictimer", parse_disable_apic_timer); |
2187 | ||
2188 | static int __init parse_nolapic_timer(char *arg) | |
2189 | { | |
2190 | disable_apic_timer = 1; | |
2191 | return 0; | |
6935d1f9 | 2192 | } |
36fef094 | 2193 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2194 | |
79af9bec CG |
2195 | static int __init apic_set_verbosity(char *arg) |
2196 | { | |
2197 | if (!arg) { | |
2198 | #ifdef CONFIG_X86_64 | |
2199 | skip_ioapic_setup = 0; | |
79af9bec CG |
2200 | return 0; |
2201 | #endif | |
2202 | return -EINVAL; | |
2203 | } | |
2204 | ||
2205 | if (strcmp("debug", arg) == 0) | |
2206 | apic_verbosity = APIC_DEBUG; | |
2207 | else if (strcmp("verbose", arg) == 0) | |
2208 | apic_verbosity = APIC_VERBOSE; | |
2209 | else { | |
ba21ebb6 | 2210 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2211 | " use apic=verbose or apic=debug\n", arg); |
2212 | return -EINVAL; | |
2213 | } | |
2214 | ||
2215 | return 0; | |
2216 | } | |
2217 | early_param("apic", apic_set_verbosity); | |
2218 | ||
1e934dda YL |
2219 | static int __init lapic_insert_resource(void) |
2220 | { | |
2221 | if (!apic_phys) | |
2222 | return -1; | |
2223 | ||
2224 | /* Put local APIC into the resource map. */ | |
2225 | lapic_resource.start = apic_phys; | |
2226 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2227 | insert_resource(&iomem_resource, &lapic_resource); | |
2228 | ||
2229 | return 0; | |
2230 | } | |
2231 | ||
2232 | /* | |
2233 | * need call insert after e820_reserve_resources() | |
2234 | * that is using request_resource | |
2235 | */ | |
2236 | late_initcall(lapic_insert_resource); |