Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
f3705136 | 26 | #include <linux/cpu.h> |
e9e2cdb4 | 27 | #include <linux/clockchips.h> |
d36b49b9 | 28 | #include <linux/acpi_pmtmr.h> |
6eb0a0fd | 29 | #include <linux/module.h> |
ad62ca2b | 30 | #include <linux/dmi.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/arch_hooks.h> | |
38 | #include <asm/hpet.h> | |
306e440d | 39 | #include <asm/i8253.h> |
3e4ff115 | 40 | #include <asm/nmi.h> |
1da177e4 LT |
41 | |
42 | #include <mach_apic.h> | |
382dbd07 | 43 | #include <mach_apicdef.h> |
6eb0a0fd | 44 | #include <mach_ipi.h> |
1da177e4 | 45 | |
e05d723f TG |
46 | /* |
47 | * Sanity check | |
48 | */ | |
ff8a03a6 | 49 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) |
e05d723f TG |
50 | # error SPURIOUS_APIC_VECTOR definition error |
51 | #endif | |
52 | ||
8f6e2ca9 AS |
53 | unsigned long mp_lapic_addr; |
54 | ||
9635b47d EB |
55 | /* |
56 | * Knob to control our willingness to enable the local APIC. | |
e05d723f | 57 | * |
914bebfa | 58 | * +1=force-enable |
9635b47d | 59 | */ |
914bebfa YL |
60 | static int force_enable_local_apic; |
61 | int disable_apic; | |
9635b47d | 62 | |
aa276e1c | 63 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
36fef094 | 64 | static int disable_apic_timer __cpuinitdata; |
e585bef8 TG |
65 | /* Local APIC timer works in C2 */ |
66 | int local_apic_timer_c2_ok; | |
67 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
e9e2cdb4 | 68 | |
ce178331 AM |
69 | int first_system_vector = 0xfe; |
70 | ||
71 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
72 | ||
1da177e4 | 73 | /* |
e05d723f | 74 | * Debug level, exported for io_apic.c |
1da177e4 | 75 | */ |
baa13188 | 76 | unsigned int apic_verbosity; |
1da177e4 | 77 | |
f3918352 AS |
78 | int pic_mode; |
79 | ||
bab4b27c AS |
80 | /* Have we found an MP table */ |
81 | int smp_found_config; | |
82 | ||
746f2eb7 CG |
83 | static struct resource lapic_resource = { |
84 | .name = "Local APIC", | |
85 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
86 | }; | |
87 | ||
e9e2cdb4 | 88 | static unsigned int calibration_result; |
1da177e4 | 89 | |
e9e2cdb4 TG |
90 | static int lapic_next_event(unsigned long delta, |
91 | struct clock_event_device *evt); | |
92 | static void lapic_timer_setup(enum clock_event_mode mode, | |
93 | struct clock_event_device *evt); | |
94 | static void lapic_timer_broadcast(cpumask_t mask); | |
95 | static void apic_pm_activate(void); | |
e05d723f | 96 | |
e9e2cdb4 TG |
97 | /* |
98 | * The local apic timer can be used for any function which is CPU local. | |
99 | */ | |
100 | static struct clock_event_device lapic_clockevent = { | |
101 | .name = "lapic", | |
102 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
d36b49b9 | 103 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
e9e2cdb4 TG |
104 | .shift = 32, |
105 | .set_mode = lapic_timer_setup, | |
106 | .set_next_event = lapic_next_event, | |
107 | .broadcast = lapic_timer_broadcast, | |
108 | .rating = 100, | |
109 | .irq = -1, | |
110 | }; | |
111 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
e05d723f TG |
112 | |
113 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ | |
114 | static int enabled_via_apicbase; | |
115 | ||
d3432896 AK |
116 | static unsigned long apic_phys; |
117 | ||
e05d723f TG |
118 | /* |
119 | * Get the LAPIC version | |
120 | */ | |
121 | static inline int lapic_get_version(void) | |
95d769aa | 122 | { |
e05d723f | 123 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
95d769aa AK |
124 | } |
125 | ||
1da177e4 | 126 | /* |
ab4a574e | 127 | * Check, if the APIC is integrated or a separate chip |
1da177e4 | 128 | */ |
e05d723f | 129 | static inline int lapic_is_integrated(void) |
1da177e4 | 130 | { |
9c803869 CG |
131 | #ifdef CONFIG_X86_64 |
132 | return 1; | |
133 | #else | |
e05d723f | 134 | return APIC_INTEGRATED(lapic_get_version()); |
9c803869 | 135 | #endif |
1da177e4 LT |
136 | } |
137 | ||
e05d723f TG |
138 | /* |
139 | * Check, whether this is a modern or a first generation APIC | |
140 | */ | |
141 | static int modern_apic(void) | |
1da177e4 | 142 | { |
e05d723f TG |
143 | /* AMD systems use old APIC versions, so check the CPU */ |
144 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
145 | boot_cpu_data.x86 >= 0xf) | |
146 | return 1; | |
147 | return lapic_get_version() >= 0x14; | |
1da177e4 LT |
148 | } |
149 | ||
9a8f0e6b SS |
150 | /* |
151 | * Paravirt kernels also might be using these below ops. So we still | |
152 | * use generic apic_read()/apic_write(), which might be pointing to different | |
153 | * ops in PARAVIRT case. | |
154 | */ | |
c535b6a1 | 155 | void xapic_wait_icr_idle(void) |
f2b218dd FLV |
156 | { |
157 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
158 | cpu_relax(); | |
159 | } | |
160 | ||
c535b6a1 | 161 | u32 safe_xapic_wait_icr_idle(void) |
f2b218dd | 162 | { |
42e0a9aa | 163 | u32 send_status; |
f2b218dd FLV |
164 | int timeout; |
165 | ||
166 | timeout = 0; | |
167 | do { | |
168 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
169 | if (!send_status) | |
170 | break; | |
171 | udelay(100); | |
172 | } while (timeout++ < 1000); | |
173 | ||
174 | return send_status; | |
175 | } | |
176 | ||
c535b6a1 YL |
177 | void xapic_icr_write(u32 low, u32 id) |
178 | { | |
f586bf7d SS |
179 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
180 | apic_write(APIC_ICR, low); | |
c535b6a1 YL |
181 | } |
182 | ||
183 | u64 xapic_icr_read(void) | |
184 | { | |
185 | u32 icr1, icr2; | |
186 | ||
187 | icr2 = apic_read(APIC_ICR2); | |
188 | icr1 = apic_read(APIC_ICR); | |
189 | ||
190 | return icr1 | ((u64)icr2 << 32); | |
191 | } | |
192 | ||
193 | static struct apic_ops xapic_ops = { | |
194 | .read = native_apic_mem_read, | |
195 | .write = native_apic_mem_write, | |
c535b6a1 YL |
196 | .icr_read = xapic_icr_read, |
197 | .icr_write = xapic_icr_write, | |
198 | .wait_icr_idle = xapic_wait_icr_idle, | |
199 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
200 | }; | |
201 | ||
202 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
203 | EXPORT_SYMBOL_GPL(apic_ops); | |
204 | ||
e05d723f TG |
205 | /** |
206 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
207 | */ | |
e9427101 | 208 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 209 | { |
d4c63ec0 | 210 | unsigned int v; |
1da177e4 | 211 | |
d4c63ec0 CG |
212 | /* unmask and set to NMI */ |
213 | v = APIC_DM_NMI; | |
214 | ||
215 | /* Level triggered for 82489DX (32bit mode) */ | |
e05d723f | 216 | if (!lapic_is_integrated()) |
1da177e4 | 217 | v |= APIC_LVT_LEVEL_TRIGGER; |
d4c63ec0 | 218 | |
593f4a78 | 219 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
220 | } |
221 | ||
e05d723f TG |
222 | /** |
223 | * get_physical_broadcast - Get number of physical broadcast IDs | |
224 | */ | |
1da177e4 LT |
225 | int get_physical_broadcast(void) |
226 | { | |
e05d723f | 227 | return modern_apic() ? 0xff : 0xf; |
1da177e4 LT |
228 | } |
229 | ||
e05d723f TG |
230 | /** |
231 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
232 | */ | |
233 | int lapic_get_maxlvt(void) | |
1da177e4 | 234 | { |
36a028de | 235 | unsigned int v; |
1da177e4 | 236 | |
36a028de CG |
237 | v = apic_read(APIC_LVR); |
238 | /* | |
239 | * - we always have APIC integrated on 64bit mode | |
240 | * - 82489DXs do not report # of LVT entries | |
241 | */ | |
e05d723f | 242 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
1da177e4 LT |
243 | } |
244 | ||
e05d723f TG |
245 | /* |
246 | * Local APIC timer | |
247 | */ | |
248 | ||
c40aaec6 CG |
249 | /* Clock divisor */ |
250 | #ifdef CONFG_X86_64 | |
251 | #define APIC_DIVISOR 1 | |
252 | #else | |
d36b49b9 | 253 | #define APIC_DIVISOR 16 |
c40aaec6 | 254 | #endif |
e05d723f TG |
255 | |
256 | /* | |
257 | * This function sets up the local APIC timer, with a timeout of | |
258 | * 'clocks' APIC bus clock. During calibration we actually call | |
259 | * this function twice on the boot CPU, once with a bogus timeout | |
260 | * value, second time for real. The other (noncalibrating) CPUs | |
261 | * call this function only once, with the real, calibrated value. | |
274cfe59 CG |
262 | * |
263 | * We do reads before writes even if unnecessary, to get around the | |
264 | * P5 APIC double write bug. | |
e05d723f | 265 | */ |
e9e2cdb4 | 266 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 267 | { |
e05d723f | 268 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 269 | |
e9e2cdb4 TG |
270 | lvtt_value = LOCAL_TIMER_VECTOR; |
271 | if (!oneshot) | |
272 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
e05d723f TG |
273 | if (!lapic_is_integrated()) |
274 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
275 | ||
e9e2cdb4 | 276 | if (!irqen) |
e05d723f TG |
277 | lvtt_value |= APIC_LVT_MASKED; |
278 | ||
593f4a78 | 279 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
280 | |
281 | /* | |
e05d723f | 282 | * Divide PICLK by 16 |
1da177e4 | 283 | */ |
e05d723f | 284 | tmp_value = apic_read(APIC_TDCR); |
593f4a78 | 285 | apic_write(APIC_TDCR, |
c40aaec6 CG |
286 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
287 | APIC_TDR_DIV_16); | |
1da177e4 | 288 | |
e9e2cdb4 | 289 | if (!oneshot) |
593f4a78 | 290 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
e9e2cdb4 TG |
291 | } |
292 | ||
274cfe59 CG |
293 | /* |
294 | * Setup extended LVT, AMD specific (K8, family 10h) | |
295 | * | |
296 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
297 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
accba5f3 IM |
298 | * |
299 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
300 | * enables the vector. See also the BKDGs. | |
274cfe59 CG |
301 | */ |
302 | ||
303 | #define APIC_EILVT_LVTOFF_MCE 0 | |
304 | #define APIC_EILVT_LVTOFF_IBS 1 | |
305 | ||
306 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
307 | { | |
308 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; | |
309 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; | |
310 | ||
311 | apic_write(reg, v); | |
312 | } | |
313 | ||
314 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) | |
315 | { | |
316 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
317 | return APIC_EILVT_LVTOFF_MCE; | |
318 | } | |
319 | ||
320 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
321 | { | |
322 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
323 | return APIC_EILVT_LVTOFF_IBS; | |
324 | } | |
accba5f3 | 325 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
274cfe59 | 326 | |
e9e2cdb4 TG |
327 | /* |
328 | * Program the next event, relative to now | |
329 | */ | |
330 | static int lapic_next_event(unsigned long delta, | |
331 | struct clock_event_device *evt) | |
332 | { | |
593f4a78 | 333 | apic_write(APIC_TMICT, delta); |
e9e2cdb4 | 334 | return 0; |
1da177e4 LT |
335 | } |
336 | ||
e9e2cdb4 TG |
337 | /* |
338 | * Setup the lapic timer in periodic or oneshot mode | |
339 | */ | |
340 | static void lapic_timer_setup(enum clock_event_mode mode, | |
341 | struct clock_event_device *evt) | |
1da177e4 | 342 | { |
e05d723f | 343 | unsigned long flags; |
e9e2cdb4 | 344 | unsigned int v; |
e05d723f | 345 | |
274cfe59 | 346 | /* Lapic used as dummy for broadcast ? */ |
64e474d1 | 347 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) |
d36b49b9 TG |
348 | return; |
349 | ||
e05d723f | 350 | local_irq_save(flags); |
1da177e4 | 351 | |
e9e2cdb4 TG |
352 | switch (mode) { |
353 | case CLOCK_EVT_MODE_PERIODIC: | |
354 | case CLOCK_EVT_MODE_ONESHOT: | |
355 | __setup_APIC_LVTT(calibration_result, | |
356 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
357 | break; | |
358 | case CLOCK_EVT_MODE_UNUSED: | |
359 | case CLOCK_EVT_MODE_SHUTDOWN: | |
360 | v = apic_read(APIC_LVTT); | |
361 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
593f4a78 | 362 | apic_write(APIC_LVTT, v); |
e9e2cdb4 | 363 | break; |
18de5bc4 TG |
364 | case CLOCK_EVT_MODE_RESUME: |
365 | /* Nothing to do here */ | |
366 | break; | |
e9e2cdb4 | 367 | } |
e05d723f TG |
368 | |
369 | local_irq_restore(flags); | |
370 | } | |
371 | ||
e9e2cdb4 TG |
372 | /* |
373 | * Local APIC timer broadcast function | |
374 | */ | |
375 | static void lapic_timer_broadcast(cpumask_t mask) | |
376 | { | |
377 | #ifdef CONFIG_SMP | |
378 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
379 | #endif | |
380 | } | |
381 | ||
382 | /* | |
383 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
384 | * of the boot CPU and register the clock event in the framework. | |
385 | */ | |
457cc52d | 386 | static void __cpuinit setup_APIC_timer(void) |
e9e2cdb4 TG |
387 | { |
388 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
389 | ||
390 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); | |
391 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
392 | ||
393 | clockevents_register_device(levt); | |
394 | } | |
395 | ||
e05d723f | 396 | /* |
d36b49b9 TG |
397 | * In this functions we calibrate APIC bus clocks to the external timer. |
398 | * | |
399 | * We want to do the calibration only once since we want to have local timer | |
400 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
401 | * frequency. | |
402 | * | |
403 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
404 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
405 | * readout is broken, so it never gets out of the wait loop again. This was | |
406 | * also reported by others. | |
e05d723f | 407 | * |
d36b49b9 TG |
408 | * Monitoring the jiffies value is inaccurate and the clockevents |
409 | * infrastructure allows us to do a simple substitution of the interrupt | |
410 | * handler. | |
e9e2cdb4 | 411 | * |
d36b49b9 TG |
412 | * The calibration routine also uses the pm_timer when possible, as the PIT |
413 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
414 | * back to normal later in the boot process). | |
e05d723f TG |
415 | */ |
416 | ||
d36b49b9 | 417 | #define LAPIC_CAL_LOOPS (HZ/10) |
e05d723f | 418 | |
f5352fd0 | 419 | static __initdata int lapic_cal_loops = -1; |
d36b49b9 TG |
420 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
421 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
422 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
423 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
1da177e4 | 424 | |
d36b49b9 TG |
425 | /* |
426 | * Temporary interrupt handler. | |
427 | */ | |
428 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
429 | { | |
430 | unsigned long long tsc = 0; | |
431 | long tapic = apic_read(APIC_TMCCT); | |
432 | unsigned long pm = acpi_pm_read_early(); | |
1da177e4 | 433 | |
d36b49b9 TG |
434 | if (cpu_has_tsc) |
435 | rdtscll(tsc); | |
436 | ||
437 | switch (lapic_cal_loops++) { | |
438 | case 0: | |
439 | lapic_cal_t1 = tapic; | |
440 | lapic_cal_tsc1 = tsc; | |
441 | lapic_cal_pm1 = pm; | |
442 | lapic_cal_j1 = jiffies; | |
443 | break; | |
e05d723f | 444 | |
d36b49b9 TG |
445 | case LAPIC_CAL_LOOPS: |
446 | lapic_cal_t2 = tapic; | |
447 | lapic_cal_tsc2 = tsc; | |
448 | if (pm < lapic_cal_pm1) | |
449 | pm += ACPI_PM_OVRRUN; | |
450 | lapic_cal_pm2 = pm; | |
451 | lapic_cal_j2 = jiffies; | |
452 | break; | |
453 | } | |
454 | } | |
1da177e4 | 455 | |
836c129d | 456 | static int __init calibrate_APIC_clock(void) |
d36b49b9 TG |
457 | { |
458 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
459 | const long pm_100ms = PMTMR_TICKS_PER_SEC/10; | |
460 | const long pm_thresh = pm_100ms/100; | |
461 | void (*real_handler)(struct clock_event_device *dev); | |
462 | unsigned long deltaj; | |
463 | long delta, deltapm; | |
ca1b940c | 464 | int pm_referenced = 0; |
1da177e4 | 465 | |
d36b49b9 TG |
466 | local_irq_disable(); |
467 | ||
468 | /* Replace the global interrupt handler */ | |
469 | real_handler = global_clock_event->event_handler; | |
470 | global_clock_event->event_handler = lapic_cal_handler; | |
1da177e4 | 471 | |
1da177e4 | 472 | /* |
d36b49b9 TG |
473 | * Setup the APIC counter to 1e9. There is no way the lapic |
474 | * can underflow in the 100ms detection time frame | |
1da177e4 | 475 | */ |
d36b49b9 | 476 | __setup_APIC_LVTT(1000000000, 0, 0); |
1da177e4 | 477 | |
d36b49b9 TG |
478 | /* Let the interrupts run */ |
479 | local_irq_enable(); | |
480 | ||
ca1b940c TG |
481 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
482 | cpu_relax(); | |
d36b49b9 TG |
483 | |
484 | local_irq_disable(); | |
485 | ||
486 | /* Restore the real event handler */ | |
487 | global_clock_event->event_handler = real_handler; | |
488 | ||
489 | /* Build delta t1-t2 as apic timer counts down */ | |
490 | delta = lapic_cal_t1 - lapic_cal_t2; | |
491 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
492 | ||
493 | /* Check, if the PM timer is available */ | |
494 | deltapm = lapic_cal_pm2 - lapic_cal_pm1; | |
495 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
496 | ||
497 | if (deltapm) { | |
498 | unsigned long mult; | |
499 | u64 res; | |
500 | ||
501 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
502 | ||
503 | if (deltapm > (pm_100ms - pm_thresh) && | |
504 | deltapm < (pm_100ms + pm_thresh)) { | |
505 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
506 | } else { | |
507 | res = (((u64) deltapm) * mult) >> 22; | |
508 | do_div(res, 1000000); | |
509 | printk(KERN_WARNING "APIC calibration not consistent " | |
510 | "with PM Timer: %ldms instead of 100ms\n", | |
511 | (long)res); | |
512 | /* Correct the lapic counter value */ | |
ff8a03a6 | 513 | res = (((u64) delta) * pm_100ms); |
d36b49b9 TG |
514 | do_div(res, deltapm); |
515 | printk(KERN_INFO "APIC delta adjusted to PM-Timer: " | |
516 | "%lu (%ld)\n", (unsigned long) res, delta); | |
517 | delta = (long) res; | |
518 | } | |
ca1b940c | 519 | pm_referenced = 1; |
d36b49b9 | 520 | } |
e05d723f | 521 | |
e9e2cdb4 | 522 | /* Calculate the scaled math multiplication factor */ |
877084fb AM |
523 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, |
524 | lapic_clockevent.shift); | |
e9e2cdb4 TG |
525 | lapic_clockevent.max_delta_ns = |
526 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
527 | lapic_clockevent.min_delta_ns = | |
528 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
529 | ||
d36b49b9 TG |
530 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
531 | ||
532 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
e9e2cdb4 | 533 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); |
d36b49b9 TG |
534 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
535 | calibration_result); | |
e9e2cdb4 | 536 | |
d36b49b9 TG |
537 | if (cpu_has_tsc) { |
538 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
e05d723f | 539 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
d36b49b9 TG |
540 | "%ld.%04ld MHz.\n", |
541 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
542 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
543 | } | |
e05d723f TG |
544 | |
545 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
d36b49b9 TG |
546 | "%u.%04u MHz.\n", |
547 | calibration_result / (1000000 / HZ), | |
548 | calibration_result % (1000000 / HZ)); | |
e05d723f | 549 | |
c2b84b30 TG |
550 | /* |
551 | * Do a sanity check on the APIC calibration result | |
552 | */ | |
553 | if (calibration_result < (1000000 / HZ)) { | |
554 | local_irq_enable(); | |
555 | printk(KERN_WARNING | |
556 | "APIC frequency too slow, disabling apic timer\n"); | |
836c129d | 557 | return -1; |
c2b84b30 TG |
558 | } |
559 | ||
64e474d1 | 560 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; |
836c129d | 561 | |
ca1b940c TG |
562 | /* We trust the pm timer based calibration */ |
563 | if (!pm_referenced) { | |
564 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
d36b49b9 | 565 | |
ca1b940c TG |
566 | /* |
567 | * Setup the apic timer manually | |
568 | */ | |
569 | levt->event_handler = lapic_cal_handler; | |
570 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
571 | lapic_cal_loops = -1; | |
d36b49b9 | 572 | |
ca1b940c TG |
573 | /* Let the interrupts run */ |
574 | local_irq_enable(); | |
d36b49b9 | 575 | |
f5352fd0 | 576 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
ca1b940c | 577 | cpu_relax(); |
d36b49b9 | 578 | |
ca1b940c | 579 | local_irq_disable(); |
d36b49b9 | 580 | |
ca1b940c TG |
581 | /* Stop the lapic timer */ |
582 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
d36b49b9 | 583 | |
ca1b940c | 584 | local_irq_enable(); |
d36b49b9 | 585 | |
ca1b940c TG |
586 | /* Jiffies delta */ |
587 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
588 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
d36b49b9 | 589 | |
d36b49b9 | 590 | /* Check, if the jiffies result is consistent */ |
ca1b940c | 591 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
d36b49b9 | 592 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
ca1b940c | 593 | else |
64e474d1 | 594 | levt->features |= CLOCK_EVT_FEAT_DUMMY; |
4edc5db8 IM |
595 | } else |
596 | local_irq_enable(); | |
e05d723f | 597 | |
64e474d1 | 598 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { |
d36b49b9 TG |
599 | printk(KERN_WARNING |
600 | "APIC timer disabled due to verification failure.\n"); | |
836c129d CG |
601 | return -1; |
602 | } | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
607 | /* | |
608 | * Setup the boot APIC | |
609 | * | |
610 | * Calibrate and verify the result. | |
611 | */ | |
612 | void __init setup_boot_APIC_clock(void) | |
613 | { | |
614 | /* | |
615 | * The local apic timer can be disabled via the kernel | |
616 | * commandline or from the CPU detection code. Register the lapic | |
617 | * timer as a dummy clock event source on SMP systems, so the | |
618 | * broadcast mechanism is used. On UP systems simply ignore it. | |
619 | */ | |
36fef094 | 620 | if (disable_apic_timer) { |
f1ee3789 | 621 | printk(KERN_INFO "Disabling APIC timer\n"); |
d36b49b9 | 622 | /* No broadcast on UP ! */ |
836c129d CG |
623 | if (num_possible_cpus() > 1) { |
624 | lapic_clockevent.mult = 1; | |
625 | setup_APIC_timer(); | |
626 | } | |
627 | return; | |
a5f5e43e | 628 | } |
d36b49b9 | 629 | |
836c129d CG |
630 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
631 | "calibrating APIC timer ...\n"); | |
632 | ||
633 | if (calibrate_APIC_clock()) { | |
634 | /* No broadcast on UP ! */ | |
635 | if (num_possible_cpus() > 1) | |
636 | setup_APIC_timer(); | |
637 | return; | |
638 | } | |
639 | ||
640 | /* | |
641 | * If nmi_watchdog is set to IO_APIC, we need the | |
642 | * PIT/HPET going. Otherwise register lapic as a dummy | |
643 | * device. | |
644 | */ | |
645 | if (nmi_watchdog != NMI_IO_APIC) | |
646 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
647 | else | |
648 | printk(KERN_WARNING "APIC timer registered as dummy," | |
649 | " due to nmi_watchdog=%d!\n", nmi_watchdog); | |
650 | ||
d36b49b9 TG |
651 | /* Setup the lapic or request the broadcast */ |
652 | setup_APIC_timer(); | |
e05d723f | 653 | } |
1da177e4 | 654 | |
457cc52d | 655 | void __cpuinit setup_secondary_APIC_clock(void) |
e05d723f | 656 | { |
e9e2cdb4 | 657 | setup_APIC_timer(); |
e05d723f | 658 | } |
1da177e4 | 659 | |
e05d723f | 660 | /* |
e9e2cdb4 | 661 | * The guts of the apic timer interrupt |
e05d723f | 662 | */ |
e9e2cdb4 | 663 | static void local_apic_timer_interrupt(void) |
e05d723f | 664 | { |
e9e2cdb4 TG |
665 | int cpu = smp_processor_id(); |
666 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
1da177e4 LT |
667 | |
668 | /* | |
d36b49b9 TG |
669 | * Normally we should not be here till LAPIC has been initialized but |
670 | * in some cases like kdump, its possible that there is a pending LAPIC | |
671 | * timer interrupt from previous kernel's context and is delivered in | |
672 | * new kernel the moment interrupts are enabled. | |
e05d723f | 673 | * |
d36b49b9 TG |
674 | * Interrupts are enabled early and LAPIC is setup much later, hence |
675 | * its possible that when we get here evt->event_handler is NULL. | |
676 | * Check for event_handler being NULL and discard the interrupt as | |
677 | * spurious. | |
1da177e4 | 678 | */ |
e9e2cdb4 TG |
679 | if (!evt->event_handler) { |
680 | printk(KERN_WARNING | |
681 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
682 | /* Switch it off */ | |
683 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
684 | return; | |
685 | } | |
686 | ||
0e078e2f TG |
687 | /* |
688 | * the NMI deadlock-detector uses this. | |
689 | */ | |
0b23e8cf CG |
690 | #ifdef CONFIG_X86_64 |
691 | add_pda(apic_timer_irqs, 1); | |
692 | #else | |
e9e2cdb4 | 693 | per_cpu(irq_stat, cpu).apic_timer_irqs++; |
0b23e8cf | 694 | #endif |
e9e2cdb4 TG |
695 | |
696 | evt->event_handler(evt); | |
e05d723f TG |
697 | } |
698 | ||
699 | /* | |
700 | * Local APIC timer interrupt. This is the most natural way for doing | |
701 | * local interrupts, but local timer interrupts can be emulated by | |
702 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
703 | * | |
704 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
705 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
706 | */ | |
75604d7f | 707 | void smp_apic_timer_interrupt(struct pt_regs *regs) |
e05d723f TG |
708 | { |
709 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1da177e4 LT |
710 | |
711 | /* | |
e05d723f TG |
712 | * NOTE! We'd better ACK the irq immediately, |
713 | * because timer handling can be slow. | |
1da177e4 | 714 | */ |
e05d723f | 715 | ack_APIC_irq(); |
1a75a3f0 | 716 | /* |
e05d723f TG |
717 | * update_process_times() expects us to have done irq_enter(). |
718 | * Besides, if we don't timer interrupts ignore the global | |
719 | * interrupt lock, which is the WrongThing (tm) to do. | |
1a75a3f0 | 720 | */ |
6460bc73 CG |
721 | #ifdef CONFIG_X86_64 |
722 | exit_idle(); | |
723 | #endif | |
e05d723f | 724 | irq_enter(); |
e9e2cdb4 | 725 | local_apic_timer_interrupt(); |
e05d723f | 726 | irq_exit(); |
1a75a3f0 | 727 | |
e9e2cdb4 | 728 | set_irq_regs(old_regs); |
e05d723f TG |
729 | } |
730 | ||
731 | int setup_profiling_timer(unsigned int multiplier) | |
732 | { | |
733 | return -EINVAL; | |
734 | } | |
735 | ||
736 | /* | |
737 | * Local APIC start and shutdown | |
738 | */ | |
739 | ||
740 | /** | |
741 | * clear_local_APIC - shutdown the local APIC | |
742 | * | |
743 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
744 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
745 | * leftovers during boot. | |
746 | */ | |
747 | void clear_local_APIC(void) | |
748 | { | |
d3432896 | 749 | int maxlvt; |
0e078e2f | 750 | u32 v; |
1da177e4 | 751 | |
d3432896 AK |
752 | /* APIC hasn't been mapped yet */ |
753 | if (!apic_phys) | |
754 | return; | |
755 | ||
756 | maxlvt = lapic_get_maxlvt(); | |
1da177e4 | 757 | /* |
e05d723f TG |
758 | * Masking an LVT entry can trigger a local APIC error |
759 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1da177e4 | 760 | */ |
e05d723f TG |
761 | if (maxlvt >= 3) { |
762 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
593f4a78 | 763 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
e05d723f | 764 | } |
1da177e4 | 765 | /* |
e05d723f TG |
766 | * Careful: we have to set masks only first to deassert |
767 | * any level-triggered sources. | |
1da177e4 | 768 | */ |
e05d723f | 769 | v = apic_read(APIC_LVTT); |
593f4a78 | 770 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
e05d723f | 771 | v = apic_read(APIC_LVT0); |
593f4a78 | 772 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
e05d723f | 773 | v = apic_read(APIC_LVT1); |
593f4a78 | 774 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
e05d723f TG |
775 | if (maxlvt >= 4) { |
776 | v = apic_read(APIC_LVTPC); | |
593f4a78 | 777 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
1da177e4 | 778 | } |
1da177e4 | 779 | |
e05d723f | 780 | /* lets not touch this if we didn't frob it */ |
6764014b | 781 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) |
e05d723f TG |
782 | if (maxlvt >= 5) { |
783 | v = apic_read(APIC_LVTTHMR); | |
593f4a78 | 784 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); |
e05d723f TG |
785 | } |
786 | #endif | |
1da177e4 | 787 | /* |
e05d723f | 788 | * Clean APIC state for other OSs: |
1da177e4 | 789 | */ |
593f4a78 MR |
790 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
791 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
792 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
e05d723f | 793 | if (maxlvt >= 3) |
593f4a78 | 794 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
e05d723f | 795 | if (maxlvt >= 4) |
593f4a78 | 796 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
1da177e4 | 797 | |
e05d723f TG |
798 | /* Integrated APIC (!82489DX) ? */ |
799 | if (lapic_is_integrated()) { | |
1da177e4 | 800 | if (maxlvt > 3) |
e05d723f | 801 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
1da177e4 | 802 | apic_write(APIC_ESR, 0); |
e05d723f | 803 | apic_read(APIC_ESR); |
1da177e4 | 804 | } |
e05d723f | 805 | } |
1da177e4 | 806 | |
e05d723f TG |
807 | /** |
808 | * disable_local_APIC - clear and disable the local APIC | |
809 | */ | |
810 | void disable_local_APIC(void) | |
811 | { | |
990b183e | 812 | unsigned int value; |
e05d723f TG |
813 | |
814 | clear_local_APIC(); | |
815 | ||
816 | /* | |
817 | * Disable APIC (implies clearing of registers | |
818 | * for 82489DX!). | |
819 | */ | |
820 | value = apic_read(APIC_SPIV); | |
821 | value &= ~APIC_SPIV_APIC_ENABLED; | |
593f4a78 | 822 | apic_write(APIC_SPIV, value); |
e05d723f | 823 | |
990b183e | 824 | #ifdef CONFIG_X86_32 |
e05d723f TG |
825 | /* |
826 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
827 | * restore the disabled state. | |
828 | */ | |
829 | if (enabled_via_apicbase) { | |
830 | unsigned int l, h; | |
831 | ||
832 | rdmsr(MSR_IA32_APICBASE, l, h); | |
833 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
834 | wrmsr(MSR_IA32_APICBASE, l, h); | |
835 | } | |
990b183e | 836 | #endif |
1da177e4 LT |
837 | } |
838 | ||
839 | /* | |
e05d723f TG |
840 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
841 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
842 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
77f72b19 | 843 | * for the case where Linux didn't enable the LAPIC. |
1da177e4 LT |
844 | */ |
845 | void lapic_shutdown(void) | |
846 | { | |
67963132 MS |
847 | unsigned long flags; |
848 | ||
77f72b19 | 849 | if (!cpu_has_apic) |
1da177e4 LT |
850 | return; |
851 | ||
67963132 | 852 | local_irq_save(flags); |
77f72b19 | 853 | |
fe4024dc CG |
854 | #ifdef CONFIG_X86_32 |
855 | if (!enabled_via_apicbase) | |
9ce122c6 | 856 | clear_local_APIC(); |
fe4024dc CG |
857 | else |
858 | #endif | |
77f72b19 ZM |
859 | disable_local_APIC(); |
860 | ||
77f72b19 | 861 | |
67963132 | 862 | local_irq_restore(flags); |
1da177e4 LT |
863 | } |
864 | ||
e05d723f TG |
865 | /* |
866 | * This is to verify that we're looking at a real local APIC. | |
867 | * Check these against your board if the CPUs aren't getting | |
868 | * started for no apparent reason. | |
869 | */ | |
870 | int __init verify_local_APIC(void) | |
1da177e4 | 871 | { |
e05d723f | 872 | unsigned int reg0, reg1; |
1da177e4 | 873 | |
e05d723f TG |
874 | /* |
875 | * The version register is read-only in a real APIC. | |
876 | */ | |
877 | reg0 = apic_read(APIC_LVR); | |
878 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
879 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
880 | reg1 = apic_read(APIC_LVR); | |
881 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
882 | ||
883 | /* | |
884 | * The two version reads above should print the same | |
885 | * numbers. If the second one is different, then we | |
886 | * poke at a non-APIC. | |
887 | */ | |
888 | if (reg1 != reg0) | |
1da177e4 LT |
889 | return 0; |
890 | ||
e05d723f TG |
891 | /* |
892 | * Check if the version looks reasonably. | |
893 | */ | |
894 | reg1 = GET_APIC_VERSION(reg0); | |
895 | if (reg1 == 0x00 || reg1 == 0xff) | |
896 | return 0; | |
897 | reg1 = lapic_get_maxlvt(); | |
898 | if (reg1 < 0x02 || reg1 == 0xff) | |
899 | return 0; | |
f990fff4 | 900 | |
e05d723f TG |
901 | /* |
902 | * The ID register is read/write in a real APIC. | |
903 | */ | |
904 | reg0 = apic_read(APIC_ID); | |
905 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
c93baa1a CG |
906 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); |
907 | reg1 = apic_read(APIC_ID); | |
908 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
909 | apic_write(APIC_ID, reg0); | |
910 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
911 | return 0; | |
e05d723f TG |
912 | |
913 | /* | |
914 | * The next two are just to see if we have sane values. | |
915 | * They're only really relevant if we're in Virtual Wire | |
916 | * compatibility mode, but most boxes are anymore. | |
917 | */ | |
918 | reg0 = apic_read(APIC_LVT0); | |
919 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
920 | reg1 = apic_read(APIC_LVT1); | |
921 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
922 | ||
923 | return 1; | |
1da177e4 LT |
924 | } |
925 | ||
e05d723f TG |
926 | /** |
927 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
928 | */ | |
929 | void __init sync_Arb_IDs(void) | |
1da177e4 | 930 | { |
e05d723f TG |
931 | /* |
932 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
933 | * needed on AMD. | |
934 | */ | |
f44d9efd | 935 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
e05d723f | 936 | return; |
6f6da97f | 937 | |
e05d723f TG |
938 | /* |
939 | * Wait for idle. | |
940 | */ | |
941 | apic_wait_icr_idle(); | |
1da177e4 | 942 | |
e05d723f | 943 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
6f6da97f CG |
944 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
945 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
e05d723f | 946 | } |
1da177e4 | 947 | |
e05d723f TG |
948 | /* |
949 | * An initial setup of the virtual wire mode. | |
950 | */ | |
951 | void __init init_bsp_APIC(void) | |
952 | { | |
638c0411 | 953 | unsigned int value; |
f990fff4 | 954 | |
e05d723f TG |
955 | /* |
956 | * Don't do the setup now if we have a SMP BIOS as the | |
957 | * through-I/O-APIC virtual wire mode might be active. | |
958 | */ | |
959 | if (smp_found_config || !cpu_has_apic) | |
960 | return; | |
1da177e4 LT |
961 | |
962 | /* | |
e05d723f | 963 | * Do not trust the local APIC being empty at bootup. |
1da177e4 | 964 | */ |
e05d723f | 965 | clear_local_APIC(); |
1da177e4 | 966 | |
e05d723f TG |
967 | /* |
968 | * Enable APIC. | |
969 | */ | |
970 | value = apic_read(APIC_SPIV); | |
971 | value &= ~APIC_VECTOR_MASK; | |
972 | value |= APIC_SPIV_APIC_ENABLED; | |
973 | ||
638c0411 | 974 | #ifdef CONFIG_X86_32 |
e05d723f TG |
975 | /* This bit is reserved on P4/Xeon and should be cleared */ |
976 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
977 | (boot_cpu_data.x86 == 15)) | |
978 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
979 | else | |
638c0411 | 980 | #endif |
e05d723f TG |
981 | value |= APIC_SPIV_FOCUS_DISABLED; |
982 | value |= SPURIOUS_APIC_VECTOR; | |
593f4a78 | 983 | apic_write(APIC_SPIV, value); |
e05d723f TG |
984 | |
985 | /* | |
986 | * Set up the virtual wire mode. | |
987 | */ | |
593f4a78 | 988 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
e05d723f TG |
989 | value = APIC_DM_NMI; |
990 | if (!lapic_is_integrated()) /* 82489DX */ | |
991 | value |= APIC_LVT_LEVEL_TRIGGER; | |
593f4a78 | 992 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
993 | } |
994 | ||
a4928cff | 995 | static void __cpuinit lapic_setup_esr(void) |
df7939ae GOC |
996 | { |
997 | unsigned long oldvalue, value, maxlvt; | |
998 | if (lapic_is_integrated() && !esr_disable) { | |
c43da2f5 CG |
999 | if (esr_disable) { |
1000 | /* | |
1001 | * Something untraceable is creating bad interrupts on | |
1002 | * secondary quads ... for the moment, just leave the | |
1003 | * ESR disabled - we can't do anything useful with the | |
1004 | * errors anyway - mbligh | |
1005 | */ | |
1006 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
1007 | return; | |
1008 | } | |
df7939ae GOC |
1009 | /* !82489DX */ |
1010 | maxlvt = lapic_get_maxlvt(); | |
1011 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1012 | apic_write(APIC_ESR, 0); | |
1013 | oldvalue = apic_read(APIC_ESR); | |
1014 | ||
1015 | /* enables sending errors */ | |
1016 | value = ERROR_APIC_VECTOR; | |
593f4a78 | 1017 | apic_write(APIC_LVTERR, value); |
df7939ae GOC |
1018 | /* |
1019 | * spec says clear errors after enabling vector. | |
1020 | */ | |
1021 | if (maxlvt > 3) | |
1022 | apic_write(APIC_ESR, 0); | |
1023 | value = apic_read(APIC_ESR); | |
1024 | if (value != oldvalue) | |
1025 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1026 | "vector: 0x%08lx after: 0x%08lx\n", | |
1027 | oldvalue, value); | |
1028 | } else { | |
c43da2f5 | 1029 | printk(KERN_INFO "No ESR for 82489DX.\n"); |
df7939ae GOC |
1030 | } |
1031 | } | |
1032 | ||
1033 | ||
e05d723f TG |
1034 | /** |
1035 | * setup_local_APIC - setup the local APIC | |
1da177e4 | 1036 | */ |
d5337983 | 1037 | void __cpuinit setup_local_APIC(void) |
e05d723f | 1038 | { |
89c38c28 | 1039 | unsigned int value; |
e05d723f | 1040 | int i, j; |
1da177e4 | 1041 | |
89c38c28 | 1042 | #ifdef CONFIG_X86_32 |
e05d723f TG |
1043 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
1044 | if (esr_disable) { | |
1045 | apic_write(APIC_ESR, 0); | |
1046 | apic_write(APIC_ESR, 0); | |
1047 | apic_write(APIC_ESR, 0); | |
1048 | apic_write(APIC_ESR, 0); | |
1049 | } | |
89c38c28 | 1050 | #endif |
1da177e4 | 1051 | |
89c38c28 | 1052 | preempt_disable(); |
1da177e4 | 1053 | |
e05d723f TG |
1054 | /* |
1055 | * Double-check whether this APIC is really registered. | |
89c38c28 | 1056 | * This is meaningless in clustered apic mode, so we skip it. |
e05d723f TG |
1057 | */ |
1058 | if (!apic_id_registered()) | |
89c38c28 | 1059 | BUG(); |
1da177e4 | 1060 | |
e05d723f TG |
1061 | /* |
1062 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1063 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1064 | * document number 292116). So here it goes... | |
1065 | */ | |
1066 | init_apic_ldr(); | |
1da177e4 | 1067 | |
e05d723f TG |
1068 | /* |
1069 | * Set Task Priority to 'accept all'. We never change this | |
1070 | * later on. | |
1071 | */ | |
1072 | value = apic_read(APIC_TASKPRI); | |
1073 | value &= ~APIC_TPRI_MASK; | |
593f4a78 | 1074 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1075 | |
e05d723f TG |
1076 | /* |
1077 | * After a crash, we no longer service the interrupts and a pending | |
1078 | * interrupt from previous kernel might still have ISR bit set. | |
1079 | * | |
1080 | * Most probably by now CPU has serviced that pending interrupt and | |
1081 | * it might not have done the ack_APIC_irq() because it thought, | |
1082 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1083 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1084 | * the interrupt. Hence a vector might get locked. It was noticed | |
1085 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1086 | */ | |
1087 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1088 | value = apic_read(APIC_ISR + i*0x10); | |
1089 | for (j = 31; j >= 0; j--) { | |
1090 | if (value & (1<<j)) | |
1091 | ack_APIC_irq(); | |
1092 | } | |
1093 | } | |
1da177e4 | 1094 | |
e05d723f TG |
1095 | /* |
1096 | * Now that we are all set up, enable the APIC | |
1097 | */ | |
1098 | value = apic_read(APIC_SPIV); | |
1099 | value &= ~APIC_VECTOR_MASK; | |
1100 | /* | |
1101 | * Enable APIC | |
1102 | */ | |
1103 | value |= APIC_SPIV_APIC_ENABLED; | |
1da177e4 | 1104 | |
89c38c28 | 1105 | #ifdef CONFIG_X86_32 |
e05d723f TG |
1106 | /* |
1107 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1108 | * certain networking cards. If high frequency interrupts are | |
1109 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1110 | * entry is masked/unmasked at a high rate as well then sooner or | |
1111 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1112 | * from the device. If focus CPU is disabled then the hang goes | |
1113 | * away, oh well :-( | |
1114 | * | |
1115 | * [ This bug can be reproduced easily with a level-triggered | |
1116 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1117 | * BX chipset. ] | |
1118 | */ | |
1119 | /* | |
1120 | * Actually disabling the focus CPU check just makes the hang less | |
1121 | * frequent as it makes the interrupt distributon model be more | |
1122 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1123 | * See also the comment in end_level_ioapic_irq(). --macro | |
1124 | */ | |
1da177e4 | 1125 | |
89c38c28 CG |
1126 | /* |
1127 | * - enable focus processor (bit==0) | |
1128 | * - 64bit mode always use processor focus | |
1129 | * so no need to set it | |
1130 | */ | |
e05d723f | 1131 | value &= ~APIC_SPIV_FOCUS_DISABLED; |
89c38c28 | 1132 | #endif |
1da177e4 | 1133 | |
e05d723f TG |
1134 | /* |
1135 | * Set spurious IRQ vector | |
1136 | */ | |
1137 | value |= SPURIOUS_APIC_VECTOR; | |
593f4a78 | 1138 | apic_write(APIC_SPIV, value); |
e05d723f TG |
1139 | |
1140 | /* | |
1141 | * Set up LVT0, LVT1: | |
1142 | * | |
1143 | * set up through-local-APIC on the BP's LINT0. This is not | |
27b46d76 | 1144 | * strictly necessary in pure symmetric-IO mode, but sometimes |
e05d723f TG |
1145 | * we delegate interrupts to the 8259A. |
1146 | */ | |
1147 | /* | |
1148 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1149 | */ | |
1150 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
1151 | if (!smp_processor_id() && (pic_mode || !value)) { | |
1152 | value = APIC_DM_EXTINT; | |
1153 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
1154 | smp_processor_id()); | |
1155 | } else { | |
1156 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
1157 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
1158 | smp_processor_id()); | |
1159 | } | |
593f4a78 | 1160 | apic_write(APIC_LVT0, value); |
e05d723f TG |
1161 | |
1162 | /* | |
1163 | * only the BP should see the LINT1 NMI signal, obviously. | |
1164 | */ | |
1165 | if (!smp_processor_id()) | |
1166 | value = APIC_DM_NMI; | |
1167 | else | |
1168 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 | 1169 | if (!lapic_is_integrated()) /* 82489DX */ |
e05d723f | 1170 | value |= APIC_LVT_LEVEL_TRIGGER; |
593f4a78 | 1171 | apic_write(APIC_LVT1, value); |
89c38c28 CG |
1172 | |
1173 | preempt_enable(); | |
ac60aae5 | 1174 | } |
e05d723f | 1175 | |
ac60aae5 GOC |
1176 | void __cpuinit end_local_APIC_setup(void) |
1177 | { | |
ac60aae5 | 1178 | lapic_setup_esr(); |
fa6b95fc CG |
1179 | |
1180 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1181 | { |
1182 | unsigned int value; | |
1183 | /* Disable the local apic timer */ | |
1184 | value = apic_read(APIC_LVTT); | |
1185 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1186 | apic_write(APIC_LVTT, value); | |
1187 | } | |
fa6b95fc | 1188 | #endif |
e9e2cdb4 | 1189 | |
e05d723f TG |
1190 | setup_apic_nmi_watchdog(NULL); |
1191 | apic_pm_activate(); | |
1da177e4 LT |
1192 | } |
1193 | ||
e05d723f TG |
1194 | /* |
1195 | * Detect and initialize APIC | |
1196 | */ | |
e83a5fdc | 1197 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1198 | { |
1199 | u32 h, l, features; | |
1da177e4 LT |
1200 | |
1201 | /* Disabled by kernel option? */ | |
914bebfa | 1202 | if (disable_apic) |
1da177e4 LT |
1203 | return -1; |
1204 | ||
1da177e4 LT |
1205 | switch (boot_cpu_data.x86_vendor) { |
1206 | case X86_VENDOR_AMD: | |
1207 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
e05d723f | 1208 | (boot_cpu_data.x86 == 15)) |
1da177e4 LT |
1209 | break; |
1210 | goto no_apic; | |
1211 | case X86_VENDOR_INTEL: | |
1212 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1213 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1214 | break; | |
1215 | goto no_apic; | |
1216 | default: | |
1217 | goto no_apic; | |
1218 | } | |
1219 | ||
1220 | if (!cpu_has_apic) { | |
1221 | /* | |
e05d723f TG |
1222 | * Over-ride BIOS and try to enable the local APIC only if |
1223 | * "lapic" specified. | |
1da177e4 | 1224 | */ |
914bebfa | 1225 | if (!force_enable_local_apic) { |
e05d723f | 1226 | printk(KERN_INFO "Local APIC disabled by BIOS -- " |
1da177e4 LT |
1227 | "you can enable it with \"lapic\"\n"); |
1228 | return -1; | |
1229 | } | |
1230 | /* | |
e05d723f TG |
1231 | * Some BIOSes disable the local APIC in the APIC_BASE |
1232 | * MSR. This can only be done in software for Intel P6 or later | |
1233 | * and AMD K7 (Model > 1) or later. | |
1da177e4 LT |
1234 | */ |
1235 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1236 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
e05d723f TG |
1237 | printk(KERN_INFO |
1238 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1da177e4 LT |
1239 | l &= ~MSR_IA32_APICBASE_BASE; |
1240 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1241 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1242 | enabled_via_apicbase = 1; | |
1243 | } | |
1244 | } | |
1245 | /* | |
1246 | * The APIC feature bit should now be enabled | |
1247 | * in `cpuid' | |
1248 | */ | |
1249 | features = cpuid_edx(1); | |
1250 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
e05d723f | 1251 | printk(KERN_WARNING "Could not enable APIC!\n"); |
1da177e4 LT |
1252 | return -1; |
1253 | } | |
53756d37 | 1254 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1da177e4 LT |
1255 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
1256 | ||
1257 | /* The BIOS may have set up the APIC at some other address */ | |
1258 | rdmsr(MSR_IA32_APICBASE, l, h); | |
e05d723f TG |
1259 | if (l & MSR_IA32_APICBASE_ENABLE) |
1260 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1da177e4 | 1261 | |
e05d723f | 1262 | printk(KERN_INFO "Found and enabled local APIC!\n"); |
1da177e4 | 1263 | |
e05d723f | 1264 | apic_pm_activate(); |
1da177e4 | 1265 | |
e05d723f | 1266 | return 0; |
1da177e4 | 1267 | |
e05d723f TG |
1268 | no_apic: |
1269 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1270 | return -1; | |
1271 | } | |
1da177e4 | 1272 | |
e05d723f TG |
1273 | /** |
1274 | * init_apic_mappings - initialize APIC mappings | |
1275 | */ | |
1276 | void __init init_apic_mappings(void) | |
1da177e4 | 1277 | { |
1da177e4 | 1278 | /* |
e05d723f TG |
1279 | * If no local APIC can be found then set up a fake all |
1280 | * zeroes page to simulate the local APIC and another | |
1281 | * one for the IO-APIC. | |
1da177e4 | 1282 | */ |
e05d723f TG |
1283 | if (!smp_found_config && detect_init_APIC()) { |
1284 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1285 | apic_phys = __pa(apic_phys); | |
1286 | } else | |
1287 | apic_phys = mp_lapic_addr; | |
1da177e4 | 1288 | |
e05d723f TG |
1289 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
1290 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
1291 | apic_phys); | |
1da177e4 | 1292 | |
e05d723f TG |
1293 | /* |
1294 | * Fetch the APIC ID of the BSP in case we have a | |
1295 | * default configuration (or the MP table is broken). | |
1296 | */ | |
1297 | if (boot_cpu_physical_apicid == -1U) | |
4c9961d5 | 1298 | boot_cpu_physical_apicid = read_apic_id(); |
1da177e4 | 1299 | |
1da177e4 LT |
1300 | } |
1301 | ||
e05d723f TG |
1302 | /* |
1303 | * This initializes the IO-APIC and APIC hardware if this is | |
1304 | * a UP kernel. | |
1305 | */ | |
e81b2c62 AS |
1306 | |
1307 | int apic_version[MAX_APICS]; | |
1308 | ||
e83a5fdc | 1309 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1310 | { |
e05d723f TG |
1311 | if (!smp_found_config && !cpu_has_apic) |
1312 | return -1; | |
6eb0a0fd | 1313 | |
e05d723f TG |
1314 | /* |
1315 | * Complain if the BIOS pretends there is one. | |
1316 | */ | |
1317 | if (!cpu_has_apic && | |
1318 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1319 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1320 | boot_cpu_physical_apicid); | |
53756d37 | 1321 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
e05d723f | 1322 | return -1; |
6eb0a0fd | 1323 | } |
6eb0a0fd | 1324 | |
e05d723f | 1325 | verify_local_APIC(); |
6eb0a0fd | 1326 | |
e05d723f | 1327 | connect_bsp_APIC(); |
6eb0a0fd | 1328 | |
e05d723f TG |
1329 | /* |
1330 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1331 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1332 | * might be zero if read from MP tables. Get it from LAPIC. | |
1333 | */ | |
1334 | #ifdef CONFIG_CRASH_DUMP | |
4c9961d5 | 1335 | boot_cpu_physical_apicid = read_apic_id(); |
e05d723f | 1336 | #endif |
b6df1b8b | 1337 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
1da177e4 | 1338 | |
e05d723f | 1339 | setup_local_APIC(); |
1da177e4 | 1340 | |
acae7d90 MR |
1341 | #ifdef CONFIG_X86_IO_APIC |
1342 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) | |
1343 | #endif | |
1344 | localise_nmi_watchdog(); | |
ac60aae5 | 1345 | end_local_APIC_setup(); |
e05d723f TG |
1346 | #ifdef CONFIG_X86_IO_APIC |
1347 | if (smp_found_config) | |
1348 | if (!skip_ioapic_setup && nr_ioapics) | |
1349 | setup_IO_APIC(); | |
1da177e4 | 1350 | #endif |
e05d723f | 1351 | setup_boot_clock(); |
1da177e4 | 1352 | |
e05d723f | 1353 | return 0; |
1da177e4 LT |
1354 | } |
1355 | ||
e05d723f TG |
1356 | /* |
1357 | * Local APIC interrupts | |
1358 | */ | |
1359 | ||
1da177e4 LT |
1360 | /* |
1361 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1362 | */ | |
e9e2cdb4 | 1363 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1364 | { |
1365 | unsigned long v; | |
1366 | ||
1367 | irq_enter(); | |
1368 | /* | |
1369 | * Check if this really is a spurious interrupt and ACK it | |
1370 | * if it is a vectored one. Just in case... | |
1371 | * Spurious interrupts should not be ACKed. | |
1372 | */ | |
1373 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1374 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1375 | ack_APIC_irq(); | |
1376 | ||
1377 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
e05d723f TG |
1378 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " |
1379 | "should never happen.\n", smp_processor_id()); | |
38e760a1 | 1380 | __get_cpu_var(irq_stat).irq_spurious_count++; |
1da177e4 LT |
1381 | irq_exit(); |
1382 | } | |
1383 | ||
1384 | /* | |
1385 | * This interrupt should never happen with our APIC/SMP architecture | |
1386 | */ | |
e9e2cdb4 | 1387 | void smp_error_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1388 | { |
1389 | unsigned long v, v1; | |
1390 | ||
1391 | irq_enter(); | |
1392 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1393 | v = apic_read(APIC_ESR); | |
1394 | apic_write(APIC_ESR, 0); | |
1395 | v1 = apic_read(APIC_ESR); | |
1396 | ack_APIC_irq(); | |
1397 | atomic_inc(&irq_err_count); | |
1398 | ||
1399 | /* Here is what the APIC error bits mean: | |
1400 | 0: Send CS error | |
1401 | 1: Receive CS error | |
1402 | 2: Send accept error | |
1403 | 3: Receive accept error | |
1404 | 4: Reserved | |
1405 | 5: Send illegal vector | |
1406 | 6: Received illegal vector | |
1407 | 7: Illegal register address | |
1408 | */ | |
ff8a03a6 | 1409 | printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", |
e05d723f | 1410 | smp_processor_id(), v , v1); |
1da177e4 LT |
1411 | irq_exit(); |
1412 | } | |
1413 | ||
e05d723f TG |
1414 | /** |
1415 | * connect_bsp_APIC - attach the APIC to the interrupt system | |
1416 | */ | |
1417 | void __init connect_bsp_APIC(void) | |
1418 | { | |
36c9d674 | 1419 | #ifdef CONFIG_X86_32 |
e05d723f TG |
1420 | if (pic_mode) { |
1421 | /* | |
1422 | * Do not trust the local APIC being empty at bootup. | |
1423 | */ | |
1424 | clear_local_APIC(); | |
1425 | /* | |
1426 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1427 | * local APIC to INT and NMI lines. | |
1428 | */ | |
1429 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1430 | "enabling APIC mode.\n"); | |
1431 | outb(0x70, 0x22); | |
1432 | outb(0x01, 0x23); | |
1da177e4 | 1433 | } |
36c9d674 | 1434 | #endif |
e05d723f TG |
1435 | enable_apic_mode(); |
1436 | } | |
1da177e4 | 1437 | |
e05d723f TG |
1438 | /** |
1439 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1440 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1441 | * | |
1442 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1443 | * APIC is disabled. | |
1444 | */ | |
1445 | void disconnect_bsp_APIC(int virt_wire_setup) | |
1446 | { | |
1b4ee4e4 CG |
1447 | unsigned int value; |
1448 | ||
c177b0bc | 1449 | #ifdef CONFIG_X86_32 |
e05d723f TG |
1450 | if (pic_mode) { |
1451 | /* | |
1452 | * Put the board back into PIC mode (has an effect only on | |
1453 | * certain older boards). Note that APIC interrupts, including | |
1454 | * IPIs, won't work beyond this point! The only exception are | |
1455 | * INIT IPIs. | |
1456 | */ | |
1457 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1458 | "entering PIC mode.\n"); | |
1459 | outb(0x70, 0x22); | |
1460 | outb(0x00, 0x23); | |
c177b0bc CG |
1461 | return; |
1462 | } | |
1463 | #endif | |
1da177e4 | 1464 | |
c177b0bc | 1465 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1466 | |
c177b0bc CG |
1467 | /* For the spurious interrupt use vector F, and enable it */ |
1468 | value = apic_read(APIC_SPIV); | |
1469 | value &= ~APIC_VECTOR_MASK; | |
1470 | value |= APIC_SPIV_APIC_ENABLED; | |
1471 | value |= 0xf; | |
1472 | apic_write(APIC_SPIV, value); | |
1da177e4 | 1473 | |
c177b0bc | 1474 | if (!virt_wire_setup) { |
e05d723f | 1475 | /* |
c177b0bc CG |
1476 | * For LVT0 make it edge triggered, active high, |
1477 | * external and enabled | |
e05d723f | 1478 | */ |
c177b0bc CG |
1479 | value = apic_read(APIC_LVT0); |
1480 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
e05d723f TG |
1481 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
1482 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1483 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
c177b0bc CG |
1484 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
1485 | apic_write(APIC_LVT0, value); | |
1486 | } else { | |
1487 | /* Disable LVT0 */ | |
1488 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
e05d723f | 1489 | } |
1da177e4 | 1490 | |
c177b0bc CG |
1491 | /* |
1492 | * For LVT1 make it edge triggered, active high, | |
1493 | * nmi and enabled | |
1494 | */ | |
1495 | value = apic_read(APIC_LVT1); | |
1496 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1497 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1498 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1499 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1500 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1501 | apic_write(APIC_LVT1, value); | |
e05d723f | 1502 | } |
903dcb5a AS |
1503 | |
1504 | void __cpuinit generic_processor_info(int apicid, int version) | |
1505 | { | |
1506 | int cpu; | |
1507 | cpumask_t tmp_map; | |
903dcb5a AS |
1508 | |
1509 | /* | |
1510 | * Validate version | |
1511 | */ | |
1512 | if (version == 0x0) { | |
1513 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1514 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1515 | version); | |
1516 | version = 0x10; | |
1517 | } | |
1518 | apic_version[apicid] = version; | |
1519 | ||
903dcb5a AS |
1520 | if (num_processors >= NR_CPUS) { |
1521 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1522 | " Processor ignored.\n", NR_CPUS); | |
1523 | return; | |
1524 | } | |
1525 | ||
903dcb5a AS |
1526 | num_processors++; |
1527 | cpus_complement(tmp_map, cpu_present_map); | |
1528 | cpu = first_cpu(tmp_map); | |
1529 | ||
1b313f4a CG |
1530 | physid_set(apicid, phys_cpu_present_map); |
1531 | if (apicid == boot_cpu_physical_apicid) { | |
903dcb5a AS |
1532 | /* |
1533 | * x86_bios_cpu_apicid is required to have processors listed | |
1534 | * in same order as logical cpu numbers. Hence the first | |
1535 | * entry is BSP, and so on. | |
1536 | */ | |
1537 | cpu = 0; | |
1b313f4a | 1538 | } |
e0da3364 YL |
1539 | if (apicid > max_physical_apicid) |
1540 | max_physical_apicid = apicid; | |
1541 | ||
1b313f4a | 1542 | #ifdef CONFIG_X86_32 |
903dcb5a AS |
1543 | /* |
1544 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1545 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1546 | * before this can be done without some confusion. | |
1547 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1548 | * - Ashok Raj <ashok.raj@intel.com> | |
1549 | */ | |
e0da3364 | 1550 | if (max_physical_apicid >= 8) { |
903dcb5a AS |
1551 | switch (boot_cpu_data.x86_vendor) { |
1552 | case X86_VENDOR_INTEL: | |
1553 | if (!APIC_XAPIC(version)) { | |
1554 | def_to_bigsmp = 0; | |
1555 | break; | |
1556 | } | |
1557 | /* If P4 and above fall through */ | |
1558 | case X86_VENDOR_AMD: | |
1559 | def_to_bigsmp = 1; | |
1560 | } | |
1561 | } | |
1b313f4a CG |
1562 | #endif |
1563 | ||
1564 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
903dcb5a | 1565 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1566 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1567 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1568 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
903dcb5a AS |
1569 | |
1570 | cpu_to_apicid[cpu] = apicid; | |
1571 | bios_cpu_apicid[cpu] = apicid; | |
1572 | } else { | |
1573 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1574 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1575 | } | |
1576 | #endif | |
1b313f4a | 1577 | |
903dcb5a AS |
1578 | cpu_set(cpu, cpu_possible_map); |
1579 | cpu_set(cpu, cpu_present_map); | |
1580 | } | |
1581 | ||
e05d723f TG |
1582 | /* |
1583 | * Power management | |
1584 | */ | |
1585 | #ifdef CONFIG_PM | |
1586 | ||
1587 | static struct { | |
274cfe59 CG |
1588 | /* |
1589 | * 'active' is true if the local APIC was enabled by us and | |
1590 | * not the BIOS; this signifies that we are also responsible | |
1591 | * for disabling it before entering apm/acpi suspend | |
1592 | */ | |
e05d723f TG |
1593 | int active; |
1594 | /* r/w apic fields */ | |
1595 | unsigned int apic_id; | |
1596 | unsigned int apic_taskpri; | |
1597 | unsigned int apic_ldr; | |
1598 | unsigned int apic_dfr; | |
1599 | unsigned int apic_spiv; | |
1600 | unsigned int apic_lvtt; | |
1601 | unsigned int apic_lvtpc; | |
1602 | unsigned int apic_lvt0; | |
1603 | unsigned int apic_lvt1; | |
1604 | unsigned int apic_lvterr; | |
1605 | unsigned int apic_tmict; | |
1606 | unsigned int apic_tdcr; | |
1607 | unsigned int apic_thmr; | |
1608 | } apic_pm_state; | |
1609 | ||
1610 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1611 | { | |
1612 | unsigned long flags; | |
1613 | int maxlvt; | |
1614 | ||
1615 | if (!apic_pm_state.active) | |
1616 | return 0; | |
1617 | ||
1618 | maxlvt = lapic_get_maxlvt(); | |
1619 | ||
1620 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
1621 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1622 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1623 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1624 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1625 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1626 | if (maxlvt >= 4) | |
1627 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1628 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1629 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1630 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1631 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1632 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1633 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
e05d723f TG |
1634 | if (maxlvt >= 5) |
1635 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1da177e4 | 1636 | #endif |
1e4c85f9 | 1637 | |
e05d723f TG |
1638 | local_irq_save(flags); |
1639 | disable_local_APIC(); | |
1640 | local_irq_restore(flags); | |
1e4c85f9 | 1641 | return 0; |
1da177e4 | 1642 | } |
1a3f239d | 1643 | |
e05d723f | 1644 | static int lapic_resume(struct sys_device *dev) |
1a3f239d | 1645 | { |
e05d723f TG |
1646 | unsigned int l, h; |
1647 | unsigned long flags; | |
1648 | int maxlvt; | |
1649 | ||
1650 | if (!apic_pm_state.active) | |
1651 | return 0; | |
1652 | ||
1653 | maxlvt = lapic_get_maxlvt(); | |
1654 | ||
1655 | local_irq_save(flags); | |
1656 | ||
92206c90 CG |
1657 | #ifdef CONFIG_X86_64 |
1658 | if (x2apic) | |
1659 | enable_x2apic(); | |
1660 | else | |
1661 | #endif | |
e75bedf4 | 1662 | { |
92206c90 CG |
1663 | /* |
1664 | * Make sure the APICBASE points to the right address | |
1665 | * | |
1666 | * FIXME! This will be wrong if we ever support suspend on | |
1667 | * SMP! We'll need to do this as part of the CPU restore! | |
1668 | */ | |
1669 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1670 | l &= ~MSR_IA32_APICBASE_BASE; | |
1671 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1672 | wrmsr(MSR_IA32_APICBASE, l, h); | |
e75bedf4 | 1673 | } |
e05d723f TG |
1674 | |
1675 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1676 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1677 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1678 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1679 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1680 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1681 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1682 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 1683 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
e05d723f TG |
1684 | if (maxlvt >= 5) |
1685 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1686 | #endif | |
1687 | if (maxlvt >= 4) | |
1688 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1689 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1690 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1691 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1692 | apic_write(APIC_ESR, 0); | |
1693 | apic_read(APIC_ESR); | |
1694 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1695 | apic_write(APIC_ESR, 0); | |
1696 | apic_read(APIC_ESR); | |
92206c90 | 1697 | |
e05d723f | 1698 | local_irq_restore(flags); |
92206c90 | 1699 | |
1a3f239d RR |
1700 | return 0; |
1701 | } | |
1a3f239d | 1702 | |
e05d723f TG |
1703 | /* |
1704 | * This device has no shutdown method - fully functioning local APICs | |
1705 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1706 | */ | |
1707 | ||
1708 | static struct sysdev_class lapic_sysclass = { | |
af5ca3f4 | 1709 | .name = "lapic", |
e05d723f TG |
1710 | .resume = lapic_resume, |
1711 | .suspend = lapic_suspend, | |
1712 | }; | |
1713 | ||
1714 | static struct sys_device device_lapic = { | |
1715 | .id = 0, | |
1716 | .cls = &lapic_sysclass, | |
1717 | }; | |
1718 | ||
457cc52d | 1719 | static void __cpuinit apic_pm_activate(void) |
1a3f239d | 1720 | { |
e05d723f | 1721 | apic_pm_state.active = 1; |
1a3f239d | 1722 | } |
1a3f239d | 1723 | |
e05d723f TG |
1724 | static int __init init_lapic_sysfs(void) |
1725 | { | |
1726 | int error; | |
1727 | ||
1728 | if (!cpu_has_apic) | |
1729 | return 0; | |
1730 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
1731 | ||
1732 | error = sysdev_class_register(&lapic_sysclass); | |
1733 | if (!error) | |
1734 | error = sysdev_register(&device_lapic); | |
1735 | return error; | |
1736 | } | |
1737 | device_initcall(init_lapic_sysfs); | |
1738 | ||
1739 | #else /* CONFIG_PM */ | |
1740 | ||
1741 | static void apic_pm_activate(void) { } | |
1742 | ||
1743 | #endif /* CONFIG_PM */ | |
0e078e2f TG |
1744 | |
1745 | /* | |
1746 | * APIC command line parameters | |
1747 | */ | |
1748 | static int __init parse_lapic(char *arg) | |
1749 | { | |
914bebfa | 1750 | force_enable_local_apic = 1; |
0e078e2f TG |
1751 | return 0; |
1752 | } | |
1753 | early_param("lapic", parse_lapic); | |
1754 | ||
789fa735 | 1755 | static int __init setup_disableapic(char *arg) |
0e078e2f | 1756 | { |
914bebfa | 1757 | disable_apic = 1; |
9175fc06 | 1758 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
0e078e2f TG |
1759 | return 0; |
1760 | } | |
789fa735 | 1761 | early_param("disableapic", setup_disableapic); |
0e078e2f | 1762 | |
789fa735 CG |
1763 | /* same as disableapic, for compatibility */ |
1764 | static int __init setup_nolapic(char *arg) | |
0e078e2f | 1765 | { |
789fa735 | 1766 | return setup_disableapic(arg); |
0e078e2f | 1767 | } |
789fa735 | 1768 | early_param("nolapic", setup_nolapic); |
0e078e2f TG |
1769 | |
1770 | static int __init parse_lapic_timer_c2_ok(char *arg) | |
1771 | { | |
1772 | local_apic_timer_c2_ok = 1; | |
1773 | return 0; | |
1774 | } | |
1775 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1776 | ||
36fef094 | 1777 | static int __init parse_disable_apic_timer(char *arg) |
0e078e2f | 1778 | { |
36fef094 | 1779 | disable_apic_timer = 1; |
0e078e2f TG |
1780 | return 0; |
1781 | } | |
36fef094 CG |
1782 | early_param("noapictimer", parse_disable_apic_timer); |
1783 | ||
1784 | static int __init parse_nolapic_timer(char *arg) | |
0e078e2f | 1785 | { |
36fef094 CG |
1786 | disable_apic_timer = 1; |
1787 | return 0; | |
1788 | } | |
1789 | early_param("nolapic_timer", parse_nolapic_timer); | |
0e078e2f | 1790 | |
920fa7a5 CG |
1791 | #ifdef CONFIG_X86_64 |
1792 | static __init int setup_apicpmtimer(char *s) | |
1793 | { | |
1794 | apic_calibrate_pmtmr = 1; | |
1795 | notsc_setup(NULL); | |
1796 | return 0; | |
1797 | } | |
1798 | __setup("apicpmtimer", setup_apicpmtimer); | |
1799 | #endif | |
1800 | ||
48d97cb6 | 1801 | static int __init apic_set_verbosity(char *arg) |
0e078e2f | 1802 | { |
79af9bec CG |
1803 | if (!arg) { |
1804 | #ifdef CONFIG_X86_64 | |
1805 | skip_ioapic_setup = 0; | |
1806 | ioapic_force = 1; | |
1807 | return 0; | |
1808 | #endif | |
48d97cb6 | 1809 | return -EINVAL; |
79af9bec | 1810 | } |
48d97cb6 | 1811 | |
79af9bec | 1812 | if (strcmp("debug", arg) == 0) |
0e078e2f | 1813 | apic_verbosity = APIC_DEBUG; |
79af9bec | 1814 | else if (strcmp("verbose", arg) == 0) |
0e078e2f | 1815 | apic_verbosity = APIC_VERBOSE; |
79af9bec CG |
1816 | else { |
1817 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1818 | " use apic=verbose or apic=debug\n", arg); | |
1819 | return -EINVAL; | |
1820 | } | |
48d97cb6 | 1821 | |
fb6bef80 | 1822 | return 0; |
0e078e2f | 1823 | } |
fb6bef80 | 1824 | early_param("apic", apic_set_verbosity); |
0e078e2f | 1825 | |
746f2eb7 CG |
1826 | static int __init lapic_insert_resource(void) |
1827 | { | |
1828 | if (!apic_phys) | |
1829 | return -1; | |
1830 | ||
1831 | /* Put local APIC into the resource map. */ | |
1832 | lapic_resource.start = apic_phys; | |
1833 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1834 | insert_resource(&iomem_resource, &lapic_resource); | |
1835 | ||
1836 | return 0; | |
1837 | } | |
1838 | ||
1839 | /* | |
1840 | * need call insert after e820_reserve_resources() | |
1841 | * that is using request_resource | |
1842 | */ | |
1843 | late_initcall(lapic_insert_resource); |