Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
f3705136 | 26 | #include <linux/cpu.h> |
e9e2cdb4 | 27 | #include <linux/clockchips.h> |
d36b49b9 | 28 | #include <linux/acpi_pmtmr.h> |
6eb0a0fd | 29 | #include <linux/module.h> |
ad62ca2b | 30 | #include <linux/dmi.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/arch_hooks.h> | |
38 | #include <asm/hpet.h> | |
306e440d | 39 | #include <asm/i8253.h> |
3e4ff115 | 40 | #include <asm/nmi.h> |
1da177e4 LT |
41 | |
42 | #include <mach_apic.h> | |
382dbd07 | 43 | #include <mach_apicdef.h> |
6eb0a0fd | 44 | #include <mach_ipi.h> |
1da177e4 | 45 | |
e05d723f TG |
46 | /* |
47 | * Sanity check | |
48 | */ | |
ff8a03a6 | 49 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) |
e05d723f TG |
50 | # error SPURIOUS_APIC_VECTOR definition error |
51 | #endif | |
52 | ||
8f6e2ca9 AS |
53 | unsigned long mp_lapic_addr; |
54 | ||
9635b47d EB |
55 | /* |
56 | * Knob to control our willingness to enable the local APIC. | |
e05d723f | 57 | * |
914bebfa | 58 | * +1=force-enable |
9635b47d | 59 | */ |
914bebfa YL |
60 | static int force_enable_local_apic; |
61 | int disable_apic; | |
9635b47d | 62 | |
d36b49b9 TG |
63 | /* Local APIC timer verification ok */ |
64 | static int local_apic_timer_verify_ok; | |
aa276e1c TG |
65 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
66 | static int local_apic_timer_disabled; | |
e585bef8 TG |
67 | /* Local APIC timer works in C2 */ |
68 | int local_apic_timer_c2_ok; | |
69 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
e9e2cdb4 | 70 | |
ce178331 AM |
71 | int first_system_vector = 0xfe; |
72 | ||
73 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
74 | ||
1da177e4 | 75 | /* |
e05d723f | 76 | * Debug level, exported for io_apic.c |
1da177e4 | 77 | */ |
baa13188 | 78 | unsigned int apic_verbosity; |
1da177e4 | 79 | |
f3918352 AS |
80 | int pic_mode; |
81 | ||
bab4b27c AS |
82 | /* Have we found an MP table */ |
83 | int smp_found_config; | |
84 | ||
746f2eb7 CG |
85 | static struct resource lapic_resource = { |
86 | .name = "Local APIC", | |
87 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
88 | }; | |
89 | ||
e9e2cdb4 | 90 | static unsigned int calibration_result; |
1da177e4 | 91 | |
e9e2cdb4 TG |
92 | static int lapic_next_event(unsigned long delta, |
93 | struct clock_event_device *evt); | |
94 | static void lapic_timer_setup(enum clock_event_mode mode, | |
95 | struct clock_event_device *evt); | |
96 | static void lapic_timer_broadcast(cpumask_t mask); | |
97 | static void apic_pm_activate(void); | |
e05d723f | 98 | |
e9e2cdb4 TG |
99 | /* |
100 | * The local apic timer can be used for any function which is CPU local. | |
101 | */ | |
102 | static struct clock_event_device lapic_clockevent = { | |
103 | .name = "lapic", | |
104 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
d36b49b9 | 105 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
e9e2cdb4 TG |
106 | .shift = 32, |
107 | .set_mode = lapic_timer_setup, | |
108 | .set_next_event = lapic_next_event, | |
109 | .broadcast = lapic_timer_broadcast, | |
110 | .rating = 100, | |
111 | .irq = -1, | |
112 | }; | |
113 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
e05d723f TG |
114 | |
115 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ | |
116 | static int enabled_via_apicbase; | |
117 | ||
d3432896 AK |
118 | static unsigned long apic_phys; |
119 | ||
e05d723f TG |
120 | /* |
121 | * Get the LAPIC version | |
122 | */ | |
123 | static inline int lapic_get_version(void) | |
95d769aa | 124 | { |
e05d723f | 125 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
95d769aa AK |
126 | } |
127 | ||
1da177e4 | 128 | /* |
ab4a574e | 129 | * Check, if the APIC is integrated or a separate chip |
1da177e4 | 130 | */ |
e05d723f | 131 | static inline int lapic_is_integrated(void) |
1da177e4 | 132 | { |
e05d723f | 133 | return APIC_INTEGRATED(lapic_get_version()); |
1da177e4 LT |
134 | } |
135 | ||
e05d723f TG |
136 | /* |
137 | * Check, whether this is a modern or a first generation APIC | |
138 | */ | |
139 | static int modern_apic(void) | |
1da177e4 | 140 | { |
e05d723f TG |
141 | /* AMD systems use old APIC versions, so check the CPU */ |
142 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
143 | boot_cpu_data.x86 >= 0xf) | |
144 | return 1; | |
145 | return lapic_get_version() >= 0x14; | |
1da177e4 LT |
146 | } |
147 | ||
f2b218dd FLV |
148 | void apic_wait_icr_idle(void) |
149 | { | |
150 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
151 | cpu_relax(); | |
152 | } | |
153 | ||
42e0a9aa | 154 | u32 safe_apic_wait_icr_idle(void) |
f2b218dd | 155 | { |
42e0a9aa | 156 | u32 send_status; |
f2b218dd FLV |
157 | int timeout; |
158 | ||
159 | timeout = 0; | |
160 | do { | |
161 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
162 | if (!send_status) | |
163 | break; | |
164 | udelay(100); | |
165 | } while (timeout++ < 1000); | |
166 | ||
167 | return send_status; | |
168 | } | |
169 | ||
e05d723f TG |
170 | /** |
171 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
172 | */ | |
e9427101 | 173 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 174 | { |
e05d723f | 175 | unsigned int v = APIC_DM_NMI; |
1da177e4 | 176 | |
e05d723f TG |
177 | /* Level triggered for 82489DX */ |
178 | if (!lapic_is_integrated()) | |
1da177e4 | 179 | v |= APIC_LVT_LEVEL_TRIGGER; |
593f4a78 | 180 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
181 | } |
182 | ||
e05d723f TG |
183 | /** |
184 | * get_physical_broadcast - Get number of physical broadcast IDs | |
185 | */ | |
1da177e4 LT |
186 | int get_physical_broadcast(void) |
187 | { | |
e05d723f | 188 | return modern_apic() ? 0xff : 0xf; |
1da177e4 LT |
189 | } |
190 | ||
e05d723f TG |
191 | /** |
192 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
193 | */ | |
194 | int lapic_get_maxlvt(void) | |
1da177e4 | 195 | { |
e05d723f | 196 | unsigned int v = apic_read(APIC_LVR); |
1da177e4 | 197 | |
1da177e4 | 198 | /* 82489DXs do not report # of LVT entries. */ |
e05d723f | 199 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
1da177e4 LT |
200 | } |
201 | ||
e05d723f TG |
202 | /* |
203 | * Local APIC timer | |
204 | */ | |
205 | ||
d36b49b9 TG |
206 | /* Clock divisor is set to 16 */ |
207 | #define APIC_DIVISOR 16 | |
e05d723f TG |
208 | |
209 | /* | |
210 | * This function sets up the local APIC timer, with a timeout of | |
211 | * 'clocks' APIC bus clock. During calibration we actually call | |
212 | * this function twice on the boot CPU, once with a bogus timeout | |
213 | * value, second time for real. The other (noncalibrating) CPUs | |
214 | * call this function only once, with the real, calibrated value. | |
e05d723f | 215 | */ |
e9e2cdb4 | 216 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 217 | { |
e05d723f | 218 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 219 | |
e9e2cdb4 TG |
220 | lvtt_value = LOCAL_TIMER_VECTOR; |
221 | if (!oneshot) | |
222 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
e05d723f TG |
223 | if (!lapic_is_integrated()) |
224 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
225 | ||
e9e2cdb4 | 226 | if (!irqen) |
e05d723f TG |
227 | lvtt_value |= APIC_LVT_MASKED; |
228 | ||
593f4a78 | 229 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
230 | |
231 | /* | |
e05d723f | 232 | * Divide PICLK by 16 |
1da177e4 | 233 | */ |
e05d723f | 234 | tmp_value = apic_read(APIC_TDCR); |
593f4a78 MR |
235 | apic_write(APIC_TDCR, |
236 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
237 | APIC_TDR_DIV_16); | |
1da177e4 | 238 | |
e9e2cdb4 | 239 | if (!oneshot) |
593f4a78 | 240 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
e9e2cdb4 TG |
241 | } |
242 | ||
243 | /* | |
244 | * Program the next event, relative to now | |
245 | */ | |
246 | static int lapic_next_event(unsigned long delta, | |
247 | struct clock_event_device *evt) | |
248 | { | |
593f4a78 | 249 | apic_write(APIC_TMICT, delta); |
e9e2cdb4 | 250 | return 0; |
1da177e4 LT |
251 | } |
252 | ||
e9e2cdb4 TG |
253 | /* |
254 | * Setup the lapic timer in periodic or oneshot mode | |
255 | */ | |
256 | static void lapic_timer_setup(enum clock_event_mode mode, | |
257 | struct clock_event_device *evt) | |
1da177e4 | 258 | { |
e05d723f | 259 | unsigned long flags; |
e9e2cdb4 | 260 | unsigned int v; |
e05d723f | 261 | |
d36b49b9 TG |
262 | /* Lapic used for broadcast ? */ |
263 | if (!local_apic_timer_verify_ok) | |
264 | return; | |
265 | ||
e05d723f | 266 | local_irq_save(flags); |
1da177e4 | 267 | |
e9e2cdb4 TG |
268 | switch (mode) { |
269 | case CLOCK_EVT_MODE_PERIODIC: | |
270 | case CLOCK_EVT_MODE_ONESHOT: | |
271 | __setup_APIC_LVTT(calibration_result, | |
272 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
273 | break; | |
274 | case CLOCK_EVT_MODE_UNUSED: | |
275 | case CLOCK_EVT_MODE_SHUTDOWN: | |
276 | v = apic_read(APIC_LVTT); | |
277 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
593f4a78 | 278 | apic_write(APIC_LVTT, v); |
e9e2cdb4 | 279 | break; |
18de5bc4 TG |
280 | case CLOCK_EVT_MODE_RESUME: |
281 | /* Nothing to do here */ | |
282 | break; | |
e9e2cdb4 | 283 | } |
e05d723f TG |
284 | |
285 | local_irq_restore(flags); | |
286 | } | |
287 | ||
e9e2cdb4 TG |
288 | /* |
289 | * Local APIC timer broadcast function | |
290 | */ | |
291 | static void lapic_timer_broadcast(cpumask_t mask) | |
292 | { | |
293 | #ifdef CONFIG_SMP | |
294 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
295 | #endif | |
296 | } | |
297 | ||
298 | /* | |
299 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
300 | * of the boot CPU and register the clock event in the framework. | |
301 | */ | |
302 | static void __devinit setup_APIC_timer(void) | |
303 | { | |
304 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
305 | ||
306 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); | |
307 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
308 | ||
309 | clockevents_register_device(levt); | |
310 | } | |
311 | ||
e05d723f | 312 | /* |
d36b49b9 TG |
313 | * In this functions we calibrate APIC bus clocks to the external timer. |
314 | * | |
315 | * We want to do the calibration only once since we want to have local timer | |
316 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
317 | * frequency. | |
318 | * | |
319 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
320 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
321 | * readout is broken, so it never gets out of the wait loop again. This was | |
322 | * also reported by others. | |
e05d723f | 323 | * |
d36b49b9 TG |
324 | * Monitoring the jiffies value is inaccurate and the clockevents |
325 | * infrastructure allows us to do a simple substitution of the interrupt | |
326 | * handler. | |
e9e2cdb4 | 327 | * |
d36b49b9 TG |
328 | * The calibration routine also uses the pm_timer when possible, as the PIT |
329 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
330 | * back to normal later in the boot process). | |
e05d723f TG |
331 | */ |
332 | ||
d36b49b9 | 333 | #define LAPIC_CAL_LOOPS (HZ/10) |
e05d723f | 334 | |
f5352fd0 | 335 | static __initdata int lapic_cal_loops = -1; |
d36b49b9 TG |
336 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
337 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
338 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
339 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
1da177e4 | 340 | |
d36b49b9 TG |
341 | /* |
342 | * Temporary interrupt handler. | |
343 | */ | |
344 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
345 | { | |
346 | unsigned long long tsc = 0; | |
347 | long tapic = apic_read(APIC_TMCCT); | |
348 | unsigned long pm = acpi_pm_read_early(); | |
1da177e4 | 349 | |
d36b49b9 TG |
350 | if (cpu_has_tsc) |
351 | rdtscll(tsc); | |
352 | ||
353 | switch (lapic_cal_loops++) { | |
354 | case 0: | |
355 | lapic_cal_t1 = tapic; | |
356 | lapic_cal_tsc1 = tsc; | |
357 | lapic_cal_pm1 = pm; | |
358 | lapic_cal_j1 = jiffies; | |
359 | break; | |
e05d723f | 360 | |
d36b49b9 TG |
361 | case LAPIC_CAL_LOOPS: |
362 | lapic_cal_t2 = tapic; | |
363 | lapic_cal_tsc2 = tsc; | |
364 | if (pm < lapic_cal_pm1) | |
365 | pm += ACPI_PM_OVRRUN; | |
366 | lapic_cal_pm2 = pm; | |
367 | lapic_cal_j2 = jiffies; | |
368 | break; | |
369 | } | |
370 | } | |
1da177e4 | 371 | |
836c129d | 372 | static int __init calibrate_APIC_clock(void) |
d36b49b9 TG |
373 | { |
374 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
375 | const long pm_100ms = PMTMR_TICKS_PER_SEC/10; | |
376 | const long pm_thresh = pm_100ms/100; | |
377 | void (*real_handler)(struct clock_event_device *dev); | |
378 | unsigned long deltaj; | |
379 | long delta, deltapm; | |
ca1b940c | 380 | int pm_referenced = 0; |
1da177e4 | 381 | |
d36b49b9 TG |
382 | local_irq_disable(); |
383 | ||
384 | /* Replace the global interrupt handler */ | |
385 | real_handler = global_clock_event->event_handler; | |
386 | global_clock_event->event_handler = lapic_cal_handler; | |
1da177e4 | 387 | |
1da177e4 | 388 | /* |
d36b49b9 TG |
389 | * Setup the APIC counter to 1e9. There is no way the lapic |
390 | * can underflow in the 100ms detection time frame | |
1da177e4 | 391 | */ |
d36b49b9 | 392 | __setup_APIC_LVTT(1000000000, 0, 0); |
1da177e4 | 393 | |
d36b49b9 TG |
394 | /* Let the interrupts run */ |
395 | local_irq_enable(); | |
396 | ||
ca1b940c TG |
397 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
398 | cpu_relax(); | |
d36b49b9 TG |
399 | |
400 | local_irq_disable(); | |
401 | ||
402 | /* Restore the real event handler */ | |
403 | global_clock_event->event_handler = real_handler; | |
404 | ||
405 | /* Build delta t1-t2 as apic timer counts down */ | |
406 | delta = lapic_cal_t1 - lapic_cal_t2; | |
407 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
408 | ||
409 | /* Check, if the PM timer is available */ | |
410 | deltapm = lapic_cal_pm2 - lapic_cal_pm1; | |
411 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
412 | ||
413 | if (deltapm) { | |
414 | unsigned long mult; | |
415 | u64 res; | |
416 | ||
417 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
418 | ||
419 | if (deltapm > (pm_100ms - pm_thresh) && | |
420 | deltapm < (pm_100ms + pm_thresh)) { | |
421 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
422 | } else { | |
423 | res = (((u64) deltapm) * mult) >> 22; | |
424 | do_div(res, 1000000); | |
425 | printk(KERN_WARNING "APIC calibration not consistent " | |
426 | "with PM Timer: %ldms instead of 100ms\n", | |
427 | (long)res); | |
428 | /* Correct the lapic counter value */ | |
ff8a03a6 | 429 | res = (((u64) delta) * pm_100ms); |
d36b49b9 TG |
430 | do_div(res, deltapm); |
431 | printk(KERN_INFO "APIC delta adjusted to PM-Timer: " | |
432 | "%lu (%ld)\n", (unsigned long) res, delta); | |
433 | delta = (long) res; | |
434 | } | |
ca1b940c | 435 | pm_referenced = 1; |
d36b49b9 | 436 | } |
e05d723f | 437 | |
e9e2cdb4 | 438 | /* Calculate the scaled math multiplication factor */ |
877084fb AM |
439 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, |
440 | lapic_clockevent.shift); | |
e9e2cdb4 TG |
441 | lapic_clockevent.max_delta_ns = |
442 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
443 | lapic_clockevent.min_delta_ns = | |
444 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
445 | ||
d36b49b9 TG |
446 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
447 | ||
448 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
e9e2cdb4 | 449 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); |
d36b49b9 TG |
450 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
451 | calibration_result); | |
e9e2cdb4 | 452 | |
d36b49b9 TG |
453 | if (cpu_has_tsc) { |
454 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
e05d723f | 455 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
d36b49b9 TG |
456 | "%ld.%04ld MHz.\n", |
457 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
458 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
459 | } | |
e05d723f TG |
460 | |
461 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
d36b49b9 TG |
462 | "%u.%04u MHz.\n", |
463 | calibration_result / (1000000 / HZ), | |
464 | calibration_result % (1000000 / HZ)); | |
e05d723f | 465 | |
c2b84b30 TG |
466 | /* |
467 | * Do a sanity check on the APIC calibration result | |
468 | */ | |
469 | if (calibration_result < (1000000 / HZ)) { | |
470 | local_irq_enable(); | |
471 | printk(KERN_WARNING | |
472 | "APIC frequency too slow, disabling apic timer\n"); | |
836c129d | 473 | return -1; |
c2b84b30 TG |
474 | } |
475 | ||
836c129d CG |
476 | local_apic_timer_verify_ok = 1; |
477 | ||
ca1b940c TG |
478 | /* We trust the pm timer based calibration */ |
479 | if (!pm_referenced) { | |
480 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
d36b49b9 | 481 | |
ca1b940c TG |
482 | /* |
483 | * Setup the apic timer manually | |
484 | */ | |
485 | levt->event_handler = lapic_cal_handler; | |
486 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
487 | lapic_cal_loops = -1; | |
d36b49b9 | 488 | |
ca1b940c TG |
489 | /* Let the interrupts run */ |
490 | local_irq_enable(); | |
d36b49b9 | 491 | |
f5352fd0 | 492 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
ca1b940c | 493 | cpu_relax(); |
d36b49b9 | 494 | |
ca1b940c | 495 | local_irq_disable(); |
d36b49b9 | 496 | |
ca1b940c TG |
497 | /* Stop the lapic timer */ |
498 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
d36b49b9 | 499 | |
ca1b940c | 500 | local_irq_enable(); |
d36b49b9 | 501 | |
ca1b940c TG |
502 | /* Jiffies delta */ |
503 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
504 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
d36b49b9 | 505 | |
d36b49b9 | 506 | /* Check, if the jiffies result is consistent */ |
ca1b940c | 507 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
d36b49b9 | 508 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
ca1b940c TG |
509 | else |
510 | local_apic_timer_verify_ok = 0; | |
4edc5db8 IM |
511 | } else |
512 | local_irq_enable(); | |
e05d723f | 513 | |
d36b49b9 TG |
514 | if (!local_apic_timer_verify_ok) { |
515 | printk(KERN_WARNING | |
516 | "APIC timer disabled due to verification failure.\n"); | |
836c129d CG |
517 | return -1; |
518 | } | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
523 | /* | |
524 | * Setup the boot APIC | |
525 | * | |
526 | * Calibrate and verify the result. | |
527 | */ | |
528 | void __init setup_boot_APIC_clock(void) | |
529 | { | |
530 | /* | |
531 | * The local apic timer can be disabled via the kernel | |
532 | * commandline or from the CPU detection code. Register the lapic | |
533 | * timer as a dummy clock event source on SMP systems, so the | |
534 | * broadcast mechanism is used. On UP systems simply ignore it. | |
535 | */ | |
536 | if (local_apic_timer_disabled) { | |
d36b49b9 | 537 | /* No broadcast on UP ! */ |
836c129d CG |
538 | if (num_possible_cpus() > 1) { |
539 | lapic_clockevent.mult = 1; | |
540 | setup_APIC_timer(); | |
541 | } | |
542 | return; | |
a5f5e43e | 543 | } |
d36b49b9 | 544 | |
836c129d CG |
545 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
546 | "calibrating APIC timer ...\n"); | |
547 | ||
548 | if (calibrate_APIC_clock()) { | |
549 | /* No broadcast on UP ! */ | |
550 | if (num_possible_cpus() > 1) | |
551 | setup_APIC_timer(); | |
552 | return; | |
553 | } | |
554 | ||
555 | /* | |
556 | * If nmi_watchdog is set to IO_APIC, we need the | |
557 | * PIT/HPET going. Otherwise register lapic as a dummy | |
558 | * device. | |
559 | */ | |
560 | if (nmi_watchdog != NMI_IO_APIC) | |
561 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
562 | else | |
563 | printk(KERN_WARNING "APIC timer registered as dummy," | |
564 | " due to nmi_watchdog=%d!\n", nmi_watchdog); | |
565 | ||
d36b49b9 TG |
566 | /* Setup the lapic or request the broadcast */ |
567 | setup_APIC_timer(); | |
e05d723f | 568 | } |
1da177e4 | 569 | |
e05d723f TG |
570 | void __devinit setup_secondary_APIC_clock(void) |
571 | { | |
e9e2cdb4 | 572 | setup_APIC_timer(); |
e05d723f | 573 | } |
1da177e4 | 574 | |
e05d723f | 575 | /* |
e9e2cdb4 | 576 | * The guts of the apic timer interrupt |
e05d723f | 577 | */ |
e9e2cdb4 | 578 | static void local_apic_timer_interrupt(void) |
e05d723f | 579 | { |
e9e2cdb4 TG |
580 | int cpu = smp_processor_id(); |
581 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
1da177e4 LT |
582 | |
583 | /* | |
d36b49b9 TG |
584 | * Normally we should not be here till LAPIC has been initialized but |
585 | * in some cases like kdump, its possible that there is a pending LAPIC | |
586 | * timer interrupt from previous kernel's context and is delivered in | |
587 | * new kernel the moment interrupts are enabled. | |
e05d723f | 588 | * |
d36b49b9 TG |
589 | * Interrupts are enabled early and LAPIC is setup much later, hence |
590 | * its possible that when we get here evt->event_handler is NULL. | |
591 | * Check for event_handler being NULL and discard the interrupt as | |
592 | * spurious. | |
1da177e4 | 593 | */ |
e9e2cdb4 TG |
594 | if (!evt->event_handler) { |
595 | printk(KERN_WARNING | |
596 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
597 | /* Switch it off */ | |
598 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
599 | return; | |
600 | } | |
601 | ||
0e078e2f TG |
602 | /* |
603 | * the NMI deadlock-detector uses this. | |
604 | */ | |
e9e2cdb4 TG |
605 | per_cpu(irq_stat, cpu).apic_timer_irqs++; |
606 | ||
607 | evt->event_handler(evt); | |
e05d723f TG |
608 | } |
609 | ||
610 | /* | |
611 | * Local APIC timer interrupt. This is the most natural way for doing | |
612 | * local interrupts, but local timer interrupts can be emulated by | |
613 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
614 | * | |
615 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
616 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
617 | */ | |
75604d7f | 618 | void smp_apic_timer_interrupt(struct pt_regs *regs) |
e05d723f TG |
619 | { |
620 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1da177e4 LT |
621 | |
622 | /* | |
e05d723f TG |
623 | * NOTE! We'd better ACK the irq immediately, |
624 | * because timer handling can be slow. | |
1da177e4 | 625 | */ |
e05d723f | 626 | ack_APIC_irq(); |
1a75a3f0 | 627 | /* |
e05d723f TG |
628 | * update_process_times() expects us to have done irq_enter(). |
629 | * Besides, if we don't timer interrupts ignore the global | |
630 | * interrupt lock, which is the WrongThing (tm) to do. | |
1a75a3f0 | 631 | */ |
e05d723f | 632 | irq_enter(); |
e9e2cdb4 | 633 | local_apic_timer_interrupt(); |
e05d723f | 634 | irq_exit(); |
1a75a3f0 | 635 | |
e9e2cdb4 | 636 | set_irq_regs(old_regs); |
e05d723f TG |
637 | } |
638 | ||
639 | int setup_profiling_timer(unsigned int multiplier) | |
640 | { | |
641 | return -EINVAL; | |
642 | } | |
643 | ||
e319e765 RR |
644 | /* |
645 | * Setup extended LVT, AMD specific (K8, family 10h) | |
646 | * | |
647 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
648 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
649 | */ | |
650 | ||
651 | #define APIC_EILVT_LVTOFF_MCE 0 | |
652 | #define APIC_EILVT_LVTOFF_IBS 1 | |
653 | ||
654 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
655 | { | |
656 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; | |
657 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; | |
658 | apic_write(reg, v); | |
659 | } | |
660 | ||
661 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) | |
662 | { | |
663 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
664 | return APIC_EILVT_LVTOFF_MCE; | |
665 | } | |
666 | ||
667 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
668 | { | |
669 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
670 | return APIC_EILVT_LVTOFF_IBS; | |
671 | } | |
672 | ||
e05d723f TG |
673 | /* |
674 | * Local APIC start and shutdown | |
675 | */ | |
676 | ||
677 | /** | |
678 | * clear_local_APIC - shutdown the local APIC | |
679 | * | |
680 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
681 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
682 | * leftovers during boot. | |
683 | */ | |
684 | void clear_local_APIC(void) | |
685 | { | |
d3432896 | 686 | int maxlvt; |
0e078e2f | 687 | u32 v; |
1da177e4 | 688 | |
d3432896 AK |
689 | /* APIC hasn't been mapped yet */ |
690 | if (!apic_phys) | |
691 | return; | |
692 | ||
693 | maxlvt = lapic_get_maxlvt(); | |
1da177e4 | 694 | /* |
e05d723f TG |
695 | * Masking an LVT entry can trigger a local APIC error |
696 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1da177e4 | 697 | */ |
e05d723f TG |
698 | if (maxlvt >= 3) { |
699 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
593f4a78 | 700 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
e05d723f | 701 | } |
1da177e4 | 702 | /* |
e05d723f TG |
703 | * Careful: we have to set masks only first to deassert |
704 | * any level-triggered sources. | |
1da177e4 | 705 | */ |
e05d723f | 706 | v = apic_read(APIC_LVTT); |
593f4a78 | 707 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
e05d723f | 708 | v = apic_read(APIC_LVT0); |
593f4a78 | 709 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
e05d723f | 710 | v = apic_read(APIC_LVT1); |
593f4a78 | 711 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
e05d723f TG |
712 | if (maxlvt >= 4) { |
713 | v = apic_read(APIC_LVTPC); | |
593f4a78 | 714 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
1da177e4 | 715 | } |
1da177e4 | 716 | |
e05d723f TG |
717 | /* lets not touch this if we didn't frob it */ |
718 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
719 | if (maxlvt >= 5) { | |
720 | v = apic_read(APIC_LVTTHMR); | |
593f4a78 | 721 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); |
e05d723f TG |
722 | } |
723 | #endif | |
1da177e4 | 724 | /* |
e05d723f | 725 | * Clean APIC state for other OSs: |
1da177e4 | 726 | */ |
593f4a78 MR |
727 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
728 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
729 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
e05d723f | 730 | if (maxlvt >= 3) |
593f4a78 | 731 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
e05d723f | 732 | if (maxlvt >= 4) |
593f4a78 | 733 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
1da177e4 | 734 | |
e05d723f TG |
735 | #ifdef CONFIG_X86_MCE_P4THERMAL |
736 | if (maxlvt >= 5) | |
593f4a78 | 737 | apic_write(APIC_LVTTHMR, APIC_LVT_MASKED); |
e05d723f TG |
738 | #endif |
739 | /* Integrated APIC (!82489DX) ? */ | |
740 | if (lapic_is_integrated()) { | |
1da177e4 | 741 | if (maxlvt > 3) |
e05d723f | 742 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
1da177e4 | 743 | apic_write(APIC_ESR, 0); |
e05d723f | 744 | apic_read(APIC_ESR); |
1da177e4 | 745 | } |
e05d723f | 746 | } |
1da177e4 | 747 | |
e05d723f TG |
748 | /** |
749 | * disable_local_APIC - clear and disable the local APIC | |
750 | */ | |
751 | void disable_local_APIC(void) | |
752 | { | |
753 | unsigned long value; | |
754 | ||
755 | clear_local_APIC(); | |
756 | ||
757 | /* | |
758 | * Disable APIC (implies clearing of registers | |
759 | * for 82489DX!). | |
760 | */ | |
761 | value = apic_read(APIC_SPIV); | |
762 | value &= ~APIC_SPIV_APIC_ENABLED; | |
593f4a78 | 763 | apic_write(APIC_SPIV, value); |
e05d723f TG |
764 | |
765 | /* | |
766 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
767 | * restore the disabled state. | |
768 | */ | |
769 | if (enabled_via_apicbase) { | |
770 | unsigned int l, h; | |
771 | ||
772 | rdmsr(MSR_IA32_APICBASE, l, h); | |
773 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
774 | wrmsr(MSR_IA32_APICBASE, l, h); | |
775 | } | |
1da177e4 LT |
776 | } |
777 | ||
778 | /* | |
e05d723f TG |
779 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
780 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
781 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
77f72b19 | 782 | * for the case where Linux didn't enable the LAPIC. |
1da177e4 LT |
783 | */ |
784 | void lapic_shutdown(void) | |
785 | { | |
67963132 MS |
786 | unsigned long flags; |
787 | ||
77f72b19 | 788 | if (!cpu_has_apic) |
1da177e4 LT |
789 | return; |
790 | ||
67963132 | 791 | local_irq_save(flags); |
77f72b19 ZM |
792 | clear_local_APIC(); |
793 | ||
794 | if (enabled_via_apicbase) | |
795 | disable_local_APIC(); | |
796 | ||
67963132 | 797 | local_irq_restore(flags); |
1da177e4 LT |
798 | } |
799 | ||
e05d723f TG |
800 | /* |
801 | * This is to verify that we're looking at a real local APIC. | |
802 | * Check these against your board if the CPUs aren't getting | |
803 | * started for no apparent reason. | |
804 | */ | |
805 | int __init verify_local_APIC(void) | |
1da177e4 | 806 | { |
e05d723f | 807 | unsigned int reg0, reg1; |
1da177e4 | 808 | |
e05d723f TG |
809 | /* |
810 | * The version register is read-only in a real APIC. | |
811 | */ | |
812 | reg0 = apic_read(APIC_LVR); | |
813 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
814 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
815 | reg1 = apic_read(APIC_LVR); | |
816 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
817 | ||
818 | /* | |
819 | * The two version reads above should print the same | |
820 | * numbers. If the second one is different, then we | |
821 | * poke at a non-APIC. | |
822 | */ | |
823 | if (reg1 != reg0) | |
1da177e4 LT |
824 | return 0; |
825 | ||
e05d723f TG |
826 | /* |
827 | * Check if the version looks reasonably. | |
828 | */ | |
829 | reg1 = GET_APIC_VERSION(reg0); | |
830 | if (reg1 == 0x00 || reg1 == 0xff) | |
831 | return 0; | |
832 | reg1 = lapic_get_maxlvt(); | |
833 | if (reg1 < 0x02 || reg1 == 0xff) | |
834 | return 0; | |
f990fff4 | 835 | |
e05d723f TG |
836 | /* |
837 | * The ID register is read/write in a real APIC. | |
838 | */ | |
839 | reg0 = apic_read(APIC_ID); | |
840 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
841 | ||
842 | /* | |
843 | * The next two are just to see if we have sane values. | |
844 | * They're only really relevant if we're in Virtual Wire | |
845 | * compatibility mode, but most boxes are anymore. | |
846 | */ | |
847 | reg0 = apic_read(APIC_LVT0); | |
848 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
849 | reg1 = apic_read(APIC_LVT1); | |
850 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
851 | ||
852 | return 1; | |
1da177e4 LT |
853 | } |
854 | ||
e05d723f TG |
855 | /** |
856 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
857 | */ | |
858 | void __init sync_Arb_IDs(void) | |
1da177e4 | 859 | { |
e05d723f TG |
860 | /* |
861 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
862 | * needed on AMD. | |
863 | */ | |
f44d9efd | 864 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
e05d723f TG |
865 | return; |
866 | /* | |
867 | * Wait for idle. | |
868 | */ | |
869 | apic_wait_icr_idle(); | |
1da177e4 | 870 | |
e05d723f | 871 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
593f4a78 MR |
872 | apic_write(APIC_ICR, |
873 | APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
e05d723f | 874 | } |
1da177e4 | 875 | |
e05d723f TG |
876 | /* |
877 | * An initial setup of the virtual wire mode. | |
878 | */ | |
879 | void __init init_bsp_APIC(void) | |
880 | { | |
881 | unsigned long value; | |
f990fff4 | 882 | |
e05d723f TG |
883 | /* |
884 | * Don't do the setup now if we have a SMP BIOS as the | |
885 | * through-I/O-APIC virtual wire mode might be active. | |
886 | */ | |
887 | if (smp_found_config || !cpu_has_apic) | |
888 | return; | |
1da177e4 LT |
889 | |
890 | /* | |
e05d723f | 891 | * Do not trust the local APIC being empty at bootup. |
1da177e4 | 892 | */ |
e05d723f | 893 | clear_local_APIC(); |
1da177e4 | 894 | |
e05d723f TG |
895 | /* |
896 | * Enable APIC. | |
897 | */ | |
898 | value = apic_read(APIC_SPIV); | |
899 | value &= ~APIC_VECTOR_MASK; | |
900 | value |= APIC_SPIV_APIC_ENABLED; | |
901 | ||
902 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
903 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
904 | (boot_cpu_data.x86 == 15)) | |
905 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
906 | else | |
907 | value |= APIC_SPIV_FOCUS_DISABLED; | |
908 | value |= SPURIOUS_APIC_VECTOR; | |
593f4a78 | 909 | apic_write(APIC_SPIV, value); |
e05d723f TG |
910 | |
911 | /* | |
912 | * Set up the virtual wire mode. | |
913 | */ | |
593f4a78 | 914 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
e05d723f TG |
915 | value = APIC_DM_NMI; |
916 | if (!lapic_is_integrated()) /* 82489DX */ | |
917 | value |= APIC_LVT_LEVEL_TRIGGER; | |
593f4a78 | 918 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
919 | } |
920 | ||
a4928cff | 921 | static void __cpuinit lapic_setup_esr(void) |
df7939ae GOC |
922 | { |
923 | unsigned long oldvalue, value, maxlvt; | |
924 | if (lapic_is_integrated() && !esr_disable) { | |
925 | /* !82489DX */ | |
926 | maxlvt = lapic_get_maxlvt(); | |
927 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
928 | apic_write(APIC_ESR, 0); | |
929 | oldvalue = apic_read(APIC_ESR); | |
930 | ||
931 | /* enables sending errors */ | |
932 | value = ERROR_APIC_VECTOR; | |
593f4a78 | 933 | apic_write(APIC_LVTERR, value); |
df7939ae GOC |
934 | /* |
935 | * spec says clear errors after enabling vector. | |
936 | */ | |
937 | if (maxlvt > 3) | |
938 | apic_write(APIC_ESR, 0); | |
939 | value = apic_read(APIC_ESR); | |
940 | if (value != oldvalue) | |
941 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
942 | "vector: 0x%08lx after: 0x%08lx\n", | |
943 | oldvalue, value); | |
944 | } else { | |
945 | if (esr_disable) | |
946 | /* | |
947 | * Something untraceable is creating bad interrupts on | |
948 | * secondary quads ... for the moment, just leave the | |
949 | * ESR disabled - we can't do anything useful with the | |
950 | * errors anyway - mbligh | |
951 | */ | |
952 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
953 | else | |
954 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
955 | } | |
956 | } | |
957 | ||
958 | ||
e05d723f TG |
959 | /** |
960 | * setup_local_APIC - setup the local APIC | |
1da177e4 | 961 | */ |
d5337983 | 962 | void __cpuinit setup_local_APIC(void) |
e05d723f | 963 | { |
df7939ae | 964 | unsigned long value, integrated; |
e05d723f | 965 | int i, j; |
1da177e4 | 966 | |
e05d723f TG |
967 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
968 | if (esr_disable) { | |
969 | apic_write(APIC_ESR, 0); | |
970 | apic_write(APIC_ESR, 0); | |
971 | apic_write(APIC_ESR, 0); | |
972 | apic_write(APIC_ESR, 0); | |
973 | } | |
1da177e4 | 974 | |
e05d723f | 975 | integrated = lapic_is_integrated(); |
1da177e4 | 976 | |
e05d723f TG |
977 | /* |
978 | * Double-check whether this APIC is really registered. | |
979 | */ | |
980 | if (!apic_id_registered()) | |
22d5c67c | 981 | WARN_ON_ONCE(1); |
1da177e4 | 982 | |
e05d723f TG |
983 | /* |
984 | * Intel recommends to set DFR, LDR and TPR before enabling | |
985 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
986 | * document number 292116). So here it goes... | |
987 | */ | |
988 | init_apic_ldr(); | |
1da177e4 | 989 | |
e05d723f TG |
990 | /* |
991 | * Set Task Priority to 'accept all'. We never change this | |
992 | * later on. | |
993 | */ | |
994 | value = apic_read(APIC_TASKPRI); | |
995 | value &= ~APIC_TPRI_MASK; | |
593f4a78 | 996 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 997 | |
e05d723f TG |
998 | /* |
999 | * After a crash, we no longer service the interrupts and a pending | |
1000 | * interrupt from previous kernel might still have ISR bit set. | |
1001 | * | |
1002 | * Most probably by now CPU has serviced that pending interrupt and | |
1003 | * it might not have done the ack_APIC_irq() because it thought, | |
1004 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1005 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1006 | * the interrupt. Hence a vector might get locked. It was noticed | |
1007 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1008 | */ | |
1009 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1010 | value = apic_read(APIC_ISR + i*0x10); | |
1011 | for (j = 31; j >= 0; j--) { | |
1012 | if (value & (1<<j)) | |
1013 | ack_APIC_irq(); | |
1014 | } | |
1015 | } | |
1da177e4 | 1016 | |
e05d723f TG |
1017 | /* |
1018 | * Now that we are all set up, enable the APIC | |
1019 | */ | |
1020 | value = apic_read(APIC_SPIV); | |
1021 | value &= ~APIC_VECTOR_MASK; | |
1022 | /* | |
1023 | * Enable APIC | |
1024 | */ | |
1025 | value |= APIC_SPIV_APIC_ENABLED; | |
1da177e4 | 1026 | |
e05d723f TG |
1027 | /* |
1028 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1029 | * certain networking cards. If high frequency interrupts are | |
1030 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1031 | * entry is masked/unmasked at a high rate as well then sooner or | |
1032 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1033 | * from the device. If focus CPU is disabled then the hang goes | |
1034 | * away, oh well :-( | |
1035 | * | |
1036 | * [ This bug can be reproduced easily with a level-triggered | |
1037 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1038 | * BX chipset. ] | |
1039 | */ | |
1040 | /* | |
1041 | * Actually disabling the focus CPU check just makes the hang less | |
1042 | * frequent as it makes the interrupt distributon model be more | |
1043 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1044 | * See also the comment in end_level_ioapic_irq(). --macro | |
1045 | */ | |
1da177e4 | 1046 | |
e05d723f TG |
1047 | /* Enable focus processor (bit==0) */ |
1048 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1049 | |
e05d723f TG |
1050 | /* |
1051 | * Set spurious IRQ vector | |
1052 | */ | |
1053 | value |= SPURIOUS_APIC_VECTOR; | |
593f4a78 | 1054 | apic_write(APIC_SPIV, value); |
e05d723f TG |
1055 | |
1056 | /* | |
1057 | * Set up LVT0, LVT1: | |
1058 | * | |
1059 | * set up through-local-APIC on the BP's LINT0. This is not | |
27b46d76 | 1060 | * strictly necessary in pure symmetric-IO mode, but sometimes |
e05d723f TG |
1061 | * we delegate interrupts to the 8259A. |
1062 | */ | |
1063 | /* | |
1064 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1065 | */ | |
1066 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
1067 | if (!smp_processor_id() && (pic_mode || !value)) { | |
1068 | value = APIC_DM_EXTINT; | |
1069 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
1070 | smp_processor_id()); | |
1071 | } else { | |
1072 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
1073 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
1074 | smp_processor_id()); | |
1075 | } | |
593f4a78 | 1076 | apic_write(APIC_LVT0, value); |
e05d723f TG |
1077 | |
1078 | /* | |
1079 | * only the BP should see the LINT1 NMI signal, obviously. | |
1080 | */ | |
1081 | if (!smp_processor_id()) | |
1082 | value = APIC_DM_NMI; | |
1083 | else | |
1084 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
1085 | if (!integrated) /* 82489DX */ | |
1086 | value |= APIC_LVT_LEVEL_TRIGGER; | |
593f4a78 | 1087 | apic_write(APIC_LVT1, value); |
ac60aae5 | 1088 | } |
e05d723f | 1089 | |
ac60aae5 GOC |
1090 | void __cpuinit end_local_APIC_setup(void) |
1091 | { | |
1092 | unsigned long value; | |
1da177e4 | 1093 | |
ac60aae5 | 1094 | lapic_setup_esr(); |
e9e2cdb4 TG |
1095 | /* Disable the local apic timer */ |
1096 | value = apic_read(APIC_LVTT); | |
1097 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
593f4a78 | 1098 | apic_write(APIC_LVTT, value); |
e9e2cdb4 | 1099 | |
e05d723f TG |
1100 | setup_apic_nmi_watchdog(NULL); |
1101 | apic_pm_activate(); | |
1da177e4 LT |
1102 | } |
1103 | ||
e05d723f TG |
1104 | /* |
1105 | * Detect and initialize APIC | |
1106 | */ | |
e83a5fdc | 1107 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1108 | { |
1109 | u32 h, l, features; | |
1da177e4 LT |
1110 | |
1111 | /* Disabled by kernel option? */ | |
914bebfa | 1112 | if (disable_apic) |
1da177e4 LT |
1113 | return -1; |
1114 | ||
1da177e4 LT |
1115 | switch (boot_cpu_data.x86_vendor) { |
1116 | case X86_VENDOR_AMD: | |
1117 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
e05d723f | 1118 | (boot_cpu_data.x86 == 15)) |
1da177e4 LT |
1119 | break; |
1120 | goto no_apic; | |
1121 | case X86_VENDOR_INTEL: | |
1122 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1123 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1124 | break; | |
1125 | goto no_apic; | |
1126 | default: | |
1127 | goto no_apic; | |
1128 | } | |
1129 | ||
1130 | if (!cpu_has_apic) { | |
1131 | /* | |
e05d723f TG |
1132 | * Over-ride BIOS and try to enable the local APIC only if |
1133 | * "lapic" specified. | |
1da177e4 | 1134 | */ |
914bebfa | 1135 | if (!force_enable_local_apic) { |
e05d723f | 1136 | printk(KERN_INFO "Local APIC disabled by BIOS -- " |
1da177e4 LT |
1137 | "you can enable it with \"lapic\"\n"); |
1138 | return -1; | |
1139 | } | |
1140 | /* | |
e05d723f TG |
1141 | * Some BIOSes disable the local APIC in the APIC_BASE |
1142 | * MSR. This can only be done in software for Intel P6 or later | |
1143 | * and AMD K7 (Model > 1) or later. | |
1da177e4 LT |
1144 | */ |
1145 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1146 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
e05d723f TG |
1147 | printk(KERN_INFO |
1148 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1da177e4 LT |
1149 | l &= ~MSR_IA32_APICBASE_BASE; |
1150 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1151 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1152 | enabled_via_apicbase = 1; | |
1153 | } | |
1154 | } | |
1155 | /* | |
1156 | * The APIC feature bit should now be enabled | |
1157 | * in `cpuid' | |
1158 | */ | |
1159 | features = cpuid_edx(1); | |
1160 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
e05d723f | 1161 | printk(KERN_WARNING "Could not enable APIC!\n"); |
1da177e4 LT |
1162 | return -1; |
1163 | } | |
53756d37 | 1164 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1da177e4 LT |
1165 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
1166 | ||
1167 | /* The BIOS may have set up the APIC at some other address */ | |
1168 | rdmsr(MSR_IA32_APICBASE, l, h); | |
e05d723f TG |
1169 | if (l & MSR_IA32_APICBASE_ENABLE) |
1170 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1da177e4 | 1171 | |
e05d723f | 1172 | printk(KERN_INFO "Found and enabled local APIC!\n"); |
1da177e4 | 1173 | |
e05d723f | 1174 | apic_pm_activate(); |
1da177e4 | 1175 | |
e05d723f | 1176 | return 0; |
1da177e4 | 1177 | |
e05d723f TG |
1178 | no_apic: |
1179 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1180 | return -1; | |
1181 | } | |
1da177e4 | 1182 | |
e05d723f TG |
1183 | /** |
1184 | * init_apic_mappings - initialize APIC mappings | |
1185 | */ | |
1186 | void __init init_apic_mappings(void) | |
1da177e4 | 1187 | { |
1da177e4 | 1188 | /* |
e05d723f TG |
1189 | * If no local APIC can be found then set up a fake all |
1190 | * zeroes page to simulate the local APIC and another | |
1191 | * one for the IO-APIC. | |
1da177e4 | 1192 | */ |
e05d723f TG |
1193 | if (!smp_found_config && detect_init_APIC()) { |
1194 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1195 | apic_phys = __pa(apic_phys); | |
1196 | } else | |
1197 | apic_phys = mp_lapic_addr; | |
1da177e4 | 1198 | |
e05d723f TG |
1199 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
1200 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
1201 | apic_phys); | |
1da177e4 | 1202 | |
e05d723f TG |
1203 | /* |
1204 | * Fetch the APIC ID of the BSP in case we have a | |
1205 | * default configuration (or the MP table is broken). | |
1206 | */ | |
1207 | if (boot_cpu_physical_apicid == -1U) | |
05f2d12c | 1208 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
1da177e4 | 1209 | |
1da177e4 LT |
1210 | } |
1211 | ||
e05d723f TG |
1212 | /* |
1213 | * This initializes the IO-APIC and APIC hardware if this is | |
1214 | * a UP kernel. | |
1215 | */ | |
e81b2c62 AS |
1216 | |
1217 | int apic_version[MAX_APICS]; | |
1218 | ||
e83a5fdc | 1219 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1220 | { |
e05d723f TG |
1221 | if (!smp_found_config && !cpu_has_apic) |
1222 | return -1; | |
6eb0a0fd | 1223 | |
e05d723f TG |
1224 | /* |
1225 | * Complain if the BIOS pretends there is one. | |
1226 | */ | |
1227 | if (!cpu_has_apic && | |
1228 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1229 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1230 | boot_cpu_physical_apicid); | |
53756d37 | 1231 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
e05d723f | 1232 | return -1; |
6eb0a0fd | 1233 | } |
6eb0a0fd | 1234 | |
e05d723f | 1235 | verify_local_APIC(); |
6eb0a0fd | 1236 | |
e05d723f | 1237 | connect_bsp_APIC(); |
6eb0a0fd | 1238 | |
e05d723f TG |
1239 | /* |
1240 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1241 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1242 | * might be zero if read from MP tables. Get it from LAPIC. | |
1243 | */ | |
1244 | #ifdef CONFIG_CRASH_DUMP | |
05f2d12c | 1245 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
e05d723f | 1246 | #endif |
b6df1b8b | 1247 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
1da177e4 | 1248 | |
e05d723f | 1249 | setup_local_APIC(); |
1da177e4 | 1250 | |
acae7d90 MR |
1251 | #ifdef CONFIG_X86_IO_APIC |
1252 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) | |
1253 | #endif | |
1254 | localise_nmi_watchdog(); | |
ac60aae5 | 1255 | end_local_APIC_setup(); |
e05d723f TG |
1256 | #ifdef CONFIG_X86_IO_APIC |
1257 | if (smp_found_config) | |
1258 | if (!skip_ioapic_setup && nr_ioapics) | |
1259 | setup_IO_APIC(); | |
1da177e4 | 1260 | #endif |
e05d723f | 1261 | setup_boot_clock(); |
1da177e4 | 1262 | |
e05d723f | 1263 | return 0; |
1da177e4 LT |
1264 | } |
1265 | ||
e05d723f TG |
1266 | /* |
1267 | * Local APIC interrupts | |
1268 | */ | |
1269 | ||
1da177e4 LT |
1270 | /* |
1271 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1272 | */ | |
e9e2cdb4 | 1273 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1274 | { |
1275 | unsigned long v; | |
1276 | ||
1277 | irq_enter(); | |
1278 | /* | |
1279 | * Check if this really is a spurious interrupt and ACK it | |
1280 | * if it is a vectored one. Just in case... | |
1281 | * Spurious interrupts should not be ACKed. | |
1282 | */ | |
1283 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1284 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1285 | ack_APIC_irq(); | |
1286 | ||
1287 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
e05d723f TG |
1288 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " |
1289 | "should never happen.\n", smp_processor_id()); | |
38e760a1 | 1290 | __get_cpu_var(irq_stat).irq_spurious_count++; |
1da177e4 LT |
1291 | irq_exit(); |
1292 | } | |
1293 | ||
1294 | /* | |
1295 | * This interrupt should never happen with our APIC/SMP architecture | |
1296 | */ | |
e9e2cdb4 | 1297 | void smp_error_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1298 | { |
1299 | unsigned long v, v1; | |
1300 | ||
1301 | irq_enter(); | |
1302 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1303 | v = apic_read(APIC_ESR); | |
1304 | apic_write(APIC_ESR, 0); | |
1305 | v1 = apic_read(APIC_ESR); | |
1306 | ack_APIC_irq(); | |
1307 | atomic_inc(&irq_err_count); | |
1308 | ||
1309 | /* Here is what the APIC error bits mean: | |
1310 | 0: Send CS error | |
1311 | 1: Receive CS error | |
1312 | 2: Send accept error | |
1313 | 3: Receive accept error | |
1314 | 4: Reserved | |
1315 | 5: Send illegal vector | |
1316 | 6: Received illegal vector | |
1317 | 7: Illegal register address | |
1318 | */ | |
ff8a03a6 | 1319 | printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", |
e05d723f | 1320 | smp_processor_id(), v , v1); |
1da177e4 LT |
1321 | irq_exit(); |
1322 | } | |
1323 | ||
17c9ab1e GOC |
1324 | #ifdef CONFIG_SMP |
1325 | void __init smp_intr_init(void) | |
1326 | { | |
1327 | /* | |
1328 | * IRQ0 must be given a fixed assignment and initialized, | |
1329 | * because it's used before the IO-APIC is set up. | |
1330 | */ | |
1331 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1332 | ||
1333 | /* | |
1334 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1335 | * IPI, driven by wakeup. | |
1336 | */ | |
305b92a2 | 1337 | alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); |
17c9ab1e GOC |
1338 | |
1339 | /* IPI for invalidation */ | |
305b92a2 | 1340 | alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); |
17c9ab1e GOC |
1341 | |
1342 | /* IPI for generic function call */ | |
305b92a2 | 1343 | alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); |
3b16cf87 JA |
1344 | |
1345 | /* IPI for single call function */ | |
1346 | set_intr_gate(CALL_FUNCTION_SINGLE_VECTOR, | |
1347 | call_function_single_interrupt); | |
17c9ab1e GOC |
1348 | } |
1349 | #endif | |
1350 | ||
1da177e4 | 1351 | /* |
e05d723f | 1352 | * Initialize APIC interrupts |
1da177e4 | 1353 | */ |
e05d723f | 1354 | void __init apic_intr_init(void) |
1da177e4 | 1355 | { |
e05d723f TG |
1356 | #ifdef CONFIG_SMP |
1357 | smp_intr_init(); | |
1358 | #endif | |
1359 | /* self generated IPI for local APIC timer */ | |
305b92a2 | 1360 | alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); |
1da177e4 | 1361 | |
e05d723f | 1362 | /* IPI vectors for APIC spurious and error interrupts */ |
305b92a2 AM |
1363 | alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); |
1364 | alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
1da177e4 | 1365 | |
e05d723f TG |
1366 | /* thermal monitor LVT interrupt */ |
1367 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
305b92a2 | 1368 | alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); |
e05d723f TG |
1369 | #endif |
1370 | } | |
1371 | ||
1372 | /** | |
1373 | * connect_bsp_APIC - attach the APIC to the interrupt system | |
1374 | */ | |
1375 | void __init connect_bsp_APIC(void) | |
1376 | { | |
1377 | if (pic_mode) { | |
1378 | /* | |
1379 | * Do not trust the local APIC being empty at bootup. | |
1380 | */ | |
1381 | clear_local_APIC(); | |
1382 | /* | |
1383 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1384 | * local APIC to INT and NMI lines. | |
1385 | */ | |
1386 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1387 | "enabling APIC mode.\n"); | |
1388 | outb(0x70, 0x22); | |
1389 | outb(0x01, 0x23); | |
1da177e4 | 1390 | } |
e05d723f TG |
1391 | enable_apic_mode(); |
1392 | } | |
1da177e4 | 1393 | |
e05d723f TG |
1394 | /** |
1395 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1396 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1397 | * | |
1398 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1399 | * APIC is disabled. | |
1400 | */ | |
1401 | void disconnect_bsp_APIC(int virt_wire_setup) | |
1402 | { | |
1403 | if (pic_mode) { | |
1404 | /* | |
1405 | * Put the board back into PIC mode (has an effect only on | |
1406 | * certain older boards). Note that APIC interrupts, including | |
1407 | * IPIs, won't work beyond this point! The only exception are | |
1408 | * INIT IPIs. | |
1409 | */ | |
1410 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1411 | "entering PIC mode.\n"); | |
1412 | outb(0x70, 0x22); | |
1413 | outb(0x00, 0x23); | |
1414 | } else { | |
1415 | /* Go back to Virtual Wire compatibility mode */ | |
1416 | unsigned long value; | |
1da177e4 | 1417 | |
e05d723f TG |
1418 | /* For the spurious interrupt use vector F, and enable it */ |
1419 | value = apic_read(APIC_SPIV); | |
1420 | value &= ~APIC_VECTOR_MASK; | |
1421 | value |= APIC_SPIV_APIC_ENABLED; | |
1422 | value |= 0xf; | |
593f4a78 | 1423 | apic_write(APIC_SPIV, value); |
1da177e4 | 1424 | |
e05d723f TG |
1425 | if (!virt_wire_setup) { |
1426 | /* | |
1427 | * For LVT0 make it edge triggered, active high, | |
1428 | * external and enabled | |
1429 | */ | |
1430 | value = apic_read(APIC_LVT0); | |
1431 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1432 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
ff8a03a6 | 1433 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
e05d723f TG |
1434 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
1435 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
593f4a78 | 1436 | apic_write(APIC_LVT0, value); |
e05d723f TG |
1437 | } else { |
1438 | /* Disable LVT0 */ | |
593f4a78 | 1439 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
e05d723f | 1440 | } |
1da177e4 | 1441 | |
e05d723f TG |
1442 | /* |
1443 | * For LVT1 make it edge triggered, active high, nmi and | |
1444 | * enabled | |
1445 | */ | |
1446 | value = apic_read(APIC_LVT1); | |
1447 | value &= ~( | |
1448 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
1449 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1450 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1451 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1452 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
593f4a78 | 1453 | apic_write(APIC_LVT1, value); |
e05d723f TG |
1454 | } |
1455 | } | |
1da177e4 | 1456 | |
903dcb5a AS |
1457 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
1458 | ||
1459 | void __cpuinit generic_processor_info(int apicid, int version) | |
1460 | { | |
1461 | int cpu; | |
1462 | cpumask_t tmp_map; | |
1463 | physid_mask_t phys_cpu; | |
1464 | ||
1465 | /* | |
1466 | * Validate version | |
1467 | */ | |
1468 | if (version == 0x0) { | |
1469 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1470 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1471 | version); | |
1472 | version = 0x10; | |
1473 | } | |
1474 | apic_version[apicid] = version; | |
1475 | ||
1476 | phys_cpu = apicid_to_cpu_present(apicid); | |
1477 | physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu); | |
1478 | ||
1479 | if (num_processors >= NR_CPUS) { | |
1480 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1481 | " Processor ignored.\n", NR_CPUS); | |
1482 | return; | |
1483 | } | |
1484 | ||
1485 | if (num_processors >= maxcpus) { | |
1486 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
1487 | " Processor ignored.\n", maxcpus); | |
1488 | return; | |
1489 | } | |
1490 | ||
1491 | num_processors++; | |
1492 | cpus_complement(tmp_map, cpu_present_map); | |
1493 | cpu = first_cpu(tmp_map); | |
1494 | ||
1495 | if (apicid == boot_cpu_physical_apicid) | |
1496 | /* | |
1497 | * x86_bios_cpu_apicid is required to have processors listed | |
1498 | * in same order as logical cpu numbers. Hence the first | |
1499 | * entry is BSP, and so on. | |
1500 | */ | |
1501 | cpu = 0; | |
1502 | ||
e0da3364 YL |
1503 | if (apicid > max_physical_apicid) |
1504 | max_physical_apicid = apicid; | |
1505 | ||
903dcb5a AS |
1506 | /* |
1507 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1508 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1509 | * before this can be done without some confusion. | |
1510 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1511 | * - Ashok Raj <ashok.raj@intel.com> | |
1512 | */ | |
e0da3364 | 1513 | if (max_physical_apicid >= 8) { |
903dcb5a AS |
1514 | switch (boot_cpu_data.x86_vendor) { |
1515 | case X86_VENDOR_INTEL: | |
1516 | if (!APIC_XAPIC(version)) { | |
1517 | def_to_bigsmp = 0; | |
1518 | break; | |
1519 | } | |
1520 | /* If P4 and above fall through */ | |
1521 | case X86_VENDOR_AMD: | |
1522 | def_to_bigsmp = 1; | |
1523 | } | |
1524 | } | |
1525 | #ifdef CONFIG_SMP | |
1526 | /* are we being called early in kernel startup? */ | |
23ca4bba MT |
1527 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1528 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1529 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
903dcb5a AS |
1530 | |
1531 | cpu_to_apicid[cpu] = apicid; | |
1532 | bios_cpu_apicid[cpu] = apicid; | |
1533 | } else { | |
1534 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1535 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1536 | } | |
1537 | #endif | |
1538 | cpu_set(cpu, cpu_possible_map); | |
1539 | cpu_set(cpu, cpu_present_map); | |
1540 | } | |
1541 | ||
e05d723f TG |
1542 | /* |
1543 | * Power management | |
1544 | */ | |
1545 | #ifdef CONFIG_PM | |
1546 | ||
1547 | static struct { | |
1548 | int active; | |
1549 | /* r/w apic fields */ | |
1550 | unsigned int apic_id; | |
1551 | unsigned int apic_taskpri; | |
1552 | unsigned int apic_ldr; | |
1553 | unsigned int apic_dfr; | |
1554 | unsigned int apic_spiv; | |
1555 | unsigned int apic_lvtt; | |
1556 | unsigned int apic_lvtpc; | |
1557 | unsigned int apic_lvt0; | |
1558 | unsigned int apic_lvt1; | |
1559 | unsigned int apic_lvterr; | |
1560 | unsigned int apic_tmict; | |
1561 | unsigned int apic_tdcr; | |
1562 | unsigned int apic_thmr; | |
1563 | } apic_pm_state; | |
1564 | ||
1565 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1566 | { | |
1567 | unsigned long flags; | |
1568 | int maxlvt; | |
1569 | ||
1570 | if (!apic_pm_state.active) | |
1571 | return 0; | |
1572 | ||
1573 | maxlvt = lapic_get_maxlvt(); | |
1574 | ||
1575 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
1576 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1577 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1578 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1579 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1580 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1581 | if (maxlvt >= 4) | |
1582 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1583 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1584 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1585 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1586 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1587 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1588 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1589 | if (maxlvt >= 5) | |
1590 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1da177e4 | 1591 | #endif |
1e4c85f9 | 1592 | |
e05d723f TG |
1593 | local_irq_save(flags); |
1594 | disable_local_APIC(); | |
1595 | local_irq_restore(flags); | |
1e4c85f9 | 1596 | return 0; |
1da177e4 | 1597 | } |
1a3f239d | 1598 | |
e05d723f | 1599 | static int lapic_resume(struct sys_device *dev) |
1a3f239d | 1600 | { |
e05d723f TG |
1601 | unsigned int l, h; |
1602 | unsigned long flags; | |
1603 | int maxlvt; | |
1604 | ||
1605 | if (!apic_pm_state.active) | |
1606 | return 0; | |
1607 | ||
1608 | maxlvt = lapic_get_maxlvt(); | |
1609 | ||
1610 | local_irq_save(flags); | |
1611 | ||
1612 | /* | |
1613 | * Make sure the APICBASE points to the right address | |
1614 | * | |
1615 | * FIXME! This will be wrong if we ever support suspend on | |
1616 | * SMP! We'll need to do this as part of the CPU restore! | |
1617 | */ | |
1618 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1619 | l &= ~MSR_IA32_APICBASE_BASE; | |
1620 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1621 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1622 | ||
1623 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1624 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1625 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1626 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1627 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1628 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1629 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1630 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1631 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1632 | if (maxlvt >= 5) | |
1633 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1634 | #endif | |
1635 | if (maxlvt >= 4) | |
1636 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1637 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1638 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1639 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1640 | apic_write(APIC_ESR, 0); | |
1641 | apic_read(APIC_ESR); | |
1642 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1643 | apic_write(APIC_ESR, 0); | |
1644 | apic_read(APIC_ESR); | |
1645 | local_irq_restore(flags); | |
1a3f239d RR |
1646 | return 0; |
1647 | } | |
1a3f239d | 1648 | |
e05d723f TG |
1649 | /* |
1650 | * This device has no shutdown method - fully functioning local APICs | |
1651 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1652 | */ | |
1653 | ||
1654 | static struct sysdev_class lapic_sysclass = { | |
af5ca3f4 | 1655 | .name = "lapic", |
e05d723f TG |
1656 | .resume = lapic_resume, |
1657 | .suspend = lapic_suspend, | |
1658 | }; | |
1659 | ||
1660 | static struct sys_device device_lapic = { | |
1661 | .id = 0, | |
1662 | .cls = &lapic_sysclass, | |
1663 | }; | |
1664 | ||
1665 | static void __devinit apic_pm_activate(void) | |
1a3f239d | 1666 | { |
e05d723f | 1667 | apic_pm_state.active = 1; |
1a3f239d | 1668 | } |
1a3f239d | 1669 | |
e05d723f TG |
1670 | static int __init init_lapic_sysfs(void) |
1671 | { | |
1672 | int error; | |
1673 | ||
1674 | if (!cpu_has_apic) | |
1675 | return 0; | |
1676 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
1677 | ||
1678 | error = sysdev_class_register(&lapic_sysclass); | |
1679 | if (!error) | |
1680 | error = sysdev_register(&device_lapic); | |
1681 | return error; | |
1682 | } | |
1683 | device_initcall(init_lapic_sysfs); | |
1684 | ||
1685 | #else /* CONFIG_PM */ | |
1686 | ||
1687 | static void apic_pm_activate(void) { } | |
1688 | ||
1689 | #endif /* CONFIG_PM */ | |
0e078e2f TG |
1690 | |
1691 | /* | |
1692 | * APIC command line parameters | |
1693 | */ | |
1694 | static int __init parse_lapic(char *arg) | |
1695 | { | |
914bebfa | 1696 | force_enable_local_apic = 1; |
0e078e2f TG |
1697 | return 0; |
1698 | } | |
1699 | early_param("lapic", parse_lapic); | |
1700 | ||
1701 | static int __init parse_nolapic(char *arg) | |
1702 | { | |
914bebfa | 1703 | disable_apic = 1; |
9175fc06 | 1704 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
0e078e2f TG |
1705 | return 0; |
1706 | } | |
1707 | early_param("nolapic", parse_nolapic); | |
1708 | ||
1709 | static int __init parse_disable_lapic_timer(char *arg) | |
1710 | { | |
1711 | local_apic_timer_disabled = 1; | |
1712 | return 0; | |
1713 | } | |
1714 | early_param("nolapic_timer", parse_disable_lapic_timer); | |
1715 | ||
1716 | static int __init parse_lapic_timer_c2_ok(char *arg) | |
1717 | { | |
1718 | local_apic_timer_c2_ok = 1; | |
1719 | return 0; | |
1720 | } | |
1721 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1722 | ||
1723 | static int __init apic_set_verbosity(char *str) | |
1724 | { | |
1725 | if (strcmp("debug", str) == 0) | |
1726 | apic_verbosity = APIC_DEBUG; | |
1727 | else if (strcmp("verbose", str) == 0) | |
1728 | apic_verbosity = APIC_VERBOSE; | |
1729 | return 1; | |
1730 | } | |
1731 | __setup("apic=", apic_set_verbosity); | |
1732 | ||
746f2eb7 CG |
1733 | static int __init lapic_insert_resource(void) |
1734 | { | |
1735 | if (!apic_phys) | |
1736 | return -1; | |
1737 | ||
1738 | /* Put local APIC into the resource map. */ | |
1739 | lapic_resource.start = apic_phys; | |
1740 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1741 | insert_resource(&iomem_resource, &lapic_resource); | |
1742 | ||
1743 | return 0; | |
1744 | } | |
1745 | ||
1746 | /* | |
1747 | * need call insert after e820_reserve_resources() | |
1748 | * that is using request_resource | |
1749 | */ | |
1750 | late_initcall(lapic_insert_resource); |