Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
f3705136 | 26 | #include <linux/cpu.h> |
e9e2cdb4 | 27 | #include <linux/clockchips.h> |
d36b49b9 | 28 | #include <linux/acpi_pmtmr.h> |
6eb0a0fd | 29 | #include <linux/module.h> |
ad62ca2b | 30 | #include <linux/dmi.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/arch_hooks.h> | |
38 | #include <asm/hpet.h> | |
306e440d | 39 | #include <asm/i8253.h> |
3e4ff115 | 40 | #include <asm/nmi.h> |
1da177e4 LT |
41 | |
42 | #include <mach_apic.h> | |
382dbd07 | 43 | #include <mach_apicdef.h> |
6eb0a0fd | 44 | #include <mach_ipi.h> |
1da177e4 | 45 | |
e05d723f TG |
46 | /* |
47 | * Sanity check | |
48 | */ | |
ff8a03a6 | 49 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) |
e05d723f TG |
50 | # error SPURIOUS_APIC_VECTOR definition error |
51 | #endif | |
52 | ||
8f6e2ca9 AS |
53 | unsigned long mp_lapic_addr; |
54 | ||
9635b47d EB |
55 | /* |
56 | * Knob to control our willingness to enable the local APIC. | |
e05d723f | 57 | * |
914bebfa | 58 | * +1=force-enable |
9635b47d | 59 | */ |
914bebfa YL |
60 | static int force_enable_local_apic; |
61 | int disable_apic; | |
9635b47d | 62 | |
aa276e1c | 63 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
36fef094 | 64 | static int disable_apic_timer __cpuinitdata; |
e585bef8 TG |
65 | /* Local APIC timer works in C2 */ |
66 | int local_apic_timer_c2_ok; | |
67 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
e9e2cdb4 | 68 | |
ce178331 AM |
69 | int first_system_vector = 0xfe; |
70 | ||
71 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
72 | ||
1da177e4 | 73 | /* |
e05d723f | 74 | * Debug level, exported for io_apic.c |
1da177e4 | 75 | */ |
baa13188 | 76 | unsigned int apic_verbosity; |
1da177e4 | 77 | |
f3918352 AS |
78 | int pic_mode; |
79 | ||
bab4b27c AS |
80 | /* Have we found an MP table */ |
81 | int smp_found_config; | |
82 | ||
746f2eb7 CG |
83 | static struct resource lapic_resource = { |
84 | .name = "Local APIC", | |
85 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
86 | }; | |
87 | ||
e9e2cdb4 | 88 | static unsigned int calibration_result; |
1da177e4 | 89 | |
e9e2cdb4 TG |
90 | static int lapic_next_event(unsigned long delta, |
91 | struct clock_event_device *evt); | |
92 | static void lapic_timer_setup(enum clock_event_mode mode, | |
93 | struct clock_event_device *evt); | |
94 | static void lapic_timer_broadcast(cpumask_t mask); | |
95 | static void apic_pm_activate(void); | |
e05d723f | 96 | |
e9e2cdb4 TG |
97 | /* |
98 | * The local apic timer can be used for any function which is CPU local. | |
99 | */ | |
100 | static struct clock_event_device lapic_clockevent = { | |
101 | .name = "lapic", | |
102 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
d36b49b9 | 103 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
e9e2cdb4 TG |
104 | .shift = 32, |
105 | .set_mode = lapic_timer_setup, | |
106 | .set_next_event = lapic_next_event, | |
107 | .broadcast = lapic_timer_broadcast, | |
108 | .rating = 100, | |
109 | .irq = -1, | |
110 | }; | |
111 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
e05d723f TG |
112 | |
113 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ | |
114 | static int enabled_via_apicbase; | |
115 | ||
d3432896 AK |
116 | static unsigned long apic_phys; |
117 | ||
e05d723f TG |
118 | /* |
119 | * Get the LAPIC version | |
120 | */ | |
121 | static inline int lapic_get_version(void) | |
95d769aa | 122 | { |
e05d723f | 123 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
95d769aa AK |
124 | } |
125 | ||
1da177e4 | 126 | /* |
ab4a574e | 127 | * Check, if the APIC is integrated or a separate chip |
1da177e4 | 128 | */ |
e05d723f | 129 | static inline int lapic_is_integrated(void) |
1da177e4 | 130 | { |
e05d723f | 131 | return APIC_INTEGRATED(lapic_get_version()); |
1da177e4 LT |
132 | } |
133 | ||
e05d723f TG |
134 | /* |
135 | * Check, whether this is a modern or a first generation APIC | |
136 | */ | |
137 | static int modern_apic(void) | |
1da177e4 | 138 | { |
e05d723f TG |
139 | /* AMD systems use old APIC versions, so check the CPU */ |
140 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
141 | boot_cpu_data.x86 >= 0xf) | |
142 | return 1; | |
143 | return lapic_get_version() >= 0x14; | |
1da177e4 LT |
144 | } |
145 | ||
9a8f0e6b SS |
146 | /* |
147 | * Paravirt kernels also might be using these below ops. So we still | |
148 | * use generic apic_read()/apic_write(), which might be pointing to different | |
149 | * ops in PARAVIRT case. | |
150 | */ | |
c535b6a1 | 151 | void xapic_wait_icr_idle(void) |
f2b218dd FLV |
152 | { |
153 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
154 | cpu_relax(); | |
155 | } | |
156 | ||
c535b6a1 | 157 | u32 safe_xapic_wait_icr_idle(void) |
f2b218dd | 158 | { |
42e0a9aa | 159 | u32 send_status; |
f2b218dd FLV |
160 | int timeout; |
161 | ||
162 | timeout = 0; | |
163 | do { | |
164 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
165 | if (!send_status) | |
166 | break; | |
167 | udelay(100); | |
168 | } while (timeout++ < 1000); | |
169 | ||
170 | return send_status; | |
171 | } | |
172 | ||
c535b6a1 YL |
173 | void xapic_icr_write(u32 low, u32 id) |
174 | { | |
f586bf7d SS |
175 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
176 | apic_write(APIC_ICR, low); | |
c535b6a1 YL |
177 | } |
178 | ||
179 | u64 xapic_icr_read(void) | |
180 | { | |
181 | u32 icr1, icr2; | |
182 | ||
183 | icr2 = apic_read(APIC_ICR2); | |
184 | icr1 = apic_read(APIC_ICR); | |
185 | ||
186 | return icr1 | ((u64)icr2 << 32); | |
187 | } | |
188 | ||
189 | static struct apic_ops xapic_ops = { | |
190 | .read = native_apic_mem_read, | |
191 | .write = native_apic_mem_write, | |
c535b6a1 YL |
192 | .icr_read = xapic_icr_read, |
193 | .icr_write = xapic_icr_write, | |
194 | .wait_icr_idle = xapic_wait_icr_idle, | |
195 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
196 | }; | |
197 | ||
198 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
199 | EXPORT_SYMBOL_GPL(apic_ops); | |
200 | ||
e05d723f TG |
201 | /** |
202 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
203 | */ | |
e9427101 | 204 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 205 | { |
d4c63ec0 | 206 | unsigned int v; |
1da177e4 | 207 | |
d4c63ec0 CG |
208 | /* unmask and set to NMI */ |
209 | v = APIC_DM_NMI; | |
210 | ||
211 | /* Level triggered for 82489DX (32bit mode) */ | |
e05d723f | 212 | if (!lapic_is_integrated()) |
1da177e4 | 213 | v |= APIC_LVT_LEVEL_TRIGGER; |
d4c63ec0 | 214 | |
593f4a78 | 215 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
216 | } |
217 | ||
e05d723f TG |
218 | /** |
219 | * get_physical_broadcast - Get number of physical broadcast IDs | |
220 | */ | |
1da177e4 LT |
221 | int get_physical_broadcast(void) |
222 | { | |
e05d723f | 223 | return modern_apic() ? 0xff : 0xf; |
1da177e4 LT |
224 | } |
225 | ||
e05d723f TG |
226 | /** |
227 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
228 | */ | |
229 | int lapic_get_maxlvt(void) | |
1da177e4 | 230 | { |
36a028de | 231 | unsigned int v; |
1da177e4 | 232 | |
36a028de CG |
233 | v = apic_read(APIC_LVR); |
234 | /* | |
235 | * - we always have APIC integrated on 64bit mode | |
236 | * - 82489DXs do not report # of LVT entries | |
237 | */ | |
e05d723f | 238 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
1da177e4 LT |
239 | } |
240 | ||
e05d723f TG |
241 | /* |
242 | * Local APIC timer | |
243 | */ | |
244 | ||
d36b49b9 TG |
245 | /* Clock divisor is set to 16 */ |
246 | #define APIC_DIVISOR 16 | |
e05d723f TG |
247 | |
248 | /* | |
249 | * This function sets up the local APIC timer, with a timeout of | |
250 | * 'clocks' APIC bus clock. During calibration we actually call | |
251 | * this function twice on the boot CPU, once with a bogus timeout | |
252 | * value, second time for real. The other (noncalibrating) CPUs | |
253 | * call this function only once, with the real, calibrated value. | |
e05d723f | 254 | */ |
e9e2cdb4 | 255 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 256 | { |
e05d723f | 257 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 258 | |
e9e2cdb4 TG |
259 | lvtt_value = LOCAL_TIMER_VECTOR; |
260 | if (!oneshot) | |
261 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
e05d723f TG |
262 | if (!lapic_is_integrated()) |
263 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
264 | ||
e9e2cdb4 | 265 | if (!irqen) |
e05d723f TG |
266 | lvtt_value |= APIC_LVT_MASKED; |
267 | ||
593f4a78 | 268 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
269 | |
270 | /* | |
e05d723f | 271 | * Divide PICLK by 16 |
1da177e4 | 272 | */ |
e05d723f | 273 | tmp_value = apic_read(APIC_TDCR); |
593f4a78 MR |
274 | apic_write(APIC_TDCR, |
275 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
276 | APIC_TDR_DIV_16); | |
1da177e4 | 277 | |
e9e2cdb4 | 278 | if (!oneshot) |
593f4a78 | 279 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
e9e2cdb4 TG |
280 | } |
281 | ||
282 | /* | |
283 | * Program the next event, relative to now | |
284 | */ | |
285 | static int lapic_next_event(unsigned long delta, | |
286 | struct clock_event_device *evt) | |
287 | { | |
593f4a78 | 288 | apic_write(APIC_TMICT, delta); |
e9e2cdb4 | 289 | return 0; |
1da177e4 LT |
290 | } |
291 | ||
e9e2cdb4 TG |
292 | /* |
293 | * Setup the lapic timer in periodic or oneshot mode | |
294 | */ | |
295 | static void lapic_timer_setup(enum clock_event_mode mode, | |
296 | struct clock_event_device *evt) | |
1da177e4 | 297 | { |
e05d723f | 298 | unsigned long flags; |
e9e2cdb4 | 299 | unsigned int v; |
e05d723f | 300 | |
d36b49b9 | 301 | /* Lapic used for broadcast ? */ |
64e474d1 | 302 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) |
d36b49b9 TG |
303 | return; |
304 | ||
e05d723f | 305 | local_irq_save(flags); |
1da177e4 | 306 | |
e9e2cdb4 TG |
307 | switch (mode) { |
308 | case CLOCK_EVT_MODE_PERIODIC: | |
309 | case CLOCK_EVT_MODE_ONESHOT: | |
310 | __setup_APIC_LVTT(calibration_result, | |
311 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
312 | break; | |
313 | case CLOCK_EVT_MODE_UNUSED: | |
314 | case CLOCK_EVT_MODE_SHUTDOWN: | |
315 | v = apic_read(APIC_LVTT); | |
316 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
593f4a78 | 317 | apic_write(APIC_LVTT, v); |
e9e2cdb4 | 318 | break; |
18de5bc4 TG |
319 | case CLOCK_EVT_MODE_RESUME: |
320 | /* Nothing to do here */ | |
321 | break; | |
e9e2cdb4 | 322 | } |
e05d723f TG |
323 | |
324 | local_irq_restore(flags); | |
325 | } | |
326 | ||
e9e2cdb4 TG |
327 | /* |
328 | * Local APIC timer broadcast function | |
329 | */ | |
330 | static void lapic_timer_broadcast(cpumask_t mask) | |
331 | { | |
332 | #ifdef CONFIG_SMP | |
333 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
334 | #endif | |
335 | } | |
336 | ||
337 | /* | |
338 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
339 | * of the boot CPU and register the clock event in the framework. | |
340 | */ | |
341 | static void __devinit setup_APIC_timer(void) | |
342 | { | |
343 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
344 | ||
345 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); | |
346 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
347 | ||
348 | clockevents_register_device(levt); | |
349 | } | |
350 | ||
e05d723f | 351 | /* |
d36b49b9 TG |
352 | * In this functions we calibrate APIC bus clocks to the external timer. |
353 | * | |
354 | * We want to do the calibration only once since we want to have local timer | |
355 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
356 | * frequency. | |
357 | * | |
358 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
359 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
360 | * readout is broken, so it never gets out of the wait loop again. This was | |
361 | * also reported by others. | |
e05d723f | 362 | * |
d36b49b9 TG |
363 | * Monitoring the jiffies value is inaccurate and the clockevents |
364 | * infrastructure allows us to do a simple substitution of the interrupt | |
365 | * handler. | |
e9e2cdb4 | 366 | * |
d36b49b9 TG |
367 | * The calibration routine also uses the pm_timer when possible, as the PIT |
368 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
369 | * back to normal later in the boot process). | |
e05d723f TG |
370 | */ |
371 | ||
d36b49b9 | 372 | #define LAPIC_CAL_LOOPS (HZ/10) |
e05d723f | 373 | |
f5352fd0 | 374 | static __initdata int lapic_cal_loops = -1; |
d36b49b9 TG |
375 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
376 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
377 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
378 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
1da177e4 | 379 | |
d36b49b9 TG |
380 | /* |
381 | * Temporary interrupt handler. | |
382 | */ | |
383 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
384 | { | |
385 | unsigned long long tsc = 0; | |
386 | long tapic = apic_read(APIC_TMCCT); | |
387 | unsigned long pm = acpi_pm_read_early(); | |
1da177e4 | 388 | |
d36b49b9 TG |
389 | if (cpu_has_tsc) |
390 | rdtscll(tsc); | |
391 | ||
392 | switch (lapic_cal_loops++) { | |
393 | case 0: | |
394 | lapic_cal_t1 = tapic; | |
395 | lapic_cal_tsc1 = tsc; | |
396 | lapic_cal_pm1 = pm; | |
397 | lapic_cal_j1 = jiffies; | |
398 | break; | |
e05d723f | 399 | |
d36b49b9 TG |
400 | case LAPIC_CAL_LOOPS: |
401 | lapic_cal_t2 = tapic; | |
402 | lapic_cal_tsc2 = tsc; | |
403 | if (pm < lapic_cal_pm1) | |
404 | pm += ACPI_PM_OVRRUN; | |
405 | lapic_cal_pm2 = pm; | |
406 | lapic_cal_j2 = jiffies; | |
407 | break; | |
408 | } | |
409 | } | |
1da177e4 | 410 | |
836c129d | 411 | static int __init calibrate_APIC_clock(void) |
d36b49b9 TG |
412 | { |
413 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
414 | const long pm_100ms = PMTMR_TICKS_PER_SEC/10; | |
415 | const long pm_thresh = pm_100ms/100; | |
416 | void (*real_handler)(struct clock_event_device *dev); | |
417 | unsigned long deltaj; | |
418 | long delta, deltapm; | |
ca1b940c | 419 | int pm_referenced = 0; |
1da177e4 | 420 | |
d36b49b9 TG |
421 | local_irq_disable(); |
422 | ||
423 | /* Replace the global interrupt handler */ | |
424 | real_handler = global_clock_event->event_handler; | |
425 | global_clock_event->event_handler = lapic_cal_handler; | |
1da177e4 | 426 | |
1da177e4 | 427 | /* |
d36b49b9 TG |
428 | * Setup the APIC counter to 1e9. There is no way the lapic |
429 | * can underflow in the 100ms detection time frame | |
1da177e4 | 430 | */ |
d36b49b9 | 431 | __setup_APIC_LVTT(1000000000, 0, 0); |
1da177e4 | 432 | |
d36b49b9 TG |
433 | /* Let the interrupts run */ |
434 | local_irq_enable(); | |
435 | ||
ca1b940c TG |
436 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
437 | cpu_relax(); | |
d36b49b9 TG |
438 | |
439 | local_irq_disable(); | |
440 | ||
441 | /* Restore the real event handler */ | |
442 | global_clock_event->event_handler = real_handler; | |
443 | ||
444 | /* Build delta t1-t2 as apic timer counts down */ | |
445 | delta = lapic_cal_t1 - lapic_cal_t2; | |
446 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
447 | ||
448 | /* Check, if the PM timer is available */ | |
449 | deltapm = lapic_cal_pm2 - lapic_cal_pm1; | |
450 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
451 | ||
452 | if (deltapm) { | |
453 | unsigned long mult; | |
454 | u64 res; | |
455 | ||
456 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
457 | ||
458 | if (deltapm > (pm_100ms - pm_thresh) && | |
459 | deltapm < (pm_100ms + pm_thresh)) { | |
460 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
461 | } else { | |
462 | res = (((u64) deltapm) * mult) >> 22; | |
463 | do_div(res, 1000000); | |
464 | printk(KERN_WARNING "APIC calibration not consistent " | |
465 | "with PM Timer: %ldms instead of 100ms\n", | |
466 | (long)res); | |
467 | /* Correct the lapic counter value */ | |
ff8a03a6 | 468 | res = (((u64) delta) * pm_100ms); |
d36b49b9 TG |
469 | do_div(res, deltapm); |
470 | printk(KERN_INFO "APIC delta adjusted to PM-Timer: " | |
471 | "%lu (%ld)\n", (unsigned long) res, delta); | |
472 | delta = (long) res; | |
473 | } | |
ca1b940c | 474 | pm_referenced = 1; |
d36b49b9 | 475 | } |
e05d723f | 476 | |
e9e2cdb4 | 477 | /* Calculate the scaled math multiplication factor */ |
877084fb AM |
478 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, |
479 | lapic_clockevent.shift); | |
e9e2cdb4 TG |
480 | lapic_clockevent.max_delta_ns = |
481 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
482 | lapic_clockevent.min_delta_ns = | |
483 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
484 | ||
d36b49b9 TG |
485 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
486 | ||
487 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
e9e2cdb4 | 488 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); |
d36b49b9 TG |
489 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
490 | calibration_result); | |
e9e2cdb4 | 491 | |
d36b49b9 TG |
492 | if (cpu_has_tsc) { |
493 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
e05d723f | 494 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
d36b49b9 TG |
495 | "%ld.%04ld MHz.\n", |
496 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
497 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
498 | } | |
e05d723f TG |
499 | |
500 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
d36b49b9 TG |
501 | "%u.%04u MHz.\n", |
502 | calibration_result / (1000000 / HZ), | |
503 | calibration_result % (1000000 / HZ)); | |
e05d723f | 504 | |
c2b84b30 TG |
505 | /* |
506 | * Do a sanity check on the APIC calibration result | |
507 | */ | |
508 | if (calibration_result < (1000000 / HZ)) { | |
509 | local_irq_enable(); | |
510 | printk(KERN_WARNING | |
511 | "APIC frequency too slow, disabling apic timer\n"); | |
836c129d | 512 | return -1; |
c2b84b30 TG |
513 | } |
514 | ||
64e474d1 | 515 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; |
836c129d | 516 | |
ca1b940c TG |
517 | /* We trust the pm timer based calibration */ |
518 | if (!pm_referenced) { | |
519 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
d36b49b9 | 520 | |
ca1b940c TG |
521 | /* |
522 | * Setup the apic timer manually | |
523 | */ | |
524 | levt->event_handler = lapic_cal_handler; | |
525 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
526 | lapic_cal_loops = -1; | |
d36b49b9 | 527 | |
ca1b940c TG |
528 | /* Let the interrupts run */ |
529 | local_irq_enable(); | |
d36b49b9 | 530 | |
f5352fd0 | 531 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
ca1b940c | 532 | cpu_relax(); |
d36b49b9 | 533 | |
ca1b940c | 534 | local_irq_disable(); |
d36b49b9 | 535 | |
ca1b940c TG |
536 | /* Stop the lapic timer */ |
537 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
d36b49b9 | 538 | |
ca1b940c | 539 | local_irq_enable(); |
d36b49b9 | 540 | |
ca1b940c TG |
541 | /* Jiffies delta */ |
542 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
543 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
d36b49b9 | 544 | |
d36b49b9 | 545 | /* Check, if the jiffies result is consistent */ |
ca1b940c | 546 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
d36b49b9 | 547 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
ca1b940c | 548 | else |
64e474d1 | 549 | levt->features |= CLOCK_EVT_FEAT_DUMMY; |
4edc5db8 IM |
550 | } else |
551 | local_irq_enable(); | |
e05d723f | 552 | |
64e474d1 | 553 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { |
d36b49b9 TG |
554 | printk(KERN_WARNING |
555 | "APIC timer disabled due to verification failure.\n"); | |
836c129d CG |
556 | return -1; |
557 | } | |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
562 | /* | |
563 | * Setup the boot APIC | |
564 | * | |
565 | * Calibrate and verify the result. | |
566 | */ | |
567 | void __init setup_boot_APIC_clock(void) | |
568 | { | |
569 | /* | |
570 | * The local apic timer can be disabled via the kernel | |
571 | * commandline or from the CPU detection code. Register the lapic | |
572 | * timer as a dummy clock event source on SMP systems, so the | |
573 | * broadcast mechanism is used. On UP systems simply ignore it. | |
574 | */ | |
36fef094 | 575 | if (disable_apic_timer) { |
d36b49b9 | 576 | /* No broadcast on UP ! */ |
836c129d CG |
577 | if (num_possible_cpus() > 1) { |
578 | lapic_clockevent.mult = 1; | |
579 | setup_APIC_timer(); | |
580 | } | |
581 | return; | |
a5f5e43e | 582 | } |
d36b49b9 | 583 | |
836c129d CG |
584 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
585 | "calibrating APIC timer ...\n"); | |
586 | ||
587 | if (calibrate_APIC_clock()) { | |
588 | /* No broadcast on UP ! */ | |
589 | if (num_possible_cpus() > 1) | |
590 | setup_APIC_timer(); | |
591 | return; | |
592 | } | |
593 | ||
594 | /* | |
595 | * If nmi_watchdog is set to IO_APIC, we need the | |
596 | * PIT/HPET going. Otherwise register lapic as a dummy | |
597 | * device. | |
598 | */ | |
599 | if (nmi_watchdog != NMI_IO_APIC) | |
600 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
601 | else | |
602 | printk(KERN_WARNING "APIC timer registered as dummy," | |
603 | " due to nmi_watchdog=%d!\n", nmi_watchdog); | |
604 | ||
d36b49b9 TG |
605 | /* Setup the lapic or request the broadcast */ |
606 | setup_APIC_timer(); | |
e05d723f | 607 | } |
1da177e4 | 608 | |
e05d723f TG |
609 | void __devinit setup_secondary_APIC_clock(void) |
610 | { | |
e9e2cdb4 | 611 | setup_APIC_timer(); |
e05d723f | 612 | } |
1da177e4 | 613 | |
e05d723f | 614 | /* |
e9e2cdb4 | 615 | * The guts of the apic timer interrupt |
e05d723f | 616 | */ |
e9e2cdb4 | 617 | static void local_apic_timer_interrupt(void) |
e05d723f | 618 | { |
e9e2cdb4 TG |
619 | int cpu = smp_processor_id(); |
620 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
1da177e4 LT |
621 | |
622 | /* | |
d36b49b9 TG |
623 | * Normally we should not be here till LAPIC has been initialized but |
624 | * in some cases like kdump, its possible that there is a pending LAPIC | |
625 | * timer interrupt from previous kernel's context and is delivered in | |
626 | * new kernel the moment interrupts are enabled. | |
e05d723f | 627 | * |
d36b49b9 TG |
628 | * Interrupts are enabled early and LAPIC is setup much later, hence |
629 | * its possible that when we get here evt->event_handler is NULL. | |
630 | * Check for event_handler being NULL and discard the interrupt as | |
631 | * spurious. | |
1da177e4 | 632 | */ |
e9e2cdb4 TG |
633 | if (!evt->event_handler) { |
634 | printk(KERN_WARNING | |
635 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
636 | /* Switch it off */ | |
637 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
638 | return; | |
639 | } | |
640 | ||
0e078e2f TG |
641 | /* |
642 | * the NMI deadlock-detector uses this. | |
643 | */ | |
e9e2cdb4 TG |
644 | per_cpu(irq_stat, cpu).apic_timer_irqs++; |
645 | ||
646 | evt->event_handler(evt); | |
e05d723f TG |
647 | } |
648 | ||
649 | /* | |
650 | * Local APIC timer interrupt. This is the most natural way for doing | |
651 | * local interrupts, but local timer interrupts can be emulated by | |
652 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
653 | * | |
654 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
655 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
656 | */ | |
75604d7f | 657 | void smp_apic_timer_interrupt(struct pt_regs *regs) |
e05d723f TG |
658 | { |
659 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1da177e4 LT |
660 | |
661 | /* | |
e05d723f TG |
662 | * NOTE! We'd better ACK the irq immediately, |
663 | * because timer handling can be slow. | |
1da177e4 | 664 | */ |
e05d723f | 665 | ack_APIC_irq(); |
1a75a3f0 | 666 | /* |
e05d723f TG |
667 | * update_process_times() expects us to have done irq_enter(). |
668 | * Besides, if we don't timer interrupts ignore the global | |
669 | * interrupt lock, which is the WrongThing (tm) to do. | |
1a75a3f0 | 670 | */ |
e05d723f | 671 | irq_enter(); |
e9e2cdb4 | 672 | local_apic_timer_interrupt(); |
e05d723f | 673 | irq_exit(); |
1a75a3f0 | 674 | |
e9e2cdb4 | 675 | set_irq_regs(old_regs); |
e05d723f TG |
676 | } |
677 | ||
678 | int setup_profiling_timer(unsigned int multiplier) | |
679 | { | |
680 | return -EINVAL; | |
681 | } | |
682 | ||
e319e765 RR |
683 | /* |
684 | * Setup extended LVT, AMD specific (K8, family 10h) | |
685 | * | |
686 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
687 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
688 | */ | |
689 | ||
690 | #define APIC_EILVT_LVTOFF_MCE 0 | |
691 | #define APIC_EILVT_LVTOFF_IBS 1 | |
692 | ||
693 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
694 | { | |
695 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; | |
696 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; | |
697 | apic_write(reg, v); | |
698 | } | |
699 | ||
700 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) | |
701 | { | |
702 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
703 | return APIC_EILVT_LVTOFF_MCE; | |
704 | } | |
705 | ||
706 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
707 | { | |
708 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
709 | return APIC_EILVT_LVTOFF_IBS; | |
710 | } | |
711 | ||
e05d723f TG |
712 | /* |
713 | * Local APIC start and shutdown | |
714 | */ | |
715 | ||
716 | /** | |
717 | * clear_local_APIC - shutdown the local APIC | |
718 | * | |
719 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
720 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
721 | * leftovers during boot. | |
722 | */ | |
723 | void clear_local_APIC(void) | |
724 | { | |
d3432896 | 725 | int maxlvt; |
0e078e2f | 726 | u32 v; |
1da177e4 | 727 | |
d3432896 AK |
728 | /* APIC hasn't been mapped yet */ |
729 | if (!apic_phys) | |
730 | return; | |
731 | ||
732 | maxlvt = lapic_get_maxlvt(); | |
1da177e4 | 733 | /* |
e05d723f TG |
734 | * Masking an LVT entry can trigger a local APIC error |
735 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1da177e4 | 736 | */ |
e05d723f TG |
737 | if (maxlvt >= 3) { |
738 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
593f4a78 | 739 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
e05d723f | 740 | } |
1da177e4 | 741 | /* |
e05d723f TG |
742 | * Careful: we have to set masks only first to deassert |
743 | * any level-triggered sources. | |
1da177e4 | 744 | */ |
e05d723f | 745 | v = apic_read(APIC_LVTT); |
593f4a78 | 746 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
e05d723f | 747 | v = apic_read(APIC_LVT0); |
593f4a78 | 748 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
e05d723f | 749 | v = apic_read(APIC_LVT1); |
593f4a78 | 750 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
e05d723f TG |
751 | if (maxlvt >= 4) { |
752 | v = apic_read(APIC_LVTPC); | |
593f4a78 | 753 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
1da177e4 | 754 | } |
1da177e4 | 755 | |
e05d723f TG |
756 | /* lets not touch this if we didn't frob it */ |
757 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
758 | if (maxlvt >= 5) { | |
759 | v = apic_read(APIC_LVTTHMR); | |
593f4a78 | 760 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); |
e05d723f TG |
761 | } |
762 | #endif | |
1da177e4 | 763 | /* |
e05d723f | 764 | * Clean APIC state for other OSs: |
1da177e4 | 765 | */ |
593f4a78 MR |
766 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
767 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
768 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
e05d723f | 769 | if (maxlvt >= 3) |
593f4a78 | 770 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
e05d723f | 771 | if (maxlvt >= 4) |
593f4a78 | 772 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
1da177e4 | 773 | |
e05d723f TG |
774 | #ifdef CONFIG_X86_MCE_P4THERMAL |
775 | if (maxlvt >= 5) | |
593f4a78 | 776 | apic_write(APIC_LVTTHMR, APIC_LVT_MASKED); |
e05d723f TG |
777 | #endif |
778 | /* Integrated APIC (!82489DX) ? */ | |
779 | if (lapic_is_integrated()) { | |
1da177e4 | 780 | if (maxlvt > 3) |
e05d723f | 781 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
1da177e4 | 782 | apic_write(APIC_ESR, 0); |
e05d723f | 783 | apic_read(APIC_ESR); |
1da177e4 | 784 | } |
e05d723f | 785 | } |
1da177e4 | 786 | |
e05d723f TG |
787 | /** |
788 | * disable_local_APIC - clear and disable the local APIC | |
789 | */ | |
790 | void disable_local_APIC(void) | |
791 | { | |
792 | unsigned long value; | |
793 | ||
794 | clear_local_APIC(); | |
795 | ||
796 | /* | |
797 | * Disable APIC (implies clearing of registers | |
798 | * for 82489DX!). | |
799 | */ | |
800 | value = apic_read(APIC_SPIV); | |
801 | value &= ~APIC_SPIV_APIC_ENABLED; | |
593f4a78 | 802 | apic_write(APIC_SPIV, value); |
e05d723f TG |
803 | |
804 | /* | |
805 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
806 | * restore the disabled state. | |
807 | */ | |
808 | if (enabled_via_apicbase) { | |
809 | unsigned int l, h; | |
810 | ||
811 | rdmsr(MSR_IA32_APICBASE, l, h); | |
812 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
813 | wrmsr(MSR_IA32_APICBASE, l, h); | |
814 | } | |
1da177e4 LT |
815 | } |
816 | ||
817 | /* | |
e05d723f TG |
818 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
819 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
820 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
77f72b19 | 821 | * for the case where Linux didn't enable the LAPIC. |
1da177e4 LT |
822 | */ |
823 | void lapic_shutdown(void) | |
824 | { | |
67963132 MS |
825 | unsigned long flags; |
826 | ||
77f72b19 | 827 | if (!cpu_has_apic) |
1da177e4 LT |
828 | return; |
829 | ||
67963132 | 830 | local_irq_save(flags); |
77f72b19 ZM |
831 | |
832 | if (enabled_via_apicbase) | |
833 | disable_local_APIC(); | |
9ce122c6 CG |
834 | else |
835 | clear_local_APIC(); | |
77f72b19 | 836 | |
67963132 | 837 | local_irq_restore(flags); |
1da177e4 LT |
838 | } |
839 | ||
e05d723f TG |
840 | /* |
841 | * This is to verify that we're looking at a real local APIC. | |
842 | * Check these against your board if the CPUs aren't getting | |
843 | * started for no apparent reason. | |
844 | */ | |
845 | int __init verify_local_APIC(void) | |
1da177e4 | 846 | { |
e05d723f | 847 | unsigned int reg0, reg1; |
1da177e4 | 848 | |
e05d723f TG |
849 | /* |
850 | * The version register is read-only in a real APIC. | |
851 | */ | |
852 | reg0 = apic_read(APIC_LVR); | |
853 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
854 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
855 | reg1 = apic_read(APIC_LVR); | |
856 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
857 | ||
858 | /* | |
859 | * The two version reads above should print the same | |
860 | * numbers. If the second one is different, then we | |
861 | * poke at a non-APIC. | |
862 | */ | |
863 | if (reg1 != reg0) | |
1da177e4 LT |
864 | return 0; |
865 | ||
e05d723f TG |
866 | /* |
867 | * Check if the version looks reasonably. | |
868 | */ | |
869 | reg1 = GET_APIC_VERSION(reg0); | |
870 | if (reg1 == 0x00 || reg1 == 0xff) | |
871 | return 0; | |
872 | reg1 = lapic_get_maxlvt(); | |
873 | if (reg1 < 0x02 || reg1 == 0xff) | |
874 | return 0; | |
f990fff4 | 875 | |
e05d723f TG |
876 | /* |
877 | * The ID register is read/write in a real APIC. | |
878 | */ | |
879 | reg0 = apic_read(APIC_ID); | |
880 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
c93baa1a CG |
881 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); |
882 | reg1 = apic_read(APIC_ID); | |
883 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
884 | apic_write(APIC_ID, reg0); | |
885 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
886 | return 0; | |
e05d723f TG |
887 | |
888 | /* | |
889 | * The next two are just to see if we have sane values. | |
890 | * They're only really relevant if we're in Virtual Wire | |
891 | * compatibility mode, but most boxes are anymore. | |
892 | */ | |
893 | reg0 = apic_read(APIC_LVT0); | |
894 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
895 | reg1 = apic_read(APIC_LVT1); | |
896 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
897 | ||
898 | return 1; | |
1da177e4 LT |
899 | } |
900 | ||
e05d723f TG |
901 | /** |
902 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
903 | */ | |
904 | void __init sync_Arb_IDs(void) | |
1da177e4 | 905 | { |
e05d723f TG |
906 | /* |
907 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
908 | * needed on AMD. | |
909 | */ | |
f44d9efd | 910 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
e05d723f TG |
911 | return; |
912 | /* | |
913 | * Wait for idle. | |
914 | */ | |
915 | apic_wait_icr_idle(); | |
1da177e4 | 916 | |
e05d723f | 917 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
296cb951 | 918 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT); |
e05d723f | 919 | } |
1da177e4 | 920 | |
e05d723f TG |
921 | /* |
922 | * An initial setup of the virtual wire mode. | |
923 | */ | |
924 | void __init init_bsp_APIC(void) | |
925 | { | |
926 | unsigned long value; | |
f990fff4 | 927 | |
e05d723f TG |
928 | /* |
929 | * Don't do the setup now if we have a SMP BIOS as the | |
930 | * through-I/O-APIC virtual wire mode might be active. | |
931 | */ | |
932 | if (smp_found_config || !cpu_has_apic) | |
933 | return; | |
1da177e4 LT |
934 | |
935 | /* | |
e05d723f | 936 | * Do not trust the local APIC being empty at bootup. |
1da177e4 | 937 | */ |
e05d723f | 938 | clear_local_APIC(); |
1da177e4 | 939 | |
e05d723f TG |
940 | /* |
941 | * Enable APIC. | |
942 | */ | |
943 | value = apic_read(APIC_SPIV); | |
944 | value &= ~APIC_VECTOR_MASK; | |
945 | value |= APIC_SPIV_APIC_ENABLED; | |
946 | ||
947 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
948 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
949 | (boot_cpu_data.x86 == 15)) | |
950 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
951 | else | |
952 | value |= APIC_SPIV_FOCUS_DISABLED; | |
953 | value |= SPURIOUS_APIC_VECTOR; | |
593f4a78 | 954 | apic_write(APIC_SPIV, value); |
e05d723f TG |
955 | |
956 | /* | |
957 | * Set up the virtual wire mode. | |
958 | */ | |
593f4a78 | 959 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
e05d723f TG |
960 | value = APIC_DM_NMI; |
961 | if (!lapic_is_integrated()) /* 82489DX */ | |
962 | value |= APIC_LVT_LEVEL_TRIGGER; | |
593f4a78 | 963 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
964 | } |
965 | ||
a4928cff | 966 | static void __cpuinit lapic_setup_esr(void) |
df7939ae GOC |
967 | { |
968 | unsigned long oldvalue, value, maxlvt; | |
969 | if (lapic_is_integrated() && !esr_disable) { | |
970 | /* !82489DX */ | |
971 | maxlvt = lapic_get_maxlvt(); | |
972 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
973 | apic_write(APIC_ESR, 0); | |
974 | oldvalue = apic_read(APIC_ESR); | |
975 | ||
976 | /* enables sending errors */ | |
977 | value = ERROR_APIC_VECTOR; | |
593f4a78 | 978 | apic_write(APIC_LVTERR, value); |
df7939ae GOC |
979 | /* |
980 | * spec says clear errors after enabling vector. | |
981 | */ | |
982 | if (maxlvt > 3) | |
983 | apic_write(APIC_ESR, 0); | |
984 | value = apic_read(APIC_ESR); | |
985 | if (value != oldvalue) | |
986 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
987 | "vector: 0x%08lx after: 0x%08lx\n", | |
988 | oldvalue, value); | |
989 | } else { | |
990 | if (esr_disable) | |
991 | /* | |
992 | * Something untraceable is creating bad interrupts on | |
993 | * secondary quads ... for the moment, just leave the | |
994 | * ESR disabled - we can't do anything useful with the | |
995 | * errors anyway - mbligh | |
996 | */ | |
997 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
998 | else | |
999 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
1000 | } | |
1001 | } | |
1002 | ||
1003 | ||
e05d723f TG |
1004 | /** |
1005 | * setup_local_APIC - setup the local APIC | |
1da177e4 | 1006 | */ |
d5337983 | 1007 | void __cpuinit setup_local_APIC(void) |
e05d723f | 1008 | { |
df7939ae | 1009 | unsigned long value, integrated; |
e05d723f | 1010 | int i, j; |
1da177e4 | 1011 | |
e05d723f TG |
1012 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
1013 | if (esr_disable) { | |
1014 | apic_write(APIC_ESR, 0); | |
1015 | apic_write(APIC_ESR, 0); | |
1016 | apic_write(APIC_ESR, 0); | |
1017 | apic_write(APIC_ESR, 0); | |
1018 | } | |
1da177e4 | 1019 | |
e05d723f | 1020 | integrated = lapic_is_integrated(); |
1da177e4 | 1021 | |
e05d723f TG |
1022 | /* |
1023 | * Double-check whether this APIC is really registered. | |
1024 | */ | |
1025 | if (!apic_id_registered()) | |
22d5c67c | 1026 | WARN_ON_ONCE(1); |
1da177e4 | 1027 | |
e05d723f TG |
1028 | /* |
1029 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1030 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1031 | * document number 292116). So here it goes... | |
1032 | */ | |
1033 | init_apic_ldr(); | |
1da177e4 | 1034 | |
e05d723f TG |
1035 | /* |
1036 | * Set Task Priority to 'accept all'. We never change this | |
1037 | * later on. | |
1038 | */ | |
1039 | value = apic_read(APIC_TASKPRI); | |
1040 | value &= ~APIC_TPRI_MASK; | |
593f4a78 | 1041 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1042 | |
e05d723f TG |
1043 | /* |
1044 | * After a crash, we no longer service the interrupts and a pending | |
1045 | * interrupt from previous kernel might still have ISR bit set. | |
1046 | * | |
1047 | * Most probably by now CPU has serviced that pending interrupt and | |
1048 | * it might not have done the ack_APIC_irq() because it thought, | |
1049 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1050 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1051 | * the interrupt. Hence a vector might get locked. It was noticed | |
1052 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1053 | */ | |
1054 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1055 | value = apic_read(APIC_ISR + i*0x10); | |
1056 | for (j = 31; j >= 0; j--) { | |
1057 | if (value & (1<<j)) | |
1058 | ack_APIC_irq(); | |
1059 | } | |
1060 | } | |
1da177e4 | 1061 | |
e05d723f TG |
1062 | /* |
1063 | * Now that we are all set up, enable the APIC | |
1064 | */ | |
1065 | value = apic_read(APIC_SPIV); | |
1066 | value &= ~APIC_VECTOR_MASK; | |
1067 | /* | |
1068 | * Enable APIC | |
1069 | */ | |
1070 | value |= APIC_SPIV_APIC_ENABLED; | |
1da177e4 | 1071 | |
e05d723f TG |
1072 | /* |
1073 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1074 | * certain networking cards. If high frequency interrupts are | |
1075 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1076 | * entry is masked/unmasked at a high rate as well then sooner or | |
1077 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1078 | * from the device. If focus CPU is disabled then the hang goes | |
1079 | * away, oh well :-( | |
1080 | * | |
1081 | * [ This bug can be reproduced easily with a level-triggered | |
1082 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1083 | * BX chipset. ] | |
1084 | */ | |
1085 | /* | |
1086 | * Actually disabling the focus CPU check just makes the hang less | |
1087 | * frequent as it makes the interrupt distributon model be more | |
1088 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1089 | * See also the comment in end_level_ioapic_irq(). --macro | |
1090 | */ | |
1da177e4 | 1091 | |
e05d723f TG |
1092 | /* Enable focus processor (bit==0) */ |
1093 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1094 | |
e05d723f TG |
1095 | /* |
1096 | * Set spurious IRQ vector | |
1097 | */ | |
1098 | value |= SPURIOUS_APIC_VECTOR; | |
593f4a78 | 1099 | apic_write(APIC_SPIV, value); |
e05d723f TG |
1100 | |
1101 | /* | |
1102 | * Set up LVT0, LVT1: | |
1103 | * | |
1104 | * set up through-local-APIC on the BP's LINT0. This is not | |
27b46d76 | 1105 | * strictly necessary in pure symmetric-IO mode, but sometimes |
e05d723f TG |
1106 | * we delegate interrupts to the 8259A. |
1107 | */ | |
1108 | /* | |
1109 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1110 | */ | |
1111 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
1112 | if (!smp_processor_id() && (pic_mode || !value)) { | |
1113 | value = APIC_DM_EXTINT; | |
1114 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
1115 | smp_processor_id()); | |
1116 | } else { | |
1117 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
1118 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
1119 | smp_processor_id()); | |
1120 | } | |
593f4a78 | 1121 | apic_write(APIC_LVT0, value); |
e05d723f TG |
1122 | |
1123 | /* | |
1124 | * only the BP should see the LINT1 NMI signal, obviously. | |
1125 | */ | |
1126 | if (!smp_processor_id()) | |
1127 | value = APIC_DM_NMI; | |
1128 | else | |
1129 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
1130 | if (!integrated) /* 82489DX */ | |
1131 | value |= APIC_LVT_LEVEL_TRIGGER; | |
593f4a78 | 1132 | apic_write(APIC_LVT1, value); |
ac60aae5 | 1133 | } |
e05d723f | 1134 | |
ac60aae5 GOC |
1135 | void __cpuinit end_local_APIC_setup(void) |
1136 | { | |
1137 | unsigned long value; | |
1da177e4 | 1138 | |
ac60aae5 | 1139 | lapic_setup_esr(); |
e9e2cdb4 TG |
1140 | /* Disable the local apic timer */ |
1141 | value = apic_read(APIC_LVTT); | |
1142 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
593f4a78 | 1143 | apic_write(APIC_LVTT, value); |
e9e2cdb4 | 1144 | |
e05d723f TG |
1145 | setup_apic_nmi_watchdog(NULL); |
1146 | apic_pm_activate(); | |
1da177e4 LT |
1147 | } |
1148 | ||
e05d723f TG |
1149 | /* |
1150 | * Detect and initialize APIC | |
1151 | */ | |
e83a5fdc | 1152 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1153 | { |
1154 | u32 h, l, features; | |
1da177e4 LT |
1155 | |
1156 | /* Disabled by kernel option? */ | |
914bebfa | 1157 | if (disable_apic) |
1da177e4 LT |
1158 | return -1; |
1159 | ||
1da177e4 LT |
1160 | switch (boot_cpu_data.x86_vendor) { |
1161 | case X86_VENDOR_AMD: | |
1162 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
e05d723f | 1163 | (boot_cpu_data.x86 == 15)) |
1da177e4 LT |
1164 | break; |
1165 | goto no_apic; | |
1166 | case X86_VENDOR_INTEL: | |
1167 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1168 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1169 | break; | |
1170 | goto no_apic; | |
1171 | default: | |
1172 | goto no_apic; | |
1173 | } | |
1174 | ||
1175 | if (!cpu_has_apic) { | |
1176 | /* | |
e05d723f TG |
1177 | * Over-ride BIOS and try to enable the local APIC only if |
1178 | * "lapic" specified. | |
1da177e4 | 1179 | */ |
914bebfa | 1180 | if (!force_enable_local_apic) { |
e05d723f | 1181 | printk(KERN_INFO "Local APIC disabled by BIOS -- " |
1da177e4 LT |
1182 | "you can enable it with \"lapic\"\n"); |
1183 | return -1; | |
1184 | } | |
1185 | /* | |
e05d723f TG |
1186 | * Some BIOSes disable the local APIC in the APIC_BASE |
1187 | * MSR. This can only be done in software for Intel P6 or later | |
1188 | * and AMD K7 (Model > 1) or later. | |
1da177e4 LT |
1189 | */ |
1190 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1191 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
e05d723f TG |
1192 | printk(KERN_INFO |
1193 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1da177e4 LT |
1194 | l &= ~MSR_IA32_APICBASE_BASE; |
1195 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1196 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1197 | enabled_via_apicbase = 1; | |
1198 | } | |
1199 | } | |
1200 | /* | |
1201 | * The APIC feature bit should now be enabled | |
1202 | * in `cpuid' | |
1203 | */ | |
1204 | features = cpuid_edx(1); | |
1205 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
e05d723f | 1206 | printk(KERN_WARNING "Could not enable APIC!\n"); |
1da177e4 LT |
1207 | return -1; |
1208 | } | |
53756d37 | 1209 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1da177e4 LT |
1210 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
1211 | ||
1212 | /* The BIOS may have set up the APIC at some other address */ | |
1213 | rdmsr(MSR_IA32_APICBASE, l, h); | |
e05d723f TG |
1214 | if (l & MSR_IA32_APICBASE_ENABLE) |
1215 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1da177e4 | 1216 | |
e05d723f | 1217 | printk(KERN_INFO "Found and enabled local APIC!\n"); |
1da177e4 | 1218 | |
e05d723f | 1219 | apic_pm_activate(); |
1da177e4 | 1220 | |
e05d723f | 1221 | return 0; |
1da177e4 | 1222 | |
e05d723f TG |
1223 | no_apic: |
1224 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1225 | return -1; | |
1226 | } | |
1da177e4 | 1227 | |
e05d723f TG |
1228 | /** |
1229 | * init_apic_mappings - initialize APIC mappings | |
1230 | */ | |
1231 | void __init init_apic_mappings(void) | |
1da177e4 | 1232 | { |
1da177e4 | 1233 | /* |
e05d723f TG |
1234 | * If no local APIC can be found then set up a fake all |
1235 | * zeroes page to simulate the local APIC and another | |
1236 | * one for the IO-APIC. | |
1da177e4 | 1237 | */ |
e05d723f TG |
1238 | if (!smp_found_config && detect_init_APIC()) { |
1239 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1240 | apic_phys = __pa(apic_phys); | |
1241 | } else | |
1242 | apic_phys = mp_lapic_addr; | |
1da177e4 | 1243 | |
e05d723f TG |
1244 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
1245 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
1246 | apic_phys); | |
1da177e4 | 1247 | |
e05d723f TG |
1248 | /* |
1249 | * Fetch the APIC ID of the BSP in case we have a | |
1250 | * default configuration (or the MP table is broken). | |
1251 | */ | |
1252 | if (boot_cpu_physical_apicid == -1U) | |
4c9961d5 | 1253 | boot_cpu_physical_apicid = read_apic_id(); |
1da177e4 | 1254 | |
1da177e4 LT |
1255 | } |
1256 | ||
e05d723f TG |
1257 | /* |
1258 | * This initializes the IO-APIC and APIC hardware if this is | |
1259 | * a UP kernel. | |
1260 | */ | |
e81b2c62 AS |
1261 | |
1262 | int apic_version[MAX_APICS]; | |
1263 | ||
e83a5fdc | 1264 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1265 | { |
e05d723f TG |
1266 | if (!smp_found_config && !cpu_has_apic) |
1267 | return -1; | |
6eb0a0fd | 1268 | |
e05d723f TG |
1269 | /* |
1270 | * Complain if the BIOS pretends there is one. | |
1271 | */ | |
1272 | if (!cpu_has_apic && | |
1273 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1274 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1275 | boot_cpu_physical_apicid); | |
53756d37 | 1276 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
e05d723f | 1277 | return -1; |
6eb0a0fd | 1278 | } |
6eb0a0fd | 1279 | |
e05d723f | 1280 | verify_local_APIC(); |
6eb0a0fd | 1281 | |
e05d723f | 1282 | connect_bsp_APIC(); |
6eb0a0fd | 1283 | |
e05d723f TG |
1284 | /* |
1285 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1286 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1287 | * might be zero if read from MP tables. Get it from LAPIC. | |
1288 | */ | |
1289 | #ifdef CONFIG_CRASH_DUMP | |
4c9961d5 | 1290 | boot_cpu_physical_apicid = read_apic_id(); |
e05d723f | 1291 | #endif |
b6df1b8b | 1292 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
1da177e4 | 1293 | |
e05d723f | 1294 | setup_local_APIC(); |
1da177e4 | 1295 | |
acae7d90 MR |
1296 | #ifdef CONFIG_X86_IO_APIC |
1297 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) | |
1298 | #endif | |
1299 | localise_nmi_watchdog(); | |
ac60aae5 | 1300 | end_local_APIC_setup(); |
e05d723f TG |
1301 | #ifdef CONFIG_X86_IO_APIC |
1302 | if (smp_found_config) | |
1303 | if (!skip_ioapic_setup && nr_ioapics) | |
1304 | setup_IO_APIC(); | |
1da177e4 | 1305 | #endif |
e05d723f | 1306 | setup_boot_clock(); |
1da177e4 | 1307 | |
e05d723f | 1308 | return 0; |
1da177e4 LT |
1309 | } |
1310 | ||
e05d723f TG |
1311 | /* |
1312 | * Local APIC interrupts | |
1313 | */ | |
1314 | ||
1da177e4 LT |
1315 | /* |
1316 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1317 | */ | |
e9e2cdb4 | 1318 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1319 | { |
1320 | unsigned long v; | |
1321 | ||
1322 | irq_enter(); | |
1323 | /* | |
1324 | * Check if this really is a spurious interrupt and ACK it | |
1325 | * if it is a vectored one. Just in case... | |
1326 | * Spurious interrupts should not be ACKed. | |
1327 | */ | |
1328 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1329 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1330 | ack_APIC_irq(); | |
1331 | ||
1332 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
e05d723f TG |
1333 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " |
1334 | "should never happen.\n", smp_processor_id()); | |
38e760a1 | 1335 | __get_cpu_var(irq_stat).irq_spurious_count++; |
1da177e4 LT |
1336 | irq_exit(); |
1337 | } | |
1338 | ||
1339 | /* | |
1340 | * This interrupt should never happen with our APIC/SMP architecture | |
1341 | */ | |
e9e2cdb4 | 1342 | void smp_error_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1343 | { |
1344 | unsigned long v, v1; | |
1345 | ||
1346 | irq_enter(); | |
1347 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1348 | v = apic_read(APIC_ESR); | |
1349 | apic_write(APIC_ESR, 0); | |
1350 | v1 = apic_read(APIC_ESR); | |
1351 | ack_APIC_irq(); | |
1352 | atomic_inc(&irq_err_count); | |
1353 | ||
1354 | /* Here is what the APIC error bits mean: | |
1355 | 0: Send CS error | |
1356 | 1: Receive CS error | |
1357 | 2: Send accept error | |
1358 | 3: Receive accept error | |
1359 | 4: Reserved | |
1360 | 5: Send illegal vector | |
1361 | 6: Received illegal vector | |
1362 | 7: Illegal register address | |
1363 | */ | |
ff8a03a6 | 1364 | printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", |
e05d723f | 1365 | smp_processor_id(), v , v1); |
1da177e4 LT |
1366 | irq_exit(); |
1367 | } | |
1368 | ||
e05d723f TG |
1369 | /** |
1370 | * connect_bsp_APIC - attach the APIC to the interrupt system | |
1371 | */ | |
1372 | void __init connect_bsp_APIC(void) | |
1373 | { | |
1374 | if (pic_mode) { | |
1375 | /* | |
1376 | * Do not trust the local APIC being empty at bootup. | |
1377 | */ | |
1378 | clear_local_APIC(); | |
1379 | /* | |
1380 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1381 | * local APIC to INT and NMI lines. | |
1382 | */ | |
1383 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1384 | "enabling APIC mode.\n"); | |
1385 | outb(0x70, 0x22); | |
1386 | outb(0x01, 0x23); | |
1da177e4 | 1387 | } |
e05d723f TG |
1388 | enable_apic_mode(); |
1389 | } | |
1da177e4 | 1390 | |
e05d723f TG |
1391 | /** |
1392 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1393 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1394 | * | |
1395 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1396 | * APIC is disabled. | |
1397 | */ | |
1398 | void disconnect_bsp_APIC(int virt_wire_setup) | |
1399 | { | |
1400 | if (pic_mode) { | |
1401 | /* | |
1402 | * Put the board back into PIC mode (has an effect only on | |
1403 | * certain older boards). Note that APIC interrupts, including | |
1404 | * IPIs, won't work beyond this point! The only exception are | |
1405 | * INIT IPIs. | |
1406 | */ | |
1407 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1408 | "entering PIC mode.\n"); | |
1409 | outb(0x70, 0x22); | |
1410 | outb(0x00, 0x23); | |
1411 | } else { | |
1412 | /* Go back to Virtual Wire compatibility mode */ | |
1413 | unsigned long value; | |
1da177e4 | 1414 | |
e05d723f TG |
1415 | /* For the spurious interrupt use vector F, and enable it */ |
1416 | value = apic_read(APIC_SPIV); | |
1417 | value &= ~APIC_VECTOR_MASK; | |
1418 | value |= APIC_SPIV_APIC_ENABLED; | |
1419 | value |= 0xf; | |
593f4a78 | 1420 | apic_write(APIC_SPIV, value); |
1da177e4 | 1421 | |
e05d723f TG |
1422 | if (!virt_wire_setup) { |
1423 | /* | |
1424 | * For LVT0 make it edge triggered, active high, | |
1425 | * external and enabled | |
1426 | */ | |
1427 | value = apic_read(APIC_LVT0); | |
1428 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1429 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
ff8a03a6 | 1430 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
e05d723f TG |
1431 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
1432 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
593f4a78 | 1433 | apic_write(APIC_LVT0, value); |
e05d723f TG |
1434 | } else { |
1435 | /* Disable LVT0 */ | |
593f4a78 | 1436 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
e05d723f | 1437 | } |
1da177e4 | 1438 | |
e05d723f TG |
1439 | /* |
1440 | * For LVT1 make it edge triggered, active high, nmi and | |
1441 | * enabled | |
1442 | */ | |
1443 | value = apic_read(APIC_LVT1); | |
1444 | value &= ~( | |
1445 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
1446 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1447 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1448 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1449 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
593f4a78 | 1450 | apic_write(APIC_LVT1, value); |
e05d723f TG |
1451 | } |
1452 | } | |
1da177e4 | 1453 | |
903dcb5a AS |
1454 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
1455 | ||
1456 | void __cpuinit generic_processor_info(int apicid, int version) | |
1457 | { | |
1458 | int cpu; | |
1459 | cpumask_t tmp_map; | |
1460 | physid_mask_t phys_cpu; | |
1461 | ||
1462 | /* | |
1463 | * Validate version | |
1464 | */ | |
1465 | if (version == 0x0) { | |
1466 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1467 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1468 | version); | |
1469 | version = 0x10; | |
1470 | } | |
1471 | apic_version[apicid] = version; | |
1472 | ||
1473 | phys_cpu = apicid_to_cpu_present(apicid); | |
1474 | physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu); | |
1475 | ||
1476 | if (num_processors >= NR_CPUS) { | |
1477 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1478 | " Processor ignored.\n", NR_CPUS); | |
1479 | return; | |
1480 | } | |
1481 | ||
1482 | if (num_processors >= maxcpus) { | |
1483 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
1484 | " Processor ignored.\n", maxcpus); | |
1485 | return; | |
1486 | } | |
1487 | ||
1488 | num_processors++; | |
1489 | cpus_complement(tmp_map, cpu_present_map); | |
1490 | cpu = first_cpu(tmp_map); | |
1491 | ||
1492 | if (apicid == boot_cpu_physical_apicid) | |
1493 | /* | |
1494 | * x86_bios_cpu_apicid is required to have processors listed | |
1495 | * in same order as logical cpu numbers. Hence the first | |
1496 | * entry is BSP, and so on. | |
1497 | */ | |
1498 | cpu = 0; | |
1499 | ||
e0da3364 YL |
1500 | if (apicid > max_physical_apicid) |
1501 | max_physical_apicid = apicid; | |
1502 | ||
903dcb5a AS |
1503 | /* |
1504 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1505 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1506 | * before this can be done without some confusion. | |
1507 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1508 | * - Ashok Raj <ashok.raj@intel.com> | |
1509 | */ | |
e0da3364 | 1510 | if (max_physical_apicid >= 8) { |
903dcb5a AS |
1511 | switch (boot_cpu_data.x86_vendor) { |
1512 | case X86_VENDOR_INTEL: | |
1513 | if (!APIC_XAPIC(version)) { | |
1514 | def_to_bigsmp = 0; | |
1515 | break; | |
1516 | } | |
1517 | /* If P4 and above fall through */ | |
1518 | case X86_VENDOR_AMD: | |
1519 | def_to_bigsmp = 1; | |
1520 | } | |
1521 | } | |
1522 | #ifdef CONFIG_SMP | |
1523 | /* are we being called early in kernel startup? */ | |
23ca4bba MT |
1524 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1525 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1526 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
903dcb5a AS |
1527 | |
1528 | cpu_to_apicid[cpu] = apicid; | |
1529 | bios_cpu_apicid[cpu] = apicid; | |
1530 | } else { | |
1531 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1532 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1533 | } | |
1534 | #endif | |
1535 | cpu_set(cpu, cpu_possible_map); | |
1536 | cpu_set(cpu, cpu_present_map); | |
1537 | } | |
1538 | ||
e05d723f TG |
1539 | /* |
1540 | * Power management | |
1541 | */ | |
1542 | #ifdef CONFIG_PM | |
1543 | ||
1544 | static struct { | |
1545 | int active; | |
1546 | /* r/w apic fields */ | |
1547 | unsigned int apic_id; | |
1548 | unsigned int apic_taskpri; | |
1549 | unsigned int apic_ldr; | |
1550 | unsigned int apic_dfr; | |
1551 | unsigned int apic_spiv; | |
1552 | unsigned int apic_lvtt; | |
1553 | unsigned int apic_lvtpc; | |
1554 | unsigned int apic_lvt0; | |
1555 | unsigned int apic_lvt1; | |
1556 | unsigned int apic_lvterr; | |
1557 | unsigned int apic_tmict; | |
1558 | unsigned int apic_tdcr; | |
1559 | unsigned int apic_thmr; | |
1560 | } apic_pm_state; | |
1561 | ||
1562 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1563 | { | |
1564 | unsigned long flags; | |
1565 | int maxlvt; | |
1566 | ||
1567 | if (!apic_pm_state.active) | |
1568 | return 0; | |
1569 | ||
1570 | maxlvt = lapic_get_maxlvt(); | |
1571 | ||
1572 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
1573 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1574 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1575 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1576 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1577 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1578 | if (maxlvt >= 4) | |
1579 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1580 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1581 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1582 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1583 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1584 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1585 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1586 | if (maxlvt >= 5) | |
1587 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1da177e4 | 1588 | #endif |
1e4c85f9 | 1589 | |
e05d723f TG |
1590 | local_irq_save(flags); |
1591 | disable_local_APIC(); | |
1592 | local_irq_restore(flags); | |
1e4c85f9 | 1593 | return 0; |
1da177e4 | 1594 | } |
1a3f239d | 1595 | |
e05d723f | 1596 | static int lapic_resume(struct sys_device *dev) |
1a3f239d | 1597 | { |
e05d723f TG |
1598 | unsigned int l, h; |
1599 | unsigned long flags; | |
1600 | int maxlvt; | |
1601 | ||
1602 | if (!apic_pm_state.active) | |
1603 | return 0; | |
1604 | ||
1605 | maxlvt = lapic_get_maxlvt(); | |
1606 | ||
1607 | local_irq_save(flags); | |
1608 | ||
1609 | /* | |
1610 | * Make sure the APICBASE points to the right address | |
1611 | * | |
1612 | * FIXME! This will be wrong if we ever support suspend on | |
1613 | * SMP! We'll need to do this as part of the CPU restore! | |
1614 | */ | |
1615 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1616 | l &= ~MSR_IA32_APICBASE_BASE; | |
1617 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1618 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1619 | ||
1620 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1621 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1622 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1623 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1624 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1625 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1626 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1627 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1628 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1629 | if (maxlvt >= 5) | |
1630 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1631 | #endif | |
1632 | if (maxlvt >= 4) | |
1633 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1634 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1635 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1636 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1637 | apic_write(APIC_ESR, 0); | |
1638 | apic_read(APIC_ESR); | |
1639 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1640 | apic_write(APIC_ESR, 0); | |
1641 | apic_read(APIC_ESR); | |
1642 | local_irq_restore(flags); | |
1a3f239d RR |
1643 | return 0; |
1644 | } | |
1a3f239d | 1645 | |
e05d723f TG |
1646 | /* |
1647 | * This device has no shutdown method - fully functioning local APICs | |
1648 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1649 | */ | |
1650 | ||
1651 | static struct sysdev_class lapic_sysclass = { | |
af5ca3f4 | 1652 | .name = "lapic", |
e05d723f TG |
1653 | .resume = lapic_resume, |
1654 | .suspend = lapic_suspend, | |
1655 | }; | |
1656 | ||
1657 | static struct sys_device device_lapic = { | |
1658 | .id = 0, | |
1659 | .cls = &lapic_sysclass, | |
1660 | }; | |
1661 | ||
1662 | static void __devinit apic_pm_activate(void) | |
1a3f239d | 1663 | { |
e05d723f | 1664 | apic_pm_state.active = 1; |
1a3f239d | 1665 | } |
1a3f239d | 1666 | |
e05d723f TG |
1667 | static int __init init_lapic_sysfs(void) |
1668 | { | |
1669 | int error; | |
1670 | ||
1671 | if (!cpu_has_apic) | |
1672 | return 0; | |
1673 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
1674 | ||
1675 | error = sysdev_class_register(&lapic_sysclass); | |
1676 | if (!error) | |
1677 | error = sysdev_register(&device_lapic); | |
1678 | return error; | |
1679 | } | |
1680 | device_initcall(init_lapic_sysfs); | |
1681 | ||
1682 | #else /* CONFIG_PM */ | |
1683 | ||
1684 | static void apic_pm_activate(void) { } | |
1685 | ||
1686 | #endif /* CONFIG_PM */ | |
0e078e2f TG |
1687 | |
1688 | /* | |
1689 | * APIC command line parameters | |
1690 | */ | |
1691 | static int __init parse_lapic(char *arg) | |
1692 | { | |
914bebfa | 1693 | force_enable_local_apic = 1; |
0e078e2f TG |
1694 | return 0; |
1695 | } | |
1696 | early_param("lapic", parse_lapic); | |
1697 | ||
1698 | static int __init parse_nolapic(char *arg) | |
1699 | { | |
914bebfa | 1700 | disable_apic = 1; |
9175fc06 | 1701 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
0e078e2f TG |
1702 | return 0; |
1703 | } | |
1704 | early_param("nolapic", parse_nolapic); | |
1705 | ||
36fef094 | 1706 | static int __init parse_disable_apic_timer(char *arg) |
0e078e2f | 1707 | { |
36fef094 | 1708 | disable_apic_timer = 1; |
0e078e2f TG |
1709 | return 0; |
1710 | } | |
36fef094 CG |
1711 | early_param("noapictimer", parse_disable_apic_timer); |
1712 | ||
1713 | static int __init parse_nolapic_timer(char *arg) | |
1714 | { | |
1715 | disable_apic_timer = 1; | |
1716 | return 0; | |
1717 | } | |
1718 | early_param("nolapic_timer", parse_nolapic_timer); | |
0e078e2f TG |
1719 | |
1720 | static int __init parse_lapic_timer_c2_ok(char *arg) | |
1721 | { | |
1722 | local_apic_timer_c2_ok = 1; | |
1723 | return 0; | |
1724 | } | |
1725 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1726 | ||
48d97cb6 | 1727 | static int __init apic_set_verbosity(char *arg) |
0e078e2f | 1728 | { |
48d97cb6 RH |
1729 | if (!arg) |
1730 | return -EINVAL; | |
1731 | ||
1732 | if (strcmp(arg, "debug") == 0) | |
0e078e2f | 1733 | apic_verbosity = APIC_DEBUG; |
48d97cb6 | 1734 | else if (strcmp(arg, "verbose") == 0) |
0e078e2f | 1735 | apic_verbosity = APIC_VERBOSE; |
48d97cb6 | 1736 | |
fb6bef80 | 1737 | return 0; |
0e078e2f | 1738 | } |
fb6bef80 | 1739 | early_param("apic", apic_set_verbosity); |
0e078e2f | 1740 | |
746f2eb7 CG |
1741 | static int __init lapic_insert_resource(void) |
1742 | { | |
1743 | if (!apic_phys) | |
1744 | return -1; | |
1745 | ||
1746 | /* Put local APIC into the resource map. */ | |
1747 | lapic_resource.start = apic_phys; | |
1748 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1749 | insert_resource(&iomem_resource, &lapic_resource); | |
1750 | ||
1751 | return 0; | |
1752 | } | |
1753 | ||
1754 | /* | |
1755 | * need call insert after e820_reserve_resources() | |
1756 | * that is using request_resource | |
1757 | */ | |
1758 | late_initcall(lapic_insert_resource); |