Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
f3705136 | 26 | #include <linux/cpu.h> |
e9e2cdb4 | 27 | #include <linux/clockchips.h> |
d36b49b9 | 28 | #include <linux/acpi_pmtmr.h> |
6eb0a0fd | 29 | #include <linux/module.h> |
ad62ca2b | 30 | #include <linux/dmi.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/arch_hooks.h> | |
38 | #include <asm/hpet.h> | |
306e440d | 39 | #include <asm/i8253.h> |
3e4ff115 | 40 | #include <asm/nmi.h> |
1da177e4 LT |
41 | |
42 | #include <mach_apic.h> | |
382dbd07 | 43 | #include <mach_apicdef.h> |
6eb0a0fd | 44 | #include <mach_ipi.h> |
1da177e4 | 45 | |
e05d723f TG |
46 | /* |
47 | * Sanity check | |
48 | */ | |
ff8a03a6 | 49 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) |
e05d723f TG |
50 | # error SPURIOUS_APIC_VECTOR definition error |
51 | #endif | |
52 | ||
8f6e2ca9 AS |
53 | unsigned long mp_lapic_addr; |
54 | ||
9635b47d EB |
55 | /* |
56 | * Knob to control our willingness to enable the local APIC. | |
e05d723f | 57 | * |
914bebfa | 58 | * +1=force-enable |
9635b47d | 59 | */ |
914bebfa YL |
60 | static int force_enable_local_apic; |
61 | int disable_apic; | |
9635b47d | 62 | |
d36b49b9 TG |
63 | /* Local APIC timer verification ok */ |
64 | static int local_apic_timer_verify_ok; | |
aa276e1c TG |
65 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
66 | static int local_apic_timer_disabled; | |
e585bef8 TG |
67 | /* Local APIC timer works in C2 */ |
68 | int local_apic_timer_c2_ok; | |
69 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
e9e2cdb4 | 70 | |
ce178331 AM |
71 | int first_system_vector = 0xfe; |
72 | ||
73 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
74 | ||
1da177e4 | 75 | /* |
e05d723f | 76 | * Debug level, exported for io_apic.c |
1da177e4 LT |
77 | */ |
78 | int apic_verbosity; | |
79 | ||
f3918352 AS |
80 | int pic_mode; |
81 | ||
bab4b27c AS |
82 | /* Have we found an MP table */ |
83 | int smp_found_config; | |
84 | ||
746f2eb7 CG |
85 | static struct resource lapic_resource = { |
86 | .name = "Local APIC", | |
87 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
88 | }; | |
89 | ||
e9e2cdb4 | 90 | static unsigned int calibration_result; |
1da177e4 | 91 | |
e9e2cdb4 TG |
92 | static int lapic_next_event(unsigned long delta, |
93 | struct clock_event_device *evt); | |
94 | static void lapic_timer_setup(enum clock_event_mode mode, | |
95 | struct clock_event_device *evt); | |
96 | static void lapic_timer_broadcast(cpumask_t mask); | |
97 | static void apic_pm_activate(void); | |
e05d723f | 98 | |
e9e2cdb4 TG |
99 | /* |
100 | * The local apic timer can be used for any function which is CPU local. | |
101 | */ | |
102 | static struct clock_event_device lapic_clockevent = { | |
103 | .name = "lapic", | |
104 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
d36b49b9 | 105 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
e9e2cdb4 TG |
106 | .shift = 32, |
107 | .set_mode = lapic_timer_setup, | |
108 | .set_next_event = lapic_next_event, | |
109 | .broadcast = lapic_timer_broadcast, | |
110 | .rating = 100, | |
111 | .irq = -1, | |
112 | }; | |
113 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
e05d723f TG |
114 | |
115 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ | |
116 | static int enabled_via_apicbase; | |
117 | ||
d3432896 AK |
118 | static unsigned long apic_phys; |
119 | ||
e05d723f TG |
120 | /* |
121 | * Get the LAPIC version | |
122 | */ | |
123 | static inline int lapic_get_version(void) | |
95d769aa | 124 | { |
e05d723f | 125 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
95d769aa AK |
126 | } |
127 | ||
1da177e4 | 128 | /* |
ab4a574e | 129 | * Check, if the APIC is integrated or a separate chip |
1da177e4 | 130 | */ |
e05d723f | 131 | static inline int lapic_is_integrated(void) |
1da177e4 | 132 | { |
e05d723f | 133 | return APIC_INTEGRATED(lapic_get_version()); |
1da177e4 LT |
134 | } |
135 | ||
e05d723f TG |
136 | /* |
137 | * Check, whether this is a modern or a first generation APIC | |
138 | */ | |
139 | static int modern_apic(void) | |
1da177e4 | 140 | { |
e05d723f TG |
141 | /* AMD systems use old APIC versions, so check the CPU */ |
142 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
143 | boot_cpu_data.x86 >= 0xf) | |
144 | return 1; | |
145 | return lapic_get_version() >= 0x14; | |
1da177e4 LT |
146 | } |
147 | ||
c535b6a1 | 148 | void xapic_wait_icr_idle(void) |
f2b218dd FLV |
149 | { |
150 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
151 | cpu_relax(); | |
152 | } | |
153 | ||
c535b6a1 | 154 | u32 safe_xapic_wait_icr_idle(void) |
f2b218dd | 155 | { |
42e0a9aa | 156 | u32 send_status; |
f2b218dd FLV |
157 | int timeout; |
158 | ||
159 | timeout = 0; | |
160 | do { | |
161 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
162 | if (!send_status) | |
163 | break; | |
164 | udelay(100); | |
165 | } while (timeout++ < 1000); | |
166 | ||
167 | return send_status; | |
168 | } | |
169 | ||
c535b6a1 YL |
170 | void xapic_icr_write(u32 low, u32 id) |
171 | { | |
172 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(id)); | |
173 | apic_write_around(APIC_ICR, low); | |
174 | } | |
175 | ||
176 | u64 xapic_icr_read(void) | |
177 | { | |
178 | u32 icr1, icr2; | |
179 | ||
180 | icr2 = apic_read(APIC_ICR2); | |
181 | icr1 = apic_read(APIC_ICR); | |
182 | ||
183 | return icr1 | ((u64)icr2 << 32); | |
184 | } | |
185 | ||
186 | static struct apic_ops xapic_ops = { | |
187 | .read = native_apic_mem_read, | |
188 | .write = native_apic_mem_write, | |
189 | .write_atomic = native_apic_mem_write_atomic, | |
190 | .icr_read = xapic_icr_read, | |
191 | .icr_write = xapic_icr_write, | |
192 | .wait_icr_idle = xapic_wait_icr_idle, | |
193 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
194 | }; | |
195 | ||
196 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
197 | EXPORT_SYMBOL_GPL(apic_ops); | |
198 | ||
e05d723f TG |
199 | /** |
200 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
201 | */ | |
e9427101 | 202 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 203 | { |
e05d723f | 204 | unsigned int v = APIC_DM_NMI; |
1da177e4 | 205 | |
e05d723f TG |
206 | /* Level triggered for 82489DX */ |
207 | if (!lapic_is_integrated()) | |
1da177e4 LT |
208 | v |= APIC_LVT_LEVEL_TRIGGER; |
209 | apic_write_around(APIC_LVT0, v); | |
210 | } | |
211 | ||
e05d723f TG |
212 | /** |
213 | * get_physical_broadcast - Get number of physical broadcast IDs | |
214 | */ | |
1da177e4 LT |
215 | int get_physical_broadcast(void) |
216 | { | |
e05d723f | 217 | return modern_apic() ? 0xff : 0xf; |
1da177e4 LT |
218 | } |
219 | ||
e05d723f TG |
220 | /** |
221 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
222 | */ | |
223 | int lapic_get_maxlvt(void) | |
1da177e4 | 224 | { |
e05d723f | 225 | unsigned int v = apic_read(APIC_LVR); |
1da177e4 | 226 | |
1da177e4 | 227 | /* 82489DXs do not report # of LVT entries. */ |
e05d723f | 228 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
1da177e4 LT |
229 | } |
230 | ||
e05d723f TG |
231 | /* |
232 | * Local APIC timer | |
233 | */ | |
234 | ||
d36b49b9 TG |
235 | /* Clock divisor is set to 16 */ |
236 | #define APIC_DIVISOR 16 | |
e05d723f TG |
237 | |
238 | /* | |
239 | * This function sets up the local APIC timer, with a timeout of | |
240 | * 'clocks' APIC bus clock. During calibration we actually call | |
241 | * this function twice on the boot CPU, once with a bogus timeout | |
242 | * value, second time for real. The other (noncalibrating) CPUs | |
243 | * call this function only once, with the real, calibrated value. | |
244 | * | |
245 | * We do reads before writes even if unnecessary, to get around the | |
246 | * P5 APIC double write bug. | |
247 | */ | |
e9e2cdb4 | 248 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 249 | { |
e05d723f | 250 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 251 | |
e9e2cdb4 TG |
252 | lvtt_value = LOCAL_TIMER_VECTOR; |
253 | if (!oneshot) | |
254 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
e05d723f TG |
255 | if (!lapic_is_integrated()) |
256 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
257 | ||
e9e2cdb4 | 258 | if (!irqen) |
e05d723f TG |
259 | lvtt_value |= APIC_LVT_MASKED; |
260 | ||
261 | apic_write_around(APIC_LVTT, lvtt_value); | |
1da177e4 LT |
262 | |
263 | /* | |
e05d723f | 264 | * Divide PICLK by 16 |
1da177e4 | 265 | */ |
e05d723f TG |
266 | tmp_value = apic_read(APIC_TDCR); |
267 | apic_write_around(APIC_TDCR, (tmp_value | |
268 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
269 | | APIC_TDR_DIV_16); | |
1da177e4 | 270 | |
e9e2cdb4 TG |
271 | if (!oneshot) |
272 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); | |
273 | } | |
274 | ||
275 | /* | |
276 | * Program the next event, relative to now | |
277 | */ | |
278 | static int lapic_next_event(unsigned long delta, | |
279 | struct clock_event_device *evt) | |
280 | { | |
281 | apic_write_around(APIC_TMICT, delta); | |
282 | return 0; | |
1da177e4 LT |
283 | } |
284 | ||
e9e2cdb4 TG |
285 | /* |
286 | * Setup the lapic timer in periodic or oneshot mode | |
287 | */ | |
288 | static void lapic_timer_setup(enum clock_event_mode mode, | |
289 | struct clock_event_device *evt) | |
1da177e4 | 290 | { |
e05d723f | 291 | unsigned long flags; |
e9e2cdb4 | 292 | unsigned int v; |
e05d723f | 293 | |
d36b49b9 TG |
294 | /* Lapic used for broadcast ? */ |
295 | if (!local_apic_timer_verify_ok) | |
296 | return; | |
297 | ||
e05d723f | 298 | local_irq_save(flags); |
1da177e4 | 299 | |
e9e2cdb4 TG |
300 | switch (mode) { |
301 | case CLOCK_EVT_MODE_PERIODIC: | |
302 | case CLOCK_EVT_MODE_ONESHOT: | |
303 | __setup_APIC_LVTT(calibration_result, | |
304 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
305 | break; | |
306 | case CLOCK_EVT_MODE_UNUSED: | |
307 | case CLOCK_EVT_MODE_SHUTDOWN: | |
308 | v = apic_read(APIC_LVTT); | |
309 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
310 | apic_write_around(APIC_LVTT, v); | |
311 | break; | |
18de5bc4 TG |
312 | case CLOCK_EVT_MODE_RESUME: |
313 | /* Nothing to do here */ | |
314 | break; | |
e9e2cdb4 | 315 | } |
e05d723f TG |
316 | |
317 | local_irq_restore(flags); | |
318 | } | |
319 | ||
e9e2cdb4 TG |
320 | /* |
321 | * Local APIC timer broadcast function | |
322 | */ | |
323 | static void lapic_timer_broadcast(cpumask_t mask) | |
324 | { | |
325 | #ifdef CONFIG_SMP | |
326 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
327 | #endif | |
328 | } | |
329 | ||
330 | /* | |
331 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
332 | * of the boot CPU and register the clock event in the framework. | |
333 | */ | |
334 | static void __devinit setup_APIC_timer(void) | |
335 | { | |
336 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
337 | ||
338 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); | |
339 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
340 | ||
341 | clockevents_register_device(levt); | |
342 | } | |
343 | ||
e05d723f | 344 | /* |
d36b49b9 TG |
345 | * In this functions we calibrate APIC bus clocks to the external timer. |
346 | * | |
347 | * We want to do the calibration only once since we want to have local timer | |
348 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
349 | * frequency. | |
350 | * | |
351 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
352 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
353 | * readout is broken, so it never gets out of the wait loop again. This was | |
354 | * also reported by others. | |
e05d723f | 355 | * |
d36b49b9 TG |
356 | * Monitoring the jiffies value is inaccurate and the clockevents |
357 | * infrastructure allows us to do a simple substitution of the interrupt | |
358 | * handler. | |
e9e2cdb4 | 359 | * |
d36b49b9 TG |
360 | * The calibration routine also uses the pm_timer when possible, as the PIT |
361 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
362 | * back to normal later in the boot process). | |
e05d723f TG |
363 | */ |
364 | ||
d36b49b9 | 365 | #define LAPIC_CAL_LOOPS (HZ/10) |
e05d723f | 366 | |
f5352fd0 | 367 | static __initdata int lapic_cal_loops = -1; |
d36b49b9 TG |
368 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
369 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
370 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
371 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
1da177e4 | 372 | |
d36b49b9 TG |
373 | /* |
374 | * Temporary interrupt handler. | |
375 | */ | |
376 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
377 | { | |
378 | unsigned long long tsc = 0; | |
379 | long tapic = apic_read(APIC_TMCCT); | |
380 | unsigned long pm = acpi_pm_read_early(); | |
1da177e4 | 381 | |
d36b49b9 TG |
382 | if (cpu_has_tsc) |
383 | rdtscll(tsc); | |
384 | ||
385 | switch (lapic_cal_loops++) { | |
386 | case 0: | |
387 | lapic_cal_t1 = tapic; | |
388 | lapic_cal_tsc1 = tsc; | |
389 | lapic_cal_pm1 = pm; | |
390 | lapic_cal_j1 = jiffies; | |
391 | break; | |
e05d723f | 392 | |
d36b49b9 TG |
393 | case LAPIC_CAL_LOOPS: |
394 | lapic_cal_t2 = tapic; | |
395 | lapic_cal_tsc2 = tsc; | |
396 | if (pm < lapic_cal_pm1) | |
397 | pm += ACPI_PM_OVRRUN; | |
398 | lapic_cal_pm2 = pm; | |
399 | lapic_cal_j2 = jiffies; | |
400 | break; | |
401 | } | |
402 | } | |
1da177e4 | 403 | |
d36b49b9 TG |
404 | /* |
405 | * Setup the boot APIC | |
406 | * | |
407 | * Calibrate and verify the result. | |
408 | */ | |
409 | void __init setup_boot_APIC_clock(void) | |
410 | { | |
411 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
412 | const long pm_100ms = PMTMR_TICKS_PER_SEC/10; | |
413 | const long pm_thresh = pm_100ms/100; | |
414 | void (*real_handler)(struct clock_event_device *dev); | |
415 | unsigned long deltaj; | |
416 | long delta, deltapm; | |
ca1b940c | 417 | int pm_referenced = 0; |
1da177e4 | 418 | |
ad62ca2b TG |
419 | /* |
420 | * The local apic timer can be disabled via the kernel | |
d3f7eae1 | 421 | * commandline or from the CPU detection code. Register the lapic |
ad62ca2b TG |
422 | * timer as a dummy clock event source on SMP systems, so the |
423 | * broadcast mechanism is used. On UP systems simply ignore it. | |
424 | */ | |
425 | if (local_apic_timer_disabled) { | |
426 | /* No broadcast on UP ! */ | |
9d09951d TG |
427 | if (num_possible_cpus() > 1) { |
428 | lapic_clockevent.mult = 1; | |
ad62ca2b | 429 | setup_APIC_timer(); |
9d09951d | 430 | } |
ad62ca2b TG |
431 | return; |
432 | } | |
433 | ||
d36b49b9 TG |
434 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
435 | "calibrating APIC timer ...\n"); | |
1da177e4 | 436 | |
d36b49b9 TG |
437 | local_irq_disable(); |
438 | ||
439 | /* Replace the global interrupt handler */ | |
440 | real_handler = global_clock_event->event_handler; | |
441 | global_clock_event->event_handler = lapic_cal_handler; | |
1da177e4 | 442 | |
1da177e4 | 443 | /* |
d36b49b9 TG |
444 | * Setup the APIC counter to 1e9. There is no way the lapic |
445 | * can underflow in the 100ms detection time frame | |
1da177e4 | 446 | */ |
d36b49b9 | 447 | __setup_APIC_LVTT(1000000000, 0, 0); |
1da177e4 | 448 | |
d36b49b9 TG |
449 | /* Let the interrupts run */ |
450 | local_irq_enable(); | |
451 | ||
ca1b940c TG |
452 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
453 | cpu_relax(); | |
d36b49b9 TG |
454 | |
455 | local_irq_disable(); | |
456 | ||
457 | /* Restore the real event handler */ | |
458 | global_clock_event->event_handler = real_handler; | |
459 | ||
460 | /* Build delta t1-t2 as apic timer counts down */ | |
461 | delta = lapic_cal_t1 - lapic_cal_t2; | |
462 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
463 | ||
464 | /* Check, if the PM timer is available */ | |
465 | deltapm = lapic_cal_pm2 - lapic_cal_pm1; | |
466 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
467 | ||
468 | if (deltapm) { | |
469 | unsigned long mult; | |
470 | u64 res; | |
471 | ||
472 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
473 | ||
474 | if (deltapm > (pm_100ms - pm_thresh) && | |
475 | deltapm < (pm_100ms + pm_thresh)) { | |
476 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
477 | } else { | |
478 | res = (((u64) deltapm) * mult) >> 22; | |
479 | do_div(res, 1000000); | |
480 | printk(KERN_WARNING "APIC calibration not consistent " | |
481 | "with PM Timer: %ldms instead of 100ms\n", | |
482 | (long)res); | |
483 | /* Correct the lapic counter value */ | |
ff8a03a6 | 484 | res = (((u64) delta) * pm_100ms); |
d36b49b9 TG |
485 | do_div(res, deltapm); |
486 | printk(KERN_INFO "APIC delta adjusted to PM-Timer: " | |
487 | "%lu (%ld)\n", (unsigned long) res, delta); | |
488 | delta = (long) res; | |
489 | } | |
ca1b940c | 490 | pm_referenced = 1; |
d36b49b9 | 491 | } |
e05d723f | 492 | |
e9e2cdb4 | 493 | /* Calculate the scaled math multiplication factor */ |
877084fb AM |
494 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, |
495 | lapic_clockevent.shift); | |
e9e2cdb4 TG |
496 | lapic_clockevent.max_delta_ns = |
497 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
498 | lapic_clockevent.min_delta_ns = | |
499 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
500 | ||
d36b49b9 TG |
501 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
502 | ||
503 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
e9e2cdb4 | 504 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); |
d36b49b9 TG |
505 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
506 | calibration_result); | |
e9e2cdb4 | 507 | |
d36b49b9 TG |
508 | if (cpu_has_tsc) { |
509 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
e05d723f | 510 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
d36b49b9 TG |
511 | "%ld.%04ld MHz.\n", |
512 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
513 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
514 | } | |
e05d723f TG |
515 | |
516 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
d36b49b9 TG |
517 | "%u.%04u MHz.\n", |
518 | calibration_result / (1000000 / HZ), | |
519 | calibration_result % (1000000 / HZ)); | |
e05d723f | 520 | |
d36b49b9 | 521 | local_apic_timer_verify_ok = 1; |
d36b49b9 | 522 | |
c2b84b30 TG |
523 | /* |
524 | * Do a sanity check on the APIC calibration result | |
525 | */ | |
526 | if (calibration_result < (1000000 / HZ)) { | |
527 | local_irq_enable(); | |
528 | printk(KERN_WARNING | |
529 | "APIC frequency too slow, disabling apic timer\n"); | |
530 | /* No broadcast on UP ! */ | |
531 | if (num_possible_cpus() > 1) | |
532 | setup_APIC_timer(); | |
533 | return; | |
534 | } | |
535 | ||
ca1b940c TG |
536 | /* We trust the pm timer based calibration */ |
537 | if (!pm_referenced) { | |
538 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
d36b49b9 | 539 | |
ca1b940c TG |
540 | /* |
541 | * Setup the apic timer manually | |
542 | */ | |
543 | levt->event_handler = lapic_cal_handler; | |
544 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
545 | lapic_cal_loops = -1; | |
d36b49b9 | 546 | |
ca1b940c TG |
547 | /* Let the interrupts run */ |
548 | local_irq_enable(); | |
d36b49b9 | 549 | |
f5352fd0 | 550 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
ca1b940c | 551 | cpu_relax(); |
d36b49b9 | 552 | |
ca1b940c | 553 | local_irq_disable(); |
d36b49b9 | 554 | |
ca1b940c TG |
555 | /* Stop the lapic timer */ |
556 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
d36b49b9 | 557 | |
ca1b940c | 558 | local_irq_enable(); |
d36b49b9 | 559 | |
ca1b940c TG |
560 | /* Jiffies delta */ |
561 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
562 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
d36b49b9 | 563 | |
d36b49b9 | 564 | /* Check, if the jiffies result is consistent */ |
ca1b940c | 565 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
d36b49b9 | 566 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
ca1b940c TG |
567 | else |
568 | local_apic_timer_verify_ok = 0; | |
4edc5db8 IM |
569 | } else |
570 | local_irq_enable(); | |
e05d723f | 571 | |
d36b49b9 TG |
572 | if (!local_apic_timer_verify_ok) { |
573 | printk(KERN_WARNING | |
574 | "APIC timer disabled due to verification failure.\n"); | |
575 | /* No broadcast on UP ! */ | |
576 | if (num_possible_cpus() == 1) | |
577 | return; | |
a5f5e43e TG |
578 | } else { |
579 | /* | |
580 | * If nmi_watchdog is set to IO_APIC, we need the | |
581 | * PIT/HPET going. Otherwise register lapic as a dummy | |
582 | * device. | |
583 | */ | |
584 | if (nmi_watchdog != NMI_IO_APIC) | |
585 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
820de5c3 IM |
586 | else |
587 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 588 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
a5f5e43e | 589 | } |
d36b49b9 TG |
590 | |
591 | /* Setup the lapic or request the broadcast */ | |
592 | setup_APIC_timer(); | |
e05d723f | 593 | } |
1da177e4 | 594 | |
e05d723f TG |
595 | void __devinit setup_secondary_APIC_clock(void) |
596 | { | |
e9e2cdb4 | 597 | setup_APIC_timer(); |
e05d723f | 598 | } |
1da177e4 | 599 | |
e05d723f | 600 | /* |
e9e2cdb4 | 601 | * The guts of the apic timer interrupt |
e05d723f | 602 | */ |
e9e2cdb4 | 603 | static void local_apic_timer_interrupt(void) |
e05d723f | 604 | { |
e9e2cdb4 TG |
605 | int cpu = smp_processor_id(); |
606 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
1da177e4 LT |
607 | |
608 | /* | |
d36b49b9 TG |
609 | * Normally we should not be here till LAPIC has been initialized but |
610 | * in some cases like kdump, its possible that there is a pending LAPIC | |
611 | * timer interrupt from previous kernel's context and is delivered in | |
612 | * new kernel the moment interrupts are enabled. | |
e05d723f | 613 | * |
d36b49b9 TG |
614 | * Interrupts are enabled early and LAPIC is setup much later, hence |
615 | * its possible that when we get here evt->event_handler is NULL. | |
616 | * Check for event_handler being NULL and discard the interrupt as | |
617 | * spurious. | |
1da177e4 | 618 | */ |
e9e2cdb4 TG |
619 | if (!evt->event_handler) { |
620 | printk(KERN_WARNING | |
621 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
622 | /* Switch it off */ | |
623 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
624 | return; | |
625 | } | |
626 | ||
0e078e2f TG |
627 | /* |
628 | * the NMI deadlock-detector uses this. | |
629 | */ | |
e9e2cdb4 TG |
630 | per_cpu(irq_stat, cpu).apic_timer_irqs++; |
631 | ||
632 | evt->event_handler(evt); | |
e05d723f TG |
633 | } |
634 | ||
635 | /* | |
636 | * Local APIC timer interrupt. This is the most natural way for doing | |
637 | * local interrupts, but local timer interrupts can be emulated by | |
638 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
639 | * | |
640 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
641 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
642 | */ | |
75604d7f | 643 | void smp_apic_timer_interrupt(struct pt_regs *regs) |
e05d723f TG |
644 | { |
645 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1da177e4 LT |
646 | |
647 | /* | |
e05d723f TG |
648 | * NOTE! We'd better ACK the irq immediately, |
649 | * because timer handling can be slow. | |
1da177e4 | 650 | */ |
e05d723f | 651 | ack_APIC_irq(); |
1a75a3f0 | 652 | /* |
e05d723f TG |
653 | * update_process_times() expects us to have done irq_enter(). |
654 | * Besides, if we don't timer interrupts ignore the global | |
655 | * interrupt lock, which is the WrongThing (tm) to do. | |
1a75a3f0 | 656 | */ |
e05d723f | 657 | irq_enter(); |
e9e2cdb4 | 658 | local_apic_timer_interrupt(); |
e05d723f | 659 | irq_exit(); |
1a75a3f0 | 660 | |
e9e2cdb4 | 661 | set_irq_regs(old_regs); |
e05d723f TG |
662 | } |
663 | ||
664 | int setup_profiling_timer(unsigned int multiplier) | |
665 | { | |
666 | return -EINVAL; | |
667 | } | |
668 | ||
e319e765 RR |
669 | /* |
670 | * Setup extended LVT, AMD specific (K8, family 10h) | |
671 | * | |
672 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
673 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
674 | */ | |
675 | ||
676 | #define APIC_EILVT_LVTOFF_MCE 0 | |
677 | #define APIC_EILVT_LVTOFF_IBS 1 | |
678 | ||
679 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
680 | { | |
681 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; | |
682 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; | |
683 | apic_write(reg, v); | |
684 | } | |
685 | ||
686 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) | |
687 | { | |
688 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
689 | return APIC_EILVT_LVTOFF_MCE; | |
690 | } | |
691 | ||
692 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
693 | { | |
694 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
695 | return APIC_EILVT_LVTOFF_IBS; | |
696 | } | |
697 | ||
e05d723f TG |
698 | /* |
699 | * Local APIC start and shutdown | |
700 | */ | |
701 | ||
702 | /** | |
703 | * clear_local_APIC - shutdown the local APIC | |
704 | * | |
705 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
706 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
707 | * leftovers during boot. | |
708 | */ | |
709 | void clear_local_APIC(void) | |
710 | { | |
d3432896 | 711 | int maxlvt; |
0e078e2f | 712 | u32 v; |
1da177e4 | 713 | |
d3432896 AK |
714 | /* APIC hasn't been mapped yet */ |
715 | if (!apic_phys) | |
716 | return; | |
717 | ||
718 | maxlvt = lapic_get_maxlvt(); | |
1da177e4 | 719 | /* |
e05d723f TG |
720 | * Masking an LVT entry can trigger a local APIC error |
721 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1da177e4 | 722 | */ |
e05d723f TG |
723 | if (maxlvt >= 3) { |
724 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
725 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); | |
726 | } | |
1da177e4 | 727 | /* |
e05d723f TG |
728 | * Careful: we have to set masks only first to deassert |
729 | * any level-triggered sources. | |
1da177e4 | 730 | */ |
e05d723f TG |
731 | v = apic_read(APIC_LVTT); |
732 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
733 | v = apic_read(APIC_LVT0); | |
734 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
735 | v = apic_read(APIC_LVT1); | |
736 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); | |
737 | if (maxlvt >= 4) { | |
738 | v = apic_read(APIC_LVTPC); | |
739 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1da177e4 | 740 | } |
1da177e4 | 741 | |
e05d723f TG |
742 | /* lets not touch this if we didn't frob it */ |
743 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
744 | if (maxlvt >= 5) { | |
745 | v = apic_read(APIC_LVTTHMR); | |
746 | apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
747 | } | |
748 | #endif | |
1da177e4 | 749 | /* |
e05d723f | 750 | * Clean APIC state for other OSs: |
1da177e4 | 751 | */ |
e05d723f TG |
752 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); |
753 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
754 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); | |
755 | if (maxlvt >= 3) | |
756 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); | |
757 | if (maxlvt >= 4) | |
758 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); | |
1da177e4 | 759 | |
e05d723f TG |
760 | #ifdef CONFIG_X86_MCE_P4THERMAL |
761 | if (maxlvt >= 5) | |
762 | apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); | |
763 | #endif | |
764 | /* Integrated APIC (!82489DX) ? */ | |
765 | if (lapic_is_integrated()) { | |
1da177e4 | 766 | if (maxlvt > 3) |
e05d723f | 767 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
1da177e4 | 768 | apic_write(APIC_ESR, 0); |
e05d723f | 769 | apic_read(APIC_ESR); |
1da177e4 | 770 | } |
e05d723f | 771 | } |
1da177e4 | 772 | |
e05d723f TG |
773 | /** |
774 | * disable_local_APIC - clear and disable the local APIC | |
775 | */ | |
776 | void disable_local_APIC(void) | |
777 | { | |
778 | unsigned long value; | |
779 | ||
780 | clear_local_APIC(); | |
781 | ||
782 | /* | |
783 | * Disable APIC (implies clearing of registers | |
784 | * for 82489DX!). | |
785 | */ | |
786 | value = apic_read(APIC_SPIV); | |
787 | value &= ~APIC_SPIV_APIC_ENABLED; | |
788 | apic_write_around(APIC_SPIV, value); | |
789 | ||
790 | /* | |
791 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
792 | * restore the disabled state. | |
793 | */ | |
794 | if (enabled_via_apicbase) { | |
795 | unsigned int l, h; | |
796 | ||
797 | rdmsr(MSR_IA32_APICBASE, l, h); | |
798 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
799 | wrmsr(MSR_IA32_APICBASE, l, h); | |
800 | } | |
1da177e4 LT |
801 | } |
802 | ||
803 | /* | |
e05d723f TG |
804 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
805 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
806 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
77f72b19 | 807 | * for the case where Linux didn't enable the LAPIC. |
1da177e4 LT |
808 | */ |
809 | void lapic_shutdown(void) | |
810 | { | |
67963132 MS |
811 | unsigned long flags; |
812 | ||
77f72b19 | 813 | if (!cpu_has_apic) |
1da177e4 LT |
814 | return; |
815 | ||
67963132 | 816 | local_irq_save(flags); |
77f72b19 ZM |
817 | clear_local_APIC(); |
818 | ||
819 | if (enabled_via_apicbase) | |
820 | disable_local_APIC(); | |
821 | ||
67963132 | 822 | local_irq_restore(flags); |
1da177e4 LT |
823 | } |
824 | ||
e05d723f TG |
825 | /* |
826 | * This is to verify that we're looking at a real local APIC. | |
827 | * Check these against your board if the CPUs aren't getting | |
828 | * started for no apparent reason. | |
829 | */ | |
830 | int __init verify_local_APIC(void) | |
1da177e4 | 831 | { |
e05d723f | 832 | unsigned int reg0, reg1; |
1da177e4 | 833 | |
e05d723f TG |
834 | /* |
835 | * The version register is read-only in a real APIC. | |
836 | */ | |
837 | reg0 = apic_read(APIC_LVR); | |
838 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
839 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
840 | reg1 = apic_read(APIC_LVR); | |
841 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
842 | ||
843 | /* | |
844 | * The two version reads above should print the same | |
845 | * numbers. If the second one is different, then we | |
846 | * poke at a non-APIC. | |
847 | */ | |
848 | if (reg1 != reg0) | |
1da177e4 LT |
849 | return 0; |
850 | ||
e05d723f TG |
851 | /* |
852 | * Check if the version looks reasonably. | |
853 | */ | |
854 | reg1 = GET_APIC_VERSION(reg0); | |
855 | if (reg1 == 0x00 || reg1 == 0xff) | |
856 | return 0; | |
857 | reg1 = lapic_get_maxlvt(); | |
858 | if (reg1 < 0x02 || reg1 == 0xff) | |
859 | return 0; | |
f990fff4 | 860 | |
e05d723f TG |
861 | /* |
862 | * The ID register is read/write in a real APIC. | |
863 | */ | |
864 | reg0 = apic_read(APIC_ID); | |
865 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
866 | ||
867 | /* | |
868 | * The next two are just to see if we have sane values. | |
869 | * They're only really relevant if we're in Virtual Wire | |
870 | * compatibility mode, but most boxes are anymore. | |
871 | */ | |
872 | reg0 = apic_read(APIC_LVT0); | |
873 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
874 | reg1 = apic_read(APIC_LVT1); | |
875 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
876 | ||
877 | return 1; | |
1da177e4 LT |
878 | } |
879 | ||
e05d723f TG |
880 | /** |
881 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
882 | */ | |
883 | void __init sync_Arb_IDs(void) | |
1da177e4 | 884 | { |
e05d723f TG |
885 | /* |
886 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
887 | * needed on AMD. | |
888 | */ | |
f44d9efd | 889 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
e05d723f TG |
890 | return; |
891 | /* | |
892 | * Wait for idle. | |
893 | */ | |
894 | apic_wait_icr_idle(); | |
1da177e4 | 895 | |
e05d723f TG |
896 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
897 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | |
898 | | APIC_DM_INIT); | |
899 | } | |
1da177e4 | 900 | |
e05d723f TG |
901 | /* |
902 | * An initial setup of the virtual wire mode. | |
903 | */ | |
904 | void __init init_bsp_APIC(void) | |
905 | { | |
906 | unsigned long value; | |
f990fff4 | 907 | |
e05d723f TG |
908 | /* |
909 | * Don't do the setup now if we have a SMP BIOS as the | |
910 | * through-I/O-APIC virtual wire mode might be active. | |
911 | */ | |
912 | if (smp_found_config || !cpu_has_apic) | |
913 | return; | |
1da177e4 LT |
914 | |
915 | /* | |
e05d723f | 916 | * Do not trust the local APIC being empty at bootup. |
1da177e4 | 917 | */ |
e05d723f | 918 | clear_local_APIC(); |
1da177e4 | 919 | |
e05d723f TG |
920 | /* |
921 | * Enable APIC. | |
922 | */ | |
923 | value = apic_read(APIC_SPIV); | |
924 | value &= ~APIC_VECTOR_MASK; | |
925 | value |= APIC_SPIV_APIC_ENABLED; | |
926 | ||
927 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
928 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
929 | (boot_cpu_data.x86 == 15)) | |
930 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
931 | else | |
932 | value |= APIC_SPIV_FOCUS_DISABLED; | |
933 | value |= SPURIOUS_APIC_VECTOR; | |
934 | apic_write_around(APIC_SPIV, value); | |
935 | ||
936 | /* | |
937 | * Set up the virtual wire mode. | |
938 | */ | |
939 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
940 | value = APIC_DM_NMI; | |
941 | if (!lapic_is_integrated()) /* 82489DX */ | |
942 | value |= APIC_LVT_LEVEL_TRIGGER; | |
943 | apic_write_around(APIC_LVT1, value); | |
1da177e4 LT |
944 | } |
945 | ||
a4928cff | 946 | static void __cpuinit lapic_setup_esr(void) |
df7939ae GOC |
947 | { |
948 | unsigned long oldvalue, value, maxlvt; | |
949 | if (lapic_is_integrated() && !esr_disable) { | |
950 | /* !82489DX */ | |
951 | maxlvt = lapic_get_maxlvt(); | |
952 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
953 | apic_write(APIC_ESR, 0); | |
954 | oldvalue = apic_read(APIC_ESR); | |
955 | ||
956 | /* enables sending errors */ | |
957 | value = ERROR_APIC_VECTOR; | |
958 | apic_write_around(APIC_LVTERR, value); | |
959 | /* | |
960 | * spec says clear errors after enabling vector. | |
961 | */ | |
962 | if (maxlvt > 3) | |
963 | apic_write(APIC_ESR, 0); | |
964 | value = apic_read(APIC_ESR); | |
965 | if (value != oldvalue) | |
966 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
967 | "vector: 0x%08lx after: 0x%08lx\n", | |
968 | oldvalue, value); | |
969 | } else { | |
970 | if (esr_disable) | |
971 | /* | |
972 | * Something untraceable is creating bad interrupts on | |
973 | * secondary quads ... for the moment, just leave the | |
974 | * ESR disabled - we can't do anything useful with the | |
975 | * errors anyway - mbligh | |
976 | */ | |
977 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
978 | else | |
979 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
980 | } | |
981 | } | |
982 | ||
983 | ||
e05d723f TG |
984 | /** |
985 | * setup_local_APIC - setup the local APIC | |
1da177e4 | 986 | */ |
d5337983 | 987 | void __cpuinit setup_local_APIC(void) |
e05d723f | 988 | { |
df7939ae | 989 | unsigned long value, integrated; |
e05d723f | 990 | int i, j; |
1da177e4 | 991 | |
e05d723f TG |
992 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
993 | if (esr_disable) { | |
994 | apic_write(APIC_ESR, 0); | |
995 | apic_write(APIC_ESR, 0); | |
996 | apic_write(APIC_ESR, 0); | |
997 | apic_write(APIC_ESR, 0); | |
998 | } | |
1da177e4 | 999 | |
e05d723f | 1000 | integrated = lapic_is_integrated(); |
1da177e4 | 1001 | |
e05d723f TG |
1002 | /* |
1003 | * Double-check whether this APIC is really registered. | |
1004 | */ | |
1005 | if (!apic_id_registered()) | |
22d5c67c | 1006 | WARN_ON_ONCE(1); |
1da177e4 | 1007 | |
e05d723f TG |
1008 | /* |
1009 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1010 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1011 | * document number 292116). So here it goes... | |
1012 | */ | |
1013 | init_apic_ldr(); | |
1da177e4 | 1014 | |
e05d723f TG |
1015 | /* |
1016 | * Set Task Priority to 'accept all'. We never change this | |
1017 | * later on. | |
1018 | */ | |
1019 | value = apic_read(APIC_TASKPRI); | |
1020 | value &= ~APIC_TPRI_MASK; | |
1021 | apic_write_around(APIC_TASKPRI, value); | |
1da177e4 | 1022 | |
e05d723f TG |
1023 | /* |
1024 | * After a crash, we no longer service the interrupts and a pending | |
1025 | * interrupt from previous kernel might still have ISR bit set. | |
1026 | * | |
1027 | * Most probably by now CPU has serviced that pending interrupt and | |
1028 | * it might not have done the ack_APIC_irq() because it thought, | |
1029 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1030 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1031 | * the interrupt. Hence a vector might get locked. It was noticed | |
1032 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1033 | */ | |
1034 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1035 | value = apic_read(APIC_ISR + i*0x10); | |
1036 | for (j = 31; j >= 0; j--) { | |
1037 | if (value & (1<<j)) | |
1038 | ack_APIC_irq(); | |
1039 | } | |
1040 | } | |
1da177e4 | 1041 | |
e05d723f TG |
1042 | /* |
1043 | * Now that we are all set up, enable the APIC | |
1044 | */ | |
1045 | value = apic_read(APIC_SPIV); | |
1046 | value &= ~APIC_VECTOR_MASK; | |
1047 | /* | |
1048 | * Enable APIC | |
1049 | */ | |
1050 | value |= APIC_SPIV_APIC_ENABLED; | |
1da177e4 | 1051 | |
e05d723f TG |
1052 | /* |
1053 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1054 | * certain networking cards. If high frequency interrupts are | |
1055 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1056 | * entry is masked/unmasked at a high rate as well then sooner or | |
1057 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1058 | * from the device. If focus CPU is disabled then the hang goes | |
1059 | * away, oh well :-( | |
1060 | * | |
1061 | * [ This bug can be reproduced easily with a level-triggered | |
1062 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1063 | * BX chipset. ] | |
1064 | */ | |
1065 | /* | |
1066 | * Actually disabling the focus CPU check just makes the hang less | |
1067 | * frequent as it makes the interrupt distributon model be more | |
1068 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1069 | * See also the comment in end_level_ioapic_irq(). --macro | |
1070 | */ | |
1da177e4 | 1071 | |
e05d723f TG |
1072 | /* Enable focus processor (bit==0) */ |
1073 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1074 | |
e05d723f TG |
1075 | /* |
1076 | * Set spurious IRQ vector | |
1077 | */ | |
1078 | value |= SPURIOUS_APIC_VECTOR; | |
1079 | apic_write_around(APIC_SPIV, value); | |
1080 | ||
1081 | /* | |
1082 | * Set up LVT0, LVT1: | |
1083 | * | |
1084 | * set up through-local-APIC on the BP's LINT0. This is not | |
27b46d76 | 1085 | * strictly necessary in pure symmetric-IO mode, but sometimes |
e05d723f TG |
1086 | * we delegate interrupts to the 8259A. |
1087 | */ | |
1088 | /* | |
1089 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1090 | */ | |
1091 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
1092 | if (!smp_processor_id() && (pic_mode || !value)) { | |
1093 | value = APIC_DM_EXTINT; | |
1094 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
1095 | smp_processor_id()); | |
1096 | } else { | |
1097 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
1098 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
1099 | smp_processor_id()); | |
1100 | } | |
1101 | apic_write_around(APIC_LVT0, value); | |
1102 | ||
1103 | /* | |
1104 | * only the BP should see the LINT1 NMI signal, obviously. | |
1105 | */ | |
1106 | if (!smp_processor_id()) | |
1107 | value = APIC_DM_NMI; | |
1108 | else | |
1109 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
1110 | if (!integrated) /* 82489DX */ | |
1111 | value |= APIC_LVT_LEVEL_TRIGGER; | |
1112 | apic_write_around(APIC_LVT1, value); | |
ac60aae5 | 1113 | } |
e05d723f | 1114 | |
ac60aae5 GOC |
1115 | void __cpuinit end_local_APIC_setup(void) |
1116 | { | |
1117 | unsigned long value; | |
1da177e4 | 1118 | |
ac60aae5 | 1119 | lapic_setup_esr(); |
e9e2cdb4 TG |
1120 | /* Disable the local apic timer */ |
1121 | value = apic_read(APIC_LVTT); | |
1122 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1123 | apic_write_around(APIC_LVTT, value); | |
1124 | ||
e05d723f TG |
1125 | setup_apic_nmi_watchdog(NULL); |
1126 | apic_pm_activate(); | |
1da177e4 LT |
1127 | } |
1128 | ||
e05d723f TG |
1129 | /* |
1130 | * Detect and initialize APIC | |
1131 | */ | |
e83a5fdc | 1132 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1133 | { |
1134 | u32 h, l, features; | |
1da177e4 LT |
1135 | |
1136 | /* Disabled by kernel option? */ | |
914bebfa | 1137 | if (disable_apic) |
1da177e4 LT |
1138 | return -1; |
1139 | ||
1da177e4 LT |
1140 | switch (boot_cpu_data.x86_vendor) { |
1141 | case X86_VENDOR_AMD: | |
1142 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
e05d723f | 1143 | (boot_cpu_data.x86 == 15)) |
1da177e4 LT |
1144 | break; |
1145 | goto no_apic; | |
1146 | case X86_VENDOR_INTEL: | |
1147 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1148 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1149 | break; | |
1150 | goto no_apic; | |
1151 | default: | |
1152 | goto no_apic; | |
1153 | } | |
1154 | ||
1155 | if (!cpu_has_apic) { | |
1156 | /* | |
e05d723f TG |
1157 | * Over-ride BIOS and try to enable the local APIC only if |
1158 | * "lapic" specified. | |
1da177e4 | 1159 | */ |
914bebfa | 1160 | if (!force_enable_local_apic) { |
e05d723f | 1161 | printk(KERN_INFO "Local APIC disabled by BIOS -- " |
1da177e4 LT |
1162 | "you can enable it with \"lapic\"\n"); |
1163 | return -1; | |
1164 | } | |
1165 | /* | |
e05d723f TG |
1166 | * Some BIOSes disable the local APIC in the APIC_BASE |
1167 | * MSR. This can only be done in software for Intel P6 or later | |
1168 | * and AMD K7 (Model > 1) or later. | |
1da177e4 LT |
1169 | */ |
1170 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1171 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
e05d723f TG |
1172 | printk(KERN_INFO |
1173 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1da177e4 LT |
1174 | l &= ~MSR_IA32_APICBASE_BASE; |
1175 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1176 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1177 | enabled_via_apicbase = 1; | |
1178 | } | |
1179 | } | |
1180 | /* | |
1181 | * The APIC feature bit should now be enabled | |
1182 | * in `cpuid' | |
1183 | */ | |
1184 | features = cpuid_edx(1); | |
1185 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
e05d723f | 1186 | printk(KERN_WARNING "Could not enable APIC!\n"); |
1da177e4 LT |
1187 | return -1; |
1188 | } | |
53756d37 | 1189 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1da177e4 LT |
1190 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
1191 | ||
1192 | /* The BIOS may have set up the APIC at some other address */ | |
1193 | rdmsr(MSR_IA32_APICBASE, l, h); | |
e05d723f TG |
1194 | if (l & MSR_IA32_APICBASE_ENABLE) |
1195 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1da177e4 | 1196 | |
e05d723f | 1197 | printk(KERN_INFO "Found and enabled local APIC!\n"); |
1da177e4 | 1198 | |
e05d723f | 1199 | apic_pm_activate(); |
1da177e4 | 1200 | |
e05d723f | 1201 | return 0; |
1da177e4 | 1202 | |
e05d723f TG |
1203 | no_apic: |
1204 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1205 | return -1; | |
1206 | } | |
1da177e4 | 1207 | |
e05d723f TG |
1208 | /** |
1209 | * init_apic_mappings - initialize APIC mappings | |
1210 | */ | |
1211 | void __init init_apic_mappings(void) | |
1da177e4 | 1212 | { |
1da177e4 | 1213 | /* |
e05d723f TG |
1214 | * If no local APIC can be found then set up a fake all |
1215 | * zeroes page to simulate the local APIC and another | |
1216 | * one for the IO-APIC. | |
1da177e4 | 1217 | */ |
e05d723f TG |
1218 | if (!smp_found_config && detect_init_APIC()) { |
1219 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1220 | apic_phys = __pa(apic_phys); | |
1221 | } else | |
1222 | apic_phys = mp_lapic_addr; | |
1da177e4 | 1223 | |
e05d723f TG |
1224 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
1225 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
1226 | apic_phys); | |
1da177e4 | 1227 | |
e05d723f TG |
1228 | /* |
1229 | * Fetch the APIC ID of the BSP in case we have a | |
1230 | * default configuration (or the MP table is broken). | |
1231 | */ | |
1232 | if (boot_cpu_physical_apicid == -1U) | |
4c9961d5 | 1233 | boot_cpu_physical_apicid = read_apic_id(); |
1da177e4 | 1234 | |
1da177e4 LT |
1235 | } |
1236 | ||
e05d723f TG |
1237 | /* |
1238 | * This initializes the IO-APIC and APIC hardware if this is | |
1239 | * a UP kernel. | |
1240 | */ | |
e81b2c62 AS |
1241 | |
1242 | int apic_version[MAX_APICS]; | |
1243 | ||
e83a5fdc | 1244 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1245 | { |
914bebfa | 1246 | if (disable_apic) |
53756d37 | 1247 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1da177e4 | 1248 | |
e05d723f TG |
1249 | if (!smp_found_config && !cpu_has_apic) |
1250 | return -1; | |
6eb0a0fd | 1251 | |
e05d723f TG |
1252 | /* |
1253 | * Complain if the BIOS pretends there is one. | |
1254 | */ | |
1255 | if (!cpu_has_apic && | |
1256 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1257 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1258 | boot_cpu_physical_apicid); | |
53756d37 | 1259 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
e05d723f | 1260 | return -1; |
6eb0a0fd | 1261 | } |
6eb0a0fd | 1262 | |
e05d723f | 1263 | verify_local_APIC(); |
6eb0a0fd | 1264 | |
e05d723f | 1265 | connect_bsp_APIC(); |
6eb0a0fd | 1266 | |
e05d723f TG |
1267 | /* |
1268 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1269 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1270 | * might be zero if read from MP tables. Get it from LAPIC. | |
1271 | */ | |
1272 | #ifdef CONFIG_CRASH_DUMP | |
4c9961d5 | 1273 | boot_cpu_physical_apicid = read_apic_id(); |
e05d723f | 1274 | #endif |
b6df1b8b | 1275 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
1da177e4 | 1276 | |
e05d723f | 1277 | setup_local_APIC(); |
1da177e4 | 1278 | |
acae7d90 MR |
1279 | #ifdef CONFIG_X86_IO_APIC |
1280 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) | |
1281 | #endif | |
1282 | localise_nmi_watchdog(); | |
ac60aae5 | 1283 | end_local_APIC_setup(); |
e05d723f TG |
1284 | #ifdef CONFIG_X86_IO_APIC |
1285 | if (smp_found_config) | |
1286 | if (!skip_ioapic_setup && nr_ioapics) | |
1287 | setup_IO_APIC(); | |
1da177e4 | 1288 | #endif |
e05d723f | 1289 | setup_boot_clock(); |
1da177e4 | 1290 | |
e05d723f | 1291 | return 0; |
1da177e4 LT |
1292 | } |
1293 | ||
e05d723f TG |
1294 | /* |
1295 | * Local APIC interrupts | |
1296 | */ | |
1297 | ||
1da177e4 LT |
1298 | /* |
1299 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1300 | */ | |
e9e2cdb4 | 1301 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1302 | { |
1303 | unsigned long v; | |
1304 | ||
1305 | irq_enter(); | |
1306 | /* | |
1307 | * Check if this really is a spurious interrupt and ACK it | |
1308 | * if it is a vectored one. Just in case... | |
1309 | * Spurious interrupts should not be ACKed. | |
1310 | */ | |
1311 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1312 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1313 | ack_APIC_irq(); | |
1314 | ||
1315 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
e05d723f TG |
1316 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " |
1317 | "should never happen.\n", smp_processor_id()); | |
38e760a1 | 1318 | __get_cpu_var(irq_stat).irq_spurious_count++; |
1da177e4 LT |
1319 | irq_exit(); |
1320 | } | |
1321 | ||
1322 | /* | |
1323 | * This interrupt should never happen with our APIC/SMP architecture | |
1324 | */ | |
e9e2cdb4 | 1325 | void smp_error_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1326 | { |
1327 | unsigned long v, v1; | |
1328 | ||
1329 | irq_enter(); | |
1330 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1331 | v = apic_read(APIC_ESR); | |
1332 | apic_write(APIC_ESR, 0); | |
1333 | v1 = apic_read(APIC_ESR); | |
1334 | ack_APIC_irq(); | |
1335 | atomic_inc(&irq_err_count); | |
1336 | ||
1337 | /* Here is what the APIC error bits mean: | |
1338 | 0: Send CS error | |
1339 | 1: Receive CS error | |
1340 | 2: Send accept error | |
1341 | 3: Receive accept error | |
1342 | 4: Reserved | |
1343 | 5: Send illegal vector | |
1344 | 6: Received illegal vector | |
1345 | 7: Illegal register address | |
1346 | */ | |
ff8a03a6 | 1347 | printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", |
e05d723f | 1348 | smp_processor_id(), v , v1); |
1da177e4 LT |
1349 | irq_exit(); |
1350 | } | |
1351 | ||
17c9ab1e GOC |
1352 | #ifdef CONFIG_SMP |
1353 | void __init smp_intr_init(void) | |
1354 | { | |
1355 | /* | |
1356 | * IRQ0 must be given a fixed assignment and initialized, | |
1357 | * because it's used before the IO-APIC is set up. | |
1358 | */ | |
1359 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1360 | ||
1361 | /* | |
1362 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1363 | * IPI, driven by wakeup. | |
1364 | */ | |
305b92a2 | 1365 | alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); |
17c9ab1e GOC |
1366 | |
1367 | /* IPI for invalidation */ | |
305b92a2 | 1368 | alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); |
17c9ab1e GOC |
1369 | |
1370 | /* IPI for generic function call */ | |
305b92a2 | 1371 | alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); |
17c9ab1e GOC |
1372 | } |
1373 | #endif | |
1374 | ||
1da177e4 | 1375 | /* |
e05d723f | 1376 | * Initialize APIC interrupts |
1da177e4 | 1377 | */ |
e05d723f | 1378 | void __init apic_intr_init(void) |
1da177e4 | 1379 | { |
e05d723f TG |
1380 | #ifdef CONFIG_SMP |
1381 | smp_intr_init(); | |
1382 | #endif | |
1383 | /* self generated IPI for local APIC timer */ | |
305b92a2 | 1384 | alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); |
1da177e4 | 1385 | |
e05d723f | 1386 | /* IPI vectors for APIC spurious and error interrupts */ |
305b92a2 AM |
1387 | alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); |
1388 | alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
1da177e4 | 1389 | |
e05d723f TG |
1390 | /* thermal monitor LVT interrupt */ |
1391 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
305b92a2 | 1392 | alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); |
e05d723f TG |
1393 | #endif |
1394 | } | |
1395 | ||
1396 | /** | |
1397 | * connect_bsp_APIC - attach the APIC to the interrupt system | |
1398 | */ | |
1399 | void __init connect_bsp_APIC(void) | |
1400 | { | |
1401 | if (pic_mode) { | |
1402 | /* | |
1403 | * Do not trust the local APIC being empty at bootup. | |
1404 | */ | |
1405 | clear_local_APIC(); | |
1406 | /* | |
1407 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1408 | * local APIC to INT and NMI lines. | |
1409 | */ | |
1410 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1411 | "enabling APIC mode.\n"); | |
1412 | outb(0x70, 0x22); | |
1413 | outb(0x01, 0x23); | |
1da177e4 | 1414 | } |
e05d723f TG |
1415 | enable_apic_mode(); |
1416 | } | |
1da177e4 | 1417 | |
e05d723f TG |
1418 | /** |
1419 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1420 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1421 | * | |
1422 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1423 | * APIC is disabled. | |
1424 | */ | |
1425 | void disconnect_bsp_APIC(int virt_wire_setup) | |
1426 | { | |
1427 | if (pic_mode) { | |
1428 | /* | |
1429 | * Put the board back into PIC mode (has an effect only on | |
1430 | * certain older boards). Note that APIC interrupts, including | |
1431 | * IPIs, won't work beyond this point! The only exception are | |
1432 | * INIT IPIs. | |
1433 | */ | |
1434 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1435 | "entering PIC mode.\n"); | |
1436 | outb(0x70, 0x22); | |
1437 | outb(0x00, 0x23); | |
1438 | } else { | |
1439 | /* Go back to Virtual Wire compatibility mode */ | |
1440 | unsigned long value; | |
1da177e4 | 1441 | |
e05d723f TG |
1442 | /* For the spurious interrupt use vector F, and enable it */ |
1443 | value = apic_read(APIC_SPIV); | |
1444 | value &= ~APIC_VECTOR_MASK; | |
1445 | value |= APIC_SPIV_APIC_ENABLED; | |
1446 | value |= 0xf; | |
1447 | apic_write_around(APIC_SPIV, value); | |
1da177e4 | 1448 | |
e05d723f TG |
1449 | if (!virt_wire_setup) { |
1450 | /* | |
1451 | * For LVT0 make it edge triggered, active high, | |
1452 | * external and enabled | |
1453 | */ | |
1454 | value = apic_read(APIC_LVT0); | |
1455 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1456 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
ff8a03a6 | 1457 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
e05d723f TG |
1458 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
1459 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1460 | apic_write_around(APIC_LVT0, value); | |
1461 | } else { | |
1462 | /* Disable LVT0 */ | |
1463 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
1464 | } | |
1da177e4 | 1465 | |
e05d723f TG |
1466 | /* |
1467 | * For LVT1 make it edge triggered, active high, nmi and | |
1468 | * enabled | |
1469 | */ | |
1470 | value = apic_read(APIC_LVT1); | |
1471 | value &= ~( | |
1472 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
1473 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1474 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1475 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1476 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1477 | apic_write_around(APIC_LVT1, value); | |
1478 | } | |
1479 | } | |
1da177e4 | 1480 | |
903dcb5a AS |
1481 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
1482 | ||
1483 | void __cpuinit generic_processor_info(int apicid, int version) | |
1484 | { | |
1485 | int cpu; | |
1486 | cpumask_t tmp_map; | |
1487 | physid_mask_t phys_cpu; | |
1488 | ||
1489 | /* | |
1490 | * Validate version | |
1491 | */ | |
1492 | if (version == 0x0) { | |
1493 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1494 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1495 | version); | |
1496 | version = 0x10; | |
1497 | } | |
1498 | apic_version[apicid] = version; | |
1499 | ||
1500 | phys_cpu = apicid_to_cpu_present(apicid); | |
1501 | physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu); | |
1502 | ||
1503 | if (num_processors >= NR_CPUS) { | |
1504 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1505 | " Processor ignored.\n", NR_CPUS); | |
1506 | return; | |
1507 | } | |
1508 | ||
1509 | if (num_processors >= maxcpus) { | |
1510 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
1511 | " Processor ignored.\n", maxcpus); | |
1512 | return; | |
1513 | } | |
1514 | ||
1515 | num_processors++; | |
1516 | cpus_complement(tmp_map, cpu_present_map); | |
1517 | cpu = first_cpu(tmp_map); | |
1518 | ||
1519 | if (apicid == boot_cpu_physical_apicid) | |
1520 | /* | |
1521 | * x86_bios_cpu_apicid is required to have processors listed | |
1522 | * in same order as logical cpu numbers. Hence the first | |
1523 | * entry is BSP, and so on. | |
1524 | */ | |
1525 | cpu = 0; | |
1526 | ||
e0da3364 YL |
1527 | if (apicid > max_physical_apicid) |
1528 | max_physical_apicid = apicid; | |
1529 | ||
903dcb5a AS |
1530 | /* |
1531 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1532 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1533 | * before this can be done without some confusion. | |
1534 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1535 | * - Ashok Raj <ashok.raj@intel.com> | |
1536 | */ | |
e0da3364 | 1537 | if (max_physical_apicid >= 8) { |
903dcb5a AS |
1538 | switch (boot_cpu_data.x86_vendor) { |
1539 | case X86_VENDOR_INTEL: | |
1540 | if (!APIC_XAPIC(version)) { | |
1541 | def_to_bigsmp = 0; | |
1542 | break; | |
1543 | } | |
1544 | /* If P4 and above fall through */ | |
1545 | case X86_VENDOR_AMD: | |
1546 | def_to_bigsmp = 1; | |
1547 | } | |
1548 | } | |
1549 | #ifdef CONFIG_SMP | |
1550 | /* are we being called early in kernel startup? */ | |
23ca4bba MT |
1551 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1552 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1553 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
903dcb5a AS |
1554 | |
1555 | cpu_to_apicid[cpu] = apicid; | |
1556 | bios_cpu_apicid[cpu] = apicid; | |
1557 | } else { | |
1558 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1559 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1560 | } | |
1561 | #endif | |
1562 | cpu_set(cpu, cpu_possible_map); | |
1563 | cpu_set(cpu, cpu_present_map); | |
1564 | } | |
1565 | ||
e05d723f TG |
1566 | /* |
1567 | * Power management | |
1568 | */ | |
1569 | #ifdef CONFIG_PM | |
1570 | ||
1571 | static struct { | |
1572 | int active; | |
1573 | /* r/w apic fields */ | |
1574 | unsigned int apic_id; | |
1575 | unsigned int apic_taskpri; | |
1576 | unsigned int apic_ldr; | |
1577 | unsigned int apic_dfr; | |
1578 | unsigned int apic_spiv; | |
1579 | unsigned int apic_lvtt; | |
1580 | unsigned int apic_lvtpc; | |
1581 | unsigned int apic_lvt0; | |
1582 | unsigned int apic_lvt1; | |
1583 | unsigned int apic_lvterr; | |
1584 | unsigned int apic_tmict; | |
1585 | unsigned int apic_tdcr; | |
1586 | unsigned int apic_thmr; | |
1587 | } apic_pm_state; | |
1588 | ||
1589 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1590 | { | |
1591 | unsigned long flags; | |
1592 | int maxlvt; | |
1593 | ||
1594 | if (!apic_pm_state.active) | |
1595 | return 0; | |
1596 | ||
1597 | maxlvt = lapic_get_maxlvt(); | |
1598 | ||
1599 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
1600 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1601 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1602 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1603 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1604 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1605 | if (maxlvt >= 4) | |
1606 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1607 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1608 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1609 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1610 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1611 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1612 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1613 | if (maxlvt >= 5) | |
1614 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1da177e4 | 1615 | #endif |
1e4c85f9 | 1616 | |
e05d723f TG |
1617 | local_irq_save(flags); |
1618 | disable_local_APIC(); | |
1619 | local_irq_restore(flags); | |
1e4c85f9 | 1620 | return 0; |
1da177e4 | 1621 | } |
1a3f239d | 1622 | |
e05d723f | 1623 | static int lapic_resume(struct sys_device *dev) |
1a3f239d | 1624 | { |
e05d723f TG |
1625 | unsigned int l, h; |
1626 | unsigned long flags; | |
1627 | int maxlvt; | |
1628 | ||
1629 | if (!apic_pm_state.active) | |
1630 | return 0; | |
1631 | ||
1632 | maxlvt = lapic_get_maxlvt(); | |
1633 | ||
1634 | local_irq_save(flags); | |
1635 | ||
1636 | /* | |
1637 | * Make sure the APICBASE points to the right address | |
1638 | * | |
1639 | * FIXME! This will be wrong if we ever support suspend on | |
1640 | * SMP! We'll need to do this as part of the CPU restore! | |
1641 | */ | |
1642 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1643 | l &= ~MSR_IA32_APICBASE_BASE; | |
1644 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1645 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1646 | ||
1647 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1648 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1649 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1650 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1651 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1652 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1653 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1654 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1655 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1656 | if (maxlvt >= 5) | |
1657 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1658 | #endif | |
1659 | if (maxlvt >= 4) | |
1660 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1661 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1662 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1663 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1664 | apic_write(APIC_ESR, 0); | |
1665 | apic_read(APIC_ESR); | |
1666 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1667 | apic_write(APIC_ESR, 0); | |
1668 | apic_read(APIC_ESR); | |
1669 | local_irq_restore(flags); | |
1a3f239d RR |
1670 | return 0; |
1671 | } | |
1a3f239d | 1672 | |
e05d723f TG |
1673 | /* |
1674 | * This device has no shutdown method - fully functioning local APICs | |
1675 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1676 | */ | |
1677 | ||
1678 | static struct sysdev_class lapic_sysclass = { | |
af5ca3f4 | 1679 | .name = "lapic", |
e05d723f TG |
1680 | .resume = lapic_resume, |
1681 | .suspend = lapic_suspend, | |
1682 | }; | |
1683 | ||
1684 | static struct sys_device device_lapic = { | |
1685 | .id = 0, | |
1686 | .cls = &lapic_sysclass, | |
1687 | }; | |
1688 | ||
1689 | static void __devinit apic_pm_activate(void) | |
1a3f239d | 1690 | { |
e05d723f | 1691 | apic_pm_state.active = 1; |
1a3f239d | 1692 | } |
1a3f239d | 1693 | |
e05d723f TG |
1694 | static int __init init_lapic_sysfs(void) |
1695 | { | |
1696 | int error; | |
1697 | ||
1698 | if (!cpu_has_apic) | |
1699 | return 0; | |
1700 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
1701 | ||
1702 | error = sysdev_class_register(&lapic_sysclass); | |
1703 | if (!error) | |
1704 | error = sysdev_register(&device_lapic); | |
1705 | return error; | |
1706 | } | |
1707 | device_initcall(init_lapic_sysfs); | |
1708 | ||
1709 | #else /* CONFIG_PM */ | |
1710 | ||
1711 | static void apic_pm_activate(void) { } | |
1712 | ||
1713 | #endif /* CONFIG_PM */ | |
0e078e2f TG |
1714 | |
1715 | /* | |
1716 | * APIC command line parameters | |
1717 | */ | |
1718 | static int __init parse_lapic(char *arg) | |
1719 | { | |
914bebfa | 1720 | force_enable_local_apic = 1; |
0e078e2f TG |
1721 | return 0; |
1722 | } | |
1723 | early_param("lapic", parse_lapic); | |
1724 | ||
1725 | static int __init parse_nolapic(char *arg) | |
1726 | { | |
914bebfa | 1727 | disable_apic = 1; |
53756d37 | 1728 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
0e078e2f TG |
1729 | return 0; |
1730 | } | |
1731 | early_param("nolapic", parse_nolapic); | |
1732 | ||
1733 | static int __init parse_disable_lapic_timer(char *arg) | |
1734 | { | |
1735 | local_apic_timer_disabled = 1; | |
1736 | return 0; | |
1737 | } | |
1738 | early_param("nolapic_timer", parse_disable_lapic_timer); | |
1739 | ||
1740 | static int __init parse_lapic_timer_c2_ok(char *arg) | |
1741 | { | |
1742 | local_apic_timer_c2_ok = 1; | |
1743 | return 0; | |
1744 | } | |
1745 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1746 | ||
1747 | static int __init apic_set_verbosity(char *str) | |
1748 | { | |
1749 | if (strcmp("debug", str) == 0) | |
1750 | apic_verbosity = APIC_DEBUG; | |
1751 | else if (strcmp("verbose", str) == 0) | |
1752 | apic_verbosity = APIC_VERBOSE; | |
1753 | return 1; | |
1754 | } | |
1755 | __setup("apic=", apic_set_verbosity); | |
1756 | ||
746f2eb7 CG |
1757 | static int __init lapic_insert_resource(void) |
1758 | { | |
1759 | if (!apic_phys) | |
1760 | return -1; | |
1761 | ||
1762 | /* Put local APIC into the resource map. */ | |
1763 | lapic_resource.start = apic_phys; | |
1764 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1765 | insert_resource(&iomem_resource, &lapic_resource); | |
1766 | ||
1767 | return 0; | |
1768 | } | |
1769 | ||
1770 | /* | |
1771 | * need call insert after e820_reserve_resources() | |
1772 | * that is using request_resource | |
1773 | */ | |
1774 | late_initcall(lapic_insert_resource); |