Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
773763df | 26 | #include <linux/ioport.h> |
f3705136 | 27 | #include <linux/cpu.h> |
e9e2cdb4 | 28 | #include <linux/clockchips.h> |
d36b49b9 | 29 | #include <linux/acpi_pmtmr.h> |
6eb0a0fd | 30 | #include <linux/module.h> |
ad62ca2b | 31 | #include <linux/dmi.h> |
773763df | 32 | #include <linux/dmar.h> |
1da177e4 LT |
33 | |
34 | #include <asm/atomic.h> | |
35 | #include <asm/smp.h> | |
36 | #include <asm/mtrr.h> | |
37 | #include <asm/mpspec.h> | |
38 | #include <asm/desc.h> | |
39 | #include <asm/arch_hooks.h> | |
40 | #include <asm/hpet.h> | |
773763df | 41 | #include <asm/pgalloc.h> |
306e440d | 42 | #include <asm/i8253.h> |
3e4ff115 | 43 | #include <asm/nmi.h> |
773763df YL |
44 | #include <asm/idle.h> |
45 | #include <asm/proto.h> | |
46 | #include <asm/timex.h> | |
47 | #include <asm/apic.h> | |
48 | #include <asm/i8259.h> | |
1da177e4 LT |
49 | |
50 | #include <mach_apic.h> | |
382dbd07 | 51 | #include <mach_apicdef.h> |
6eb0a0fd | 52 | #include <mach_ipi.h> |
1da177e4 | 53 | |
e05d723f TG |
54 | /* |
55 | * Sanity check | |
56 | */ | |
ff8a03a6 | 57 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) |
e05d723f TG |
58 | # error SPURIOUS_APIC_VECTOR definition error |
59 | #endif | |
60 | ||
b3c51170 | 61 | #ifdef CONFIG_X86_32 |
9635b47d EB |
62 | /* |
63 | * Knob to control our willingness to enable the local APIC. | |
e05d723f | 64 | * |
914bebfa | 65 | * +1=force-enable |
9635b47d | 66 | */ |
914bebfa | 67 | static int force_enable_local_apic; |
b3c51170 YL |
68 | /* |
69 | * APIC command line parameters | |
70 | */ | |
71 | static int __init parse_lapic(char *arg) | |
72 | { | |
73 | force_enable_local_apic = 1; | |
74 | return 0; | |
75 | } | |
76 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
77 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
78 | static int enabled_via_apicbase; | |
79 | ||
b3c51170 | 80 | #endif |
9635b47d | 81 | |
b3c51170 YL |
82 | #ifdef CONFIG_X86_64 |
83 | static int apic_calibrate_pmtmr __initdata; | |
84 | static __init int setup_apicpmtimer(char *s) | |
85 | { | |
86 | apic_calibrate_pmtmr = 1; | |
87 | notsc_setup(NULL); | |
88 | return 0; | |
89 | } | |
90 | __setup("apicpmtimer", setup_apicpmtimer); | |
91 | #endif | |
92 | ||
93 | unsigned long mp_lapic_addr; | |
94 | int disable_apic; | |
aa276e1c | 95 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
36fef094 | 96 | static int disable_apic_timer __cpuinitdata; |
e585bef8 TG |
97 | /* Local APIC timer works in C2 */ |
98 | int local_apic_timer_c2_ok; | |
99 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
e9e2cdb4 | 100 | |
ce178331 AM |
101 | int first_system_vector = 0xfe; |
102 | ||
103 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
104 | ||
1da177e4 | 105 | /* |
e05d723f | 106 | * Debug level, exported for io_apic.c |
1da177e4 | 107 | */ |
baa13188 | 108 | unsigned int apic_verbosity; |
1da177e4 | 109 | |
f3918352 AS |
110 | int pic_mode; |
111 | ||
bab4b27c AS |
112 | /* Have we found an MP table */ |
113 | int smp_found_config; | |
114 | ||
746f2eb7 CG |
115 | static struct resource lapic_resource = { |
116 | .name = "Local APIC", | |
117 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
118 | }; | |
119 | ||
e9e2cdb4 | 120 | static unsigned int calibration_result; |
1da177e4 | 121 | |
e9e2cdb4 TG |
122 | static int lapic_next_event(unsigned long delta, |
123 | struct clock_event_device *evt); | |
124 | static void lapic_timer_setup(enum clock_event_mode mode, | |
125 | struct clock_event_device *evt); | |
126 | static void lapic_timer_broadcast(cpumask_t mask); | |
127 | static void apic_pm_activate(void); | |
e05d723f | 128 | |
e9e2cdb4 TG |
129 | /* |
130 | * The local apic timer can be used for any function which is CPU local. | |
131 | */ | |
132 | static struct clock_event_device lapic_clockevent = { | |
133 | .name = "lapic", | |
134 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
d36b49b9 | 135 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
e9e2cdb4 TG |
136 | .shift = 32, |
137 | .set_mode = lapic_timer_setup, | |
138 | .set_next_event = lapic_next_event, | |
139 | .broadcast = lapic_timer_broadcast, | |
140 | .rating = 100, | |
141 | .irq = -1, | |
142 | }; | |
143 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
e05d723f | 144 | |
d3432896 AK |
145 | static unsigned long apic_phys; |
146 | ||
e05d723f TG |
147 | /* |
148 | * Get the LAPIC version | |
149 | */ | |
150 | static inline int lapic_get_version(void) | |
95d769aa | 151 | { |
e05d723f | 152 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
95d769aa AK |
153 | } |
154 | ||
1da177e4 | 155 | /* |
ab4a574e | 156 | * Check, if the APIC is integrated or a separate chip |
1da177e4 | 157 | */ |
e05d723f | 158 | static inline int lapic_is_integrated(void) |
1da177e4 | 159 | { |
9c803869 CG |
160 | #ifdef CONFIG_X86_64 |
161 | return 1; | |
162 | #else | |
e05d723f | 163 | return APIC_INTEGRATED(lapic_get_version()); |
9c803869 | 164 | #endif |
1da177e4 LT |
165 | } |
166 | ||
e05d723f TG |
167 | /* |
168 | * Check, whether this is a modern or a first generation APIC | |
169 | */ | |
170 | static int modern_apic(void) | |
1da177e4 | 171 | { |
e05d723f TG |
172 | /* AMD systems use old APIC versions, so check the CPU */ |
173 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
174 | boot_cpu_data.x86 >= 0xf) | |
175 | return 1; | |
176 | return lapic_get_version() >= 0x14; | |
1da177e4 LT |
177 | } |
178 | ||
9a8f0e6b SS |
179 | /* |
180 | * Paravirt kernels also might be using these below ops. So we still | |
181 | * use generic apic_read()/apic_write(), which might be pointing to different | |
182 | * ops in PARAVIRT case. | |
183 | */ | |
c535b6a1 | 184 | void xapic_wait_icr_idle(void) |
f2b218dd FLV |
185 | { |
186 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
187 | cpu_relax(); | |
188 | } | |
189 | ||
c535b6a1 | 190 | u32 safe_xapic_wait_icr_idle(void) |
f2b218dd | 191 | { |
42e0a9aa | 192 | u32 send_status; |
f2b218dd FLV |
193 | int timeout; |
194 | ||
195 | timeout = 0; | |
196 | do { | |
197 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
198 | if (!send_status) | |
199 | break; | |
200 | udelay(100); | |
201 | } while (timeout++ < 1000); | |
202 | ||
203 | return send_status; | |
204 | } | |
205 | ||
c535b6a1 YL |
206 | void xapic_icr_write(u32 low, u32 id) |
207 | { | |
f586bf7d SS |
208 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
209 | apic_write(APIC_ICR, low); | |
c535b6a1 YL |
210 | } |
211 | ||
212 | u64 xapic_icr_read(void) | |
213 | { | |
214 | u32 icr1, icr2; | |
215 | ||
216 | icr2 = apic_read(APIC_ICR2); | |
217 | icr1 = apic_read(APIC_ICR); | |
218 | ||
219 | return icr1 | ((u64)icr2 << 32); | |
220 | } | |
221 | ||
222 | static struct apic_ops xapic_ops = { | |
223 | .read = native_apic_mem_read, | |
224 | .write = native_apic_mem_write, | |
c535b6a1 YL |
225 | .icr_read = xapic_icr_read, |
226 | .icr_write = xapic_icr_write, | |
227 | .wait_icr_idle = xapic_wait_icr_idle, | |
228 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
229 | }; | |
230 | ||
231 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
232 | EXPORT_SYMBOL_GPL(apic_ops); | |
233 | ||
e05d723f TG |
234 | /** |
235 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
236 | */ | |
e9427101 | 237 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 238 | { |
d4c63ec0 | 239 | unsigned int v; |
1da177e4 | 240 | |
d4c63ec0 CG |
241 | /* unmask and set to NMI */ |
242 | v = APIC_DM_NMI; | |
243 | ||
244 | /* Level triggered for 82489DX (32bit mode) */ | |
e05d723f | 245 | if (!lapic_is_integrated()) |
1da177e4 | 246 | v |= APIC_LVT_LEVEL_TRIGGER; |
d4c63ec0 | 247 | |
593f4a78 | 248 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
249 | } |
250 | ||
f28c0ae2 | 251 | #ifdef CONFIG_X86_32 |
e05d723f TG |
252 | /** |
253 | * get_physical_broadcast - Get number of physical broadcast IDs | |
254 | */ | |
1da177e4 LT |
255 | int get_physical_broadcast(void) |
256 | { | |
e05d723f | 257 | return modern_apic() ? 0xff : 0xf; |
1da177e4 | 258 | } |
f28c0ae2 | 259 | #endif |
1da177e4 | 260 | |
e05d723f TG |
261 | /** |
262 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
263 | */ | |
264 | int lapic_get_maxlvt(void) | |
1da177e4 | 265 | { |
36a028de | 266 | unsigned int v; |
1da177e4 | 267 | |
36a028de CG |
268 | v = apic_read(APIC_LVR); |
269 | /* | |
270 | * - we always have APIC integrated on 64bit mode | |
271 | * - 82489DXs do not report # of LVT entries | |
272 | */ | |
e05d723f | 273 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
1da177e4 LT |
274 | } |
275 | ||
e05d723f TG |
276 | /* |
277 | * Local APIC timer | |
278 | */ | |
279 | ||
c40aaec6 CG |
280 | /* Clock divisor */ |
281 | #ifdef CONFG_X86_64 | |
282 | #define APIC_DIVISOR 1 | |
283 | #else | |
d36b49b9 | 284 | #define APIC_DIVISOR 16 |
c40aaec6 | 285 | #endif |
e05d723f TG |
286 | |
287 | /* | |
288 | * This function sets up the local APIC timer, with a timeout of | |
289 | * 'clocks' APIC bus clock. During calibration we actually call | |
290 | * this function twice on the boot CPU, once with a bogus timeout | |
291 | * value, second time for real. The other (noncalibrating) CPUs | |
292 | * call this function only once, with the real, calibrated value. | |
274cfe59 CG |
293 | * |
294 | * We do reads before writes even if unnecessary, to get around the | |
295 | * P5 APIC double write bug. | |
e05d723f | 296 | */ |
e9e2cdb4 | 297 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 298 | { |
e05d723f | 299 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 300 | |
e9e2cdb4 TG |
301 | lvtt_value = LOCAL_TIMER_VECTOR; |
302 | if (!oneshot) | |
303 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
e05d723f TG |
304 | if (!lapic_is_integrated()) |
305 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
306 | ||
e9e2cdb4 | 307 | if (!irqen) |
e05d723f TG |
308 | lvtt_value |= APIC_LVT_MASKED; |
309 | ||
593f4a78 | 310 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
311 | |
312 | /* | |
e05d723f | 313 | * Divide PICLK by 16 |
1da177e4 | 314 | */ |
e05d723f | 315 | tmp_value = apic_read(APIC_TDCR); |
593f4a78 | 316 | apic_write(APIC_TDCR, |
c40aaec6 CG |
317 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
318 | APIC_TDR_DIV_16); | |
1da177e4 | 319 | |
e9e2cdb4 | 320 | if (!oneshot) |
593f4a78 | 321 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
e9e2cdb4 TG |
322 | } |
323 | ||
274cfe59 CG |
324 | /* |
325 | * Setup extended LVT, AMD specific (K8, family 10h) | |
326 | * | |
327 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
328 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
accba5f3 IM |
329 | * |
330 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
331 | * enables the vector. See also the BKDGs. | |
274cfe59 CG |
332 | */ |
333 | ||
334 | #define APIC_EILVT_LVTOFF_MCE 0 | |
335 | #define APIC_EILVT_LVTOFF_IBS 1 | |
336 | ||
337 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
338 | { | |
339 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; | |
340 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; | |
341 | ||
342 | apic_write(reg, v); | |
343 | } | |
344 | ||
345 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) | |
346 | { | |
347 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
348 | return APIC_EILVT_LVTOFF_MCE; | |
349 | } | |
350 | ||
351 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
352 | { | |
353 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
354 | return APIC_EILVT_LVTOFF_IBS; | |
355 | } | |
accba5f3 | 356 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
274cfe59 | 357 | |
e9e2cdb4 TG |
358 | /* |
359 | * Program the next event, relative to now | |
360 | */ | |
361 | static int lapic_next_event(unsigned long delta, | |
362 | struct clock_event_device *evt) | |
363 | { | |
593f4a78 | 364 | apic_write(APIC_TMICT, delta); |
e9e2cdb4 | 365 | return 0; |
1da177e4 LT |
366 | } |
367 | ||
e9e2cdb4 TG |
368 | /* |
369 | * Setup the lapic timer in periodic or oneshot mode | |
370 | */ | |
371 | static void lapic_timer_setup(enum clock_event_mode mode, | |
372 | struct clock_event_device *evt) | |
1da177e4 | 373 | { |
e05d723f | 374 | unsigned long flags; |
e9e2cdb4 | 375 | unsigned int v; |
e05d723f | 376 | |
274cfe59 | 377 | /* Lapic used as dummy for broadcast ? */ |
64e474d1 | 378 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) |
d36b49b9 TG |
379 | return; |
380 | ||
e05d723f | 381 | local_irq_save(flags); |
1da177e4 | 382 | |
e9e2cdb4 TG |
383 | switch (mode) { |
384 | case CLOCK_EVT_MODE_PERIODIC: | |
385 | case CLOCK_EVT_MODE_ONESHOT: | |
386 | __setup_APIC_LVTT(calibration_result, | |
387 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
388 | break; | |
389 | case CLOCK_EVT_MODE_UNUSED: | |
390 | case CLOCK_EVT_MODE_SHUTDOWN: | |
391 | v = apic_read(APIC_LVTT); | |
392 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
593f4a78 | 393 | apic_write(APIC_LVTT, v); |
e9e2cdb4 | 394 | break; |
18de5bc4 TG |
395 | case CLOCK_EVT_MODE_RESUME: |
396 | /* Nothing to do here */ | |
397 | break; | |
e9e2cdb4 | 398 | } |
e05d723f TG |
399 | |
400 | local_irq_restore(flags); | |
401 | } | |
402 | ||
e9e2cdb4 TG |
403 | /* |
404 | * Local APIC timer broadcast function | |
405 | */ | |
406 | static void lapic_timer_broadcast(cpumask_t mask) | |
407 | { | |
408 | #ifdef CONFIG_SMP | |
409 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
410 | #endif | |
411 | } | |
412 | ||
413 | /* | |
414 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
415 | * of the boot CPU and register the clock event in the framework. | |
416 | */ | |
457cc52d | 417 | static void __cpuinit setup_APIC_timer(void) |
e9e2cdb4 TG |
418 | { |
419 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
420 | ||
421 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); | |
422 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
423 | ||
424 | clockevents_register_device(levt); | |
425 | } | |
426 | ||
e05d723f | 427 | /* |
d36b49b9 TG |
428 | * In this functions we calibrate APIC bus clocks to the external timer. |
429 | * | |
430 | * We want to do the calibration only once since we want to have local timer | |
431 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
432 | * frequency. | |
433 | * | |
434 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
435 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
436 | * readout is broken, so it never gets out of the wait loop again. This was | |
437 | * also reported by others. | |
e05d723f | 438 | * |
d36b49b9 TG |
439 | * Monitoring the jiffies value is inaccurate and the clockevents |
440 | * infrastructure allows us to do a simple substitution of the interrupt | |
441 | * handler. | |
e9e2cdb4 | 442 | * |
d36b49b9 TG |
443 | * The calibration routine also uses the pm_timer when possible, as the PIT |
444 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
445 | * back to normal later in the boot process). | |
e05d723f TG |
446 | */ |
447 | ||
d36b49b9 | 448 | #define LAPIC_CAL_LOOPS (HZ/10) |
e05d723f | 449 | |
f5352fd0 | 450 | static __initdata int lapic_cal_loops = -1; |
d36b49b9 TG |
451 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
452 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
453 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
454 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
1da177e4 | 455 | |
d36b49b9 TG |
456 | /* |
457 | * Temporary interrupt handler. | |
458 | */ | |
459 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
460 | { | |
461 | unsigned long long tsc = 0; | |
462 | long tapic = apic_read(APIC_TMCCT); | |
463 | unsigned long pm = acpi_pm_read_early(); | |
1da177e4 | 464 | |
d36b49b9 TG |
465 | if (cpu_has_tsc) |
466 | rdtscll(tsc); | |
467 | ||
468 | switch (lapic_cal_loops++) { | |
469 | case 0: | |
470 | lapic_cal_t1 = tapic; | |
471 | lapic_cal_tsc1 = tsc; | |
472 | lapic_cal_pm1 = pm; | |
473 | lapic_cal_j1 = jiffies; | |
474 | break; | |
e05d723f | 475 | |
d36b49b9 TG |
476 | case LAPIC_CAL_LOOPS: |
477 | lapic_cal_t2 = tapic; | |
478 | lapic_cal_tsc2 = tsc; | |
479 | if (pm < lapic_cal_pm1) | |
480 | pm += ACPI_PM_OVRRUN; | |
481 | lapic_cal_pm2 = pm; | |
482 | lapic_cal_j2 = jiffies; | |
483 | break; | |
484 | } | |
485 | } | |
1da177e4 | 486 | |
836c129d | 487 | static int __init calibrate_APIC_clock(void) |
d36b49b9 TG |
488 | { |
489 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
490 | const long pm_100ms = PMTMR_TICKS_PER_SEC/10; | |
491 | const long pm_thresh = pm_100ms/100; | |
492 | void (*real_handler)(struct clock_event_device *dev); | |
493 | unsigned long deltaj; | |
494 | long delta, deltapm; | |
ca1b940c | 495 | int pm_referenced = 0; |
1da177e4 | 496 | |
d36b49b9 TG |
497 | local_irq_disable(); |
498 | ||
499 | /* Replace the global interrupt handler */ | |
500 | real_handler = global_clock_event->event_handler; | |
501 | global_clock_event->event_handler = lapic_cal_handler; | |
1da177e4 | 502 | |
1da177e4 | 503 | /* |
d36b49b9 TG |
504 | * Setup the APIC counter to 1e9. There is no way the lapic |
505 | * can underflow in the 100ms detection time frame | |
1da177e4 | 506 | */ |
d36b49b9 | 507 | __setup_APIC_LVTT(1000000000, 0, 0); |
1da177e4 | 508 | |
d36b49b9 TG |
509 | /* Let the interrupts run */ |
510 | local_irq_enable(); | |
511 | ||
ca1b940c TG |
512 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
513 | cpu_relax(); | |
d36b49b9 TG |
514 | |
515 | local_irq_disable(); | |
516 | ||
517 | /* Restore the real event handler */ | |
518 | global_clock_event->event_handler = real_handler; | |
519 | ||
520 | /* Build delta t1-t2 as apic timer counts down */ | |
521 | delta = lapic_cal_t1 - lapic_cal_t2; | |
522 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
523 | ||
524 | /* Check, if the PM timer is available */ | |
525 | deltapm = lapic_cal_pm2 - lapic_cal_pm1; | |
526 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
527 | ||
528 | if (deltapm) { | |
529 | unsigned long mult; | |
530 | u64 res; | |
531 | ||
532 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
533 | ||
534 | if (deltapm > (pm_100ms - pm_thresh) && | |
535 | deltapm < (pm_100ms + pm_thresh)) { | |
536 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
537 | } else { | |
538 | res = (((u64) deltapm) * mult) >> 22; | |
539 | do_div(res, 1000000); | |
540 | printk(KERN_WARNING "APIC calibration not consistent " | |
541 | "with PM Timer: %ldms instead of 100ms\n", | |
542 | (long)res); | |
543 | /* Correct the lapic counter value */ | |
ff8a03a6 | 544 | res = (((u64) delta) * pm_100ms); |
d36b49b9 TG |
545 | do_div(res, deltapm); |
546 | printk(KERN_INFO "APIC delta adjusted to PM-Timer: " | |
547 | "%lu (%ld)\n", (unsigned long) res, delta); | |
548 | delta = (long) res; | |
549 | } | |
ca1b940c | 550 | pm_referenced = 1; |
d36b49b9 | 551 | } |
e05d723f | 552 | |
e9e2cdb4 | 553 | /* Calculate the scaled math multiplication factor */ |
877084fb AM |
554 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, |
555 | lapic_clockevent.shift); | |
e9e2cdb4 TG |
556 | lapic_clockevent.max_delta_ns = |
557 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
558 | lapic_clockevent.min_delta_ns = | |
559 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
560 | ||
d36b49b9 TG |
561 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
562 | ||
563 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
e9e2cdb4 | 564 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); |
d36b49b9 TG |
565 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
566 | calibration_result); | |
e9e2cdb4 | 567 | |
d36b49b9 TG |
568 | if (cpu_has_tsc) { |
569 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
e05d723f | 570 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
d36b49b9 TG |
571 | "%ld.%04ld MHz.\n", |
572 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
573 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
574 | } | |
e05d723f TG |
575 | |
576 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
d36b49b9 TG |
577 | "%u.%04u MHz.\n", |
578 | calibration_result / (1000000 / HZ), | |
579 | calibration_result % (1000000 / HZ)); | |
e05d723f | 580 | |
c2b84b30 TG |
581 | /* |
582 | * Do a sanity check on the APIC calibration result | |
583 | */ | |
584 | if (calibration_result < (1000000 / HZ)) { | |
585 | local_irq_enable(); | |
586 | printk(KERN_WARNING | |
587 | "APIC frequency too slow, disabling apic timer\n"); | |
836c129d | 588 | return -1; |
c2b84b30 TG |
589 | } |
590 | ||
64e474d1 | 591 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; |
836c129d | 592 | |
ca1b940c TG |
593 | /* We trust the pm timer based calibration */ |
594 | if (!pm_referenced) { | |
595 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
d36b49b9 | 596 | |
ca1b940c TG |
597 | /* |
598 | * Setup the apic timer manually | |
599 | */ | |
600 | levt->event_handler = lapic_cal_handler; | |
601 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
602 | lapic_cal_loops = -1; | |
d36b49b9 | 603 | |
ca1b940c TG |
604 | /* Let the interrupts run */ |
605 | local_irq_enable(); | |
d36b49b9 | 606 | |
f5352fd0 | 607 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
ca1b940c | 608 | cpu_relax(); |
d36b49b9 | 609 | |
ca1b940c | 610 | local_irq_disable(); |
d36b49b9 | 611 | |
ca1b940c TG |
612 | /* Stop the lapic timer */ |
613 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
d36b49b9 | 614 | |
ca1b940c | 615 | local_irq_enable(); |
d36b49b9 | 616 | |
ca1b940c TG |
617 | /* Jiffies delta */ |
618 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
619 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
d36b49b9 | 620 | |
d36b49b9 | 621 | /* Check, if the jiffies result is consistent */ |
ca1b940c | 622 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
d36b49b9 | 623 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
ca1b940c | 624 | else |
64e474d1 | 625 | levt->features |= CLOCK_EVT_FEAT_DUMMY; |
4edc5db8 IM |
626 | } else |
627 | local_irq_enable(); | |
e05d723f | 628 | |
64e474d1 | 629 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { |
d36b49b9 TG |
630 | printk(KERN_WARNING |
631 | "APIC timer disabled due to verification failure.\n"); | |
836c129d CG |
632 | return -1; |
633 | } | |
634 | ||
635 | return 0; | |
636 | } | |
637 | ||
638 | /* | |
639 | * Setup the boot APIC | |
640 | * | |
641 | * Calibrate and verify the result. | |
642 | */ | |
643 | void __init setup_boot_APIC_clock(void) | |
644 | { | |
645 | /* | |
646 | * The local apic timer can be disabled via the kernel | |
647 | * commandline or from the CPU detection code. Register the lapic | |
648 | * timer as a dummy clock event source on SMP systems, so the | |
649 | * broadcast mechanism is used. On UP systems simply ignore it. | |
650 | */ | |
36fef094 | 651 | if (disable_apic_timer) { |
f1ee3789 | 652 | printk(KERN_INFO "Disabling APIC timer\n"); |
d36b49b9 | 653 | /* No broadcast on UP ! */ |
836c129d CG |
654 | if (num_possible_cpus() > 1) { |
655 | lapic_clockevent.mult = 1; | |
656 | setup_APIC_timer(); | |
657 | } | |
658 | return; | |
a5f5e43e | 659 | } |
d36b49b9 | 660 | |
836c129d CG |
661 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
662 | "calibrating APIC timer ...\n"); | |
663 | ||
664 | if (calibrate_APIC_clock()) { | |
665 | /* No broadcast on UP ! */ | |
666 | if (num_possible_cpus() > 1) | |
667 | setup_APIC_timer(); | |
668 | return; | |
669 | } | |
670 | ||
671 | /* | |
672 | * If nmi_watchdog is set to IO_APIC, we need the | |
673 | * PIT/HPET going. Otherwise register lapic as a dummy | |
674 | * device. | |
675 | */ | |
676 | if (nmi_watchdog != NMI_IO_APIC) | |
677 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
678 | else | |
679 | printk(KERN_WARNING "APIC timer registered as dummy," | |
680 | " due to nmi_watchdog=%d!\n", nmi_watchdog); | |
681 | ||
d36b49b9 TG |
682 | /* Setup the lapic or request the broadcast */ |
683 | setup_APIC_timer(); | |
e05d723f | 684 | } |
1da177e4 | 685 | |
457cc52d | 686 | void __cpuinit setup_secondary_APIC_clock(void) |
e05d723f | 687 | { |
e9e2cdb4 | 688 | setup_APIC_timer(); |
e05d723f | 689 | } |
1da177e4 | 690 | |
e05d723f | 691 | /* |
e9e2cdb4 | 692 | * The guts of the apic timer interrupt |
e05d723f | 693 | */ |
e9e2cdb4 | 694 | static void local_apic_timer_interrupt(void) |
e05d723f | 695 | { |
e9e2cdb4 TG |
696 | int cpu = smp_processor_id(); |
697 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
1da177e4 LT |
698 | |
699 | /* | |
d36b49b9 TG |
700 | * Normally we should not be here till LAPIC has been initialized but |
701 | * in some cases like kdump, its possible that there is a pending LAPIC | |
702 | * timer interrupt from previous kernel's context and is delivered in | |
703 | * new kernel the moment interrupts are enabled. | |
e05d723f | 704 | * |
d36b49b9 TG |
705 | * Interrupts are enabled early and LAPIC is setup much later, hence |
706 | * its possible that when we get here evt->event_handler is NULL. | |
707 | * Check for event_handler being NULL and discard the interrupt as | |
708 | * spurious. | |
1da177e4 | 709 | */ |
e9e2cdb4 TG |
710 | if (!evt->event_handler) { |
711 | printk(KERN_WARNING | |
712 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
713 | /* Switch it off */ | |
714 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
715 | return; | |
716 | } | |
717 | ||
0e078e2f TG |
718 | /* |
719 | * the NMI deadlock-detector uses this. | |
720 | */ | |
0b23e8cf CG |
721 | #ifdef CONFIG_X86_64 |
722 | add_pda(apic_timer_irqs, 1); | |
723 | #else | |
e9e2cdb4 | 724 | per_cpu(irq_stat, cpu).apic_timer_irqs++; |
0b23e8cf | 725 | #endif |
e9e2cdb4 TG |
726 | |
727 | evt->event_handler(evt); | |
e05d723f TG |
728 | } |
729 | ||
730 | /* | |
731 | * Local APIC timer interrupt. This is the most natural way for doing | |
732 | * local interrupts, but local timer interrupts can be emulated by | |
733 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
734 | * | |
735 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
736 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
737 | */ | |
75604d7f | 738 | void smp_apic_timer_interrupt(struct pt_regs *regs) |
e05d723f TG |
739 | { |
740 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1da177e4 LT |
741 | |
742 | /* | |
e05d723f TG |
743 | * NOTE! We'd better ACK the irq immediately, |
744 | * because timer handling can be slow. | |
1da177e4 | 745 | */ |
e05d723f | 746 | ack_APIC_irq(); |
1a75a3f0 | 747 | /* |
e05d723f TG |
748 | * update_process_times() expects us to have done irq_enter(). |
749 | * Besides, if we don't timer interrupts ignore the global | |
750 | * interrupt lock, which is the WrongThing (tm) to do. | |
1a75a3f0 | 751 | */ |
6460bc73 CG |
752 | #ifdef CONFIG_X86_64 |
753 | exit_idle(); | |
754 | #endif | |
e05d723f | 755 | irq_enter(); |
e9e2cdb4 | 756 | local_apic_timer_interrupt(); |
e05d723f | 757 | irq_exit(); |
1a75a3f0 | 758 | |
e9e2cdb4 | 759 | set_irq_regs(old_regs); |
e05d723f TG |
760 | } |
761 | ||
762 | int setup_profiling_timer(unsigned int multiplier) | |
763 | { | |
764 | return -EINVAL; | |
765 | } | |
766 | ||
767 | /* | |
768 | * Local APIC start and shutdown | |
769 | */ | |
770 | ||
771 | /** | |
772 | * clear_local_APIC - shutdown the local APIC | |
773 | * | |
774 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
775 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
776 | * leftovers during boot. | |
777 | */ | |
778 | void clear_local_APIC(void) | |
779 | { | |
d3432896 | 780 | int maxlvt; |
0e078e2f | 781 | u32 v; |
1da177e4 | 782 | |
d3432896 AK |
783 | /* APIC hasn't been mapped yet */ |
784 | if (!apic_phys) | |
785 | return; | |
786 | ||
787 | maxlvt = lapic_get_maxlvt(); | |
1da177e4 | 788 | /* |
e05d723f TG |
789 | * Masking an LVT entry can trigger a local APIC error |
790 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1da177e4 | 791 | */ |
e05d723f TG |
792 | if (maxlvt >= 3) { |
793 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
593f4a78 | 794 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
e05d723f | 795 | } |
1da177e4 | 796 | /* |
e05d723f TG |
797 | * Careful: we have to set masks only first to deassert |
798 | * any level-triggered sources. | |
1da177e4 | 799 | */ |
e05d723f | 800 | v = apic_read(APIC_LVTT); |
593f4a78 | 801 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
e05d723f | 802 | v = apic_read(APIC_LVT0); |
593f4a78 | 803 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
e05d723f | 804 | v = apic_read(APIC_LVT1); |
593f4a78 | 805 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
e05d723f TG |
806 | if (maxlvt >= 4) { |
807 | v = apic_read(APIC_LVTPC); | |
593f4a78 | 808 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
1da177e4 | 809 | } |
1da177e4 | 810 | |
e05d723f | 811 | /* lets not touch this if we didn't frob it */ |
6764014b | 812 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) |
e05d723f TG |
813 | if (maxlvt >= 5) { |
814 | v = apic_read(APIC_LVTTHMR); | |
593f4a78 | 815 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); |
e05d723f TG |
816 | } |
817 | #endif | |
1da177e4 | 818 | /* |
e05d723f | 819 | * Clean APIC state for other OSs: |
1da177e4 | 820 | */ |
593f4a78 MR |
821 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
822 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
823 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
e05d723f | 824 | if (maxlvt >= 3) |
593f4a78 | 825 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
e05d723f | 826 | if (maxlvt >= 4) |
593f4a78 | 827 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
1da177e4 | 828 | |
e05d723f TG |
829 | /* Integrated APIC (!82489DX) ? */ |
830 | if (lapic_is_integrated()) { | |
1da177e4 | 831 | if (maxlvt > 3) |
e05d723f | 832 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
1da177e4 | 833 | apic_write(APIC_ESR, 0); |
e05d723f | 834 | apic_read(APIC_ESR); |
1da177e4 | 835 | } |
e05d723f | 836 | } |
1da177e4 | 837 | |
e05d723f TG |
838 | /** |
839 | * disable_local_APIC - clear and disable the local APIC | |
840 | */ | |
841 | void disable_local_APIC(void) | |
842 | { | |
990b183e | 843 | unsigned int value; |
e05d723f TG |
844 | |
845 | clear_local_APIC(); | |
846 | ||
847 | /* | |
848 | * Disable APIC (implies clearing of registers | |
849 | * for 82489DX!). | |
850 | */ | |
851 | value = apic_read(APIC_SPIV); | |
852 | value &= ~APIC_SPIV_APIC_ENABLED; | |
593f4a78 | 853 | apic_write(APIC_SPIV, value); |
e05d723f | 854 | |
990b183e | 855 | #ifdef CONFIG_X86_32 |
e05d723f TG |
856 | /* |
857 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
858 | * restore the disabled state. | |
859 | */ | |
860 | if (enabled_via_apicbase) { | |
861 | unsigned int l, h; | |
862 | ||
863 | rdmsr(MSR_IA32_APICBASE, l, h); | |
864 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
865 | wrmsr(MSR_IA32_APICBASE, l, h); | |
866 | } | |
990b183e | 867 | #endif |
1da177e4 LT |
868 | } |
869 | ||
870 | /* | |
e05d723f TG |
871 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
872 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
873 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
77f72b19 | 874 | * for the case where Linux didn't enable the LAPIC. |
1da177e4 LT |
875 | */ |
876 | void lapic_shutdown(void) | |
877 | { | |
67963132 MS |
878 | unsigned long flags; |
879 | ||
77f72b19 | 880 | if (!cpu_has_apic) |
1da177e4 LT |
881 | return; |
882 | ||
67963132 | 883 | local_irq_save(flags); |
77f72b19 | 884 | |
fe4024dc CG |
885 | #ifdef CONFIG_X86_32 |
886 | if (!enabled_via_apicbase) | |
9ce122c6 | 887 | clear_local_APIC(); |
fe4024dc CG |
888 | else |
889 | #endif | |
77f72b19 ZM |
890 | disable_local_APIC(); |
891 | ||
77f72b19 | 892 | |
67963132 | 893 | local_irq_restore(flags); |
1da177e4 LT |
894 | } |
895 | ||
e05d723f TG |
896 | /* |
897 | * This is to verify that we're looking at a real local APIC. | |
898 | * Check these against your board if the CPUs aren't getting | |
899 | * started for no apparent reason. | |
900 | */ | |
901 | int __init verify_local_APIC(void) | |
1da177e4 | 902 | { |
e05d723f | 903 | unsigned int reg0, reg1; |
1da177e4 | 904 | |
e05d723f TG |
905 | /* |
906 | * The version register is read-only in a real APIC. | |
907 | */ | |
908 | reg0 = apic_read(APIC_LVR); | |
909 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
910 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
911 | reg1 = apic_read(APIC_LVR); | |
912 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
913 | ||
914 | /* | |
915 | * The two version reads above should print the same | |
916 | * numbers. If the second one is different, then we | |
917 | * poke at a non-APIC. | |
918 | */ | |
919 | if (reg1 != reg0) | |
1da177e4 LT |
920 | return 0; |
921 | ||
e05d723f TG |
922 | /* |
923 | * Check if the version looks reasonably. | |
924 | */ | |
925 | reg1 = GET_APIC_VERSION(reg0); | |
926 | if (reg1 == 0x00 || reg1 == 0xff) | |
927 | return 0; | |
928 | reg1 = lapic_get_maxlvt(); | |
929 | if (reg1 < 0x02 || reg1 == 0xff) | |
930 | return 0; | |
f990fff4 | 931 | |
e05d723f TG |
932 | /* |
933 | * The ID register is read/write in a real APIC. | |
934 | */ | |
935 | reg0 = apic_read(APIC_ID); | |
936 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
c93baa1a CG |
937 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); |
938 | reg1 = apic_read(APIC_ID); | |
939 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
940 | apic_write(APIC_ID, reg0); | |
941 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
942 | return 0; | |
e05d723f TG |
943 | |
944 | /* | |
945 | * The next two are just to see if we have sane values. | |
946 | * They're only really relevant if we're in Virtual Wire | |
947 | * compatibility mode, but most boxes are anymore. | |
948 | */ | |
949 | reg0 = apic_read(APIC_LVT0); | |
950 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
951 | reg1 = apic_read(APIC_LVT1); | |
952 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
953 | ||
954 | return 1; | |
1da177e4 LT |
955 | } |
956 | ||
e05d723f TG |
957 | /** |
958 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
959 | */ | |
960 | void __init sync_Arb_IDs(void) | |
1da177e4 | 961 | { |
e05d723f TG |
962 | /* |
963 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
964 | * needed on AMD. | |
965 | */ | |
f44d9efd | 966 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
e05d723f | 967 | return; |
6f6da97f | 968 | |
e05d723f TG |
969 | /* |
970 | * Wait for idle. | |
971 | */ | |
972 | apic_wait_icr_idle(); | |
1da177e4 | 973 | |
e05d723f | 974 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
6f6da97f CG |
975 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
976 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
e05d723f | 977 | } |
1da177e4 | 978 | |
e05d723f TG |
979 | /* |
980 | * An initial setup of the virtual wire mode. | |
981 | */ | |
982 | void __init init_bsp_APIC(void) | |
983 | { | |
638c0411 | 984 | unsigned int value; |
f990fff4 | 985 | |
e05d723f TG |
986 | /* |
987 | * Don't do the setup now if we have a SMP BIOS as the | |
988 | * through-I/O-APIC virtual wire mode might be active. | |
989 | */ | |
990 | if (smp_found_config || !cpu_has_apic) | |
991 | return; | |
1da177e4 LT |
992 | |
993 | /* | |
e05d723f | 994 | * Do not trust the local APIC being empty at bootup. |
1da177e4 | 995 | */ |
e05d723f | 996 | clear_local_APIC(); |
1da177e4 | 997 | |
e05d723f TG |
998 | /* |
999 | * Enable APIC. | |
1000 | */ | |
1001 | value = apic_read(APIC_SPIV); | |
1002 | value &= ~APIC_VECTOR_MASK; | |
1003 | value |= APIC_SPIV_APIC_ENABLED; | |
1004 | ||
638c0411 | 1005 | #ifdef CONFIG_X86_32 |
e05d723f TG |
1006 | /* This bit is reserved on P4/Xeon and should be cleared */ |
1007 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1008 | (boot_cpu_data.x86 == 15)) | |
1009 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1010 | else | |
638c0411 | 1011 | #endif |
e05d723f TG |
1012 | value |= APIC_SPIV_FOCUS_DISABLED; |
1013 | value |= SPURIOUS_APIC_VECTOR; | |
593f4a78 | 1014 | apic_write(APIC_SPIV, value); |
e05d723f TG |
1015 | |
1016 | /* | |
1017 | * Set up the virtual wire mode. | |
1018 | */ | |
593f4a78 | 1019 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
e05d723f TG |
1020 | value = APIC_DM_NMI; |
1021 | if (!lapic_is_integrated()) /* 82489DX */ | |
1022 | value |= APIC_LVT_LEVEL_TRIGGER; | |
593f4a78 | 1023 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1024 | } |
1025 | ||
a4928cff | 1026 | static void __cpuinit lapic_setup_esr(void) |
df7939ae GOC |
1027 | { |
1028 | unsigned long oldvalue, value, maxlvt; | |
1029 | if (lapic_is_integrated() && !esr_disable) { | |
c43da2f5 CG |
1030 | if (esr_disable) { |
1031 | /* | |
1032 | * Something untraceable is creating bad interrupts on | |
1033 | * secondary quads ... for the moment, just leave the | |
1034 | * ESR disabled - we can't do anything useful with the | |
1035 | * errors anyway - mbligh | |
1036 | */ | |
1037 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
1038 | return; | |
1039 | } | |
df7939ae GOC |
1040 | /* !82489DX */ |
1041 | maxlvt = lapic_get_maxlvt(); | |
1042 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1043 | apic_write(APIC_ESR, 0); | |
1044 | oldvalue = apic_read(APIC_ESR); | |
1045 | ||
1046 | /* enables sending errors */ | |
1047 | value = ERROR_APIC_VECTOR; | |
593f4a78 | 1048 | apic_write(APIC_LVTERR, value); |
df7939ae GOC |
1049 | /* |
1050 | * spec says clear errors after enabling vector. | |
1051 | */ | |
1052 | if (maxlvt > 3) | |
1053 | apic_write(APIC_ESR, 0); | |
1054 | value = apic_read(APIC_ESR); | |
1055 | if (value != oldvalue) | |
1056 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1057 | "vector: 0x%08lx after: 0x%08lx\n", | |
1058 | oldvalue, value); | |
1059 | } else { | |
c43da2f5 | 1060 | printk(KERN_INFO "No ESR for 82489DX.\n"); |
df7939ae GOC |
1061 | } |
1062 | } | |
1063 | ||
1064 | ||
e05d723f TG |
1065 | /** |
1066 | * setup_local_APIC - setup the local APIC | |
1da177e4 | 1067 | */ |
d5337983 | 1068 | void __cpuinit setup_local_APIC(void) |
e05d723f | 1069 | { |
89c38c28 | 1070 | unsigned int value; |
e05d723f | 1071 | int i, j; |
1da177e4 | 1072 | |
89c38c28 | 1073 | #ifdef CONFIG_X86_32 |
e05d723f TG |
1074 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
1075 | if (esr_disable) { | |
1076 | apic_write(APIC_ESR, 0); | |
1077 | apic_write(APIC_ESR, 0); | |
1078 | apic_write(APIC_ESR, 0); | |
1079 | apic_write(APIC_ESR, 0); | |
1080 | } | |
89c38c28 | 1081 | #endif |
1da177e4 | 1082 | |
89c38c28 | 1083 | preempt_disable(); |
1da177e4 | 1084 | |
e05d723f TG |
1085 | /* |
1086 | * Double-check whether this APIC is really registered. | |
89c38c28 | 1087 | * This is meaningless in clustered apic mode, so we skip it. |
e05d723f TG |
1088 | */ |
1089 | if (!apic_id_registered()) | |
89c38c28 | 1090 | BUG(); |
1da177e4 | 1091 | |
e05d723f TG |
1092 | /* |
1093 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1094 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1095 | * document number 292116). So here it goes... | |
1096 | */ | |
1097 | init_apic_ldr(); | |
1da177e4 | 1098 | |
e05d723f TG |
1099 | /* |
1100 | * Set Task Priority to 'accept all'. We never change this | |
1101 | * later on. | |
1102 | */ | |
1103 | value = apic_read(APIC_TASKPRI); | |
1104 | value &= ~APIC_TPRI_MASK; | |
593f4a78 | 1105 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1106 | |
e05d723f TG |
1107 | /* |
1108 | * After a crash, we no longer service the interrupts and a pending | |
1109 | * interrupt from previous kernel might still have ISR bit set. | |
1110 | * | |
1111 | * Most probably by now CPU has serviced that pending interrupt and | |
1112 | * it might not have done the ack_APIC_irq() because it thought, | |
1113 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1114 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1115 | * the interrupt. Hence a vector might get locked. It was noticed | |
1116 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1117 | */ | |
1118 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1119 | value = apic_read(APIC_ISR + i*0x10); | |
1120 | for (j = 31; j >= 0; j--) { | |
1121 | if (value & (1<<j)) | |
1122 | ack_APIC_irq(); | |
1123 | } | |
1124 | } | |
1da177e4 | 1125 | |
e05d723f TG |
1126 | /* |
1127 | * Now that we are all set up, enable the APIC | |
1128 | */ | |
1129 | value = apic_read(APIC_SPIV); | |
1130 | value &= ~APIC_VECTOR_MASK; | |
1131 | /* | |
1132 | * Enable APIC | |
1133 | */ | |
1134 | value |= APIC_SPIV_APIC_ENABLED; | |
1da177e4 | 1135 | |
89c38c28 | 1136 | #ifdef CONFIG_X86_32 |
e05d723f TG |
1137 | /* |
1138 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1139 | * certain networking cards. If high frequency interrupts are | |
1140 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1141 | * entry is masked/unmasked at a high rate as well then sooner or | |
1142 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1143 | * from the device. If focus CPU is disabled then the hang goes | |
1144 | * away, oh well :-( | |
1145 | * | |
1146 | * [ This bug can be reproduced easily with a level-triggered | |
1147 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1148 | * BX chipset. ] | |
1149 | */ | |
1150 | /* | |
1151 | * Actually disabling the focus CPU check just makes the hang less | |
1152 | * frequent as it makes the interrupt distributon model be more | |
1153 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1154 | * See also the comment in end_level_ioapic_irq(). --macro | |
1155 | */ | |
1da177e4 | 1156 | |
89c38c28 CG |
1157 | /* |
1158 | * - enable focus processor (bit==0) | |
1159 | * - 64bit mode always use processor focus | |
1160 | * so no need to set it | |
1161 | */ | |
e05d723f | 1162 | value &= ~APIC_SPIV_FOCUS_DISABLED; |
89c38c28 | 1163 | #endif |
1da177e4 | 1164 | |
e05d723f TG |
1165 | /* |
1166 | * Set spurious IRQ vector | |
1167 | */ | |
1168 | value |= SPURIOUS_APIC_VECTOR; | |
593f4a78 | 1169 | apic_write(APIC_SPIV, value); |
e05d723f TG |
1170 | |
1171 | /* | |
1172 | * Set up LVT0, LVT1: | |
1173 | * | |
1174 | * set up through-local-APIC on the BP's LINT0. This is not | |
27b46d76 | 1175 | * strictly necessary in pure symmetric-IO mode, but sometimes |
e05d723f TG |
1176 | * we delegate interrupts to the 8259A. |
1177 | */ | |
1178 | /* | |
1179 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1180 | */ | |
1181 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
1182 | if (!smp_processor_id() && (pic_mode || !value)) { | |
1183 | value = APIC_DM_EXTINT; | |
1184 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
1185 | smp_processor_id()); | |
1186 | } else { | |
1187 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
1188 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
1189 | smp_processor_id()); | |
1190 | } | |
593f4a78 | 1191 | apic_write(APIC_LVT0, value); |
e05d723f TG |
1192 | |
1193 | /* | |
1194 | * only the BP should see the LINT1 NMI signal, obviously. | |
1195 | */ | |
1196 | if (!smp_processor_id()) | |
1197 | value = APIC_DM_NMI; | |
1198 | else | |
1199 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 | 1200 | if (!lapic_is_integrated()) /* 82489DX */ |
e05d723f | 1201 | value |= APIC_LVT_LEVEL_TRIGGER; |
593f4a78 | 1202 | apic_write(APIC_LVT1, value); |
89c38c28 CG |
1203 | |
1204 | preempt_enable(); | |
ac60aae5 | 1205 | } |
e05d723f | 1206 | |
ac60aae5 GOC |
1207 | void __cpuinit end_local_APIC_setup(void) |
1208 | { | |
ac60aae5 | 1209 | lapic_setup_esr(); |
fa6b95fc CG |
1210 | |
1211 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1212 | { |
1213 | unsigned int value; | |
1214 | /* Disable the local apic timer */ | |
1215 | value = apic_read(APIC_LVTT); | |
1216 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1217 | apic_write(APIC_LVTT, value); | |
1218 | } | |
fa6b95fc | 1219 | #endif |
e9e2cdb4 | 1220 | |
e05d723f TG |
1221 | setup_apic_nmi_watchdog(NULL); |
1222 | apic_pm_activate(); | |
1da177e4 LT |
1223 | } |
1224 | ||
be7a656f YL |
1225 | #ifdef CONFIG_X86_64 |
1226 | /* | |
1227 | * Detect and enable local APICs on non-SMP boards. | |
1228 | * Original code written by Keir Fraser. | |
1229 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
1230 | * not correctly set up (usually the APIC timer won't work etc.) | |
1231 | */ | |
1232 | static int __init detect_init_APIC(void) | |
1233 | { | |
1234 | if (!cpu_has_apic) { | |
1235 | printk(KERN_INFO "No local APIC present\n"); | |
1236 | return -1; | |
1237 | } | |
1238 | ||
1239 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1240 | boot_cpu_physical_apicid = 0; | |
1241 | return 0; | |
1242 | } | |
1243 | #else | |
e05d723f TG |
1244 | /* |
1245 | * Detect and initialize APIC | |
1246 | */ | |
e83a5fdc | 1247 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1248 | { |
1249 | u32 h, l, features; | |
1da177e4 LT |
1250 | |
1251 | /* Disabled by kernel option? */ | |
914bebfa | 1252 | if (disable_apic) |
1da177e4 LT |
1253 | return -1; |
1254 | ||
1da177e4 LT |
1255 | switch (boot_cpu_data.x86_vendor) { |
1256 | case X86_VENDOR_AMD: | |
1257 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
e05d723f | 1258 | (boot_cpu_data.x86 == 15)) |
1da177e4 LT |
1259 | break; |
1260 | goto no_apic; | |
1261 | case X86_VENDOR_INTEL: | |
1262 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1263 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1264 | break; | |
1265 | goto no_apic; | |
1266 | default: | |
1267 | goto no_apic; | |
1268 | } | |
1269 | ||
1270 | if (!cpu_has_apic) { | |
1271 | /* | |
e05d723f TG |
1272 | * Over-ride BIOS and try to enable the local APIC only if |
1273 | * "lapic" specified. | |
1da177e4 | 1274 | */ |
914bebfa | 1275 | if (!force_enable_local_apic) { |
e05d723f | 1276 | printk(KERN_INFO "Local APIC disabled by BIOS -- " |
1da177e4 LT |
1277 | "you can enable it with \"lapic\"\n"); |
1278 | return -1; | |
1279 | } | |
1280 | /* | |
e05d723f TG |
1281 | * Some BIOSes disable the local APIC in the APIC_BASE |
1282 | * MSR. This can only be done in software for Intel P6 or later | |
1283 | * and AMD K7 (Model > 1) or later. | |
1da177e4 LT |
1284 | */ |
1285 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1286 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
e05d723f TG |
1287 | printk(KERN_INFO |
1288 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1da177e4 LT |
1289 | l &= ~MSR_IA32_APICBASE_BASE; |
1290 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1291 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1292 | enabled_via_apicbase = 1; | |
1293 | } | |
1294 | } | |
1295 | /* | |
1296 | * The APIC feature bit should now be enabled | |
1297 | * in `cpuid' | |
1298 | */ | |
1299 | features = cpuid_edx(1); | |
1300 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
e05d723f | 1301 | printk(KERN_WARNING "Could not enable APIC!\n"); |
1da177e4 LT |
1302 | return -1; |
1303 | } | |
53756d37 | 1304 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1da177e4 LT |
1305 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
1306 | ||
1307 | /* The BIOS may have set up the APIC at some other address */ | |
1308 | rdmsr(MSR_IA32_APICBASE, l, h); | |
e05d723f TG |
1309 | if (l & MSR_IA32_APICBASE_ENABLE) |
1310 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1da177e4 | 1311 | |
e05d723f | 1312 | printk(KERN_INFO "Found and enabled local APIC!\n"); |
1da177e4 | 1313 | |
e05d723f | 1314 | apic_pm_activate(); |
1da177e4 | 1315 | |
e05d723f | 1316 | return 0; |
1da177e4 | 1317 | |
e05d723f TG |
1318 | no_apic: |
1319 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1320 | return -1; | |
1321 | } | |
be7a656f | 1322 | #endif |
1da177e4 | 1323 | |
f28c0ae2 YL |
1324 | #ifdef CONFIG_X86_64 |
1325 | void __init early_init_lapic_mapping(void) | |
1326 | { | |
1327 | unsigned long phys_addr; | |
1328 | ||
1329 | /* | |
1330 | * If no local APIC can be found then go out | |
1331 | * : it means there is no mpatable and MADT | |
1332 | */ | |
1333 | if (!smp_found_config) | |
1334 | return; | |
1335 | ||
1336 | phys_addr = mp_lapic_addr; | |
1337 | ||
1338 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); | |
1339 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", | |
1340 | APIC_BASE, phys_addr); | |
1341 | ||
1342 | /* | |
1343 | * Fetch the APIC ID of the BSP in case we have a | |
1344 | * default configuration (or the MP table is broken). | |
1345 | */ | |
1346 | boot_cpu_physical_apicid = read_apic_id(); | |
1347 | } | |
1348 | #endif | |
1349 | ||
e05d723f TG |
1350 | /** |
1351 | * init_apic_mappings - initialize APIC mappings | |
1352 | */ | |
1353 | void __init init_apic_mappings(void) | |
1da177e4 | 1354 | { |
1da177e4 | 1355 | /* |
e05d723f TG |
1356 | * If no local APIC can be found then set up a fake all |
1357 | * zeroes page to simulate the local APIC and another | |
1358 | * one for the IO-APIC. | |
1da177e4 | 1359 | */ |
e05d723f TG |
1360 | if (!smp_found_config && detect_init_APIC()) { |
1361 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1362 | apic_phys = __pa(apic_phys); | |
1363 | } else | |
1364 | apic_phys = mp_lapic_addr; | |
1da177e4 | 1365 | |
e05d723f | 1366 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
f28c0ae2 YL |
1367 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
1368 | APIC_BASE, apic_phys); | |
1da177e4 | 1369 | |
e05d723f TG |
1370 | /* |
1371 | * Fetch the APIC ID of the BSP in case we have a | |
1372 | * default configuration (or the MP table is broken). | |
1373 | */ | |
1374 | if (boot_cpu_physical_apicid == -1U) | |
4c9961d5 | 1375 | boot_cpu_physical_apicid = read_apic_id(); |
1da177e4 LT |
1376 | } |
1377 | ||
e05d723f TG |
1378 | /* |
1379 | * This initializes the IO-APIC and APIC hardware if this is | |
1380 | * a UP kernel. | |
1381 | */ | |
e81b2c62 AS |
1382 | int apic_version[MAX_APICS]; |
1383 | ||
e83a5fdc | 1384 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1385 | { |
fa2bd35a YL |
1386 | #ifdef CONFIG_X86_64 |
1387 | if (disable_apic) { | |
1388 | printk(KERN_INFO "Apic disabled\n"); | |
1389 | return -1; | |
1390 | } | |
1391 | if (!cpu_has_apic) { | |
1392 | disable_apic = 1; | |
1393 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1394 | return -1; | |
1395 | } | |
1396 | #else | |
e05d723f TG |
1397 | if (!smp_found_config && !cpu_has_apic) |
1398 | return -1; | |
6eb0a0fd | 1399 | |
e05d723f TG |
1400 | /* |
1401 | * Complain if the BIOS pretends there is one. | |
1402 | */ | |
1403 | if (!cpu_has_apic && | |
1404 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1405 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1406 | boot_cpu_physical_apicid); | |
53756d37 | 1407 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
e05d723f | 1408 | return -1; |
6eb0a0fd | 1409 | } |
fa2bd35a | 1410 | #endif |
6eb0a0fd | 1411 | |
fa2bd35a YL |
1412 | #ifdef HAVE_X2APIC |
1413 | enable_IR_x2apic(); | |
1414 | #endif | |
1415 | #ifdef CONFIG_X86_64 | |
1416 | setup_apic_routing(); | |
1417 | #endif | |
e05d723f | 1418 | verify_local_APIC(); |
e05d723f | 1419 | connect_bsp_APIC(); |
6eb0a0fd | 1420 | |
fa2bd35a YL |
1421 | #ifdef CONFIG_X86_64 |
1422 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); | |
1423 | #else | |
e05d723f TG |
1424 | /* |
1425 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1426 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1427 | * might be zero if read from MP tables. Get it from LAPIC. | |
1428 | */ | |
fa2bd35a | 1429 | # ifdef CONFIG_CRASH_DUMP |
4c9961d5 | 1430 | boot_cpu_physical_apicid = read_apic_id(); |
fa2bd35a | 1431 | # endif |
e05d723f | 1432 | #endif |
b6df1b8b | 1433 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
e05d723f | 1434 | setup_local_APIC(); |
1da177e4 | 1435 | |
fa2bd35a YL |
1436 | #ifdef CONFIG_X86_64 |
1437 | /* | |
1438 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1439 | * We need clear_IO_APIC before enabling vector on BP | |
1440 | */ | |
1441 | if (!skip_ioapic_setup && nr_ioapics) | |
1442 | enable_IO_APIC(); | |
1443 | #endif | |
1444 | ||
acae7d90 MR |
1445 | #ifdef CONFIG_X86_IO_APIC |
1446 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) | |
1447 | #endif | |
1448 | localise_nmi_watchdog(); | |
ac60aae5 | 1449 | end_local_APIC_setup(); |
fa2bd35a | 1450 | |
e05d723f | 1451 | #ifdef CONFIG_X86_IO_APIC |
fa2bd35a YL |
1452 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1453 | setup_IO_APIC(); | |
1454 | # ifdef CONFIG_X86_64 | |
1455 | else | |
1456 | nr_ioapics = 0; | |
1457 | # endif | |
1da177e4 | 1458 | #endif |
fa2bd35a YL |
1459 | |
1460 | #ifdef CONFIG_X86_64 | |
1461 | setup_boot_APIC_clock(); | |
1462 | check_nmi_watchdog(); | |
1463 | #else | |
e05d723f | 1464 | setup_boot_clock(); |
fa2bd35a | 1465 | #endif |
1da177e4 | 1466 | |
e05d723f | 1467 | return 0; |
1da177e4 LT |
1468 | } |
1469 | ||
e05d723f TG |
1470 | /* |
1471 | * Local APIC interrupts | |
1472 | */ | |
1473 | ||
1da177e4 LT |
1474 | /* |
1475 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1476 | */ | |
e9e2cdb4 | 1477 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1478 | { |
1479 | unsigned long v; | |
1480 | ||
1481 | irq_enter(); | |
1482 | /* | |
1483 | * Check if this really is a spurious interrupt and ACK it | |
1484 | * if it is a vectored one. Just in case... | |
1485 | * Spurious interrupts should not be ACKed. | |
1486 | */ | |
1487 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1488 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1489 | ack_APIC_irq(); | |
1490 | ||
1491 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
e05d723f TG |
1492 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " |
1493 | "should never happen.\n", smp_processor_id()); | |
38e760a1 | 1494 | __get_cpu_var(irq_stat).irq_spurious_count++; |
1da177e4 LT |
1495 | irq_exit(); |
1496 | } | |
1497 | ||
1498 | /* | |
1499 | * This interrupt should never happen with our APIC/SMP architecture | |
1500 | */ | |
e9e2cdb4 | 1501 | void smp_error_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1502 | { |
1503 | unsigned long v, v1; | |
1504 | ||
1505 | irq_enter(); | |
1506 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1507 | v = apic_read(APIC_ESR); | |
1508 | apic_write(APIC_ESR, 0); | |
1509 | v1 = apic_read(APIC_ESR); | |
1510 | ack_APIC_irq(); | |
1511 | atomic_inc(&irq_err_count); | |
1512 | ||
1513 | /* Here is what the APIC error bits mean: | |
1514 | 0: Send CS error | |
1515 | 1: Receive CS error | |
1516 | 2: Send accept error | |
1517 | 3: Receive accept error | |
1518 | 4: Reserved | |
1519 | 5: Send illegal vector | |
1520 | 6: Received illegal vector | |
1521 | 7: Illegal register address | |
1522 | */ | |
ff8a03a6 | 1523 | printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", |
e05d723f | 1524 | smp_processor_id(), v , v1); |
1da177e4 LT |
1525 | irq_exit(); |
1526 | } | |
1527 | ||
e05d723f TG |
1528 | /** |
1529 | * connect_bsp_APIC - attach the APIC to the interrupt system | |
1530 | */ | |
1531 | void __init connect_bsp_APIC(void) | |
1532 | { | |
36c9d674 | 1533 | #ifdef CONFIG_X86_32 |
e05d723f TG |
1534 | if (pic_mode) { |
1535 | /* | |
1536 | * Do not trust the local APIC being empty at bootup. | |
1537 | */ | |
1538 | clear_local_APIC(); | |
1539 | /* | |
1540 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1541 | * local APIC to INT and NMI lines. | |
1542 | */ | |
1543 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1544 | "enabling APIC mode.\n"); | |
1545 | outb(0x70, 0x22); | |
1546 | outb(0x01, 0x23); | |
1da177e4 | 1547 | } |
36c9d674 | 1548 | #endif |
e05d723f TG |
1549 | enable_apic_mode(); |
1550 | } | |
1da177e4 | 1551 | |
e05d723f TG |
1552 | /** |
1553 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1554 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1555 | * | |
1556 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1557 | * APIC is disabled. | |
1558 | */ | |
1559 | void disconnect_bsp_APIC(int virt_wire_setup) | |
1560 | { | |
1b4ee4e4 CG |
1561 | unsigned int value; |
1562 | ||
c177b0bc | 1563 | #ifdef CONFIG_X86_32 |
e05d723f TG |
1564 | if (pic_mode) { |
1565 | /* | |
1566 | * Put the board back into PIC mode (has an effect only on | |
1567 | * certain older boards). Note that APIC interrupts, including | |
1568 | * IPIs, won't work beyond this point! The only exception are | |
1569 | * INIT IPIs. | |
1570 | */ | |
1571 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1572 | "entering PIC mode.\n"); | |
1573 | outb(0x70, 0x22); | |
1574 | outb(0x00, 0x23); | |
c177b0bc CG |
1575 | return; |
1576 | } | |
1577 | #endif | |
1da177e4 | 1578 | |
c177b0bc | 1579 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1580 | |
c177b0bc CG |
1581 | /* For the spurious interrupt use vector F, and enable it */ |
1582 | value = apic_read(APIC_SPIV); | |
1583 | value &= ~APIC_VECTOR_MASK; | |
1584 | value |= APIC_SPIV_APIC_ENABLED; | |
1585 | value |= 0xf; | |
1586 | apic_write(APIC_SPIV, value); | |
1da177e4 | 1587 | |
c177b0bc | 1588 | if (!virt_wire_setup) { |
e05d723f | 1589 | /* |
c177b0bc CG |
1590 | * For LVT0 make it edge triggered, active high, |
1591 | * external and enabled | |
e05d723f | 1592 | */ |
c177b0bc CG |
1593 | value = apic_read(APIC_LVT0); |
1594 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
e05d723f TG |
1595 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
1596 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1597 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
c177b0bc CG |
1598 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
1599 | apic_write(APIC_LVT0, value); | |
1600 | } else { | |
1601 | /* Disable LVT0 */ | |
1602 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
e05d723f | 1603 | } |
1da177e4 | 1604 | |
c177b0bc CG |
1605 | /* |
1606 | * For LVT1 make it edge triggered, active high, | |
1607 | * nmi and enabled | |
1608 | */ | |
1609 | value = apic_read(APIC_LVT1); | |
1610 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1611 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1612 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1613 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1614 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1615 | apic_write(APIC_LVT1, value); | |
e05d723f | 1616 | } |
903dcb5a AS |
1617 | |
1618 | void __cpuinit generic_processor_info(int apicid, int version) | |
1619 | { | |
1620 | int cpu; | |
1621 | cpumask_t tmp_map; | |
903dcb5a AS |
1622 | |
1623 | /* | |
1624 | * Validate version | |
1625 | */ | |
1626 | if (version == 0x0) { | |
1627 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1628 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1629 | version); | |
1630 | version = 0x10; | |
1631 | } | |
1632 | apic_version[apicid] = version; | |
1633 | ||
903dcb5a AS |
1634 | if (num_processors >= NR_CPUS) { |
1635 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1636 | " Processor ignored.\n", NR_CPUS); | |
1637 | return; | |
1638 | } | |
1639 | ||
903dcb5a AS |
1640 | num_processors++; |
1641 | cpus_complement(tmp_map, cpu_present_map); | |
1642 | cpu = first_cpu(tmp_map); | |
1643 | ||
1b313f4a CG |
1644 | physid_set(apicid, phys_cpu_present_map); |
1645 | if (apicid == boot_cpu_physical_apicid) { | |
903dcb5a AS |
1646 | /* |
1647 | * x86_bios_cpu_apicid is required to have processors listed | |
1648 | * in same order as logical cpu numbers. Hence the first | |
1649 | * entry is BSP, and so on. | |
1650 | */ | |
1651 | cpu = 0; | |
1b313f4a | 1652 | } |
e0da3364 YL |
1653 | if (apicid > max_physical_apicid) |
1654 | max_physical_apicid = apicid; | |
1655 | ||
1b313f4a | 1656 | #ifdef CONFIG_X86_32 |
903dcb5a AS |
1657 | /* |
1658 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1659 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1660 | * before this can be done without some confusion. | |
1661 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1662 | * - Ashok Raj <ashok.raj@intel.com> | |
1663 | */ | |
e0da3364 | 1664 | if (max_physical_apicid >= 8) { |
903dcb5a AS |
1665 | switch (boot_cpu_data.x86_vendor) { |
1666 | case X86_VENDOR_INTEL: | |
1667 | if (!APIC_XAPIC(version)) { | |
1668 | def_to_bigsmp = 0; | |
1669 | break; | |
1670 | } | |
1671 | /* If P4 and above fall through */ | |
1672 | case X86_VENDOR_AMD: | |
1673 | def_to_bigsmp = 1; | |
1674 | } | |
1675 | } | |
1b313f4a CG |
1676 | #endif |
1677 | ||
1678 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
903dcb5a | 1679 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1680 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1681 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1682 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
903dcb5a AS |
1683 | |
1684 | cpu_to_apicid[cpu] = apicid; | |
1685 | bios_cpu_apicid[cpu] = apicid; | |
1686 | } else { | |
1687 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1688 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1689 | } | |
1690 | #endif | |
1b313f4a | 1691 | |
903dcb5a AS |
1692 | cpu_set(cpu, cpu_possible_map); |
1693 | cpu_set(cpu, cpu_present_map); | |
1694 | } | |
1695 | ||
3491998d YL |
1696 | #ifdef CONFIG_X86_64 |
1697 | int hard_smp_processor_id(void) | |
1698 | { | |
1699 | return read_apic_id(); | |
1700 | } | |
1701 | #endif | |
1702 | ||
e05d723f TG |
1703 | /* |
1704 | * Power management | |
1705 | */ | |
1706 | #ifdef CONFIG_PM | |
1707 | ||
1708 | static struct { | |
274cfe59 CG |
1709 | /* |
1710 | * 'active' is true if the local APIC was enabled by us and | |
1711 | * not the BIOS; this signifies that we are also responsible | |
1712 | * for disabling it before entering apm/acpi suspend | |
1713 | */ | |
e05d723f TG |
1714 | int active; |
1715 | /* r/w apic fields */ | |
1716 | unsigned int apic_id; | |
1717 | unsigned int apic_taskpri; | |
1718 | unsigned int apic_ldr; | |
1719 | unsigned int apic_dfr; | |
1720 | unsigned int apic_spiv; | |
1721 | unsigned int apic_lvtt; | |
1722 | unsigned int apic_lvtpc; | |
1723 | unsigned int apic_lvt0; | |
1724 | unsigned int apic_lvt1; | |
1725 | unsigned int apic_lvterr; | |
1726 | unsigned int apic_tmict; | |
1727 | unsigned int apic_tdcr; | |
1728 | unsigned int apic_thmr; | |
1729 | } apic_pm_state; | |
1730 | ||
1731 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1732 | { | |
1733 | unsigned long flags; | |
1734 | int maxlvt; | |
1735 | ||
1736 | if (!apic_pm_state.active) | |
1737 | return 0; | |
1738 | ||
1739 | maxlvt = lapic_get_maxlvt(); | |
1740 | ||
1741 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
1742 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1743 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1744 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1745 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1746 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1747 | if (maxlvt >= 4) | |
1748 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1749 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1750 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1751 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1752 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1753 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1754 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
e05d723f TG |
1755 | if (maxlvt >= 5) |
1756 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1da177e4 | 1757 | #endif |
1e4c85f9 | 1758 | |
e05d723f TG |
1759 | local_irq_save(flags); |
1760 | disable_local_APIC(); | |
1761 | local_irq_restore(flags); | |
1e4c85f9 | 1762 | return 0; |
1da177e4 | 1763 | } |
1a3f239d | 1764 | |
e05d723f | 1765 | static int lapic_resume(struct sys_device *dev) |
1a3f239d | 1766 | { |
e05d723f TG |
1767 | unsigned int l, h; |
1768 | unsigned long flags; | |
1769 | int maxlvt; | |
1770 | ||
1771 | if (!apic_pm_state.active) | |
1772 | return 0; | |
1773 | ||
1774 | maxlvt = lapic_get_maxlvt(); | |
1775 | ||
1776 | local_irq_save(flags); | |
1777 | ||
e75bedf4 | 1778 | { |
92206c90 CG |
1779 | /* |
1780 | * Make sure the APICBASE points to the right address | |
1781 | * | |
1782 | * FIXME! This will be wrong if we ever support suspend on | |
1783 | * SMP! We'll need to do this as part of the CPU restore! | |
1784 | */ | |
1785 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1786 | l &= ~MSR_IA32_APICBASE_BASE; | |
1787 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1788 | wrmsr(MSR_IA32_APICBASE, l, h); | |
e75bedf4 | 1789 | } |
e05d723f TG |
1790 | |
1791 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1792 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1793 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1794 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1795 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1796 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1797 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1798 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 1799 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
e05d723f TG |
1800 | if (maxlvt >= 5) |
1801 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1802 | #endif | |
1803 | if (maxlvt >= 4) | |
1804 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1805 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1806 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1807 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1808 | apic_write(APIC_ESR, 0); | |
1809 | apic_read(APIC_ESR); | |
1810 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1811 | apic_write(APIC_ESR, 0); | |
1812 | apic_read(APIC_ESR); | |
92206c90 | 1813 | |
e05d723f | 1814 | local_irq_restore(flags); |
92206c90 | 1815 | |
1a3f239d RR |
1816 | return 0; |
1817 | } | |
1a3f239d | 1818 | |
e05d723f TG |
1819 | /* |
1820 | * This device has no shutdown method - fully functioning local APICs | |
1821 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1822 | */ | |
1823 | ||
1824 | static struct sysdev_class lapic_sysclass = { | |
af5ca3f4 | 1825 | .name = "lapic", |
e05d723f TG |
1826 | .resume = lapic_resume, |
1827 | .suspend = lapic_suspend, | |
1828 | }; | |
1829 | ||
1830 | static struct sys_device device_lapic = { | |
1831 | .id = 0, | |
1832 | .cls = &lapic_sysclass, | |
1833 | }; | |
1834 | ||
457cc52d | 1835 | static void __cpuinit apic_pm_activate(void) |
1a3f239d | 1836 | { |
e05d723f | 1837 | apic_pm_state.active = 1; |
1a3f239d | 1838 | } |
1a3f239d | 1839 | |
e05d723f TG |
1840 | static int __init init_lapic_sysfs(void) |
1841 | { | |
1842 | int error; | |
1843 | ||
1844 | if (!cpu_has_apic) | |
1845 | return 0; | |
1846 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
1847 | ||
1848 | error = sysdev_class_register(&lapic_sysclass); | |
1849 | if (!error) | |
1850 | error = sysdev_register(&device_lapic); | |
1851 | return error; | |
1852 | } | |
1853 | device_initcall(init_lapic_sysfs); | |
1854 | ||
1855 | #else /* CONFIG_PM */ | |
1856 | ||
1857 | static void apic_pm_activate(void) { } | |
1858 | ||
1859 | #endif /* CONFIG_PM */ | |
0e078e2f | 1860 | |
f28c0ae2 YL |
1861 | #ifdef CONFIG_X86_64 |
1862 | /* | |
1863 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
1864 | * | |
1865 | * Thus far, the major user of this is IBM's Summit2 series: | |
1866 | * | |
1867 | * Clustered boxes may have unsynced TSC problems if they are | |
1868 | * multi-chassis. Use available data to take a good guess. | |
1869 | * If in doubt, go HPET. | |
1870 | */ | |
1871 | __cpuinit int apic_is_clustered_box(void) | |
1872 | { | |
1873 | int i, clusters, zeros; | |
1874 | unsigned id; | |
1875 | u16 *bios_cpu_apicid; | |
1876 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); | |
1877 | ||
1878 | /* | |
1879 | * there is not this kind of box with AMD CPU yet. | |
1880 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1881 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
1882 | * vsmp box still need checking... | |
1883 | */ | |
1884 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) | |
1885 | return 0; | |
1886 | ||
1887 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
1888 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); | |
1889 | ||
1890 | for (i = 0; i < NR_CPUS; i++) { | |
1891 | /* are we being called early in kernel startup? */ | |
1892 | if (bios_cpu_apicid) { | |
1893 | id = bios_cpu_apicid[i]; | |
1894 | } | |
1895 | else if (i < nr_cpu_ids) { | |
1896 | if (cpu_present(i)) | |
1897 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1898 | else | |
1899 | continue; | |
1900 | } | |
1901 | else | |
1902 | break; | |
0e078e2f | 1903 | |
f28c0ae2 YL |
1904 | if (id != BAD_APICID) |
1905 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1906 | } | |
1907 | ||
1908 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1909 | * the APIC clusters they have been allocated. Only present CPUs have | |
1910 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. | |
1911 | * Since clusters are allocated sequentially, count zeros only if | |
1912 | * they are bounded by ones. | |
1913 | */ | |
1914 | clusters = 0; | |
1915 | zeros = 0; | |
1916 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1917 | if (test_bit(i, clustermap)) { | |
1918 | clusters += 1 + zeros; | |
1919 | zeros = 0; | |
1920 | } else | |
1921 | ++zeros; | |
1922 | } | |
1923 | ||
1924 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are | |
1925 | * not guaranteed to be synced between boards | |
1926 | */ | |
1927 | if (is_vsmp_box() && clusters > 1) | |
1928 | return 1; | |
1929 | ||
1930 | /* | |
1931 | * If clusters > 2, then should be multi-chassis. | |
1932 | * May have to revisit this when multi-core + hyperthreaded CPUs come | |
1933 | * out, but AFAIK this will work even for them. | |
1934 | */ | |
1935 | return (clusters > 2); | |
1936 | } | |
1937 | #endif | |
1938 | ||
1939 | /* | |
1940 | * APIC command line parameters | |
1941 | */ | |
789fa735 | 1942 | static int __init setup_disableapic(char *arg) |
0e078e2f | 1943 | { |
914bebfa | 1944 | disable_apic = 1; |
9175fc06 | 1945 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
0e078e2f TG |
1946 | return 0; |
1947 | } | |
789fa735 | 1948 | early_param("disableapic", setup_disableapic); |
0e078e2f | 1949 | |
789fa735 CG |
1950 | /* same as disableapic, for compatibility */ |
1951 | static int __init setup_nolapic(char *arg) | |
0e078e2f | 1952 | { |
789fa735 | 1953 | return setup_disableapic(arg); |
0e078e2f | 1954 | } |
789fa735 | 1955 | early_param("nolapic", setup_nolapic); |
0e078e2f TG |
1956 | |
1957 | static int __init parse_lapic_timer_c2_ok(char *arg) | |
1958 | { | |
1959 | local_apic_timer_c2_ok = 1; | |
1960 | return 0; | |
1961 | } | |
1962 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1963 | ||
36fef094 | 1964 | static int __init parse_disable_apic_timer(char *arg) |
0e078e2f | 1965 | { |
36fef094 | 1966 | disable_apic_timer = 1; |
0e078e2f TG |
1967 | return 0; |
1968 | } | |
36fef094 CG |
1969 | early_param("noapictimer", parse_disable_apic_timer); |
1970 | ||
1971 | static int __init parse_nolapic_timer(char *arg) | |
0e078e2f | 1972 | { |
36fef094 CG |
1973 | disable_apic_timer = 1; |
1974 | return 0; | |
1975 | } | |
1976 | early_param("nolapic_timer", parse_nolapic_timer); | |
0e078e2f | 1977 | |
48d97cb6 | 1978 | static int __init apic_set_verbosity(char *arg) |
0e078e2f | 1979 | { |
79af9bec CG |
1980 | if (!arg) { |
1981 | #ifdef CONFIG_X86_64 | |
1982 | skip_ioapic_setup = 0; | |
1983 | ioapic_force = 1; | |
1984 | return 0; | |
1985 | #endif | |
48d97cb6 | 1986 | return -EINVAL; |
79af9bec | 1987 | } |
48d97cb6 | 1988 | |
79af9bec | 1989 | if (strcmp("debug", arg) == 0) |
0e078e2f | 1990 | apic_verbosity = APIC_DEBUG; |
79af9bec | 1991 | else if (strcmp("verbose", arg) == 0) |
0e078e2f | 1992 | apic_verbosity = APIC_VERBOSE; |
79af9bec CG |
1993 | else { |
1994 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1995 | " use apic=verbose or apic=debug\n", arg); | |
1996 | return -EINVAL; | |
1997 | } | |
48d97cb6 | 1998 | |
fb6bef80 | 1999 | return 0; |
0e078e2f | 2000 | } |
fb6bef80 | 2001 | early_param("apic", apic_set_verbosity); |
0e078e2f | 2002 | |
746f2eb7 CG |
2003 | static int __init lapic_insert_resource(void) |
2004 | { | |
2005 | if (!apic_phys) | |
2006 | return -1; | |
2007 | ||
2008 | /* Put local APIC into the resource map. */ | |
2009 | lapic_resource.start = apic_phys; | |
2010 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2011 | insert_resource(&iomem_resource, &lapic_resource); | |
2012 | ||
2013 | return 0; | |
2014 | } | |
2015 | ||
2016 | /* | |
2017 | * need call insert after e820_reserve_resources() | |
2018 | * that is using request_resource | |
2019 | */ | |
2020 | late_initcall(lapic_insert_resource); |