Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
f3705136 | 26 | #include <linux/cpu.h> |
e9e2cdb4 | 27 | #include <linux/clockchips.h> |
d36b49b9 | 28 | #include <linux/acpi_pmtmr.h> |
6eb0a0fd | 29 | #include <linux/module.h> |
ad62ca2b | 30 | #include <linux/dmi.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/arch_hooks.h> | |
38 | #include <asm/hpet.h> | |
306e440d | 39 | #include <asm/i8253.h> |
3e4ff115 | 40 | #include <asm/nmi.h> |
1da177e4 LT |
41 | |
42 | #include <mach_apic.h> | |
382dbd07 | 43 | #include <mach_apicdef.h> |
6eb0a0fd | 44 | #include <mach_ipi.h> |
1da177e4 | 45 | |
e05d723f TG |
46 | /* |
47 | * Sanity check | |
48 | */ | |
49 | #if (SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F | |
50 | # error SPURIOUS_APIC_VECTOR definition error | |
51 | #endif | |
52 | ||
9635b47d EB |
53 | /* |
54 | * Knob to control our willingness to enable the local APIC. | |
e05d723f TG |
55 | * |
56 | * -1=force-disable, +1=force-enable | |
9635b47d | 57 | */ |
e05d723f | 58 | static int enable_local_apic __initdata = 0; |
9635b47d | 59 | |
d36b49b9 TG |
60 | /* Local APIC timer verification ok */ |
61 | static int local_apic_timer_verify_ok; | |
d3f7eae1 AK |
62 | /* Disable local APIC timer from the kernel commandline or via dmi quirk |
63 | or using CPU MSR check */ | |
64 | int local_apic_timer_disabled; | |
e585bef8 TG |
65 | /* Local APIC timer works in C2 */ |
66 | int local_apic_timer_c2_ok; | |
67 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
e9e2cdb4 | 68 | |
1da177e4 | 69 | /* |
e05d723f | 70 | * Debug level, exported for io_apic.c |
1da177e4 LT |
71 | */ |
72 | int apic_verbosity; | |
73 | ||
e9e2cdb4 | 74 | static unsigned int calibration_result; |
1da177e4 | 75 | |
e9e2cdb4 TG |
76 | static int lapic_next_event(unsigned long delta, |
77 | struct clock_event_device *evt); | |
78 | static void lapic_timer_setup(enum clock_event_mode mode, | |
79 | struct clock_event_device *evt); | |
80 | static void lapic_timer_broadcast(cpumask_t mask); | |
81 | static void apic_pm_activate(void); | |
e05d723f | 82 | |
e9e2cdb4 TG |
83 | /* |
84 | * The local apic timer can be used for any function which is CPU local. | |
85 | */ | |
86 | static struct clock_event_device lapic_clockevent = { | |
87 | .name = "lapic", | |
88 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
d36b49b9 | 89 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
e9e2cdb4 TG |
90 | .shift = 32, |
91 | .set_mode = lapic_timer_setup, | |
92 | .set_next_event = lapic_next_event, | |
93 | .broadcast = lapic_timer_broadcast, | |
94 | .rating = 100, | |
95 | .irq = -1, | |
96 | }; | |
97 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
e05d723f TG |
98 | |
99 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ | |
100 | static int enabled_via_apicbase; | |
101 | ||
102 | /* | |
103 | * Get the LAPIC version | |
104 | */ | |
105 | static inline int lapic_get_version(void) | |
95d769aa | 106 | { |
e05d723f | 107 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
95d769aa AK |
108 | } |
109 | ||
1da177e4 | 110 | /* |
e05d723f | 111 | * Check, if the APIC is integrated or a seperate chip |
1da177e4 | 112 | */ |
e05d723f | 113 | static inline int lapic_is_integrated(void) |
1da177e4 | 114 | { |
e05d723f | 115 | return APIC_INTEGRATED(lapic_get_version()); |
1da177e4 LT |
116 | } |
117 | ||
e05d723f TG |
118 | /* |
119 | * Check, whether this is a modern or a first generation APIC | |
120 | */ | |
121 | static int modern_apic(void) | |
1da177e4 | 122 | { |
e05d723f TG |
123 | /* AMD systems use old APIC versions, so check the CPU */ |
124 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
125 | boot_cpu_data.x86 >= 0xf) | |
126 | return 1; | |
127 | return lapic_get_version() >= 0x14; | |
1da177e4 LT |
128 | } |
129 | ||
f2b218dd FLV |
130 | void apic_wait_icr_idle(void) |
131 | { | |
132 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
133 | cpu_relax(); | |
134 | } | |
135 | ||
42e0a9aa | 136 | u32 safe_apic_wait_icr_idle(void) |
f2b218dd | 137 | { |
42e0a9aa | 138 | u32 send_status; |
f2b218dd FLV |
139 | int timeout; |
140 | ||
141 | timeout = 0; | |
142 | do { | |
143 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
144 | if (!send_status) | |
145 | break; | |
146 | udelay(100); | |
147 | } while (timeout++ < 1000); | |
148 | ||
149 | return send_status; | |
150 | } | |
151 | ||
e05d723f TG |
152 | /** |
153 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
154 | */ | |
1da177e4 LT |
155 | void enable_NMI_through_LVT0 (void * dummy) |
156 | { | |
e05d723f | 157 | unsigned int v = APIC_DM_NMI; |
1da177e4 | 158 | |
e05d723f TG |
159 | /* Level triggered for 82489DX */ |
160 | if (!lapic_is_integrated()) | |
1da177e4 LT |
161 | v |= APIC_LVT_LEVEL_TRIGGER; |
162 | apic_write_around(APIC_LVT0, v); | |
163 | } | |
164 | ||
e05d723f TG |
165 | /** |
166 | * get_physical_broadcast - Get number of physical broadcast IDs | |
167 | */ | |
1da177e4 LT |
168 | int get_physical_broadcast(void) |
169 | { | |
e05d723f | 170 | return modern_apic() ? 0xff : 0xf; |
1da177e4 LT |
171 | } |
172 | ||
e05d723f TG |
173 | /** |
174 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
175 | */ | |
176 | int lapic_get_maxlvt(void) | |
1da177e4 | 177 | { |
e05d723f | 178 | unsigned int v = apic_read(APIC_LVR); |
1da177e4 | 179 | |
1da177e4 | 180 | /* 82489DXs do not report # of LVT entries. */ |
e05d723f | 181 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
1da177e4 LT |
182 | } |
183 | ||
e05d723f TG |
184 | /* |
185 | * Local APIC timer | |
186 | */ | |
187 | ||
d36b49b9 TG |
188 | /* Clock divisor is set to 16 */ |
189 | #define APIC_DIVISOR 16 | |
e05d723f TG |
190 | |
191 | /* | |
192 | * This function sets up the local APIC timer, with a timeout of | |
193 | * 'clocks' APIC bus clock. During calibration we actually call | |
194 | * this function twice on the boot CPU, once with a bogus timeout | |
195 | * value, second time for real. The other (noncalibrating) CPUs | |
196 | * call this function only once, with the real, calibrated value. | |
197 | * | |
198 | * We do reads before writes even if unnecessary, to get around the | |
199 | * P5 APIC double write bug. | |
200 | */ | |
e9e2cdb4 | 201 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 202 | { |
e05d723f | 203 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 204 | |
e9e2cdb4 TG |
205 | lvtt_value = LOCAL_TIMER_VECTOR; |
206 | if (!oneshot) | |
207 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
e05d723f TG |
208 | if (!lapic_is_integrated()) |
209 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
210 | ||
e9e2cdb4 | 211 | if (!irqen) |
e05d723f TG |
212 | lvtt_value |= APIC_LVT_MASKED; |
213 | ||
214 | apic_write_around(APIC_LVTT, lvtt_value); | |
1da177e4 LT |
215 | |
216 | /* | |
e05d723f | 217 | * Divide PICLK by 16 |
1da177e4 | 218 | */ |
e05d723f TG |
219 | tmp_value = apic_read(APIC_TDCR); |
220 | apic_write_around(APIC_TDCR, (tmp_value | |
221 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
222 | | APIC_TDR_DIV_16); | |
1da177e4 | 223 | |
e9e2cdb4 TG |
224 | if (!oneshot) |
225 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); | |
226 | } | |
227 | ||
228 | /* | |
229 | * Program the next event, relative to now | |
230 | */ | |
231 | static int lapic_next_event(unsigned long delta, | |
232 | struct clock_event_device *evt) | |
233 | { | |
234 | apic_write_around(APIC_TMICT, delta); | |
235 | return 0; | |
1da177e4 LT |
236 | } |
237 | ||
e9e2cdb4 TG |
238 | /* |
239 | * Setup the lapic timer in periodic or oneshot mode | |
240 | */ | |
241 | static void lapic_timer_setup(enum clock_event_mode mode, | |
242 | struct clock_event_device *evt) | |
1da177e4 | 243 | { |
e05d723f | 244 | unsigned long flags; |
e9e2cdb4 | 245 | unsigned int v; |
e05d723f | 246 | |
d36b49b9 TG |
247 | /* Lapic used for broadcast ? */ |
248 | if (!local_apic_timer_verify_ok) | |
249 | return; | |
250 | ||
e05d723f | 251 | local_irq_save(flags); |
1da177e4 | 252 | |
e9e2cdb4 TG |
253 | switch (mode) { |
254 | case CLOCK_EVT_MODE_PERIODIC: | |
255 | case CLOCK_EVT_MODE_ONESHOT: | |
256 | __setup_APIC_LVTT(calibration_result, | |
257 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
258 | break; | |
259 | case CLOCK_EVT_MODE_UNUSED: | |
260 | case CLOCK_EVT_MODE_SHUTDOWN: | |
261 | v = apic_read(APIC_LVTT); | |
262 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
263 | apic_write_around(APIC_LVTT, v); | |
264 | break; | |
18de5bc4 TG |
265 | case CLOCK_EVT_MODE_RESUME: |
266 | /* Nothing to do here */ | |
267 | break; | |
e9e2cdb4 | 268 | } |
e05d723f TG |
269 | |
270 | local_irq_restore(flags); | |
271 | } | |
272 | ||
e9e2cdb4 TG |
273 | /* |
274 | * Local APIC timer broadcast function | |
275 | */ | |
276 | static void lapic_timer_broadcast(cpumask_t mask) | |
277 | { | |
278 | #ifdef CONFIG_SMP | |
279 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
280 | #endif | |
281 | } | |
282 | ||
283 | /* | |
284 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
285 | * of the boot CPU and register the clock event in the framework. | |
286 | */ | |
287 | static void __devinit setup_APIC_timer(void) | |
288 | { | |
289 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
290 | ||
291 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); | |
292 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
293 | ||
294 | clockevents_register_device(levt); | |
295 | } | |
296 | ||
e05d723f | 297 | /* |
d36b49b9 TG |
298 | * In this functions we calibrate APIC bus clocks to the external timer. |
299 | * | |
300 | * We want to do the calibration only once since we want to have local timer | |
301 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
302 | * frequency. | |
303 | * | |
304 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
305 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
306 | * readout is broken, so it never gets out of the wait loop again. This was | |
307 | * also reported by others. | |
e05d723f | 308 | * |
d36b49b9 TG |
309 | * Monitoring the jiffies value is inaccurate and the clockevents |
310 | * infrastructure allows us to do a simple substitution of the interrupt | |
311 | * handler. | |
e9e2cdb4 | 312 | * |
d36b49b9 TG |
313 | * The calibration routine also uses the pm_timer when possible, as the PIT |
314 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
315 | * back to normal later in the boot process). | |
e05d723f TG |
316 | */ |
317 | ||
d36b49b9 | 318 | #define LAPIC_CAL_LOOPS (HZ/10) |
e05d723f | 319 | |
f5352fd0 | 320 | static __initdata int lapic_cal_loops = -1; |
d36b49b9 TG |
321 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
322 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
323 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
324 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
1da177e4 | 325 | |
d36b49b9 TG |
326 | /* |
327 | * Temporary interrupt handler. | |
328 | */ | |
329 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
330 | { | |
331 | unsigned long long tsc = 0; | |
332 | long tapic = apic_read(APIC_TMCCT); | |
333 | unsigned long pm = acpi_pm_read_early(); | |
1da177e4 | 334 | |
d36b49b9 TG |
335 | if (cpu_has_tsc) |
336 | rdtscll(tsc); | |
337 | ||
338 | switch (lapic_cal_loops++) { | |
339 | case 0: | |
340 | lapic_cal_t1 = tapic; | |
341 | lapic_cal_tsc1 = tsc; | |
342 | lapic_cal_pm1 = pm; | |
343 | lapic_cal_j1 = jiffies; | |
344 | break; | |
e05d723f | 345 | |
d36b49b9 TG |
346 | case LAPIC_CAL_LOOPS: |
347 | lapic_cal_t2 = tapic; | |
348 | lapic_cal_tsc2 = tsc; | |
349 | if (pm < lapic_cal_pm1) | |
350 | pm += ACPI_PM_OVRRUN; | |
351 | lapic_cal_pm2 = pm; | |
352 | lapic_cal_j2 = jiffies; | |
353 | break; | |
354 | } | |
355 | } | |
1da177e4 | 356 | |
d36b49b9 TG |
357 | /* |
358 | * Setup the boot APIC | |
359 | * | |
360 | * Calibrate and verify the result. | |
361 | */ | |
362 | void __init setup_boot_APIC_clock(void) | |
363 | { | |
364 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
365 | const long pm_100ms = PMTMR_TICKS_PER_SEC/10; | |
366 | const long pm_thresh = pm_100ms/100; | |
367 | void (*real_handler)(struct clock_event_device *dev); | |
368 | unsigned long deltaj; | |
369 | long delta, deltapm; | |
ca1b940c | 370 | int pm_referenced = 0; |
1da177e4 | 371 | |
ad62ca2b TG |
372 | /* |
373 | * The local apic timer can be disabled via the kernel | |
d3f7eae1 | 374 | * commandline or from the CPU detection code. Register the lapic |
ad62ca2b TG |
375 | * timer as a dummy clock event source on SMP systems, so the |
376 | * broadcast mechanism is used. On UP systems simply ignore it. | |
377 | */ | |
378 | if (local_apic_timer_disabled) { | |
379 | /* No broadcast on UP ! */ | |
380 | if (num_possible_cpus() > 1) | |
381 | setup_APIC_timer(); | |
382 | return; | |
383 | } | |
384 | ||
d36b49b9 TG |
385 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
386 | "calibrating APIC timer ...\n"); | |
1da177e4 | 387 | |
d36b49b9 TG |
388 | local_irq_disable(); |
389 | ||
390 | /* Replace the global interrupt handler */ | |
391 | real_handler = global_clock_event->event_handler; | |
392 | global_clock_event->event_handler = lapic_cal_handler; | |
1da177e4 | 393 | |
1da177e4 | 394 | /* |
d36b49b9 TG |
395 | * Setup the APIC counter to 1e9. There is no way the lapic |
396 | * can underflow in the 100ms detection time frame | |
1da177e4 | 397 | */ |
d36b49b9 | 398 | __setup_APIC_LVTT(1000000000, 0, 0); |
1da177e4 | 399 | |
d36b49b9 TG |
400 | /* Let the interrupts run */ |
401 | local_irq_enable(); | |
402 | ||
ca1b940c TG |
403 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
404 | cpu_relax(); | |
d36b49b9 TG |
405 | |
406 | local_irq_disable(); | |
407 | ||
408 | /* Restore the real event handler */ | |
409 | global_clock_event->event_handler = real_handler; | |
410 | ||
411 | /* Build delta t1-t2 as apic timer counts down */ | |
412 | delta = lapic_cal_t1 - lapic_cal_t2; | |
413 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
414 | ||
415 | /* Check, if the PM timer is available */ | |
416 | deltapm = lapic_cal_pm2 - lapic_cal_pm1; | |
417 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
418 | ||
419 | if (deltapm) { | |
420 | unsigned long mult; | |
421 | u64 res; | |
422 | ||
423 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
424 | ||
425 | if (deltapm > (pm_100ms - pm_thresh) && | |
426 | deltapm < (pm_100ms + pm_thresh)) { | |
427 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
428 | } else { | |
429 | res = (((u64) deltapm) * mult) >> 22; | |
430 | do_div(res, 1000000); | |
431 | printk(KERN_WARNING "APIC calibration not consistent " | |
432 | "with PM Timer: %ldms instead of 100ms\n", | |
433 | (long)res); | |
434 | /* Correct the lapic counter value */ | |
435 | res = (((u64) delta ) * pm_100ms); | |
436 | do_div(res, deltapm); | |
437 | printk(KERN_INFO "APIC delta adjusted to PM-Timer: " | |
438 | "%lu (%ld)\n", (unsigned long) res, delta); | |
439 | delta = (long) res; | |
440 | } | |
ca1b940c | 441 | pm_referenced = 1; |
d36b49b9 | 442 | } |
e05d723f | 443 | |
e9e2cdb4 | 444 | /* Calculate the scaled math multiplication factor */ |
d36b49b9 | 445 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 32); |
e9e2cdb4 TG |
446 | lapic_clockevent.max_delta_ns = |
447 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
448 | lapic_clockevent.min_delta_ns = | |
449 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
450 | ||
d36b49b9 TG |
451 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
452 | ||
453 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
e9e2cdb4 | 454 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); |
d36b49b9 TG |
455 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
456 | calibration_result); | |
e9e2cdb4 | 457 | |
d36b49b9 TG |
458 | if (cpu_has_tsc) { |
459 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
e05d723f | 460 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
d36b49b9 TG |
461 | "%ld.%04ld MHz.\n", |
462 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
463 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
464 | } | |
e05d723f TG |
465 | |
466 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
d36b49b9 TG |
467 | "%u.%04u MHz.\n", |
468 | calibration_result / (1000000 / HZ), | |
469 | calibration_result % (1000000 / HZ)); | |
e05d723f | 470 | |
d36b49b9 | 471 | local_apic_timer_verify_ok = 1; |
d36b49b9 | 472 | |
ca1b940c TG |
473 | /* We trust the pm timer based calibration */ |
474 | if (!pm_referenced) { | |
475 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
d36b49b9 | 476 | |
ca1b940c TG |
477 | /* |
478 | * Setup the apic timer manually | |
479 | */ | |
480 | levt->event_handler = lapic_cal_handler; | |
481 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
482 | lapic_cal_loops = -1; | |
d36b49b9 | 483 | |
ca1b940c TG |
484 | /* Let the interrupts run */ |
485 | local_irq_enable(); | |
d36b49b9 | 486 | |
f5352fd0 | 487 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
ca1b940c | 488 | cpu_relax(); |
d36b49b9 | 489 | |
ca1b940c | 490 | local_irq_disable(); |
d36b49b9 | 491 | |
ca1b940c TG |
492 | /* Stop the lapic timer */ |
493 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
d36b49b9 | 494 | |
ca1b940c | 495 | local_irq_enable(); |
d36b49b9 | 496 | |
ca1b940c TG |
497 | /* Jiffies delta */ |
498 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
499 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
d36b49b9 | 500 | |
d36b49b9 | 501 | /* Check, if the jiffies result is consistent */ |
ca1b940c | 502 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
d36b49b9 | 503 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
ca1b940c TG |
504 | else |
505 | local_apic_timer_verify_ok = 0; | |
4edc5db8 IM |
506 | } else |
507 | local_irq_enable(); | |
e05d723f | 508 | |
d36b49b9 TG |
509 | if (!local_apic_timer_verify_ok) { |
510 | printk(KERN_WARNING | |
511 | "APIC timer disabled due to verification failure.\n"); | |
512 | /* No broadcast on UP ! */ | |
513 | if (num_possible_cpus() == 1) | |
514 | return; | |
a5f5e43e TG |
515 | } else { |
516 | /* | |
517 | * If nmi_watchdog is set to IO_APIC, we need the | |
518 | * PIT/HPET going. Otherwise register lapic as a dummy | |
519 | * device. | |
520 | */ | |
521 | if (nmi_watchdog != NMI_IO_APIC) | |
522 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
820de5c3 IM |
523 | else |
524 | printk(KERN_WARNING "APIC timer registered as dummy," | |
525 | " due to nmi_watchdog=1!\n"); | |
a5f5e43e | 526 | } |
d36b49b9 TG |
527 | |
528 | /* Setup the lapic or request the broadcast */ | |
529 | setup_APIC_timer(); | |
e05d723f | 530 | } |
1da177e4 | 531 | |
e05d723f TG |
532 | void __devinit setup_secondary_APIC_clock(void) |
533 | { | |
e9e2cdb4 | 534 | setup_APIC_timer(); |
e05d723f | 535 | } |
1da177e4 | 536 | |
e05d723f | 537 | /* |
e9e2cdb4 | 538 | * The guts of the apic timer interrupt |
e05d723f | 539 | */ |
e9e2cdb4 | 540 | static void local_apic_timer_interrupt(void) |
e05d723f | 541 | { |
e9e2cdb4 TG |
542 | int cpu = smp_processor_id(); |
543 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
1da177e4 LT |
544 | |
545 | /* | |
d36b49b9 TG |
546 | * Normally we should not be here till LAPIC has been initialized but |
547 | * in some cases like kdump, its possible that there is a pending LAPIC | |
548 | * timer interrupt from previous kernel's context and is delivered in | |
549 | * new kernel the moment interrupts are enabled. | |
e05d723f | 550 | * |
d36b49b9 TG |
551 | * Interrupts are enabled early and LAPIC is setup much later, hence |
552 | * its possible that when we get here evt->event_handler is NULL. | |
553 | * Check for event_handler being NULL and discard the interrupt as | |
554 | * spurious. | |
1da177e4 | 555 | */ |
e9e2cdb4 TG |
556 | if (!evt->event_handler) { |
557 | printk(KERN_WARNING | |
558 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
559 | /* Switch it off */ | |
560 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
561 | return; | |
562 | } | |
563 | ||
0e078e2f TG |
564 | /* |
565 | * the NMI deadlock-detector uses this. | |
566 | */ | |
e9e2cdb4 TG |
567 | per_cpu(irq_stat, cpu).apic_timer_irqs++; |
568 | ||
569 | evt->event_handler(evt); | |
e05d723f TG |
570 | } |
571 | ||
572 | /* | |
573 | * Local APIC timer interrupt. This is the most natural way for doing | |
574 | * local interrupts, but local timer interrupts can be emulated by | |
575 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
576 | * | |
577 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
578 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
579 | */ | |
580 | ||
75604d7f | 581 | void smp_apic_timer_interrupt(struct pt_regs *regs) |
e05d723f TG |
582 | { |
583 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1da177e4 LT |
584 | |
585 | /* | |
e05d723f TG |
586 | * NOTE! We'd better ACK the irq immediately, |
587 | * because timer handling can be slow. | |
1da177e4 | 588 | */ |
e05d723f | 589 | ack_APIC_irq(); |
1a75a3f0 | 590 | /* |
e05d723f TG |
591 | * update_process_times() expects us to have done irq_enter(). |
592 | * Besides, if we don't timer interrupts ignore the global | |
593 | * interrupt lock, which is the WrongThing (tm) to do. | |
1a75a3f0 | 594 | */ |
e05d723f | 595 | irq_enter(); |
e9e2cdb4 | 596 | local_apic_timer_interrupt(); |
e05d723f | 597 | irq_exit(); |
1a75a3f0 | 598 | |
e9e2cdb4 | 599 | set_irq_regs(old_regs); |
e05d723f TG |
600 | } |
601 | ||
602 | int setup_profiling_timer(unsigned int multiplier) | |
603 | { | |
604 | return -EINVAL; | |
605 | } | |
606 | ||
607 | /* | |
608 | * Local APIC start and shutdown | |
609 | */ | |
610 | ||
611 | /** | |
612 | * clear_local_APIC - shutdown the local APIC | |
613 | * | |
614 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
615 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
616 | * leftovers during boot. | |
617 | */ | |
618 | void clear_local_APIC(void) | |
619 | { | |
620 | int maxlvt = lapic_get_maxlvt(); | |
0e078e2f | 621 | u32 v; |
1da177e4 LT |
622 | |
623 | /* | |
e05d723f TG |
624 | * Masking an LVT entry can trigger a local APIC error |
625 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1da177e4 | 626 | */ |
e05d723f TG |
627 | if (maxlvt >= 3) { |
628 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
629 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); | |
630 | } | |
1da177e4 | 631 | /* |
e05d723f TG |
632 | * Careful: we have to set masks only first to deassert |
633 | * any level-triggered sources. | |
1da177e4 | 634 | */ |
e05d723f TG |
635 | v = apic_read(APIC_LVTT); |
636 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
637 | v = apic_read(APIC_LVT0); | |
638 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
639 | v = apic_read(APIC_LVT1); | |
640 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); | |
641 | if (maxlvt >= 4) { | |
642 | v = apic_read(APIC_LVTPC); | |
643 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1da177e4 | 644 | } |
1da177e4 | 645 | |
e05d723f TG |
646 | /* lets not touch this if we didn't frob it */ |
647 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
648 | if (maxlvt >= 5) { | |
649 | v = apic_read(APIC_LVTTHMR); | |
650 | apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
651 | } | |
652 | #endif | |
1da177e4 | 653 | /* |
e05d723f | 654 | * Clean APIC state for other OSs: |
1da177e4 | 655 | */ |
e05d723f TG |
656 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); |
657 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
658 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); | |
659 | if (maxlvt >= 3) | |
660 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); | |
661 | if (maxlvt >= 4) | |
662 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); | |
1da177e4 | 663 | |
e05d723f TG |
664 | #ifdef CONFIG_X86_MCE_P4THERMAL |
665 | if (maxlvt >= 5) | |
666 | apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); | |
667 | #endif | |
668 | /* Integrated APIC (!82489DX) ? */ | |
669 | if (lapic_is_integrated()) { | |
1da177e4 | 670 | if (maxlvt > 3) |
e05d723f | 671 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
1da177e4 | 672 | apic_write(APIC_ESR, 0); |
e05d723f | 673 | apic_read(APIC_ESR); |
1da177e4 | 674 | } |
e05d723f | 675 | } |
1da177e4 | 676 | |
e05d723f TG |
677 | /** |
678 | * disable_local_APIC - clear and disable the local APIC | |
679 | */ | |
680 | void disable_local_APIC(void) | |
681 | { | |
682 | unsigned long value; | |
683 | ||
684 | clear_local_APIC(); | |
685 | ||
686 | /* | |
687 | * Disable APIC (implies clearing of registers | |
688 | * for 82489DX!). | |
689 | */ | |
690 | value = apic_read(APIC_SPIV); | |
691 | value &= ~APIC_SPIV_APIC_ENABLED; | |
692 | apic_write_around(APIC_SPIV, value); | |
693 | ||
694 | /* | |
695 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
696 | * restore the disabled state. | |
697 | */ | |
698 | if (enabled_via_apicbase) { | |
699 | unsigned int l, h; | |
700 | ||
701 | rdmsr(MSR_IA32_APICBASE, l, h); | |
702 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
703 | wrmsr(MSR_IA32_APICBASE, l, h); | |
704 | } | |
1da177e4 LT |
705 | } |
706 | ||
707 | /* | |
e05d723f TG |
708 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
709 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
710 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
77f72b19 | 711 | * for the case where Linux didn't enable the LAPIC. |
1da177e4 LT |
712 | */ |
713 | void lapic_shutdown(void) | |
714 | { | |
67963132 MS |
715 | unsigned long flags; |
716 | ||
77f72b19 | 717 | if (!cpu_has_apic) |
1da177e4 LT |
718 | return; |
719 | ||
67963132 | 720 | local_irq_save(flags); |
77f72b19 ZM |
721 | clear_local_APIC(); |
722 | ||
723 | if (enabled_via_apicbase) | |
724 | disable_local_APIC(); | |
725 | ||
67963132 | 726 | local_irq_restore(flags); |
1da177e4 LT |
727 | } |
728 | ||
e05d723f TG |
729 | /* |
730 | * This is to verify that we're looking at a real local APIC. | |
731 | * Check these against your board if the CPUs aren't getting | |
732 | * started for no apparent reason. | |
733 | */ | |
734 | int __init verify_local_APIC(void) | |
1da177e4 | 735 | { |
e05d723f | 736 | unsigned int reg0, reg1; |
1da177e4 | 737 | |
e05d723f TG |
738 | /* |
739 | * The version register is read-only in a real APIC. | |
740 | */ | |
741 | reg0 = apic_read(APIC_LVR); | |
742 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
743 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
744 | reg1 = apic_read(APIC_LVR); | |
745 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
746 | ||
747 | /* | |
748 | * The two version reads above should print the same | |
749 | * numbers. If the second one is different, then we | |
750 | * poke at a non-APIC. | |
751 | */ | |
752 | if (reg1 != reg0) | |
1da177e4 LT |
753 | return 0; |
754 | ||
e05d723f TG |
755 | /* |
756 | * Check if the version looks reasonably. | |
757 | */ | |
758 | reg1 = GET_APIC_VERSION(reg0); | |
759 | if (reg1 == 0x00 || reg1 == 0xff) | |
760 | return 0; | |
761 | reg1 = lapic_get_maxlvt(); | |
762 | if (reg1 < 0x02 || reg1 == 0xff) | |
763 | return 0; | |
f990fff4 | 764 | |
e05d723f TG |
765 | /* |
766 | * The ID register is read/write in a real APIC. | |
767 | */ | |
768 | reg0 = apic_read(APIC_ID); | |
769 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
770 | ||
771 | /* | |
772 | * The next two are just to see if we have sane values. | |
773 | * They're only really relevant if we're in Virtual Wire | |
774 | * compatibility mode, but most boxes are anymore. | |
775 | */ | |
776 | reg0 = apic_read(APIC_LVT0); | |
777 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
778 | reg1 = apic_read(APIC_LVT1); | |
779 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
780 | ||
781 | return 1; | |
1da177e4 LT |
782 | } |
783 | ||
e05d723f TG |
784 | /** |
785 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
786 | */ | |
787 | void __init sync_Arb_IDs(void) | |
1da177e4 | 788 | { |
e05d723f TG |
789 | /* |
790 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
791 | * needed on AMD. | |
792 | */ | |
f44d9efd | 793 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
e05d723f TG |
794 | return; |
795 | /* | |
796 | * Wait for idle. | |
797 | */ | |
798 | apic_wait_icr_idle(); | |
1da177e4 | 799 | |
e05d723f TG |
800 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
801 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | |
802 | | APIC_DM_INIT); | |
803 | } | |
1da177e4 | 804 | |
e05d723f TG |
805 | /* |
806 | * An initial setup of the virtual wire mode. | |
807 | */ | |
808 | void __init init_bsp_APIC(void) | |
809 | { | |
810 | unsigned long value; | |
f990fff4 | 811 | |
e05d723f TG |
812 | /* |
813 | * Don't do the setup now if we have a SMP BIOS as the | |
814 | * through-I/O-APIC virtual wire mode might be active. | |
815 | */ | |
816 | if (smp_found_config || !cpu_has_apic) | |
817 | return; | |
1da177e4 LT |
818 | |
819 | /* | |
e05d723f | 820 | * Do not trust the local APIC being empty at bootup. |
1da177e4 | 821 | */ |
e05d723f | 822 | clear_local_APIC(); |
1da177e4 | 823 | |
e05d723f TG |
824 | /* |
825 | * Enable APIC. | |
826 | */ | |
827 | value = apic_read(APIC_SPIV); | |
828 | value &= ~APIC_VECTOR_MASK; | |
829 | value |= APIC_SPIV_APIC_ENABLED; | |
830 | ||
831 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
832 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
833 | (boot_cpu_data.x86 == 15)) | |
834 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
835 | else | |
836 | value |= APIC_SPIV_FOCUS_DISABLED; | |
837 | value |= SPURIOUS_APIC_VECTOR; | |
838 | apic_write_around(APIC_SPIV, value); | |
839 | ||
840 | /* | |
841 | * Set up the virtual wire mode. | |
842 | */ | |
843 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
844 | value = APIC_DM_NMI; | |
845 | if (!lapic_is_integrated()) /* 82489DX */ | |
846 | value |= APIC_LVT_LEVEL_TRIGGER; | |
847 | apic_write_around(APIC_LVT1, value); | |
1da177e4 LT |
848 | } |
849 | ||
e05d723f TG |
850 | /** |
851 | * setup_local_APIC - setup the local APIC | |
1da177e4 | 852 | */ |
d5337983 | 853 | void __cpuinit setup_local_APIC(void) |
e05d723f TG |
854 | { |
855 | unsigned long oldvalue, value, maxlvt, integrated; | |
856 | int i, j; | |
1da177e4 | 857 | |
e05d723f TG |
858 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
859 | if (esr_disable) { | |
860 | apic_write(APIC_ESR, 0); | |
861 | apic_write(APIC_ESR, 0); | |
862 | apic_write(APIC_ESR, 0); | |
863 | apic_write(APIC_ESR, 0); | |
864 | } | |
1da177e4 | 865 | |
e05d723f | 866 | integrated = lapic_is_integrated(); |
1da177e4 | 867 | |
e05d723f TG |
868 | /* |
869 | * Double-check whether this APIC is really registered. | |
870 | */ | |
871 | if (!apic_id_registered()) | |
872 | BUG(); | |
1da177e4 | 873 | |
e05d723f TG |
874 | /* |
875 | * Intel recommends to set DFR, LDR and TPR before enabling | |
876 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
877 | * document number 292116). So here it goes... | |
878 | */ | |
879 | init_apic_ldr(); | |
1da177e4 | 880 | |
e05d723f TG |
881 | /* |
882 | * Set Task Priority to 'accept all'. We never change this | |
883 | * later on. | |
884 | */ | |
885 | value = apic_read(APIC_TASKPRI); | |
886 | value &= ~APIC_TPRI_MASK; | |
887 | apic_write_around(APIC_TASKPRI, value); | |
1da177e4 | 888 | |
e05d723f TG |
889 | /* |
890 | * After a crash, we no longer service the interrupts and a pending | |
891 | * interrupt from previous kernel might still have ISR bit set. | |
892 | * | |
893 | * Most probably by now CPU has serviced that pending interrupt and | |
894 | * it might not have done the ack_APIC_irq() because it thought, | |
895 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
896 | * does not clear the ISR bit and cpu thinks it has already serivced | |
897 | * the interrupt. Hence a vector might get locked. It was noticed | |
898 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
899 | */ | |
900 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
901 | value = apic_read(APIC_ISR + i*0x10); | |
902 | for (j = 31; j >= 0; j--) { | |
903 | if (value & (1<<j)) | |
904 | ack_APIC_irq(); | |
905 | } | |
906 | } | |
1da177e4 | 907 | |
e05d723f TG |
908 | /* |
909 | * Now that we are all set up, enable the APIC | |
910 | */ | |
911 | value = apic_read(APIC_SPIV); | |
912 | value &= ~APIC_VECTOR_MASK; | |
913 | /* | |
914 | * Enable APIC | |
915 | */ | |
916 | value |= APIC_SPIV_APIC_ENABLED; | |
1da177e4 | 917 | |
e05d723f TG |
918 | /* |
919 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
920 | * certain networking cards. If high frequency interrupts are | |
921 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
922 | * entry is masked/unmasked at a high rate as well then sooner or | |
923 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
924 | * from the device. If focus CPU is disabled then the hang goes | |
925 | * away, oh well :-( | |
926 | * | |
927 | * [ This bug can be reproduced easily with a level-triggered | |
928 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
929 | * BX chipset. ] | |
930 | */ | |
931 | /* | |
932 | * Actually disabling the focus CPU check just makes the hang less | |
933 | * frequent as it makes the interrupt distributon model be more | |
934 | * like LRU than MRU (the short-term load is more even across CPUs). | |
935 | * See also the comment in end_level_ioapic_irq(). --macro | |
936 | */ | |
1da177e4 | 937 | |
e05d723f TG |
938 | /* Enable focus processor (bit==0) */ |
939 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 940 | |
e05d723f TG |
941 | /* |
942 | * Set spurious IRQ vector | |
943 | */ | |
944 | value |= SPURIOUS_APIC_VECTOR; | |
945 | apic_write_around(APIC_SPIV, value); | |
946 | ||
947 | /* | |
948 | * Set up LVT0, LVT1: | |
949 | * | |
950 | * set up through-local-APIC on the BP's LINT0. This is not | |
27b46d76 | 951 | * strictly necessary in pure symmetric-IO mode, but sometimes |
e05d723f TG |
952 | * we delegate interrupts to the 8259A. |
953 | */ | |
954 | /* | |
955 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
956 | */ | |
957 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
958 | if (!smp_processor_id() && (pic_mode || !value)) { | |
959 | value = APIC_DM_EXTINT; | |
960 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
961 | smp_processor_id()); | |
962 | } else { | |
963 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
964 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
965 | smp_processor_id()); | |
966 | } | |
967 | apic_write_around(APIC_LVT0, value); | |
968 | ||
969 | /* | |
970 | * only the BP should see the LINT1 NMI signal, obviously. | |
971 | */ | |
972 | if (!smp_processor_id()) | |
973 | value = APIC_DM_NMI; | |
974 | else | |
975 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
976 | if (!integrated) /* 82489DX */ | |
977 | value |= APIC_LVT_LEVEL_TRIGGER; | |
978 | apic_write_around(APIC_LVT1, value); | |
979 | ||
980 | if (integrated && !esr_disable) { /* !82489DX */ | |
981 | maxlvt = lapic_get_maxlvt(); | |
982 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
983 | apic_write(APIC_ESR, 0); | |
984 | oldvalue = apic_read(APIC_ESR); | |
985 | ||
986 | /* enables sending errors */ | |
987 | value = ERROR_APIC_VECTOR; | |
988 | apic_write_around(APIC_LVTERR, value); | |
989 | /* | |
990 | * spec says clear errors after enabling vector. | |
991 | */ | |
992 | if (maxlvt > 3) | |
993 | apic_write(APIC_ESR, 0); | |
994 | value = apic_read(APIC_ESR); | |
995 | if (value != oldvalue) | |
996 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
997 | "vector: 0x%08lx after: 0x%08lx\n", | |
998 | oldvalue, value); | |
999 | } else { | |
1000 | if (esr_disable) | |
1001 | /* | |
27b46d76 | 1002 | * Something untraceable is creating bad interrupts on |
e05d723f TG |
1003 | * secondary quads ... for the moment, just leave the |
1004 | * ESR disabled - we can't do anything useful with the | |
1005 | * errors anyway - mbligh | |
1006 | */ | |
1007 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
1008 | else | |
1009 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
1010 | } | |
1da177e4 | 1011 | |
e9e2cdb4 TG |
1012 | /* Disable the local apic timer */ |
1013 | value = apic_read(APIC_LVTT); | |
1014 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1015 | apic_write_around(APIC_LVTT, value); | |
1016 | ||
e05d723f TG |
1017 | setup_apic_nmi_watchdog(NULL); |
1018 | apic_pm_activate(); | |
1da177e4 LT |
1019 | } |
1020 | ||
e05d723f TG |
1021 | /* |
1022 | * Detect and initialize APIC | |
1023 | */ | |
1da177e4 LT |
1024 | static int __init detect_init_APIC (void) |
1025 | { | |
1026 | u32 h, l, features; | |
1da177e4 LT |
1027 | |
1028 | /* Disabled by kernel option? */ | |
1029 | if (enable_local_apic < 0) | |
1030 | return -1; | |
1031 | ||
1da177e4 LT |
1032 | switch (boot_cpu_data.x86_vendor) { |
1033 | case X86_VENDOR_AMD: | |
1034 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
e05d723f | 1035 | (boot_cpu_data.x86 == 15)) |
1da177e4 LT |
1036 | break; |
1037 | goto no_apic; | |
1038 | case X86_VENDOR_INTEL: | |
1039 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1040 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1041 | break; | |
1042 | goto no_apic; | |
1043 | default: | |
1044 | goto no_apic; | |
1045 | } | |
1046 | ||
1047 | if (!cpu_has_apic) { | |
1048 | /* | |
e05d723f TG |
1049 | * Over-ride BIOS and try to enable the local APIC only if |
1050 | * "lapic" specified. | |
1da177e4 LT |
1051 | */ |
1052 | if (enable_local_apic <= 0) { | |
e05d723f | 1053 | printk(KERN_INFO "Local APIC disabled by BIOS -- " |
1da177e4 LT |
1054 | "you can enable it with \"lapic\"\n"); |
1055 | return -1; | |
1056 | } | |
1057 | /* | |
e05d723f TG |
1058 | * Some BIOSes disable the local APIC in the APIC_BASE |
1059 | * MSR. This can only be done in software for Intel P6 or later | |
1060 | * and AMD K7 (Model > 1) or later. | |
1da177e4 LT |
1061 | */ |
1062 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1063 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
e05d723f TG |
1064 | printk(KERN_INFO |
1065 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1da177e4 LT |
1066 | l &= ~MSR_IA32_APICBASE_BASE; |
1067 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1068 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1069 | enabled_via_apicbase = 1; | |
1070 | } | |
1071 | } | |
1072 | /* | |
1073 | * The APIC feature bit should now be enabled | |
1074 | * in `cpuid' | |
1075 | */ | |
1076 | features = cpuid_edx(1); | |
1077 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
e05d723f | 1078 | printk(KERN_WARNING "Could not enable APIC!\n"); |
1da177e4 LT |
1079 | return -1; |
1080 | } | |
53756d37 | 1081 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1da177e4 LT |
1082 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
1083 | ||
1084 | /* The BIOS may have set up the APIC at some other address */ | |
1085 | rdmsr(MSR_IA32_APICBASE, l, h); | |
e05d723f TG |
1086 | if (l & MSR_IA32_APICBASE_ENABLE) |
1087 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1da177e4 | 1088 | |
0328ecef | 1089 | if (nmi_watchdog != NMI_NONE && nmi_watchdog != NMI_DISABLED) |
e05d723f | 1090 | nmi_watchdog = NMI_LOCAL_APIC; |
1da177e4 | 1091 | |
e05d723f | 1092 | printk(KERN_INFO "Found and enabled local APIC!\n"); |
1da177e4 | 1093 | |
e05d723f | 1094 | apic_pm_activate(); |
1da177e4 | 1095 | |
e05d723f | 1096 | return 0; |
1da177e4 | 1097 | |
e05d723f TG |
1098 | no_apic: |
1099 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1100 | return -1; | |
1101 | } | |
1da177e4 | 1102 | |
e05d723f TG |
1103 | /** |
1104 | * init_apic_mappings - initialize APIC mappings | |
1105 | */ | |
1106 | void __init init_apic_mappings(void) | |
1da177e4 | 1107 | { |
e05d723f | 1108 | unsigned long apic_phys; |
1da177e4 | 1109 | |
1da177e4 | 1110 | /* |
e05d723f TG |
1111 | * If no local APIC can be found then set up a fake all |
1112 | * zeroes page to simulate the local APIC and another | |
1113 | * one for the IO-APIC. | |
1da177e4 | 1114 | */ |
e05d723f TG |
1115 | if (!smp_found_config && detect_init_APIC()) { |
1116 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1117 | apic_phys = __pa(apic_phys); | |
1118 | } else | |
1119 | apic_phys = mp_lapic_addr; | |
1da177e4 | 1120 | |
e05d723f TG |
1121 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
1122 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
1123 | apic_phys); | |
1da177e4 | 1124 | |
e05d723f TG |
1125 | /* |
1126 | * Fetch the APIC ID of the BSP in case we have a | |
1127 | * default configuration (or the MP table is broken). | |
1128 | */ | |
1129 | if (boot_cpu_physical_apicid == -1U) | |
1130 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1da177e4 | 1131 | |
e05d723f TG |
1132 | #ifdef CONFIG_X86_IO_APIC |
1133 | { | |
1134 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
1135 | int i; | |
1da177e4 | 1136 | |
e05d723f TG |
1137 | for (i = 0; i < nr_ioapics; i++) { |
1138 | if (smp_found_config) { | |
1139 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
1140 | if (!ioapic_phys) { | |
1141 | printk(KERN_ERR | |
1142 | "WARNING: bogus zero IO-APIC " | |
1143 | "address found in MPTABLE, " | |
1144 | "disabling IO/APIC support!\n"); | |
1145 | smp_found_config = 0; | |
1146 | skip_ioapic_setup = 1; | |
1147 | goto fake_ioapic_page; | |
1148 | } | |
1149 | } else { | |
1150 | fake_ioapic_page: | |
1151 | ioapic_phys = (unsigned long) | |
1152 | alloc_bootmem_pages(PAGE_SIZE); | |
1153 | ioapic_phys = __pa(ioapic_phys); | |
1154 | } | |
1155 | set_fixmap_nocache(idx, ioapic_phys); | |
1156 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
1157 | __fix_to_virt(idx), ioapic_phys); | |
1158 | idx++; | |
1159 | } | |
1da177e4 | 1160 | } |
e05d723f | 1161 | #endif |
1da177e4 LT |
1162 | } |
1163 | ||
e05d723f TG |
1164 | /* |
1165 | * This initializes the IO-APIC and APIC hardware if this is | |
1166 | * a UP kernel. | |
1167 | */ | |
1168 | int __init APIC_init_uniprocessor (void) | |
1da177e4 | 1169 | { |
e05d723f | 1170 | if (enable_local_apic < 0) |
53756d37 | 1171 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1da177e4 | 1172 | |
e05d723f TG |
1173 | if (!smp_found_config && !cpu_has_apic) |
1174 | return -1; | |
6eb0a0fd | 1175 | |
e05d723f TG |
1176 | /* |
1177 | * Complain if the BIOS pretends there is one. | |
1178 | */ | |
1179 | if (!cpu_has_apic && | |
1180 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1181 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1182 | boot_cpu_physical_apicid); | |
53756d37 | 1183 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
e05d723f | 1184 | return -1; |
6eb0a0fd | 1185 | } |
6eb0a0fd | 1186 | |
e05d723f | 1187 | verify_local_APIC(); |
6eb0a0fd | 1188 | |
e05d723f | 1189 | connect_bsp_APIC(); |
6eb0a0fd | 1190 | |
e05d723f TG |
1191 | /* |
1192 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1193 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1194 | * might be zero if read from MP tables. Get it from LAPIC. | |
1195 | */ | |
1196 | #ifdef CONFIG_CRASH_DUMP | |
1197 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1198 | #endif | |
1199 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
1da177e4 | 1200 | |
e05d723f | 1201 | setup_local_APIC(); |
1da177e4 | 1202 | |
e05d723f TG |
1203 | #ifdef CONFIG_X86_IO_APIC |
1204 | if (smp_found_config) | |
1205 | if (!skip_ioapic_setup && nr_ioapics) | |
1206 | setup_IO_APIC(); | |
1da177e4 | 1207 | #endif |
e05d723f | 1208 | setup_boot_clock(); |
1da177e4 | 1209 | |
e05d723f | 1210 | return 0; |
1da177e4 LT |
1211 | } |
1212 | ||
e05d723f TG |
1213 | /* |
1214 | * Local APIC interrupts | |
1215 | */ | |
1216 | ||
1da177e4 LT |
1217 | /* |
1218 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1219 | */ | |
e9e2cdb4 | 1220 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1221 | { |
1222 | unsigned long v; | |
1223 | ||
1224 | irq_enter(); | |
1225 | /* | |
1226 | * Check if this really is a spurious interrupt and ACK it | |
1227 | * if it is a vectored one. Just in case... | |
1228 | * Spurious interrupts should not be ACKed. | |
1229 | */ | |
1230 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1231 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1232 | ack_APIC_irq(); | |
1233 | ||
1234 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
e05d723f TG |
1235 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " |
1236 | "should never happen.\n", smp_processor_id()); | |
38e760a1 | 1237 | __get_cpu_var(irq_stat).irq_spurious_count++; |
1da177e4 LT |
1238 | irq_exit(); |
1239 | } | |
1240 | ||
1241 | /* | |
1242 | * This interrupt should never happen with our APIC/SMP architecture | |
1243 | */ | |
e9e2cdb4 | 1244 | void smp_error_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1245 | { |
1246 | unsigned long v, v1; | |
1247 | ||
1248 | irq_enter(); | |
1249 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1250 | v = apic_read(APIC_ESR); | |
1251 | apic_write(APIC_ESR, 0); | |
1252 | v1 = apic_read(APIC_ESR); | |
1253 | ack_APIC_irq(); | |
1254 | atomic_inc(&irq_err_count); | |
1255 | ||
1256 | /* Here is what the APIC error bits mean: | |
1257 | 0: Send CS error | |
1258 | 1: Receive CS error | |
1259 | 2: Send accept error | |
1260 | 3: Receive accept error | |
1261 | 4: Reserved | |
1262 | 5: Send illegal vector | |
1263 | 6: Received illegal vector | |
1264 | 7: Illegal register address | |
1265 | */ | |
1266 | printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", | |
e05d723f | 1267 | smp_processor_id(), v , v1); |
1da177e4 LT |
1268 | irq_exit(); |
1269 | } | |
1270 | ||
1271 | /* | |
e05d723f | 1272 | * Initialize APIC interrupts |
1da177e4 | 1273 | */ |
e05d723f | 1274 | void __init apic_intr_init(void) |
1da177e4 | 1275 | { |
e05d723f TG |
1276 | #ifdef CONFIG_SMP |
1277 | smp_intr_init(); | |
1278 | #endif | |
1279 | /* self generated IPI for local APIC timer */ | |
1280 | set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | |
1da177e4 | 1281 | |
e05d723f TG |
1282 | /* IPI vectors for APIC spurious and error interrupts */ |
1283 | set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | |
1284 | set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
1da177e4 | 1285 | |
e05d723f TG |
1286 | /* thermal monitor LVT interrupt */ |
1287 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1288 | set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); | |
1289 | #endif | |
1290 | } | |
1291 | ||
1292 | /** | |
1293 | * connect_bsp_APIC - attach the APIC to the interrupt system | |
1294 | */ | |
1295 | void __init connect_bsp_APIC(void) | |
1296 | { | |
1297 | if (pic_mode) { | |
1298 | /* | |
1299 | * Do not trust the local APIC being empty at bootup. | |
1300 | */ | |
1301 | clear_local_APIC(); | |
1302 | /* | |
1303 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1304 | * local APIC to INT and NMI lines. | |
1305 | */ | |
1306 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1307 | "enabling APIC mode.\n"); | |
1308 | outb(0x70, 0x22); | |
1309 | outb(0x01, 0x23); | |
1da177e4 | 1310 | } |
e05d723f TG |
1311 | enable_apic_mode(); |
1312 | } | |
1da177e4 | 1313 | |
e05d723f TG |
1314 | /** |
1315 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1316 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1317 | * | |
1318 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1319 | * APIC is disabled. | |
1320 | */ | |
1321 | void disconnect_bsp_APIC(int virt_wire_setup) | |
1322 | { | |
1323 | if (pic_mode) { | |
1324 | /* | |
1325 | * Put the board back into PIC mode (has an effect only on | |
1326 | * certain older boards). Note that APIC interrupts, including | |
1327 | * IPIs, won't work beyond this point! The only exception are | |
1328 | * INIT IPIs. | |
1329 | */ | |
1330 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1331 | "entering PIC mode.\n"); | |
1332 | outb(0x70, 0x22); | |
1333 | outb(0x00, 0x23); | |
1334 | } else { | |
1335 | /* Go back to Virtual Wire compatibility mode */ | |
1336 | unsigned long value; | |
1da177e4 | 1337 | |
e05d723f TG |
1338 | /* For the spurious interrupt use vector F, and enable it */ |
1339 | value = apic_read(APIC_SPIV); | |
1340 | value &= ~APIC_VECTOR_MASK; | |
1341 | value |= APIC_SPIV_APIC_ENABLED; | |
1342 | value |= 0xf; | |
1343 | apic_write_around(APIC_SPIV, value); | |
1da177e4 | 1344 | |
e05d723f TG |
1345 | if (!virt_wire_setup) { |
1346 | /* | |
1347 | * For LVT0 make it edge triggered, active high, | |
1348 | * external and enabled | |
1349 | */ | |
1350 | value = apic_read(APIC_LVT0); | |
1351 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1352 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1353 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); | |
1354 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1355 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1356 | apic_write_around(APIC_LVT0, value); | |
1357 | } else { | |
1358 | /* Disable LVT0 */ | |
1359 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
1360 | } | |
1da177e4 | 1361 | |
e05d723f TG |
1362 | /* |
1363 | * For LVT1 make it edge triggered, active high, nmi and | |
1364 | * enabled | |
1365 | */ | |
1366 | value = apic_read(APIC_LVT1); | |
1367 | value &= ~( | |
1368 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
1369 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1370 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1371 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1372 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1373 | apic_write_around(APIC_LVT1, value); | |
1374 | } | |
1375 | } | |
1da177e4 | 1376 | |
e05d723f TG |
1377 | /* |
1378 | * Power management | |
1379 | */ | |
1380 | #ifdef CONFIG_PM | |
1381 | ||
1382 | static struct { | |
1383 | int active; | |
1384 | /* r/w apic fields */ | |
1385 | unsigned int apic_id; | |
1386 | unsigned int apic_taskpri; | |
1387 | unsigned int apic_ldr; | |
1388 | unsigned int apic_dfr; | |
1389 | unsigned int apic_spiv; | |
1390 | unsigned int apic_lvtt; | |
1391 | unsigned int apic_lvtpc; | |
1392 | unsigned int apic_lvt0; | |
1393 | unsigned int apic_lvt1; | |
1394 | unsigned int apic_lvterr; | |
1395 | unsigned int apic_tmict; | |
1396 | unsigned int apic_tdcr; | |
1397 | unsigned int apic_thmr; | |
1398 | } apic_pm_state; | |
1399 | ||
1400 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1401 | { | |
1402 | unsigned long flags; | |
1403 | int maxlvt; | |
1404 | ||
1405 | if (!apic_pm_state.active) | |
1406 | return 0; | |
1407 | ||
1408 | maxlvt = lapic_get_maxlvt(); | |
1409 | ||
1410 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
1411 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1412 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1413 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1414 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1415 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1416 | if (maxlvt >= 4) | |
1417 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1418 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1419 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1420 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1421 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1422 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1423 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1424 | if (maxlvt >= 5) | |
1425 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1da177e4 | 1426 | #endif |
1e4c85f9 | 1427 | |
e05d723f TG |
1428 | local_irq_save(flags); |
1429 | disable_local_APIC(); | |
1430 | local_irq_restore(flags); | |
1e4c85f9 | 1431 | return 0; |
1da177e4 | 1432 | } |
1a3f239d | 1433 | |
e05d723f | 1434 | static int lapic_resume(struct sys_device *dev) |
1a3f239d | 1435 | { |
e05d723f TG |
1436 | unsigned int l, h; |
1437 | unsigned long flags; | |
1438 | int maxlvt; | |
1439 | ||
1440 | if (!apic_pm_state.active) | |
1441 | return 0; | |
1442 | ||
1443 | maxlvt = lapic_get_maxlvt(); | |
1444 | ||
1445 | local_irq_save(flags); | |
1446 | ||
1447 | /* | |
1448 | * Make sure the APICBASE points to the right address | |
1449 | * | |
1450 | * FIXME! This will be wrong if we ever support suspend on | |
1451 | * SMP! We'll need to do this as part of the CPU restore! | |
1452 | */ | |
1453 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1454 | l &= ~MSR_IA32_APICBASE_BASE; | |
1455 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1456 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1457 | ||
1458 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1459 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1460 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1461 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1462 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1463 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1464 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1465 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1466 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1467 | if (maxlvt >= 5) | |
1468 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1469 | #endif | |
1470 | if (maxlvt >= 4) | |
1471 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1472 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1473 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1474 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1475 | apic_write(APIC_ESR, 0); | |
1476 | apic_read(APIC_ESR); | |
1477 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1478 | apic_write(APIC_ESR, 0); | |
1479 | apic_read(APIC_ESR); | |
1480 | local_irq_restore(flags); | |
1a3f239d RR |
1481 | return 0; |
1482 | } | |
1a3f239d | 1483 | |
e05d723f TG |
1484 | /* |
1485 | * This device has no shutdown method - fully functioning local APICs | |
1486 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1487 | */ | |
1488 | ||
1489 | static struct sysdev_class lapic_sysclass = { | |
af5ca3f4 | 1490 | .name = "lapic", |
e05d723f TG |
1491 | .resume = lapic_resume, |
1492 | .suspend = lapic_suspend, | |
1493 | }; | |
1494 | ||
1495 | static struct sys_device device_lapic = { | |
1496 | .id = 0, | |
1497 | .cls = &lapic_sysclass, | |
1498 | }; | |
1499 | ||
1500 | static void __devinit apic_pm_activate(void) | |
1a3f239d | 1501 | { |
e05d723f | 1502 | apic_pm_state.active = 1; |
1a3f239d | 1503 | } |
1a3f239d | 1504 | |
e05d723f TG |
1505 | static int __init init_lapic_sysfs(void) |
1506 | { | |
1507 | int error; | |
1508 | ||
1509 | if (!cpu_has_apic) | |
1510 | return 0; | |
1511 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
1512 | ||
1513 | error = sysdev_class_register(&lapic_sysclass); | |
1514 | if (!error) | |
1515 | error = sysdev_register(&device_lapic); | |
1516 | return error; | |
1517 | } | |
1518 | device_initcall(init_lapic_sysfs); | |
1519 | ||
1520 | #else /* CONFIG_PM */ | |
1521 | ||
1522 | static void apic_pm_activate(void) { } | |
1523 | ||
1524 | #endif /* CONFIG_PM */ | |
0e078e2f TG |
1525 | |
1526 | /* | |
1527 | * APIC command line parameters | |
1528 | */ | |
1529 | static int __init parse_lapic(char *arg) | |
1530 | { | |
1531 | enable_local_apic = 1; | |
1532 | return 0; | |
1533 | } | |
1534 | early_param("lapic", parse_lapic); | |
1535 | ||
1536 | static int __init parse_nolapic(char *arg) | |
1537 | { | |
1538 | enable_local_apic = -1; | |
53756d37 | 1539 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
0e078e2f TG |
1540 | return 0; |
1541 | } | |
1542 | early_param("nolapic", parse_nolapic); | |
1543 | ||
1544 | static int __init parse_disable_lapic_timer(char *arg) | |
1545 | { | |
1546 | local_apic_timer_disabled = 1; | |
1547 | return 0; | |
1548 | } | |
1549 | early_param("nolapic_timer", parse_disable_lapic_timer); | |
1550 | ||
1551 | static int __init parse_lapic_timer_c2_ok(char *arg) | |
1552 | { | |
1553 | local_apic_timer_c2_ok = 1; | |
1554 | return 0; | |
1555 | } | |
1556 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1557 | ||
1558 | static int __init apic_set_verbosity(char *str) | |
1559 | { | |
1560 | if (strcmp("debug", str) == 0) | |
1561 | apic_verbosity = APIC_DEBUG; | |
1562 | else if (strcmp("verbose", str) == 0) | |
1563 | apic_verbosity = APIC_VERBOSE; | |
1564 | return 1; | |
1565 | } | |
1566 | __setup("apic=", apic_set_verbosity); | |
1567 |