Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
f3705136 | 26 | #include <linux/cpu.h> |
e9e2cdb4 | 27 | #include <linux/clockchips.h> |
d36b49b9 | 28 | #include <linux/acpi_pmtmr.h> |
6eb0a0fd | 29 | #include <linux/module.h> |
ad62ca2b | 30 | #include <linux/dmi.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/arch_hooks.h> | |
38 | #include <asm/hpet.h> | |
306e440d | 39 | #include <asm/i8253.h> |
3e4ff115 | 40 | #include <asm/nmi.h> |
1da177e4 LT |
41 | |
42 | #include <mach_apic.h> | |
382dbd07 | 43 | #include <mach_apicdef.h> |
6eb0a0fd | 44 | #include <mach_ipi.h> |
1da177e4 | 45 | |
e05d723f TG |
46 | /* |
47 | * Sanity check | |
48 | */ | |
ff8a03a6 | 49 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) |
e05d723f TG |
50 | # error SPURIOUS_APIC_VECTOR definition error |
51 | #endif | |
52 | ||
9635b47d EB |
53 | /* |
54 | * Knob to control our willingness to enable the local APIC. | |
e05d723f TG |
55 | * |
56 | * -1=force-disable, +1=force-enable | |
9635b47d | 57 | */ |
ff8a03a6 | 58 | static int enable_local_apic __initdata; |
9635b47d | 59 | |
d36b49b9 TG |
60 | /* Local APIC timer verification ok */ |
61 | static int local_apic_timer_verify_ok; | |
d3f7eae1 AK |
62 | /* Disable local APIC timer from the kernel commandline or via dmi quirk |
63 | or using CPU MSR check */ | |
64 | int local_apic_timer_disabled; | |
e585bef8 TG |
65 | /* Local APIC timer works in C2 */ |
66 | int local_apic_timer_c2_ok; | |
67 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
e9e2cdb4 | 68 | |
1da177e4 | 69 | /* |
e05d723f | 70 | * Debug level, exported for io_apic.c |
1da177e4 LT |
71 | */ |
72 | int apic_verbosity; | |
73 | ||
e9e2cdb4 | 74 | static unsigned int calibration_result; |
1da177e4 | 75 | |
e9e2cdb4 TG |
76 | static int lapic_next_event(unsigned long delta, |
77 | struct clock_event_device *evt); | |
78 | static void lapic_timer_setup(enum clock_event_mode mode, | |
79 | struct clock_event_device *evt); | |
80 | static void lapic_timer_broadcast(cpumask_t mask); | |
81 | static void apic_pm_activate(void); | |
e05d723f | 82 | |
e9e2cdb4 TG |
83 | /* |
84 | * The local apic timer can be used for any function which is CPU local. | |
85 | */ | |
86 | static struct clock_event_device lapic_clockevent = { | |
87 | .name = "lapic", | |
88 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
d36b49b9 | 89 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
e9e2cdb4 TG |
90 | .shift = 32, |
91 | .set_mode = lapic_timer_setup, | |
92 | .set_next_event = lapic_next_event, | |
93 | .broadcast = lapic_timer_broadcast, | |
94 | .rating = 100, | |
95 | .irq = -1, | |
96 | }; | |
97 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
e05d723f TG |
98 | |
99 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ | |
100 | static int enabled_via_apicbase; | |
101 | ||
d3432896 AK |
102 | static unsigned long apic_phys; |
103 | ||
e05d723f TG |
104 | /* |
105 | * Get the LAPIC version | |
106 | */ | |
107 | static inline int lapic_get_version(void) | |
95d769aa | 108 | { |
e05d723f | 109 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
95d769aa AK |
110 | } |
111 | ||
1da177e4 | 112 | /* |
ab4a574e | 113 | * Check, if the APIC is integrated or a separate chip |
1da177e4 | 114 | */ |
e05d723f | 115 | static inline int lapic_is_integrated(void) |
1da177e4 | 116 | { |
e05d723f | 117 | return APIC_INTEGRATED(lapic_get_version()); |
1da177e4 LT |
118 | } |
119 | ||
e05d723f TG |
120 | /* |
121 | * Check, whether this is a modern or a first generation APIC | |
122 | */ | |
123 | static int modern_apic(void) | |
1da177e4 | 124 | { |
e05d723f TG |
125 | /* AMD systems use old APIC versions, so check the CPU */ |
126 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
127 | boot_cpu_data.x86 >= 0xf) | |
128 | return 1; | |
129 | return lapic_get_version() >= 0x14; | |
1da177e4 LT |
130 | } |
131 | ||
f2b218dd FLV |
132 | void apic_wait_icr_idle(void) |
133 | { | |
134 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
135 | cpu_relax(); | |
136 | } | |
137 | ||
42e0a9aa | 138 | u32 safe_apic_wait_icr_idle(void) |
f2b218dd | 139 | { |
42e0a9aa | 140 | u32 send_status; |
f2b218dd FLV |
141 | int timeout; |
142 | ||
143 | timeout = 0; | |
144 | do { | |
145 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
146 | if (!send_status) | |
147 | break; | |
148 | udelay(100); | |
149 | } while (timeout++ < 1000); | |
150 | ||
151 | return send_status; | |
152 | } | |
153 | ||
e05d723f TG |
154 | /** |
155 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
156 | */ | |
e9427101 | 157 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 158 | { |
e05d723f | 159 | unsigned int v = APIC_DM_NMI; |
1da177e4 | 160 | |
e05d723f TG |
161 | /* Level triggered for 82489DX */ |
162 | if (!lapic_is_integrated()) | |
1da177e4 LT |
163 | v |= APIC_LVT_LEVEL_TRIGGER; |
164 | apic_write_around(APIC_LVT0, v); | |
165 | } | |
166 | ||
e05d723f TG |
167 | /** |
168 | * get_physical_broadcast - Get number of physical broadcast IDs | |
169 | */ | |
1da177e4 LT |
170 | int get_physical_broadcast(void) |
171 | { | |
e05d723f | 172 | return modern_apic() ? 0xff : 0xf; |
1da177e4 LT |
173 | } |
174 | ||
e05d723f TG |
175 | /** |
176 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
177 | */ | |
178 | int lapic_get_maxlvt(void) | |
1da177e4 | 179 | { |
e05d723f | 180 | unsigned int v = apic_read(APIC_LVR); |
1da177e4 | 181 | |
1da177e4 | 182 | /* 82489DXs do not report # of LVT entries. */ |
e05d723f | 183 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
1da177e4 LT |
184 | } |
185 | ||
e05d723f TG |
186 | /* |
187 | * Local APIC timer | |
188 | */ | |
189 | ||
d36b49b9 TG |
190 | /* Clock divisor is set to 16 */ |
191 | #define APIC_DIVISOR 16 | |
e05d723f TG |
192 | |
193 | /* | |
194 | * This function sets up the local APIC timer, with a timeout of | |
195 | * 'clocks' APIC bus clock. During calibration we actually call | |
196 | * this function twice on the boot CPU, once with a bogus timeout | |
197 | * value, second time for real. The other (noncalibrating) CPUs | |
198 | * call this function only once, with the real, calibrated value. | |
199 | * | |
200 | * We do reads before writes even if unnecessary, to get around the | |
201 | * P5 APIC double write bug. | |
202 | */ | |
e9e2cdb4 | 203 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 204 | { |
e05d723f | 205 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 206 | |
e9e2cdb4 TG |
207 | lvtt_value = LOCAL_TIMER_VECTOR; |
208 | if (!oneshot) | |
209 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
e05d723f TG |
210 | if (!lapic_is_integrated()) |
211 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
212 | ||
e9e2cdb4 | 213 | if (!irqen) |
e05d723f TG |
214 | lvtt_value |= APIC_LVT_MASKED; |
215 | ||
216 | apic_write_around(APIC_LVTT, lvtt_value); | |
1da177e4 LT |
217 | |
218 | /* | |
e05d723f | 219 | * Divide PICLK by 16 |
1da177e4 | 220 | */ |
e05d723f TG |
221 | tmp_value = apic_read(APIC_TDCR); |
222 | apic_write_around(APIC_TDCR, (tmp_value | |
223 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
224 | | APIC_TDR_DIV_16); | |
1da177e4 | 225 | |
e9e2cdb4 TG |
226 | if (!oneshot) |
227 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); | |
228 | } | |
229 | ||
230 | /* | |
231 | * Program the next event, relative to now | |
232 | */ | |
233 | static int lapic_next_event(unsigned long delta, | |
234 | struct clock_event_device *evt) | |
235 | { | |
236 | apic_write_around(APIC_TMICT, delta); | |
237 | return 0; | |
1da177e4 LT |
238 | } |
239 | ||
e9e2cdb4 TG |
240 | /* |
241 | * Setup the lapic timer in periodic or oneshot mode | |
242 | */ | |
243 | static void lapic_timer_setup(enum clock_event_mode mode, | |
244 | struct clock_event_device *evt) | |
1da177e4 | 245 | { |
e05d723f | 246 | unsigned long flags; |
e9e2cdb4 | 247 | unsigned int v; |
e05d723f | 248 | |
d36b49b9 TG |
249 | /* Lapic used for broadcast ? */ |
250 | if (!local_apic_timer_verify_ok) | |
251 | return; | |
252 | ||
e05d723f | 253 | local_irq_save(flags); |
1da177e4 | 254 | |
e9e2cdb4 TG |
255 | switch (mode) { |
256 | case CLOCK_EVT_MODE_PERIODIC: | |
257 | case CLOCK_EVT_MODE_ONESHOT: | |
258 | __setup_APIC_LVTT(calibration_result, | |
259 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
260 | break; | |
261 | case CLOCK_EVT_MODE_UNUSED: | |
262 | case CLOCK_EVT_MODE_SHUTDOWN: | |
263 | v = apic_read(APIC_LVTT); | |
264 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
265 | apic_write_around(APIC_LVTT, v); | |
266 | break; | |
18de5bc4 TG |
267 | case CLOCK_EVT_MODE_RESUME: |
268 | /* Nothing to do here */ | |
269 | break; | |
e9e2cdb4 | 270 | } |
e05d723f TG |
271 | |
272 | local_irq_restore(flags); | |
273 | } | |
274 | ||
e9e2cdb4 TG |
275 | /* |
276 | * Local APIC timer broadcast function | |
277 | */ | |
278 | static void lapic_timer_broadcast(cpumask_t mask) | |
279 | { | |
280 | #ifdef CONFIG_SMP | |
281 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
282 | #endif | |
283 | } | |
284 | ||
285 | /* | |
286 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
287 | * of the boot CPU and register the clock event in the framework. | |
288 | */ | |
289 | static void __devinit setup_APIC_timer(void) | |
290 | { | |
291 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
292 | ||
293 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); | |
294 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
295 | ||
296 | clockevents_register_device(levt); | |
297 | } | |
298 | ||
e05d723f | 299 | /* |
d36b49b9 TG |
300 | * In this functions we calibrate APIC bus clocks to the external timer. |
301 | * | |
302 | * We want to do the calibration only once since we want to have local timer | |
303 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
304 | * frequency. | |
305 | * | |
306 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
307 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
308 | * readout is broken, so it never gets out of the wait loop again. This was | |
309 | * also reported by others. | |
e05d723f | 310 | * |
d36b49b9 TG |
311 | * Monitoring the jiffies value is inaccurate and the clockevents |
312 | * infrastructure allows us to do a simple substitution of the interrupt | |
313 | * handler. | |
e9e2cdb4 | 314 | * |
d36b49b9 TG |
315 | * The calibration routine also uses the pm_timer when possible, as the PIT |
316 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
317 | * back to normal later in the boot process). | |
e05d723f TG |
318 | */ |
319 | ||
d36b49b9 | 320 | #define LAPIC_CAL_LOOPS (HZ/10) |
e05d723f | 321 | |
f5352fd0 | 322 | static __initdata int lapic_cal_loops = -1; |
d36b49b9 TG |
323 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
324 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
325 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
326 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
1da177e4 | 327 | |
d36b49b9 TG |
328 | /* |
329 | * Temporary interrupt handler. | |
330 | */ | |
331 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
332 | { | |
333 | unsigned long long tsc = 0; | |
334 | long tapic = apic_read(APIC_TMCCT); | |
335 | unsigned long pm = acpi_pm_read_early(); | |
1da177e4 | 336 | |
d36b49b9 TG |
337 | if (cpu_has_tsc) |
338 | rdtscll(tsc); | |
339 | ||
340 | switch (lapic_cal_loops++) { | |
341 | case 0: | |
342 | lapic_cal_t1 = tapic; | |
343 | lapic_cal_tsc1 = tsc; | |
344 | lapic_cal_pm1 = pm; | |
345 | lapic_cal_j1 = jiffies; | |
346 | break; | |
e05d723f | 347 | |
d36b49b9 TG |
348 | case LAPIC_CAL_LOOPS: |
349 | lapic_cal_t2 = tapic; | |
350 | lapic_cal_tsc2 = tsc; | |
351 | if (pm < lapic_cal_pm1) | |
352 | pm += ACPI_PM_OVRRUN; | |
353 | lapic_cal_pm2 = pm; | |
354 | lapic_cal_j2 = jiffies; | |
355 | break; | |
356 | } | |
357 | } | |
1da177e4 | 358 | |
d36b49b9 TG |
359 | /* |
360 | * Setup the boot APIC | |
361 | * | |
362 | * Calibrate and verify the result. | |
363 | */ | |
364 | void __init setup_boot_APIC_clock(void) | |
365 | { | |
366 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
367 | const long pm_100ms = PMTMR_TICKS_PER_SEC/10; | |
368 | const long pm_thresh = pm_100ms/100; | |
369 | void (*real_handler)(struct clock_event_device *dev); | |
370 | unsigned long deltaj; | |
371 | long delta, deltapm; | |
ca1b940c | 372 | int pm_referenced = 0; |
1da177e4 | 373 | |
ad62ca2b TG |
374 | /* |
375 | * The local apic timer can be disabled via the kernel | |
d3f7eae1 | 376 | * commandline or from the CPU detection code. Register the lapic |
ad62ca2b TG |
377 | * timer as a dummy clock event source on SMP systems, so the |
378 | * broadcast mechanism is used. On UP systems simply ignore it. | |
379 | */ | |
380 | if (local_apic_timer_disabled) { | |
381 | /* No broadcast on UP ! */ | |
9d09951d TG |
382 | if (num_possible_cpus() > 1) { |
383 | lapic_clockevent.mult = 1; | |
ad62ca2b | 384 | setup_APIC_timer(); |
9d09951d | 385 | } |
ad62ca2b TG |
386 | return; |
387 | } | |
388 | ||
d36b49b9 TG |
389 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
390 | "calibrating APIC timer ...\n"); | |
1da177e4 | 391 | |
d36b49b9 TG |
392 | local_irq_disable(); |
393 | ||
394 | /* Replace the global interrupt handler */ | |
395 | real_handler = global_clock_event->event_handler; | |
396 | global_clock_event->event_handler = lapic_cal_handler; | |
1da177e4 | 397 | |
1da177e4 | 398 | /* |
d36b49b9 TG |
399 | * Setup the APIC counter to 1e9. There is no way the lapic |
400 | * can underflow in the 100ms detection time frame | |
1da177e4 | 401 | */ |
d36b49b9 | 402 | __setup_APIC_LVTT(1000000000, 0, 0); |
1da177e4 | 403 | |
d36b49b9 TG |
404 | /* Let the interrupts run */ |
405 | local_irq_enable(); | |
406 | ||
ca1b940c TG |
407 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
408 | cpu_relax(); | |
d36b49b9 TG |
409 | |
410 | local_irq_disable(); | |
411 | ||
412 | /* Restore the real event handler */ | |
413 | global_clock_event->event_handler = real_handler; | |
414 | ||
415 | /* Build delta t1-t2 as apic timer counts down */ | |
416 | delta = lapic_cal_t1 - lapic_cal_t2; | |
417 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
418 | ||
419 | /* Check, if the PM timer is available */ | |
420 | deltapm = lapic_cal_pm2 - lapic_cal_pm1; | |
421 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
422 | ||
423 | if (deltapm) { | |
424 | unsigned long mult; | |
425 | u64 res; | |
426 | ||
427 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
428 | ||
429 | if (deltapm > (pm_100ms - pm_thresh) && | |
430 | deltapm < (pm_100ms + pm_thresh)) { | |
431 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
432 | } else { | |
433 | res = (((u64) deltapm) * mult) >> 22; | |
434 | do_div(res, 1000000); | |
435 | printk(KERN_WARNING "APIC calibration not consistent " | |
436 | "with PM Timer: %ldms instead of 100ms\n", | |
437 | (long)res); | |
438 | /* Correct the lapic counter value */ | |
ff8a03a6 | 439 | res = (((u64) delta) * pm_100ms); |
d36b49b9 TG |
440 | do_div(res, deltapm); |
441 | printk(KERN_INFO "APIC delta adjusted to PM-Timer: " | |
442 | "%lu (%ld)\n", (unsigned long) res, delta); | |
443 | delta = (long) res; | |
444 | } | |
ca1b940c | 445 | pm_referenced = 1; |
d36b49b9 | 446 | } |
e05d723f | 447 | |
e9e2cdb4 | 448 | /* Calculate the scaled math multiplication factor */ |
d36b49b9 | 449 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 32); |
e9e2cdb4 TG |
450 | lapic_clockevent.max_delta_ns = |
451 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
452 | lapic_clockevent.min_delta_ns = | |
453 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
454 | ||
d36b49b9 TG |
455 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
456 | ||
457 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
e9e2cdb4 | 458 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); |
d36b49b9 TG |
459 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
460 | calibration_result); | |
e9e2cdb4 | 461 | |
d36b49b9 TG |
462 | if (cpu_has_tsc) { |
463 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
e05d723f | 464 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
d36b49b9 TG |
465 | "%ld.%04ld MHz.\n", |
466 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
467 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
468 | } | |
e05d723f TG |
469 | |
470 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
d36b49b9 TG |
471 | "%u.%04u MHz.\n", |
472 | calibration_result / (1000000 / HZ), | |
473 | calibration_result % (1000000 / HZ)); | |
e05d723f | 474 | |
d36b49b9 | 475 | local_apic_timer_verify_ok = 1; |
d36b49b9 | 476 | |
c2b84b30 TG |
477 | /* |
478 | * Do a sanity check on the APIC calibration result | |
479 | */ | |
480 | if (calibration_result < (1000000 / HZ)) { | |
481 | local_irq_enable(); | |
482 | printk(KERN_WARNING | |
483 | "APIC frequency too slow, disabling apic timer\n"); | |
484 | /* No broadcast on UP ! */ | |
485 | if (num_possible_cpus() > 1) | |
486 | setup_APIC_timer(); | |
487 | return; | |
488 | } | |
489 | ||
ca1b940c TG |
490 | /* We trust the pm timer based calibration */ |
491 | if (!pm_referenced) { | |
492 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
d36b49b9 | 493 | |
ca1b940c TG |
494 | /* |
495 | * Setup the apic timer manually | |
496 | */ | |
497 | levt->event_handler = lapic_cal_handler; | |
498 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
499 | lapic_cal_loops = -1; | |
d36b49b9 | 500 | |
ca1b940c TG |
501 | /* Let the interrupts run */ |
502 | local_irq_enable(); | |
d36b49b9 | 503 | |
f5352fd0 | 504 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
ca1b940c | 505 | cpu_relax(); |
d36b49b9 | 506 | |
ca1b940c | 507 | local_irq_disable(); |
d36b49b9 | 508 | |
ca1b940c TG |
509 | /* Stop the lapic timer */ |
510 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
d36b49b9 | 511 | |
ca1b940c | 512 | local_irq_enable(); |
d36b49b9 | 513 | |
ca1b940c TG |
514 | /* Jiffies delta */ |
515 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
516 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
d36b49b9 | 517 | |
d36b49b9 | 518 | /* Check, if the jiffies result is consistent */ |
ca1b940c | 519 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
d36b49b9 | 520 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
ca1b940c TG |
521 | else |
522 | local_apic_timer_verify_ok = 0; | |
4edc5db8 IM |
523 | } else |
524 | local_irq_enable(); | |
e05d723f | 525 | |
d36b49b9 TG |
526 | if (!local_apic_timer_verify_ok) { |
527 | printk(KERN_WARNING | |
528 | "APIC timer disabled due to verification failure.\n"); | |
529 | /* No broadcast on UP ! */ | |
530 | if (num_possible_cpus() == 1) | |
531 | return; | |
a5f5e43e TG |
532 | } else { |
533 | /* | |
534 | * If nmi_watchdog is set to IO_APIC, we need the | |
535 | * PIT/HPET going. Otherwise register lapic as a dummy | |
536 | * device. | |
537 | */ | |
538 | if (nmi_watchdog != NMI_IO_APIC) | |
539 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
820de5c3 IM |
540 | else |
541 | printk(KERN_WARNING "APIC timer registered as dummy," | |
542 | " due to nmi_watchdog=1!\n"); | |
a5f5e43e | 543 | } |
d36b49b9 TG |
544 | |
545 | /* Setup the lapic or request the broadcast */ | |
546 | setup_APIC_timer(); | |
e05d723f | 547 | } |
1da177e4 | 548 | |
e05d723f TG |
549 | void __devinit setup_secondary_APIC_clock(void) |
550 | { | |
e9e2cdb4 | 551 | setup_APIC_timer(); |
e05d723f | 552 | } |
1da177e4 | 553 | |
e05d723f | 554 | /* |
e9e2cdb4 | 555 | * The guts of the apic timer interrupt |
e05d723f | 556 | */ |
e9e2cdb4 | 557 | static void local_apic_timer_interrupt(void) |
e05d723f | 558 | { |
e9e2cdb4 TG |
559 | int cpu = smp_processor_id(); |
560 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
1da177e4 LT |
561 | |
562 | /* | |
d36b49b9 TG |
563 | * Normally we should not be here till LAPIC has been initialized but |
564 | * in some cases like kdump, its possible that there is a pending LAPIC | |
565 | * timer interrupt from previous kernel's context and is delivered in | |
566 | * new kernel the moment interrupts are enabled. | |
e05d723f | 567 | * |
d36b49b9 TG |
568 | * Interrupts are enabled early and LAPIC is setup much later, hence |
569 | * its possible that when we get here evt->event_handler is NULL. | |
570 | * Check for event_handler being NULL and discard the interrupt as | |
571 | * spurious. | |
1da177e4 | 572 | */ |
e9e2cdb4 TG |
573 | if (!evt->event_handler) { |
574 | printk(KERN_WARNING | |
575 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
576 | /* Switch it off */ | |
577 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
578 | return; | |
579 | } | |
580 | ||
0e078e2f TG |
581 | /* |
582 | * the NMI deadlock-detector uses this. | |
583 | */ | |
e9e2cdb4 TG |
584 | per_cpu(irq_stat, cpu).apic_timer_irqs++; |
585 | ||
586 | evt->event_handler(evt); | |
e05d723f TG |
587 | } |
588 | ||
589 | /* | |
590 | * Local APIC timer interrupt. This is the most natural way for doing | |
591 | * local interrupts, but local timer interrupts can be emulated by | |
592 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
593 | * | |
594 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
595 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
596 | */ | |
75604d7f | 597 | void smp_apic_timer_interrupt(struct pt_regs *regs) |
e05d723f TG |
598 | { |
599 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1da177e4 LT |
600 | |
601 | /* | |
e05d723f TG |
602 | * NOTE! We'd better ACK the irq immediately, |
603 | * because timer handling can be slow. | |
1da177e4 | 604 | */ |
e05d723f | 605 | ack_APIC_irq(); |
1a75a3f0 | 606 | /* |
e05d723f TG |
607 | * update_process_times() expects us to have done irq_enter(). |
608 | * Besides, if we don't timer interrupts ignore the global | |
609 | * interrupt lock, which is the WrongThing (tm) to do. | |
1a75a3f0 | 610 | */ |
e05d723f | 611 | irq_enter(); |
e9e2cdb4 | 612 | local_apic_timer_interrupt(); |
e05d723f | 613 | irq_exit(); |
1a75a3f0 | 614 | |
e9e2cdb4 | 615 | set_irq_regs(old_regs); |
e05d723f TG |
616 | } |
617 | ||
618 | int setup_profiling_timer(unsigned int multiplier) | |
619 | { | |
620 | return -EINVAL; | |
621 | } | |
622 | ||
e319e765 RR |
623 | /* |
624 | * Setup extended LVT, AMD specific (K8, family 10h) | |
625 | * | |
626 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
627 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
628 | */ | |
629 | ||
630 | #define APIC_EILVT_LVTOFF_MCE 0 | |
631 | #define APIC_EILVT_LVTOFF_IBS 1 | |
632 | ||
633 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
634 | { | |
635 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; | |
636 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; | |
637 | apic_write(reg, v); | |
638 | } | |
639 | ||
640 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) | |
641 | { | |
642 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
643 | return APIC_EILVT_LVTOFF_MCE; | |
644 | } | |
645 | ||
646 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
647 | { | |
648 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
649 | return APIC_EILVT_LVTOFF_IBS; | |
650 | } | |
651 | ||
e05d723f TG |
652 | /* |
653 | * Local APIC start and shutdown | |
654 | */ | |
655 | ||
656 | /** | |
657 | * clear_local_APIC - shutdown the local APIC | |
658 | * | |
659 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
660 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
661 | * leftovers during boot. | |
662 | */ | |
663 | void clear_local_APIC(void) | |
664 | { | |
d3432896 | 665 | int maxlvt; |
0e078e2f | 666 | u32 v; |
1da177e4 | 667 | |
d3432896 AK |
668 | /* APIC hasn't been mapped yet */ |
669 | if (!apic_phys) | |
670 | return; | |
671 | ||
672 | maxlvt = lapic_get_maxlvt(); | |
1da177e4 | 673 | /* |
e05d723f TG |
674 | * Masking an LVT entry can trigger a local APIC error |
675 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1da177e4 | 676 | */ |
e05d723f TG |
677 | if (maxlvt >= 3) { |
678 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
679 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); | |
680 | } | |
1da177e4 | 681 | /* |
e05d723f TG |
682 | * Careful: we have to set masks only first to deassert |
683 | * any level-triggered sources. | |
1da177e4 | 684 | */ |
e05d723f TG |
685 | v = apic_read(APIC_LVTT); |
686 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
687 | v = apic_read(APIC_LVT0); | |
688 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
689 | v = apic_read(APIC_LVT1); | |
690 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); | |
691 | if (maxlvt >= 4) { | |
692 | v = apic_read(APIC_LVTPC); | |
693 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1da177e4 | 694 | } |
1da177e4 | 695 | |
e05d723f TG |
696 | /* lets not touch this if we didn't frob it */ |
697 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
698 | if (maxlvt >= 5) { | |
699 | v = apic_read(APIC_LVTTHMR); | |
700 | apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
701 | } | |
702 | #endif | |
1da177e4 | 703 | /* |
e05d723f | 704 | * Clean APIC state for other OSs: |
1da177e4 | 705 | */ |
e05d723f TG |
706 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); |
707 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
708 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); | |
709 | if (maxlvt >= 3) | |
710 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); | |
711 | if (maxlvt >= 4) | |
712 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); | |
1da177e4 | 713 | |
e05d723f TG |
714 | #ifdef CONFIG_X86_MCE_P4THERMAL |
715 | if (maxlvt >= 5) | |
716 | apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); | |
717 | #endif | |
718 | /* Integrated APIC (!82489DX) ? */ | |
719 | if (lapic_is_integrated()) { | |
1da177e4 | 720 | if (maxlvt > 3) |
e05d723f | 721 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
1da177e4 | 722 | apic_write(APIC_ESR, 0); |
e05d723f | 723 | apic_read(APIC_ESR); |
1da177e4 | 724 | } |
e05d723f | 725 | } |
1da177e4 | 726 | |
e05d723f TG |
727 | /** |
728 | * disable_local_APIC - clear and disable the local APIC | |
729 | */ | |
730 | void disable_local_APIC(void) | |
731 | { | |
732 | unsigned long value; | |
733 | ||
734 | clear_local_APIC(); | |
735 | ||
736 | /* | |
737 | * Disable APIC (implies clearing of registers | |
738 | * for 82489DX!). | |
739 | */ | |
740 | value = apic_read(APIC_SPIV); | |
741 | value &= ~APIC_SPIV_APIC_ENABLED; | |
742 | apic_write_around(APIC_SPIV, value); | |
743 | ||
744 | /* | |
745 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
746 | * restore the disabled state. | |
747 | */ | |
748 | if (enabled_via_apicbase) { | |
749 | unsigned int l, h; | |
750 | ||
751 | rdmsr(MSR_IA32_APICBASE, l, h); | |
752 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
753 | wrmsr(MSR_IA32_APICBASE, l, h); | |
754 | } | |
1da177e4 LT |
755 | } |
756 | ||
757 | /* | |
e05d723f TG |
758 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
759 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
760 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
77f72b19 | 761 | * for the case where Linux didn't enable the LAPIC. |
1da177e4 LT |
762 | */ |
763 | void lapic_shutdown(void) | |
764 | { | |
67963132 MS |
765 | unsigned long flags; |
766 | ||
77f72b19 | 767 | if (!cpu_has_apic) |
1da177e4 LT |
768 | return; |
769 | ||
67963132 | 770 | local_irq_save(flags); |
77f72b19 ZM |
771 | clear_local_APIC(); |
772 | ||
773 | if (enabled_via_apicbase) | |
774 | disable_local_APIC(); | |
775 | ||
67963132 | 776 | local_irq_restore(flags); |
1da177e4 LT |
777 | } |
778 | ||
e05d723f TG |
779 | /* |
780 | * This is to verify that we're looking at a real local APIC. | |
781 | * Check these against your board if the CPUs aren't getting | |
782 | * started for no apparent reason. | |
783 | */ | |
784 | int __init verify_local_APIC(void) | |
1da177e4 | 785 | { |
e05d723f | 786 | unsigned int reg0, reg1; |
1da177e4 | 787 | |
e05d723f TG |
788 | /* |
789 | * The version register is read-only in a real APIC. | |
790 | */ | |
791 | reg0 = apic_read(APIC_LVR); | |
792 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
793 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
794 | reg1 = apic_read(APIC_LVR); | |
795 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
796 | ||
797 | /* | |
798 | * The two version reads above should print the same | |
799 | * numbers. If the second one is different, then we | |
800 | * poke at a non-APIC. | |
801 | */ | |
802 | if (reg1 != reg0) | |
1da177e4 LT |
803 | return 0; |
804 | ||
e05d723f TG |
805 | /* |
806 | * Check if the version looks reasonably. | |
807 | */ | |
808 | reg1 = GET_APIC_VERSION(reg0); | |
809 | if (reg1 == 0x00 || reg1 == 0xff) | |
810 | return 0; | |
811 | reg1 = lapic_get_maxlvt(); | |
812 | if (reg1 < 0x02 || reg1 == 0xff) | |
813 | return 0; | |
f990fff4 | 814 | |
e05d723f TG |
815 | /* |
816 | * The ID register is read/write in a real APIC. | |
817 | */ | |
818 | reg0 = apic_read(APIC_ID); | |
819 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
820 | ||
821 | /* | |
822 | * The next two are just to see if we have sane values. | |
823 | * They're only really relevant if we're in Virtual Wire | |
824 | * compatibility mode, but most boxes are anymore. | |
825 | */ | |
826 | reg0 = apic_read(APIC_LVT0); | |
827 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
828 | reg1 = apic_read(APIC_LVT1); | |
829 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
830 | ||
831 | return 1; | |
1da177e4 LT |
832 | } |
833 | ||
e05d723f TG |
834 | /** |
835 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
836 | */ | |
837 | void __init sync_Arb_IDs(void) | |
1da177e4 | 838 | { |
e05d723f TG |
839 | /* |
840 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
841 | * needed on AMD. | |
842 | */ | |
f44d9efd | 843 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
e05d723f TG |
844 | return; |
845 | /* | |
846 | * Wait for idle. | |
847 | */ | |
848 | apic_wait_icr_idle(); | |
1da177e4 | 849 | |
e05d723f TG |
850 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
851 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | |
852 | | APIC_DM_INIT); | |
853 | } | |
1da177e4 | 854 | |
e05d723f TG |
855 | /* |
856 | * An initial setup of the virtual wire mode. | |
857 | */ | |
858 | void __init init_bsp_APIC(void) | |
859 | { | |
860 | unsigned long value; | |
f990fff4 | 861 | |
e05d723f TG |
862 | /* |
863 | * Don't do the setup now if we have a SMP BIOS as the | |
864 | * through-I/O-APIC virtual wire mode might be active. | |
865 | */ | |
866 | if (smp_found_config || !cpu_has_apic) | |
867 | return; | |
1da177e4 LT |
868 | |
869 | /* | |
e05d723f | 870 | * Do not trust the local APIC being empty at bootup. |
1da177e4 | 871 | */ |
e05d723f | 872 | clear_local_APIC(); |
1da177e4 | 873 | |
e05d723f TG |
874 | /* |
875 | * Enable APIC. | |
876 | */ | |
877 | value = apic_read(APIC_SPIV); | |
878 | value &= ~APIC_VECTOR_MASK; | |
879 | value |= APIC_SPIV_APIC_ENABLED; | |
880 | ||
881 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
882 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
883 | (boot_cpu_data.x86 == 15)) | |
884 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
885 | else | |
886 | value |= APIC_SPIV_FOCUS_DISABLED; | |
887 | value |= SPURIOUS_APIC_VECTOR; | |
888 | apic_write_around(APIC_SPIV, value); | |
889 | ||
890 | /* | |
891 | * Set up the virtual wire mode. | |
892 | */ | |
893 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
894 | value = APIC_DM_NMI; | |
895 | if (!lapic_is_integrated()) /* 82489DX */ | |
896 | value |= APIC_LVT_LEVEL_TRIGGER; | |
897 | apic_write_around(APIC_LVT1, value); | |
1da177e4 LT |
898 | } |
899 | ||
df7939ae GOC |
900 | void __cpuinit lapic_setup_esr(void) |
901 | { | |
902 | unsigned long oldvalue, value, maxlvt; | |
903 | if (lapic_is_integrated() && !esr_disable) { | |
904 | /* !82489DX */ | |
905 | maxlvt = lapic_get_maxlvt(); | |
906 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
907 | apic_write(APIC_ESR, 0); | |
908 | oldvalue = apic_read(APIC_ESR); | |
909 | ||
910 | /* enables sending errors */ | |
911 | value = ERROR_APIC_VECTOR; | |
912 | apic_write_around(APIC_LVTERR, value); | |
913 | /* | |
914 | * spec says clear errors after enabling vector. | |
915 | */ | |
916 | if (maxlvt > 3) | |
917 | apic_write(APIC_ESR, 0); | |
918 | value = apic_read(APIC_ESR); | |
919 | if (value != oldvalue) | |
920 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
921 | "vector: 0x%08lx after: 0x%08lx\n", | |
922 | oldvalue, value); | |
923 | } else { | |
924 | if (esr_disable) | |
925 | /* | |
926 | * Something untraceable is creating bad interrupts on | |
927 | * secondary quads ... for the moment, just leave the | |
928 | * ESR disabled - we can't do anything useful with the | |
929 | * errors anyway - mbligh | |
930 | */ | |
931 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
932 | else | |
933 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
934 | } | |
935 | } | |
936 | ||
937 | ||
e05d723f TG |
938 | /** |
939 | * setup_local_APIC - setup the local APIC | |
1da177e4 | 940 | */ |
d5337983 | 941 | void __cpuinit setup_local_APIC(void) |
e05d723f | 942 | { |
df7939ae | 943 | unsigned long value, integrated; |
e05d723f | 944 | int i, j; |
1da177e4 | 945 | |
e05d723f TG |
946 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
947 | if (esr_disable) { | |
948 | apic_write(APIC_ESR, 0); | |
949 | apic_write(APIC_ESR, 0); | |
950 | apic_write(APIC_ESR, 0); | |
951 | apic_write(APIC_ESR, 0); | |
952 | } | |
1da177e4 | 953 | |
e05d723f | 954 | integrated = lapic_is_integrated(); |
1da177e4 | 955 | |
e05d723f TG |
956 | /* |
957 | * Double-check whether this APIC is really registered. | |
958 | */ | |
959 | if (!apic_id_registered()) | |
960 | BUG(); | |
1da177e4 | 961 | |
e05d723f TG |
962 | /* |
963 | * Intel recommends to set DFR, LDR and TPR before enabling | |
964 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
965 | * document number 292116). So here it goes... | |
966 | */ | |
967 | init_apic_ldr(); | |
1da177e4 | 968 | |
e05d723f TG |
969 | /* |
970 | * Set Task Priority to 'accept all'. We never change this | |
971 | * later on. | |
972 | */ | |
973 | value = apic_read(APIC_TASKPRI); | |
974 | value &= ~APIC_TPRI_MASK; | |
975 | apic_write_around(APIC_TASKPRI, value); | |
1da177e4 | 976 | |
e05d723f TG |
977 | /* |
978 | * After a crash, we no longer service the interrupts and a pending | |
979 | * interrupt from previous kernel might still have ISR bit set. | |
980 | * | |
981 | * Most probably by now CPU has serviced that pending interrupt and | |
982 | * it might not have done the ack_APIC_irq() because it thought, | |
983 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
984 | * does not clear the ISR bit and cpu thinks it has already serivced | |
985 | * the interrupt. Hence a vector might get locked. It was noticed | |
986 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
987 | */ | |
988 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
989 | value = apic_read(APIC_ISR + i*0x10); | |
990 | for (j = 31; j >= 0; j--) { | |
991 | if (value & (1<<j)) | |
992 | ack_APIC_irq(); | |
993 | } | |
994 | } | |
1da177e4 | 995 | |
e05d723f TG |
996 | /* |
997 | * Now that we are all set up, enable the APIC | |
998 | */ | |
999 | value = apic_read(APIC_SPIV); | |
1000 | value &= ~APIC_VECTOR_MASK; | |
1001 | /* | |
1002 | * Enable APIC | |
1003 | */ | |
1004 | value |= APIC_SPIV_APIC_ENABLED; | |
1da177e4 | 1005 | |
e05d723f TG |
1006 | /* |
1007 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1008 | * certain networking cards. If high frequency interrupts are | |
1009 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1010 | * entry is masked/unmasked at a high rate as well then sooner or | |
1011 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1012 | * from the device. If focus CPU is disabled then the hang goes | |
1013 | * away, oh well :-( | |
1014 | * | |
1015 | * [ This bug can be reproduced easily with a level-triggered | |
1016 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1017 | * BX chipset. ] | |
1018 | */ | |
1019 | /* | |
1020 | * Actually disabling the focus CPU check just makes the hang less | |
1021 | * frequent as it makes the interrupt distributon model be more | |
1022 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1023 | * See also the comment in end_level_ioapic_irq(). --macro | |
1024 | */ | |
1da177e4 | 1025 | |
e05d723f TG |
1026 | /* Enable focus processor (bit==0) */ |
1027 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1028 | |
e05d723f TG |
1029 | /* |
1030 | * Set spurious IRQ vector | |
1031 | */ | |
1032 | value |= SPURIOUS_APIC_VECTOR; | |
1033 | apic_write_around(APIC_SPIV, value); | |
1034 | ||
1035 | /* | |
1036 | * Set up LVT0, LVT1: | |
1037 | * | |
1038 | * set up through-local-APIC on the BP's LINT0. This is not | |
27b46d76 | 1039 | * strictly necessary in pure symmetric-IO mode, but sometimes |
e05d723f TG |
1040 | * we delegate interrupts to the 8259A. |
1041 | */ | |
1042 | /* | |
1043 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1044 | */ | |
1045 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
1046 | if (!smp_processor_id() && (pic_mode || !value)) { | |
1047 | value = APIC_DM_EXTINT; | |
1048 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
1049 | smp_processor_id()); | |
1050 | } else { | |
1051 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
1052 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
1053 | smp_processor_id()); | |
1054 | } | |
1055 | apic_write_around(APIC_LVT0, value); | |
1056 | ||
1057 | /* | |
1058 | * only the BP should see the LINT1 NMI signal, obviously. | |
1059 | */ | |
1060 | if (!smp_processor_id()) | |
1061 | value = APIC_DM_NMI; | |
1062 | else | |
1063 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
1064 | if (!integrated) /* 82489DX */ | |
1065 | value |= APIC_LVT_LEVEL_TRIGGER; | |
1066 | apic_write_around(APIC_LVT1, value); | |
ac60aae5 | 1067 | } |
e05d723f | 1068 | |
ac60aae5 GOC |
1069 | void __cpuinit end_local_APIC_setup(void) |
1070 | { | |
1071 | unsigned long value; | |
1da177e4 | 1072 | |
ac60aae5 | 1073 | lapic_setup_esr(); |
e9e2cdb4 TG |
1074 | /* Disable the local apic timer */ |
1075 | value = apic_read(APIC_LVTT); | |
1076 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1077 | apic_write_around(APIC_LVTT, value); | |
1078 | ||
e05d723f TG |
1079 | setup_apic_nmi_watchdog(NULL); |
1080 | apic_pm_activate(); | |
1da177e4 LT |
1081 | } |
1082 | ||
e05d723f TG |
1083 | /* |
1084 | * Detect and initialize APIC | |
1085 | */ | |
e83a5fdc | 1086 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1087 | { |
1088 | u32 h, l, features; | |
1da177e4 LT |
1089 | |
1090 | /* Disabled by kernel option? */ | |
1091 | if (enable_local_apic < 0) | |
1092 | return -1; | |
1093 | ||
1da177e4 LT |
1094 | switch (boot_cpu_data.x86_vendor) { |
1095 | case X86_VENDOR_AMD: | |
1096 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
e05d723f | 1097 | (boot_cpu_data.x86 == 15)) |
1da177e4 LT |
1098 | break; |
1099 | goto no_apic; | |
1100 | case X86_VENDOR_INTEL: | |
1101 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1102 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1103 | break; | |
1104 | goto no_apic; | |
1105 | default: | |
1106 | goto no_apic; | |
1107 | } | |
1108 | ||
1109 | if (!cpu_has_apic) { | |
1110 | /* | |
e05d723f TG |
1111 | * Over-ride BIOS and try to enable the local APIC only if |
1112 | * "lapic" specified. | |
1da177e4 LT |
1113 | */ |
1114 | if (enable_local_apic <= 0) { | |
e05d723f | 1115 | printk(KERN_INFO "Local APIC disabled by BIOS -- " |
1da177e4 LT |
1116 | "you can enable it with \"lapic\"\n"); |
1117 | return -1; | |
1118 | } | |
1119 | /* | |
e05d723f TG |
1120 | * Some BIOSes disable the local APIC in the APIC_BASE |
1121 | * MSR. This can only be done in software for Intel P6 or later | |
1122 | * and AMD K7 (Model > 1) or later. | |
1da177e4 LT |
1123 | */ |
1124 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1125 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
e05d723f TG |
1126 | printk(KERN_INFO |
1127 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1da177e4 LT |
1128 | l &= ~MSR_IA32_APICBASE_BASE; |
1129 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1130 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1131 | enabled_via_apicbase = 1; | |
1132 | } | |
1133 | } | |
1134 | /* | |
1135 | * The APIC feature bit should now be enabled | |
1136 | * in `cpuid' | |
1137 | */ | |
1138 | features = cpuid_edx(1); | |
1139 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
e05d723f | 1140 | printk(KERN_WARNING "Could not enable APIC!\n"); |
1da177e4 LT |
1141 | return -1; |
1142 | } | |
53756d37 | 1143 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1da177e4 LT |
1144 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
1145 | ||
1146 | /* The BIOS may have set up the APIC at some other address */ | |
1147 | rdmsr(MSR_IA32_APICBASE, l, h); | |
e05d723f TG |
1148 | if (l & MSR_IA32_APICBASE_ENABLE) |
1149 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1da177e4 | 1150 | |
0328ecef | 1151 | if (nmi_watchdog != NMI_NONE && nmi_watchdog != NMI_DISABLED) |
e05d723f | 1152 | nmi_watchdog = NMI_LOCAL_APIC; |
1da177e4 | 1153 | |
e05d723f | 1154 | printk(KERN_INFO "Found and enabled local APIC!\n"); |
1da177e4 | 1155 | |
e05d723f | 1156 | apic_pm_activate(); |
1da177e4 | 1157 | |
e05d723f | 1158 | return 0; |
1da177e4 | 1159 | |
e05d723f TG |
1160 | no_apic: |
1161 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1162 | return -1; | |
1163 | } | |
1da177e4 | 1164 | |
e05d723f TG |
1165 | /** |
1166 | * init_apic_mappings - initialize APIC mappings | |
1167 | */ | |
1168 | void __init init_apic_mappings(void) | |
1da177e4 | 1169 | { |
1da177e4 | 1170 | /* |
e05d723f TG |
1171 | * If no local APIC can be found then set up a fake all |
1172 | * zeroes page to simulate the local APIC and another | |
1173 | * one for the IO-APIC. | |
1da177e4 | 1174 | */ |
e05d723f TG |
1175 | if (!smp_found_config && detect_init_APIC()) { |
1176 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1177 | apic_phys = __pa(apic_phys); | |
1178 | } else | |
1179 | apic_phys = mp_lapic_addr; | |
1da177e4 | 1180 | |
e05d723f TG |
1181 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
1182 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
1183 | apic_phys); | |
1da177e4 | 1184 | |
e05d723f TG |
1185 | /* |
1186 | * Fetch the APIC ID of the BSP in case we have a | |
1187 | * default configuration (or the MP table is broken). | |
1188 | */ | |
1189 | if (boot_cpu_physical_apicid == -1U) | |
1190 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1da177e4 | 1191 | |
e05d723f TG |
1192 | #ifdef CONFIG_X86_IO_APIC |
1193 | { | |
1194 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
1195 | int i; | |
1da177e4 | 1196 | |
e05d723f TG |
1197 | for (i = 0; i < nr_ioapics; i++) { |
1198 | if (smp_found_config) { | |
1199 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
1200 | if (!ioapic_phys) { | |
1201 | printk(KERN_ERR | |
1202 | "WARNING: bogus zero IO-APIC " | |
1203 | "address found in MPTABLE, " | |
1204 | "disabling IO/APIC support!\n"); | |
1205 | smp_found_config = 0; | |
1206 | skip_ioapic_setup = 1; | |
1207 | goto fake_ioapic_page; | |
1208 | } | |
1209 | } else { | |
1210 | fake_ioapic_page: | |
1211 | ioapic_phys = (unsigned long) | |
1212 | alloc_bootmem_pages(PAGE_SIZE); | |
1213 | ioapic_phys = __pa(ioapic_phys); | |
1214 | } | |
1215 | set_fixmap_nocache(idx, ioapic_phys); | |
1216 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
1217 | __fix_to_virt(idx), ioapic_phys); | |
1218 | idx++; | |
1219 | } | |
1da177e4 | 1220 | } |
e05d723f | 1221 | #endif |
1da177e4 LT |
1222 | } |
1223 | ||
e05d723f TG |
1224 | /* |
1225 | * This initializes the IO-APIC and APIC hardware if this is | |
1226 | * a UP kernel. | |
1227 | */ | |
e81b2c62 AS |
1228 | |
1229 | int apic_version[MAX_APICS]; | |
1230 | ||
e83a5fdc | 1231 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1232 | { |
e05d723f | 1233 | if (enable_local_apic < 0) |
53756d37 | 1234 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1da177e4 | 1235 | |
e05d723f TG |
1236 | if (!smp_found_config && !cpu_has_apic) |
1237 | return -1; | |
6eb0a0fd | 1238 | |
e05d723f TG |
1239 | /* |
1240 | * Complain if the BIOS pretends there is one. | |
1241 | */ | |
1242 | if (!cpu_has_apic && | |
1243 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1244 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1245 | boot_cpu_physical_apicid); | |
53756d37 | 1246 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
e05d723f | 1247 | return -1; |
6eb0a0fd | 1248 | } |
6eb0a0fd | 1249 | |
e05d723f | 1250 | verify_local_APIC(); |
6eb0a0fd | 1251 | |
e05d723f | 1252 | connect_bsp_APIC(); |
6eb0a0fd | 1253 | |
e05d723f TG |
1254 | /* |
1255 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1256 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1257 | * might be zero if read from MP tables. Get it from LAPIC. | |
1258 | */ | |
1259 | #ifdef CONFIG_CRASH_DUMP | |
1260 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1261 | #endif | |
1262 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
1da177e4 | 1263 | |
e05d723f | 1264 | setup_local_APIC(); |
1da177e4 | 1265 | |
ac60aae5 | 1266 | end_local_APIC_setup(); |
e05d723f TG |
1267 | #ifdef CONFIG_X86_IO_APIC |
1268 | if (smp_found_config) | |
1269 | if (!skip_ioapic_setup && nr_ioapics) | |
1270 | setup_IO_APIC(); | |
1da177e4 | 1271 | #endif |
e05d723f | 1272 | setup_boot_clock(); |
1da177e4 | 1273 | |
e05d723f | 1274 | return 0; |
1da177e4 LT |
1275 | } |
1276 | ||
e05d723f TG |
1277 | /* |
1278 | * Local APIC interrupts | |
1279 | */ | |
1280 | ||
1da177e4 LT |
1281 | /* |
1282 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1283 | */ | |
e9e2cdb4 | 1284 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1285 | { |
1286 | unsigned long v; | |
1287 | ||
1288 | irq_enter(); | |
1289 | /* | |
1290 | * Check if this really is a spurious interrupt and ACK it | |
1291 | * if it is a vectored one. Just in case... | |
1292 | * Spurious interrupts should not be ACKed. | |
1293 | */ | |
1294 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1295 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1296 | ack_APIC_irq(); | |
1297 | ||
1298 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
e05d723f TG |
1299 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " |
1300 | "should never happen.\n", smp_processor_id()); | |
38e760a1 | 1301 | __get_cpu_var(irq_stat).irq_spurious_count++; |
1da177e4 LT |
1302 | irq_exit(); |
1303 | } | |
1304 | ||
1305 | /* | |
1306 | * This interrupt should never happen with our APIC/SMP architecture | |
1307 | */ | |
e9e2cdb4 | 1308 | void smp_error_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1309 | { |
1310 | unsigned long v, v1; | |
1311 | ||
1312 | irq_enter(); | |
1313 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1314 | v = apic_read(APIC_ESR); | |
1315 | apic_write(APIC_ESR, 0); | |
1316 | v1 = apic_read(APIC_ESR); | |
1317 | ack_APIC_irq(); | |
1318 | atomic_inc(&irq_err_count); | |
1319 | ||
1320 | /* Here is what the APIC error bits mean: | |
1321 | 0: Send CS error | |
1322 | 1: Receive CS error | |
1323 | 2: Send accept error | |
1324 | 3: Receive accept error | |
1325 | 4: Reserved | |
1326 | 5: Send illegal vector | |
1327 | 6: Received illegal vector | |
1328 | 7: Illegal register address | |
1329 | */ | |
ff8a03a6 | 1330 | printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", |
e05d723f | 1331 | smp_processor_id(), v , v1); |
1da177e4 LT |
1332 | irq_exit(); |
1333 | } | |
1334 | ||
17c9ab1e GOC |
1335 | #ifdef CONFIG_SMP |
1336 | void __init smp_intr_init(void) | |
1337 | { | |
1338 | /* | |
1339 | * IRQ0 must be given a fixed assignment and initialized, | |
1340 | * because it's used before the IO-APIC is set up. | |
1341 | */ | |
1342 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1343 | ||
1344 | /* | |
1345 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1346 | * IPI, driven by wakeup. | |
1347 | */ | |
1348 | set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
1349 | ||
1350 | /* IPI for invalidation */ | |
1351 | set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); | |
1352 | ||
1353 | /* IPI for generic function call */ | |
1354 | set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
1355 | } | |
1356 | #endif | |
1357 | ||
1da177e4 | 1358 | /* |
e05d723f | 1359 | * Initialize APIC interrupts |
1da177e4 | 1360 | */ |
e05d723f | 1361 | void __init apic_intr_init(void) |
1da177e4 | 1362 | { |
e05d723f TG |
1363 | #ifdef CONFIG_SMP |
1364 | smp_intr_init(); | |
1365 | #endif | |
1366 | /* self generated IPI for local APIC timer */ | |
1367 | set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | |
1da177e4 | 1368 | |
e05d723f TG |
1369 | /* IPI vectors for APIC spurious and error interrupts */ |
1370 | set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | |
1371 | set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
1da177e4 | 1372 | |
e05d723f TG |
1373 | /* thermal monitor LVT interrupt */ |
1374 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1375 | set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); | |
1376 | #endif | |
1377 | } | |
1378 | ||
1379 | /** | |
1380 | * connect_bsp_APIC - attach the APIC to the interrupt system | |
1381 | */ | |
1382 | void __init connect_bsp_APIC(void) | |
1383 | { | |
1384 | if (pic_mode) { | |
1385 | /* | |
1386 | * Do not trust the local APIC being empty at bootup. | |
1387 | */ | |
1388 | clear_local_APIC(); | |
1389 | /* | |
1390 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1391 | * local APIC to INT and NMI lines. | |
1392 | */ | |
1393 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1394 | "enabling APIC mode.\n"); | |
1395 | outb(0x70, 0x22); | |
1396 | outb(0x01, 0x23); | |
1da177e4 | 1397 | } |
e05d723f TG |
1398 | enable_apic_mode(); |
1399 | } | |
1da177e4 | 1400 | |
e05d723f TG |
1401 | /** |
1402 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1403 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1404 | * | |
1405 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1406 | * APIC is disabled. | |
1407 | */ | |
1408 | void disconnect_bsp_APIC(int virt_wire_setup) | |
1409 | { | |
1410 | if (pic_mode) { | |
1411 | /* | |
1412 | * Put the board back into PIC mode (has an effect only on | |
1413 | * certain older boards). Note that APIC interrupts, including | |
1414 | * IPIs, won't work beyond this point! The only exception are | |
1415 | * INIT IPIs. | |
1416 | */ | |
1417 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1418 | "entering PIC mode.\n"); | |
1419 | outb(0x70, 0x22); | |
1420 | outb(0x00, 0x23); | |
1421 | } else { | |
1422 | /* Go back to Virtual Wire compatibility mode */ | |
1423 | unsigned long value; | |
1da177e4 | 1424 | |
e05d723f TG |
1425 | /* For the spurious interrupt use vector F, and enable it */ |
1426 | value = apic_read(APIC_SPIV); | |
1427 | value &= ~APIC_VECTOR_MASK; | |
1428 | value |= APIC_SPIV_APIC_ENABLED; | |
1429 | value |= 0xf; | |
1430 | apic_write_around(APIC_SPIV, value); | |
1da177e4 | 1431 | |
e05d723f TG |
1432 | if (!virt_wire_setup) { |
1433 | /* | |
1434 | * For LVT0 make it edge triggered, active high, | |
1435 | * external and enabled | |
1436 | */ | |
1437 | value = apic_read(APIC_LVT0); | |
1438 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1439 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
ff8a03a6 | 1440 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
e05d723f TG |
1441 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
1442 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1443 | apic_write_around(APIC_LVT0, value); | |
1444 | } else { | |
1445 | /* Disable LVT0 */ | |
1446 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
1447 | } | |
1da177e4 | 1448 | |
e05d723f TG |
1449 | /* |
1450 | * For LVT1 make it edge triggered, active high, nmi and | |
1451 | * enabled | |
1452 | */ | |
1453 | value = apic_read(APIC_LVT1); | |
1454 | value &= ~( | |
1455 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
1456 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1457 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1458 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1459 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1460 | apic_write_around(APIC_LVT1, value); | |
1461 | } | |
1462 | } | |
1da177e4 | 1463 | |
e05d723f TG |
1464 | /* |
1465 | * Power management | |
1466 | */ | |
1467 | #ifdef CONFIG_PM | |
1468 | ||
1469 | static struct { | |
1470 | int active; | |
1471 | /* r/w apic fields */ | |
1472 | unsigned int apic_id; | |
1473 | unsigned int apic_taskpri; | |
1474 | unsigned int apic_ldr; | |
1475 | unsigned int apic_dfr; | |
1476 | unsigned int apic_spiv; | |
1477 | unsigned int apic_lvtt; | |
1478 | unsigned int apic_lvtpc; | |
1479 | unsigned int apic_lvt0; | |
1480 | unsigned int apic_lvt1; | |
1481 | unsigned int apic_lvterr; | |
1482 | unsigned int apic_tmict; | |
1483 | unsigned int apic_tdcr; | |
1484 | unsigned int apic_thmr; | |
1485 | } apic_pm_state; | |
1486 | ||
1487 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1488 | { | |
1489 | unsigned long flags; | |
1490 | int maxlvt; | |
1491 | ||
1492 | if (!apic_pm_state.active) | |
1493 | return 0; | |
1494 | ||
1495 | maxlvt = lapic_get_maxlvt(); | |
1496 | ||
1497 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
1498 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1499 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1500 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1501 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1502 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1503 | if (maxlvt >= 4) | |
1504 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1505 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1506 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1507 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1508 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1509 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1510 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1511 | if (maxlvt >= 5) | |
1512 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1da177e4 | 1513 | #endif |
1e4c85f9 | 1514 | |
e05d723f TG |
1515 | local_irq_save(flags); |
1516 | disable_local_APIC(); | |
1517 | local_irq_restore(flags); | |
1e4c85f9 | 1518 | return 0; |
1da177e4 | 1519 | } |
1a3f239d | 1520 | |
e05d723f | 1521 | static int lapic_resume(struct sys_device *dev) |
1a3f239d | 1522 | { |
e05d723f TG |
1523 | unsigned int l, h; |
1524 | unsigned long flags; | |
1525 | int maxlvt; | |
1526 | ||
1527 | if (!apic_pm_state.active) | |
1528 | return 0; | |
1529 | ||
1530 | maxlvt = lapic_get_maxlvt(); | |
1531 | ||
1532 | local_irq_save(flags); | |
1533 | ||
1534 | /* | |
1535 | * Make sure the APICBASE points to the right address | |
1536 | * | |
1537 | * FIXME! This will be wrong if we ever support suspend on | |
1538 | * SMP! We'll need to do this as part of the CPU restore! | |
1539 | */ | |
1540 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1541 | l &= ~MSR_IA32_APICBASE_BASE; | |
1542 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1543 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1544 | ||
1545 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1546 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1547 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1548 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1549 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1550 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1551 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1552 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1553 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1554 | if (maxlvt >= 5) | |
1555 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1556 | #endif | |
1557 | if (maxlvt >= 4) | |
1558 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1559 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1560 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1561 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1562 | apic_write(APIC_ESR, 0); | |
1563 | apic_read(APIC_ESR); | |
1564 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1565 | apic_write(APIC_ESR, 0); | |
1566 | apic_read(APIC_ESR); | |
1567 | local_irq_restore(flags); | |
1a3f239d RR |
1568 | return 0; |
1569 | } | |
1a3f239d | 1570 | |
e05d723f TG |
1571 | /* |
1572 | * This device has no shutdown method - fully functioning local APICs | |
1573 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1574 | */ | |
1575 | ||
1576 | static struct sysdev_class lapic_sysclass = { | |
af5ca3f4 | 1577 | .name = "lapic", |
e05d723f TG |
1578 | .resume = lapic_resume, |
1579 | .suspend = lapic_suspend, | |
1580 | }; | |
1581 | ||
1582 | static struct sys_device device_lapic = { | |
1583 | .id = 0, | |
1584 | .cls = &lapic_sysclass, | |
1585 | }; | |
1586 | ||
1587 | static void __devinit apic_pm_activate(void) | |
1a3f239d | 1588 | { |
e05d723f | 1589 | apic_pm_state.active = 1; |
1a3f239d | 1590 | } |
1a3f239d | 1591 | |
e05d723f TG |
1592 | static int __init init_lapic_sysfs(void) |
1593 | { | |
1594 | int error; | |
1595 | ||
1596 | if (!cpu_has_apic) | |
1597 | return 0; | |
1598 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
1599 | ||
1600 | error = sysdev_class_register(&lapic_sysclass); | |
1601 | if (!error) | |
1602 | error = sysdev_register(&device_lapic); | |
1603 | return error; | |
1604 | } | |
1605 | device_initcall(init_lapic_sysfs); | |
1606 | ||
1607 | #else /* CONFIG_PM */ | |
1608 | ||
1609 | static void apic_pm_activate(void) { } | |
1610 | ||
1611 | #endif /* CONFIG_PM */ | |
0e078e2f TG |
1612 | |
1613 | /* | |
1614 | * APIC command line parameters | |
1615 | */ | |
1616 | static int __init parse_lapic(char *arg) | |
1617 | { | |
1618 | enable_local_apic = 1; | |
1619 | return 0; | |
1620 | } | |
1621 | early_param("lapic", parse_lapic); | |
1622 | ||
1623 | static int __init parse_nolapic(char *arg) | |
1624 | { | |
1625 | enable_local_apic = -1; | |
53756d37 | 1626 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
0e078e2f TG |
1627 | return 0; |
1628 | } | |
1629 | early_param("nolapic", parse_nolapic); | |
1630 | ||
1631 | static int __init parse_disable_lapic_timer(char *arg) | |
1632 | { | |
1633 | local_apic_timer_disabled = 1; | |
1634 | return 0; | |
1635 | } | |
1636 | early_param("nolapic_timer", parse_disable_lapic_timer); | |
1637 | ||
1638 | static int __init parse_lapic_timer_c2_ok(char *arg) | |
1639 | { | |
1640 | local_apic_timer_c2_ok = 1; | |
1641 | return 0; | |
1642 | } | |
1643 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1644 | ||
1645 | static int __init apic_set_verbosity(char *str) | |
1646 | { | |
1647 | if (strcmp("debug", str) == 0) | |
1648 | apic_verbosity = APIC_DEBUG; | |
1649 | else if (strcmp("verbose", str) == 0) | |
1650 | apic_verbosity = APIC_VERBOSE; | |
1651 | return 1; | |
1652 | } | |
1653 | __setup("apic=", apic_set_verbosity); | |
1654 |