Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
6e1cb38a | 30 | #include <linux/dmar.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
efa2559f | 36 | #include <asm/desc.h> |
e83a5fdc | 37 | #include <asm/hpet.h> |
1da177e4 | 38 | #include <asm/pgalloc.h> |
75152114 | 39 | #include <asm/nmi.h> |
95833c83 | 40 | #include <asm/idle.h> |
73dea47f AK |
41 | #include <asm/proto.h> |
42 | #include <asm/timex.h> | |
2c8c0e6b | 43 | #include <asm/apic.h> |
6e1cb38a | 44 | #include <asm/i8259.h> |
1da177e4 | 45 | |
5af5573e | 46 | #include <mach_ipi.h> |
dd46e3ca | 47 | #include <mach_apic.h> |
5af5573e | 48 | |
80e5609c CG |
49 | /* |
50 | * Sanity check | |
51 | */ | |
52 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | |
53 | # error SPURIOUS_APIC_VECTOR definition error | |
54 | #endif | |
55 | ||
b3c51170 YL |
56 | #ifdef CONFIG_X86_32 |
57 | /* | |
58 | * Knob to control our willingness to enable the local APIC. | |
59 | * | |
60 | * +1=force-enable | |
61 | */ | |
62 | static int force_enable_local_apic; | |
63 | /* | |
64 | * APIC command line parameters | |
65 | */ | |
66 | static int __init parse_lapic(char *arg) | |
67 | { | |
68 | force_enable_local_apic = 1; | |
69 | return 0; | |
70 | } | |
71 | early_param("lapic", parse_lapic); | |
72 | #endif | |
73 | ||
74 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 75 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
76 | static __init int setup_apicpmtimer(char *s) |
77 | { | |
78 | apic_calibrate_pmtmr = 1; | |
79 | notsc_setup(NULL); | |
80 | return 0; | |
81 | } | |
82 | __setup("apicpmtimer", setup_apicpmtimer); | |
83 | #endif | |
84 | ||
49899eac YL |
85 | #ifdef CONFIG_X86_64 |
86 | #define HAVE_X2APIC | |
87 | #endif | |
88 | ||
89 | #ifdef HAVE_X2APIC | |
89027d35 | 90 | int x2apic; |
6e1cb38a SS |
91 | /* x2apic enabled before OS handover */ |
92 | int x2apic_preenabled; | |
49899eac YL |
93 | int disable_x2apic; |
94 | static __init int setup_nox2apic(char *str) | |
95 | { | |
96 | disable_x2apic = 1; | |
97 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
98 | return 0; | |
99 | } | |
100 | early_param("nox2apic", setup_nox2apic); | |
101 | #endif | |
1da177e4 | 102 | |
b3c51170 YL |
103 | unsigned long mp_lapic_addr; |
104 | int disable_apic; | |
105 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
106 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 107 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
108 | int local_apic_timer_c2_ok; |
109 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
110 | ||
efa2559f YL |
111 | int first_system_vector = 0xfe; |
112 | ||
113 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
114 | ||
e83a5fdc HS |
115 | /* |
116 | * Debug level, exported for io_apic.c | |
117 | */ | |
baa13188 | 118 | unsigned int apic_verbosity; |
e83a5fdc | 119 | |
89c38c28 CG |
120 | int pic_mode; |
121 | ||
bab4b27c AS |
122 | /* Have we found an MP table */ |
123 | int smp_found_config; | |
124 | ||
39928722 AD |
125 | static struct resource lapic_resource = { |
126 | .name = "Local APIC", | |
127 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
128 | }; | |
129 | ||
d03030e9 TG |
130 | static unsigned int calibration_result; |
131 | ||
ba7eda4c TG |
132 | static int lapic_next_event(unsigned long delta, |
133 | struct clock_event_device *evt); | |
134 | static void lapic_timer_setup(enum clock_event_mode mode, | |
135 | struct clock_event_device *evt); | |
ba7eda4c | 136 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 137 | static void apic_pm_activate(void); |
ba7eda4c | 138 | |
274cfe59 CG |
139 | /* |
140 | * The local apic timer can be used for any function which is CPU local. | |
141 | */ | |
ba7eda4c TG |
142 | static struct clock_event_device lapic_clockevent = { |
143 | .name = "lapic", | |
144 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
145 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
146 | .shift = 32, | |
147 | .set_mode = lapic_timer_setup, | |
148 | .set_next_event = lapic_next_event, | |
149 | .broadcast = lapic_timer_broadcast, | |
150 | .rating = 100, | |
151 | .irq = -1, | |
152 | }; | |
153 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
154 | ||
d3432896 AK |
155 | static unsigned long apic_phys; |
156 | ||
0e078e2f TG |
157 | /* |
158 | * Get the LAPIC version | |
159 | */ | |
160 | static inline int lapic_get_version(void) | |
ba7eda4c | 161 | { |
0e078e2f | 162 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
163 | } |
164 | ||
0e078e2f | 165 | /* |
9c803869 | 166 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
167 | */ |
168 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 169 | { |
9c803869 | 170 | #ifdef CONFIG_X86_64 |
0e078e2f | 171 | return 1; |
9c803869 CG |
172 | #else |
173 | return APIC_INTEGRATED(lapic_get_version()); | |
174 | #endif | |
ba7eda4c TG |
175 | } |
176 | ||
177 | /* | |
0e078e2f | 178 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 179 | */ |
0e078e2f | 180 | static int modern_apic(void) |
ba7eda4c | 181 | { |
0e078e2f TG |
182 | /* AMD systems use old APIC versions, so check the CPU */ |
183 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
184 | boot_cpu_data.x86 >= 0xf) | |
185 | return 1; | |
186 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
187 | } |
188 | ||
274cfe59 CG |
189 | /* |
190 | * Paravirt kernels also might be using these below ops. So we still | |
191 | * use generic apic_read()/apic_write(), which might be pointing to different | |
192 | * ops in PARAVIRT case. | |
193 | */ | |
1b374e4d | 194 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
195 | { |
196 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
197 | cpu_relax(); | |
198 | } | |
199 | ||
1b374e4d | 200 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 201 | { |
3c6bb07a | 202 | u32 send_status; |
8339e9fb FLV |
203 | int timeout; |
204 | ||
205 | timeout = 0; | |
206 | do { | |
207 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
208 | if (!send_status) | |
209 | break; | |
210 | udelay(100); | |
211 | } while (timeout++ < 1000); | |
212 | ||
213 | return send_status; | |
214 | } | |
215 | ||
1b374e4d SS |
216 | void xapic_icr_write(u32 low, u32 id) |
217 | { | |
ed4e5ec1 | 218 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
219 | apic_write(APIC_ICR, low); |
220 | } | |
221 | ||
222 | u64 xapic_icr_read(void) | |
223 | { | |
224 | u32 icr1, icr2; | |
225 | ||
226 | icr2 = apic_read(APIC_ICR2); | |
227 | icr1 = apic_read(APIC_ICR); | |
228 | ||
cf9768d7 | 229 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
230 | } |
231 | ||
232 | static struct apic_ops xapic_ops = { | |
233 | .read = native_apic_mem_read, | |
234 | .write = native_apic_mem_write, | |
1b374e4d SS |
235 | .icr_read = xapic_icr_read, |
236 | .icr_write = xapic_icr_write, | |
237 | .wait_icr_idle = xapic_wait_icr_idle, | |
238 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
239 | }; | |
240 | ||
241 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
242 | EXPORT_SYMBOL_GPL(apic_ops); |
243 | ||
49899eac | 244 | #ifdef HAVE_X2APIC |
13c88fb5 SS |
245 | static void x2apic_wait_icr_idle(void) |
246 | { | |
247 | /* no need to wait for icr idle in x2apic */ | |
248 | return; | |
249 | } | |
250 | ||
251 | static u32 safe_x2apic_wait_icr_idle(void) | |
252 | { | |
253 | /* no need to wait for icr idle in x2apic */ | |
254 | return 0; | |
255 | } | |
256 | ||
257 | void x2apic_icr_write(u32 low, u32 id) | |
258 | { | |
259 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
260 | } | |
261 | ||
262 | u64 x2apic_icr_read(void) | |
263 | { | |
264 | unsigned long val; | |
265 | ||
266 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
267 | return val; | |
268 | } | |
269 | ||
270 | static struct apic_ops x2apic_ops = { | |
271 | .read = native_apic_msr_read, | |
272 | .write = native_apic_msr_write, | |
13c88fb5 SS |
273 | .icr_read = x2apic_icr_read, |
274 | .icr_write = x2apic_icr_write, | |
275 | .wait_icr_idle = x2apic_wait_icr_idle, | |
276 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
277 | }; | |
49899eac | 278 | #endif |
13c88fb5 | 279 | |
0e078e2f TG |
280 | /** |
281 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
282 | */ | |
e9427101 | 283 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 284 | { |
11a8e778 | 285 | unsigned int v; |
6935d1f9 TG |
286 | |
287 | /* unmask and set to NMI */ | |
288 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
289 | |
290 | /* Level triggered for 82489DX (32bit mode) */ | |
291 | if (!lapic_is_integrated()) | |
292 | v |= APIC_LVT_LEVEL_TRIGGER; | |
293 | ||
11a8e778 | 294 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
295 | } |
296 | ||
7c37e48b CG |
297 | #ifdef CONFIG_X86_32 |
298 | /** | |
299 | * get_physical_broadcast - Get number of physical broadcast IDs | |
300 | */ | |
301 | int get_physical_broadcast(void) | |
302 | { | |
303 | return modern_apic() ? 0xff : 0xf; | |
304 | } | |
305 | #endif | |
306 | ||
0e078e2f TG |
307 | /** |
308 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
309 | */ | |
37e650c7 | 310 | int lapic_get_maxlvt(void) |
1da177e4 | 311 | { |
36a028de | 312 | unsigned int v; |
1da177e4 LT |
313 | |
314 | v = apic_read(APIC_LVR); | |
36a028de CG |
315 | /* |
316 | * - we always have APIC integrated on 64bit mode | |
317 | * - 82489DXs do not report # of LVT entries | |
318 | */ | |
319 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
320 | } |
321 | ||
274cfe59 CG |
322 | /* |
323 | * Local APIC timer | |
324 | */ | |
325 | ||
c40aaec6 CG |
326 | /* Clock divisor */ |
327 | #ifdef CONFG_X86_64 | |
f07f4f90 | 328 | #define APIC_DIVISOR 1 |
c40aaec6 CG |
329 | #else |
330 | #define APIC_DIVISOR 16 | |
331 | #endif | |
f07f4f90 | 332 | |
0e078e2f TG |
333 | /* |
334 | * This function sets up the local APIC timer, with a timeout of | |
335 | * 'clocks' APIC bus clock. During calibration we actually call | |
336 | * this function twice on the boot CPU, once with a bogus timeout | |
337 | * value, second time for real. The other (noncalibrating) CPUs | |
338 | * call this function only once, with the real, calibrated value. | |
339 | * | |
340 | * We do reads before writes even if unnecessary, to get around the | |
341 | * P5 APIC double write bug. | |
342 | */ | |
0e078e2f | 343 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 344 | { |
0e078e2f | 345 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 346 | |
0e078e2f TG |
347 | lvtt_value = LOCAL_TIMER_VECTOR; |
348 | if (!oneshot) | |
349 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
350 | if (!lapic_is_integrated()) |
351 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
352 | ||
0e078e2f TG |
353 | if (!irqen) |
354 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 355 | |
0e078e2f | 356 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
357 | |
358 | /* | |
0e078e2f | 359 | * Divide PICLK by 16 |
1da177e4 | 360 | */ |
0e078e2f | 361 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
362 | apic_write(APIC_TDCR, |
363 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
364 | APIC_TDR_DIV_16); | |
0e078e2f TG |
365 | |
366 | if (!oneshot) | |
f07f4f90 | 367 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
368 | } |
369 | ||
0e078e2f | 370 | /* |
7b83dae7 RR |
371 | * Setup extended LVT, AMD specific (K8, family 10h) |
372 | * | |
373 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
374 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
375 | * |
376 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
377 | * enables the vector. See also the BKDGs. | |
0e078e2f | 378 | */ |
7b83dae7 RR |
379 | |
380 | #define APIC_EILVT_LVTOFF_MCE 0 | |
381 | #define APIC_EILVT_LVTOFF_IBS 1 | |
382 | ||
383 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 384 | { |
7b83dae7 | 385 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 386 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 387 | |
0e078e2f | 388 | apic_write(reg, v); |
1da177e4 LT |
389 | } |
390 | ||
7b83dae7 RR |
391 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
392 | { | |
393 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
394 | return APIC_EILVT_LVTOFF_MCE; | |
395 | } | |
396 | ||
397 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
398 | { | |
399 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
400 | return APIC_EILVT_LVTOFF_IBS; | |
401 | } | |
6aa360e6 | 402 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 403 | |
0e078e2f TG |
404 | /* |
405 | * Program the next event, relative to now | |
406 | */ | |
407 | static int lapic_next_event(unsigned long delta, | |
408 | struct clock_event_device *evt) | |
1da177e4 | 409 | { |
0e078e2f TG |
410 | apic_write(APIC_TMICT, delta); |
411 | return 0; | |
1da177e4 LT |
412 | } |
413 | ||
0e078e2f TG |
414 | /* |
415 | * Setup the lapic timer in periodic or oneshot mode | |
416 | */ | |
417 | static void lapic_timer_setup(enum clock_event_mode mode, | |
418 | struct clock_event_device *evt) | |
9b7711f0 HS |
419 | { |
420 | unsigned long flags; | |
0e078e2f | 421 | unsigned int v; |
9b7711f0 | 422 | |
0e078e2f TG |
423 | /* Lapic used as dummy for broadcast ? */ |
424 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
425 | return; |
426 | ||
427 | local_irq_save(flags); | |
428 | ||
0e078e2f TG |
429 | switch (mode) { |
430 | case CLOCK_EVT_MODE_PERIODIC: | |
431 | case CLOCK_EVT_MODE_ONESHOT: | |
432 | __setup_APIC_LVTT(calibration_result, | |
433 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
434 | break; | |
435 | case CLOCK_EVT_MODE_UNUSED: | |
436 | case CLOCK_EVT_MODE_SHUTDOWN: | |
437 | v = apic_read(APIC_LVTT); | |
438 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
439 | apic_write(APIC_LVTT, v); | |
440 | break; | |
441 | case CLOCK_EVT_MODE_RESUME: | |
442 | /* Nothing to do here */ | |
443 | break; | |
444 | } | |
9b7711f0 HS |
445 | |
446 | local_irq_restore(flags); | |
447 | } | |
448 | ||
1da177e4 | 449 | /* |
0e078e2f | 450 | * Local APIC timer broadcast function |
1da177e4 | 451 | */ |
0e078e2f | 452 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 453 | { |
0e078e2f TG |
454 | #ifdef CONFIG_SMP |
455 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
456 | #endif | |
457 | } | |
1da177e4 | 458 | |
0e078e2f TG |
459 | /* |
460 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
461 | * of the boot CPU and register the clock event in the framework. | |
462 | */ | |
db4b5525 | 463 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
464 | { |
465 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 466 | |
0e078e2f TG |
467 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
468 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 469 | |
0e078e2f TG |
470 | clockevents_register_device(levt); |
471 | } | |
1da177e4 | 472 | |
0e078e2f TG |
473 | /* |
474 | * In this function we calibrate APIC bus clocks to the external | |
475 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
476 | * to calibrate, since some later bootup code depends on getting | |
477 | * the first irq? Ugh. | |
478 | * | |
479 | * We want to do the calibration only once since we | |
480 | * want to have local timer irqs syncron. CPUs connected | |
481 | * by the same APIC bus have the very same bus frequency. | |
482 | * And we want to have irqs off anyways, no accidental | |
483 | * APIC irq that way. | |
484 | */ | |
485 | ||
486 | #define TICK_COUNT 100000000 | |
487 | ||
89b3b1f4 | 488 | static int __init calibrate_APIC_clock(void) |
0e078e2f TG |
489 | { |
490 | unsigned apic, apic_start; | |
491 | unsigned long tsc, tsc_start; | |
492 | int result; | |
493 | ||
494 | local_irq_disable(); | |
495 | ||
496 | /* | |
497 | * Put whatever arbitrary (but long enough) timeout | |
498 | * value into the APIC clock, we just want to get the | |
499 | * counter running for calibration. | |
500 | * | |
501 | * No interrupt enable ! | |
502 | */ | |
503 | __setup_APIC_LVTT(250000000, 0, 0); | |
504 | ||
505 | apic_start = apic_read(APIC_TMCCT); | |
506 | #ifdef CONFIG_X86_PM_TIMER | |
507 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
508 | pmtimer_wait(5000); /* 5ms wait */ | |
509 | apic = apic_read(APIC_TMCCT); | |
510 | result = (apic_start - apic) * 1000L / 5; | |
511 | } else | |
512 | #endif | |
513 | { | |
514 | rdtscll(tsc_start); | |
515 | ||
516 | do { | |
517 | apic = apic_read(APIC_TMCCT); | |
518 | rdtscll(tsc); | |
519 | } while ((tsc - tsc_start) < TICK_COUNT && | |
520 | (apic_start - apic) < TICK_COUNT); | |
521 | ||
522 | result = (apic_start - apic) * 1000L * tsc_khz / | |
523 | (tsc - tsc_start); | |
524 | } | |
525 | ||
526 | local_irq_enable(); | |
527 | ||
528 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
529 | ||
530 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
531 | result / 1000 / 1000, result / 1000 % 1000); | |
532 | ||
533 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
534 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
535 | lapic_clockevent.shift); | |
0e078e2f TG |
536 | lapic_clockevent.max_delta_ns = |
537 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
538 | lapic_clockevent.min_delta_ns = | |
539 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
540 | ||
f07f4f90 | 541 | calibration_result = (result * APIC_DIVISOR) / HZ; |
89b3b1f4 CG |
542 | |
543 | /* | |
544 | * Do a sanity check on the APIC calibration result | |
545 | */ | |
546 | if (calibration_result < (1000000 / HZ)) { | |
547 | printk(KERN_WARNING | |
548 | "APIC frequency too slow, disabling apic timer\n"); | |
549 | return -1; | |
550 | } | |
551 | ||
552 | return 0; | |
0e078e2f TG |
553 | } |
554 | ||
e83a5fdc HS |
555 | /* |
556 | * Setup the boot APIC | |
557 | * | |
558 | * Calibrate and verify the result. | |
559 | */ | |
0e078e2f TG |
560 | void __init setup_boot_APIC_clock(void) |
561 | { | |
562 | /* | |
274cfe59 CG |
563 | * The local apic timer can be disabled via the kernel |
564 | * commandline or from the CPU detection code. Register the lapic | |
565 | * timer as a dummy clock event source on SMP systems, so the | |
566 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
567 | */ |
568 | if (disable_apic_timer) { | |
569 | printk(KERN_INFO "Disabling APIC timer\n"); | |
570 | /* No broadcast on UP ! */ | |
9d09951d TG |
571 | if (num_possible_cpus() > 1) { |
572 | lapic_clockevent.mult = 1; | |
0e078e2f | 573 | setup_APIC_timer(); |
9d09951d | 574 | } |
0e078e2f TG |
575 | return; |
576 | } | |
577 | ||
274cfe59 CG |
578 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
579 | "calibrating APIC timer ...\n"); | |
580 | ||
89b3b1f4 | 581 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
582 | /* No broadcast on UP ! */ |
583 | if (num_possible_cpus() > 1) | |
584 | setup_APIC_timer(); | |
585 | return; | |
586 | } | |
587 | ||
0e078e2f TG |
588 | /* |
589 | * If nmi_watchdog is set to IO_APIC, we need the | |
590 | * PIT/HPET going. Otherwise register lapic as a dummy | |
591 | * device. | |
592 | */ | |
593 | if (nmi_watchdog != NMI_IO_APIC) | |
594 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
595 | else | |
596 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 597 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 598 | |
274cfe59 | 599 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
600 | setup_APIC_timer(); |
601 | } | |
602 | ||
0e078e2f TG |
603 | void __cpuinit setup_secondary_APIC_clock(void) |
604 | { | |
0e078e2f TG |
605 | setup_APIC_timer(); |
606 | } | |
607 | ||
608 | /* | |
609 | * The guts of the apic timer interrupt | |
610 | */ | |
611 | static void local_apic_timer_interrupt(void) | |
612 | { | |
613 | int cpu = smp_processor_id(); | |
614 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
615 | ||
616 | /* | |
617 | * Normally we should not be here till LAPIC has been initialized but | |
618 | * in some cases like kdump, its possible that there is a pending LAPIC | |
619 | * timer interrupt from previous kernel's context and is delivered in | |
620 | * new kernel the moment interrupts are enabled. | |
621 | * | |
622 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
623 | * its possible that when we get here evt->event_handler is NULL. | |
624 | * Check for event_handler being NULL and discard the interrupt as | |
625 | * spurious. | |
626 | */ | |
627 | if (!evt->event_handler) { | |
628 | printk(KERN_WARNING | |
629 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
630 | /* Switch it off */ | |
631 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
632 | return; | |
633 | } | |
634 | ||
635 | /* | |
636 | * the NMI deadlock-detector uses this. | |
637 | */ | |
0b23e8cf | 638 | #ifdef CONFIG_X86_64 |
0e078e2f | 639 | add_pda(apic_timer_irqs, 1); |
0b23e8cf CG |
640 | #else |
641 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
642 | #endif | |
0e078e2f TG |
643 | |
644 | evt->event_handler(evt); | |
645 | } | |
646 | ||
647 | /* | |
648 | * Local APIC timer interrupt. This is the most natural way for doing | |
649 | * local interrupts, but local timer interrupts can be emulated by | |
650 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
651 | * | |
652 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
653 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
654 | */ | |
655 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
656 | { | |
657 | struct pt_regs *old_regs = set_irq_regs(regs); | |
658 | ||
659 | /* | |
660 | * NOTE! We'd better ACK the irq immediately, | |
661 | * because timer handling can be slow. | |
662 | */ | |
663 | ack_APIC_irq(); | |
664 | /* | |
665 | * update_process_times() expects us to have done irq_enter(). | |
666 | * Besides, if we don't timer interrupts ignore the global | |
667 | * interrupt lock, which is the WrongThing (tm) to do. | |
668 | */ | |
6460bc73 | 669 | #ifdef CONFIG_X86_64 |
0e078e2f | 670 | exit_idle(); |
6460bc73 | 671 | #endif |
0e078e2f TG |
672 | irq_enter(); |
673 | local_apic_timer_interrupt(); | |
674 | irq_exit(); | |
274cfe59 | 675 | |
0e078e2f TG |
676 | set_irq_regs(old_regs); |
677 | } | |
678 | ||
679 | int setup_profiling_timer(unsigned int multiplier) | |
680 | { | |
681 | return -EINVAL; | |
682 | } | |
683 | ||
684 | ||
685 | /* | |
686 | * Local APIC start and shutdown | |
687 | */ | |
688 | ||
689 | /** | |
690 | * clear_local_APIC - shutdown the local APIC | |
691 | * | |
692 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
693 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
694 | * leftovers during boot. | |
695 | */ | |
696 | void clear_local_APIC(void) | |
697 | { | |
2584a82d | 698 | int maxlvt; |
0e078e2f TG |
699 | u32 v; |
700 | ||
d3432896 AK |
701 | /* APIC hasn't been mapped yet */ |
702 | if (!apic_phys) | |
703 | return; | |
704 | ||
705 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
706 | /* |
707 | * Masking an LVT entry can trigger a local APIC error | |
708 | * if the vector is zero. Mask LVTERR first to prevent this. | |
709 | */ | |
710 | if (maxlvt >= 3) { | |
711 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
712 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
713 | } | |
714 | /* | |
715 | * Careful: we have to set masks only first to deassert | |
716 | * any level-triggered sources. | |
717 | */ | |
718 | v = apic_read(APIC_LVTT); | |
719 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
720 | v = apic_read(APIC_LVT0); | |
721 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
722 | v = apic_read(APIC_LVT1); | |
723 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
724 | if (maxlvt >= 4) { | |
725 | v = apic_read(APIC_LVTPC); | |
726 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
727 | } | |
728 | ||
6764014b CG |
729 | /* lets not touch this if we didn't frob it */ |
730 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
731 | if (maxlvt >= 5) { | |
732 | v = apic_read(APIC_LVTTHMR); | |
733 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
734 | } | |
735 | #endif | |
0e078e2f TG |
736 | /* |
737 | * Clean APIC state for other OSs: | |
738 | */ | |
739 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
740 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
741 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
742 | if (maxlvt >= 3) | |
743 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
744 | if (maxlvt >= 4) | |
745 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
746 | |
747 | /* Integrated APIC (!82489DX) ? */ | |
748 | if (lapic_is_integrated()) { | |
749 | if (maxlvt > 3) | |
750 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
751 | apic_write(APIC_ESR, 0); | |
752 | apic_read(APIC_ESR); | |
753 | } | |
0e078e2f TG |
754 | } |
755 | ||
756 | /** | |
757 | * disable_local_APIC - clear and disable the local APIC | |
758 | */ | |
759 | void disable_local_APIC(void) | |
760 | { | |
761 | unsigned int value; | |
762 | ||
763 | clear_local_APIC(); | |
764 | ||
765 | /* | |
766 | * Disable APIC (implies clearing of registers | |
767 | * for 82489DX!). | |
768 | */ | |
769 | value = apic_read(APIC_SPIV); | |
770 | value &= ~APIC_SPIV_APIC_ENABLED; | |
771 | apic_write(APIC_SPIV, value); | |
990b183e CG |
772 | |
773 | #ifdef CONFIG_X86_32 | |
774 | /* | |
775 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
776 | * restore the disabled state. | |
777 | */ | |
778 | if (enabled_via_apicbase) { | |
779 | unsigned int l, h; | |
780 | ||
781 | rdmsr(MSR_IA32_APICBASE, l, h); | |
782 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
783 | wrmsr(MSR_IA32_APICBASE, l, h); | |
784 | } | |
785 | #endif | |
0e078e2f TG |
786 | } |
787 | ||
fe4024dc CG |
788 | /* |
789 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
790 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
791 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
792 | * for the case where Linux didn't enable the LAPIC. | |
793 | */ | |
0e078e2f TG |
794 | void lapic_shutdown(void) |
795 | { | |
796 | unsigned long flags; | |
797 | ||
798 | if (!cpu_has_apic) | |
799 | return; | |
800 | ||
801 | local_irq_save(flags); | |
802 | ||
fe4024dc CG |
803 | #ifdef CONFIG_X86_32 |
804 | if (!enabled_via_apicbase) | |
805 | clear_local_APIC(); | |
806 | else | |
807 | #endif | |
808 | disable_local_APIC(); | |
809 | ||
0e078e2f TG |
810 | |
811 | local_irq_restore(flags); | |
812 | } | |
813 | ||
814 | /* | |
815 | * This is to verify that we're looking at a real local APIC. | |
816 | * Check these against your board if the CPUs aren't getting | |
817 | * started for no apparent reason. | |
818 | */ | |
819 | int __init verify_local_APIC(void) | |
820 | { | |
821 | unsigned int reg0, reg1; | |
822 | ||
823 | /* | |
824 | * The version register is read-only in a real APIC. | |
825 | */ | |
826 | reg0 = apic_read(APIC_LVR); | |
827 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
828 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
829 | reg1 = apic_read(APIC_LVR); | |
830 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
831 | ||
832 | /* | |
833 | * The two version reads above should print the same | |
834 | * numbers. If the second one is different, then we | |
835 | * poke at a non-APIC. | |
836 | */ | |
837 | if (reg1 != reg0) | |
838 | return 0; | |
839 | ||
840 | /* | |
841 | * Check if the version looks reasonably. | |
842 | */ | |
843 | reg1 = GET_APIC_VERSION(reg0); | |
844 | if (reg1 == 0x00 || reg1 == 0xff) | |
845 | return 0; | |
846 | reg1 = lapic_get_maxlvt(); | |
847 | if (reg1 < 0x02 || reg1 == 0xff) | |
848 | return 0; | |
849 | ||
850 | /* | |
851 | * The ID register is read/write in a real APIC. | |
852 | */ | |
2d7a66d0 | 853 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
854 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
855 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 856 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
857 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
858 | apic_write(APIC_ID, reg0); | |
859 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
860 | return 0; | |
861 | ||
862 | /* | |
1da177e4 LT |
863 | * The next two are just to see if we have sane values. |
864 | * They're only really relevant if we're in Virtual Wire | |
865 | * compatibility mode, but most boxes are anymore. | |
866 | */ | |
867 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 868 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
869 | reg1 = apic_read(APIC_LVT1); |
870 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
871 | ||
872 | return 1; | |
873 | } | |
874 | ||
0e078e2f TG |
875 | /** |
876 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
877 | */ | |
1da177e4 LT |
878 | void __init sync_Arb_IDs(void) |
879 | { | |
296cb951 CG |
880 | /* |
881 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
882 | * needed on AMD. | |
883 | */ | |
884 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
885 | return; |
886 | ||
887 | /* | |
888 | * Wait for idle. | |
889 | */ | |
890 | apic_wait_icr_idle(); | |
891 | ||
892 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
893 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
894 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
895 | } |
896 | ||
1da177e4 LT |
897 | /* |
898 | * An initial setup of the virtual wire mode. | |
899 | */ | |
900 | void __init init_bsp_APIC(void) | |
901 | { | |
11a8e778 | 902 | unsigned int value; |
1da177e4 LT |
903 | |
904 | /* | |
905 | * Don't do the setup now if we have a SMP BIOS as the | |
906 | * through-I/O-APIC virtual wire mode might be active. | |
907 | */ | |
908 | if (smp_found_config || !cpu_has_apic) | |
909 | return; | |
910 | ||
1da177e4 LT |
911 | /* |
912 | * Do not trust the local APIC being empty at bootup. | |
913 | */ | |
914 | clear_local_APIC(); | |
915 | ||
916 | /* | |
917 | * Enable APIC. | |
918 | */ | |
919 | value = apic_read(APIC_SPIV); | |
920 | value &= ~APIC_VECTOR_MASK; | |
921 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
922 | |
923 | #ifdef CONFIG_X86_32 | |
924 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
925 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
926 | (boot_cpu_data.x86 == 15)) | |
927 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
928 | else | |
929 | #endif | |
930 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 931 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 932 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
933 | |
934 | /* | |
935 | * Set up the virtual wire mode. | |
936 | */ | |
11a8e778 | 937 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 938 | value = APIC_DM_NMI; |
638c0411 CG |
939 | if (!lapic_is_integrated()) /* 82489DX */ |
940 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 941 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
942 | } |
943 | ||
c43da2f5 CG |
944 | static void __cpuinit lapic_setup_esr(void) |
945 | { | |
946 | unsigned long oldvalue, value, maxlvt; | |
947 | if (lapic_is_integrated() && !esr_disable) { | |
948 | if (esr_disable) { | |
949 | /* | |
950 | * Something untraceable is creating bad interrupts on | |
951 | * secondary quads ... for the moment, just leave the | |
952 | * ESR disabled - we can't do anything useful with the | |
953 | * errors anyway - mbligh | |
954 | */ | |
955 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
956 | return; | |
957 | } | |
958 | /* !82489DX */ | |
959 | maxlvt = lapic_get_maxlvt(); | |
960 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
961 | apic_write(APIC_ESR, 0); | |
962 | oldvalue = apic_read(APIC_ESR); | |
963 | ||
964 | /* enables sending errors */ | |
965 | value = ERROR_APIC_VECTOR; | |
966 | apic_write(APIC_LVTERR, value); | |
967 | /* | |
968 | * spec says clear errors after enabling vector. | |
969 | */ | |
970 | if (maxlvt > 3) | |
971 | apic_write(APIC_ESR, 0); | |
972 | value = apic_read(APIC_ESR); | |
973 | if (value != oldvalue) | |
974 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
975 | "vector: 0x%08lx after: 0x%08lx\n", | |
976 | oldvalue, value); | |
977 | } else { | |
978 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
979 | } | |
980 | } | |
981 | ||
982 | ||
0e078e2f TG |
983 | /** |
984 | * setup_local_APIC - setup the local APIC | |
985 | */ | |
986 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 987 | { |
739f33b3 | 988 | unsigned int value; |
da7ed9f9 | 989 | int i, j; |
1da177e4 | 990 | |
89c38c28 CG |
991 | #ifdef CONFIG_X86_32 |
992 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
993 | if (esr_disable) { | |
994 | apic_write(APIC_ESR, 0); | |
995 | apic_write(APIC_ESR, 0); | |
996 | apic_write(APIC_ESR, 0); | |
997 | apic_write(APIC_ESR, 0); | |
998 | } | |
999 | #endif | |
1000 | ||
ac23d4ee | 1001 | preempt_disable(); |
1da177e4 | 1002 | |
1da177e4 LT |
1003 | /* |
1004 | * Double-check whether this APIC is really registered. | |
1005 | * This is meaningless in clustered apic mode, so we skip it. | |
1006 | */ | |
1007 | if (!apic_id_registered()) | |
1008 | BUG(); | |
1009 | ||
1010 | /* | |
1011 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1012 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1013 | * document number 292116). So here it goes... | |
1014 | */ | |
1015 | init_apic_ldr(); | |
1016 | ||
1017 | /* | |
1018 | * Set Task Priority to 'accept all'. We never change this | |
1019 | * later on. | |
1020 | */ | |
1021 | value = apic_read(APIC_TASKPRI); | |
1022 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1023 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1024 | |
da7ed9f9 VG |
1025 | /* |
1026 | * After a crash, we no longer service the interrupts and a pending | |
1027 | * interrupt from previous kernel might still have ISR bit set. | |
1028 | * | |
1029 | * Most probably by now CPU has serviced that pending interrupt and | |
1030 | * it might not have done the ack_APIC_irq() because it thought, | |
1031 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1032 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1033 | * the interrupt. Hence a vector might get locked. It was noticed | |
1034 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1035 | */ | |
1036 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1037 | value = apic_read(APIC_ISR + i*0x10); | |
1038 | for (j = 31; j >= 0; j--) { | |
1039 | if (value & (1<<j)) | |
1040 | ack_APIC_irq(); | |
1041 | } | |
1042 | } | |
1043 | ||
1da177e4 LT |
1044 | /* |
1045 | * Now that we are all set up, enable the APIC | |
1046 | */ | |
1047 | value = apic_read(APIC_SPIV); | |
1048 | value &= ~APIC_VECTOR_MASK; | |
1049 | /* | |
1050 | * Enable APIC | |
1051 | */ | |
1052 | value |= APIC_SPIV_APIC_ENABLED; | |
1053 | ||
89c38c28 CG |
1054 | #ifdef CONFIG_X86_32 |
1055 | /* | |
1056 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1057 | * certain networking cards. If high frequency interrupts are | |
1058 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1059 | * entry is masked/unmasked at a high rate as well then sooner or | |
1060 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1061 | * from the device. If focus CPU is disabled then the hang goes | |
1062 | * away, oh well :-( | |
1063 | * | |
1064 | * [ This bug can be reproduced easily with a level-triggered | |
1065 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1066 | * BX chipset. ] | |
1067 | */ | |
1068 | /* | |
1069 | * Actually disabling the focus CPU check just makes the hang less | |
1070 | * frequent as it makes the interrupt distributon model be more | |
1071 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1072 | * See also the comment in end_level_ioapic_irq(). --macro | |
1073 | */ | |
1074 | ||
1075 | /* | |
1076 | * - enable focus processor (bit==0) | |
1077 | * - 64bit mode always use processor focus | |
1078 | * so no need to set it | |
1079 | */ | |
1080 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1081 | #endif | |
3f14c746 | 1082 | |
1da177e4 LT |
1083 | /* |
1084 | * Set spurious IRQ vector | |
1085 | */ | |
1086 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1087 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1088 | |
1089 | /* | |
1090 | * Set up LVT0, LVT1: | |
1091 | * | |
1092 | * set up through-local-APIC on the BP's LINT0. This is not | |
1093 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1094 | * we delegate interrupts to the 8259A. | |
1095 | */ | |
1096 | /* | |
1097 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1098 | */ | |
1099 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1100 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1101 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1102 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1103 | smp_processor_id()); |
1da177e4 LT |
1104 | } else { |
1105 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1106 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1107 | smp_processor_id()); |
1da177e4 | 1108 | } |
11a8e778 | 1109 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1110 | |
1111 | /* | |
1112 | * only the BP should see the LINT1 NMI signal, obviously. | |
1113 | */ | |
1114 | if (!smp_processor_id()) | |
1115 | value = APIC_DM_NMI; | |
1116 | else | |
1117 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1118 | if (!lapic_is_integrated()) /* 82489DX */ |
1119 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1120 | apic_write(APIC_LVT1, value); |
89c38c28 | 1121 | |
ac23d4ee | 1122 | preempt_enable(); |
739f33b3 | 1123 | } |
1da177e4 | 1124 | |
739f33b3 AK |
1125 | void __cpuinit end_local_APIC_setup(void) |
1126 | { | |
1127 | lapic_setup_esr(); | |
fa6b95fc CG |
1128 | |
1129 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1130 | { |
1131 | unsigned int value; | |
1132 | /* Disable the local apic timer */ | |
1133 | value = apic_read(APIC_LVTT); | |
1134 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1135 | apic_write(APIC_LVTT, value); | |
1136 | } | |
fa6b95fc CG |
1137 | #endif |
1138 | ||
f2802e7f | 1139 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1140 | apic_pm_activate(); |
1da177e4 | 1141 | } |
1da177e4 | 1142 | |
49899eac | 1143 | #ifdef HAVE_X2APIC |
6e1cb38a SS |
1144 | void check_x2apic(void) |
1145 | { | |
1146 | int msr, msr2; | |
1147 | ||
1148 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1149 | ||
1150 | if (msr & X2APIC_ENABLE) { | |
1151 | printk("x2apic enabled by BIOS, switching to x2apic ops\n"); | |
1152 | x2apic_preenabled = x2apic = 1; | |
1153 | apic_ops = &x2apic_ops; | |
1154 | } | |
1155 | } | |
1156 | ||
1157 | void enable_x2apic(void) | |
1158 | { | |
1159 | int msr, msr2; | |
1160 | ||
1161 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1162 | if (!(msr & X2APIC_ENABLE)) { | |
1163 | printk("Enabling x2apic\n"); | |
1164 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); | |
1165 | } | |
1166 | } | |
1167 | ||
1168 | void enable_IR_x2apic(void) | |
1169 | { | |
1170 | #ifdef CONFIG_INTR_REMAP | |
1171 | int ret; | |
1172 | unsigned long flags; | |
1173 | ||
1174 | if (!cpu_has_x2apic) | |
1175 | return; | |
1176 | ||
1177 | if (!x2apic_preenabled && disable_x2apic) { | |
1178 | printk(KERN_INFO | |
1179 | "Skipped enabling x2apic and Interrupt-remapping " | |
1180 | "because of nox2apic\n"); | |
1181 | return; | |
1182 | } | |
1183 | ||
1184 | if (x2apic_preenabled && disable_x2apic) | |
1185 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1186 | ||
1187 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
1188 | printk(KERN_INFO | |
1189 | "Skipped enabling x2apic and Interrupt-remapping " | |
1190 | "because of skipping io-apic setup\n"); | |
1191 | return; | |
1192 | } | |
1193 | ||
1194 | ret = dmar_table_init(); | |
1195 | if (ret) { | |
1196 | printk(KERN_INFO | |
1197 | "dmar_table_init() failed with %d:\n", ret); | |
1198 | ||
1199 | if (x2apic_preenabled) | |
1200 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1201 | else | |
1202 | printk(KERN_INFO | |
1203 | "Not enabling x2apic,Intr-remapping\n"); | |
1204 | return; | |
1205 | } | |
1206 | ||
1207 | local_irq_save(flags); | |
1208 | mask_8259A(); | |
1209 | save_mask_IO_APIC_setup(); | |
1210 | ||
1211 | ret = enable_intr_remapping(1); | |
1212 | ||
1213 | if (ret && x2apic_preenabled) { | |
1214 | local_irq_restore(flags); | |
1215 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1216 | } | |
1217 | ||
1218 | if (ret) | |
1219 | goto end; | |
1220 | ||
1221 | if (!x2apic) { | |
1222 | x2apic = 1; | |
1223 | apic_ops = &x2apic_ops; | |
1224 | enable_x2apic(); | |
1225 | } | |
1226 | end: | |
1227 | if (ret) | |
1228 | /* | |
1229 | * IR enabling failed | |
1230 | */ | |
1231 | restore_IO_APIC_setup(); | |
1232 | else | |
1233 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1234 | ||
1235 | unmask_8259A(); | |
1236 | local_irq_restore(flags); | |
1237 | ||
1238 | if (!ret) { | |
1239 | if (!x2apic_preenabled) | |
1240 | printk(KERN_INFO | |
1241 | "Enabled x2apic and interrupt-remapping\n"); | |
1242 | else | |
1243 | printk(KERN_INFO | |
1244 | "Enabled Interrupt-remapping\n"); | |
1245 | } else | |
1246 | printk(KERN_ERR | |
1247 | "Failed to enable Interrupt-remapping and x2apic\n"); | |
1248 | #else | |
1249 | if (!cpu_has_x2apic) | |
1250 | return; | |
1251 | ||
1252 | if (x2apic_preenabled) | |
1253 | panic("x2apic enabled prior OS handover," | |
1254 | " enable CONFIG_INTR_REMAP"); | |
1255 | ||
1256 | printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " | |
1257 | " and x2apic\n"); | |
1258 | #endif | |
1259 | ||
1260 | return; | |
1261 | } | |
49899eac | 1262 | #endif /* HAVE_X2APIC */ |
6e1cb38a | 1263 | |
1da177e4 LT |
1264 | /* |
1265 | * Detect and enable local APICs on non-SMP boards. | |
1266 | * Original code written by Keir Fraser. | |
1267 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1268 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1269 | */ |
0e078e2f | 1270 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1271 | { |
1272 | if (!cpu_has_apic) { | |
1273 | printk(KERN_INFO "No local APIC present\n"); | |
1274 | return -1; | |
1275 | } | |
1276 | ||
1277 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1278 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1279 | return 0; |
1280 | } | |
1281 | ||
8643f9d0 YL |
1282 | void __init early_init_lapic_mapping(void) |
1283 | { | |
431ee79d | 1284 | unsigned long phys_addr; |
8643f9d0 YL |
1285 | |
1286 | /* | |
1287 | * If no local APIC can be found then go out | |
1288 | * : it means there is no mpatable and MADT | |
1289 | */ | |
1290 | if (!smp_found_config) | |
1291 | return; | |
1292 | ||
431ee79d | 1293 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1294 | |
431ee79d | 1295 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1296 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1297 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1298 | |
1299 | /* | |
1300 | * Fetch the APIC ID of the BSP in case we have a | |
1301 | * default configuration (or the MP table is broken). | |
1302 | */ | |
4c9961d5 | 1303 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 YL |
1304 | } |
1305 | ||
0e078e2f TG |
1306 | /** |
1307 | * init_apic_mappings - initialize APIC mappings | |
1308 | */ | |
1da177e4 LT |
1309 | void __init init_apic_mappings(void) |
1310 | { | |
49899eac | 1311 | #ifdef HAVE_X2APIC |
6e1cb38a | 1312 | if (x2apic) { |
4c9961d5 | 1313 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1314 | return; |
1315 | } | |
49899eac | 1316 | #endif |
6e1cb38a | 1317 | |
1da177e4 LT |
1318 | /* |
1319 | * If no local APIC can be found then set up a fake all | |
1320 | * zeroes page to simulate the local APIC and another | |
1321 | * one for the IO-APIC. | |
1322 | */ | |
1323 | if (!smp_found_config && detect_init_APIC()) { | |
1324 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1325 | apic_phys = __pa(apic_phys); | |
1326 | } else | |
1327 | apic_phys = mp_lapic_addr; | |
1328 | ||
1329 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
1330 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
1331 | APIC_BASE, apic_phys); | |
1da177e4 LT |
1332 | |
1333 | /* | |
1334 | * Fetch the APIC ID of the BSP in case we have a | |
1335 | * default configuration (or the MP table is broken). | |
1336 | */ | |
4c9961d5 | 1337 | boot_cpu_physical_apicid = read_apic_id(); |
1da177e4 LT |
1338 | } |
1339 | ||
1340 | /* | |
0e078e2f TG |
1341 | * This initializes the IO-APIC and APIC hardware if this is |
1342 | * a UP kernel. | |
1da177e4 | 1343 | */ |
1b313f4a CG |
1344 | int apic_version[MAX_APICS]; |
1345 | ||
0e078e2f | 1346 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1347 | { |
0e078e2f TG |
1348 | if (disable_apic) { |
1349 | printk(KERN_INFO "Apic disabled\n"); | |
1350 | return -1; | |
1351 | } | |
1352 | if (!cpu_has_apic) { | |
1353 | disable_apic = 1; | |
1354 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1355 | return -1; | |
1356 | } | |
49899eac | 1357 | #ifdef HAVE_X2APIC |
6e1cb38a | 1358 | enable_IR_x2apic(); |
49899eac | 1359 | #endif |
6e1cb38a SS |
1360 | setup_apic_routing(); |
1361 | ||
0e078e2f | 1362 | verify_local_APIC(); |
1da177e4 | 1363 | |
b5841765 GC |
1364 | connect_bsp_APIC(); |
1365 | ||
b6df1b8b | 1366 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
c70dcb74 | 1367 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
1da177e4 | 1368 | |
0e078e2f | 1369 | setup_local_APIC(); |
1da177e4 | 1370 | |
739f33b3 AK |
1371 | /* |
1372 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1373 | * We need clear_IO_APIC before enabling vector on BP | |
1374 | */ | |
1375 | if (!skip_ioapic_setup && nr_ioapics) | |
1376 | enable_IO_APIC(); | |
1377 | ||
acae7d90 MR |
1378 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
1379 | localise_nmi_watchdog(); | |
739f33b3 AK |
1380 | end_local_APIC_setup(); |
1381 | ||
0e078e2f TG |
1382 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1383 | setup_IO_APIC(); | |
1384 | else | |
1385 | nr_ioapics = 0; | |
1386 | setup_boot_APIC_clock(); | |
1387 | check_nmi_watchdog(); | |
1388 | return 0; | |
1da177e4 LT |
1389 | } |
1390 | ||
1391 | /* | |
0e078e2f | 1392 | * Local APIC interrupts |
1da177e4 LT |
1393 | */ |
1394 | ||
0e078e2f TG |
1395 | /* |
1396 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1397 | */ | |
1398 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 1399 | { |
0e078e2f TG |
1400 | unsigned int v; |
1401 | exit_idle(); | |
1402 | irq_enter(); | |
1da177e4 | 1403 | /* |
0e078e2f TG |
1404 | * Check if this really is a spurious interrupt and ACK it |
1405 | * if it is a vectored one. Just in case... | |
1406 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1407 | */ |
0e078e2f TG |
1408 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1409 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1410 | ack_APIC_irq(); | |
c4d58cbd | 1411 | |
0e078e2f TG |
1412 | add_pda(irq_spurious_count, 1); |
1413 | irq_exit(); | |
1414 | } | |
1da177e4 | 1415 | |
0e078e2f TG |
1416 | /* |
1417 | * This interrupt should never happen with our APIC/SMP architecture | |
1418 | */ | |
1419 | asmlinkage void smp_error_interrupt(void) | |
1420 | { | |
1421 | unsigned int v, v1; | |
1da177e4 | 1422 | |
0e078e2f TG |
1423 | exit_idle(); |
1424 | irq_enter(); | |
1425 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1426 | v = apic_read(APIC_ESR); | |
1427 | apic_write(APIC_ESR, 0); | |
1428 | v1 = apic_read(APIC_ESR); | |
1429 | ack_APIC_irq(); | |
1430 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1431 | |
0e078e2f TG |
1432 | /* Here is what the APIC error bits mean: |
1433 | 0: Send CS error | |
1434 | 1: Receive CS error | |
1435 | 2: Send accept error | |
1436 | 3: Receive accept error | |
1437 | 4: Reserved | |
1438 | 5: Send illegal vector | |
1439 | 6: Received illegal vector | |
1440 | 7: Illegal register address | |
1441 | */ | |
1442 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1443 | smp_processor_id(), v , v1); | |
1444 | irq_exit(); | |
1da177e4 LT |
1445 | } |
1446 | ||
b5841765 | 1447 | /** |
36c9d674 CG |
1448 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1449 | */ | |
b5841765 GC |
1450 | void __init connect_bsp_APIC(void) |
1451 | { | |
36c9d674 CG |
1452 | #ifdef CONFIG_X86_32 |
1453 | if (pic_mode) { | |
1454 | /* | |
1455 | * Do not trust the local APIC being empty at bootup. | |
1456 | */ | |
1457 | clear_local_APIC(); | |
1458 | /* | |
1459 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1460 | * local APIC to INT and NMI lines. | |
1461 | */ | |
1462 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1463 | "enabling APIC mode.\n"); | |
1464 | outb(0x70, 0x22); | |
1465 | outb(0x01, 0x23); | |
1466 | } | |
1467 | #endif | |
b5841765 GC |
1468 | enable_apic_mode(); |
1469 | } | |
1470 | ||
274cfe59 CG |
1471 | /** |
1472 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1473 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1474 | * | |
1475 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1476 | * APIC is disabled. | |
1477 | */ | |
0e078e2f | 1478 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1479 | { |
1b4ee4e4 CG |
1480 | unsigned int value; |
1481 | ||
c177b0bc CG |
1482 | #ifdef CONFIG_X86_32 |
1483 | if (pic_mode) { | |
1484 | /* | |
1485 | * Put the board back into PIC mode (has an effect only on | |
1486 | * certain older boards). Note that APIC interrupts, including | |
1487 | * IPIs, won't work beyond this point! The only exception are | |
1488 | * INIT IPIs. | |
1489 | */ | |
1490 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1491 | "entering PIC mode.\n"); | |
1492 | outb(0x70, 0x22); | |
1493 | outb(0x00, 0x23); | |
1494 | return; | |
1495 | } | |
1496 | #endif | |
1497 | ||
0e078e2f | 1498 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1499 | |
0e078e2f TG |
1500 | /* For the spurious interrupt use vector F, and enable it */ |
1501 | value = apic_read(APIC_SPIV); | |
1502 | value &= ~APIC_VECTOR_MASK; | |
1503 | value |= APIC_SPIV_APIC_ENABLED; | |
1504 | value |= 0xf; | |
1505 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1506 | |
0e078e2f TG |
1507 | if (!virt_wire_setup) { |
1508 | /* | |
1509 | * For LVT0 make it edge triggered, active high, | |
1510 | * external and enabled | |
1511 | */ | |
1512 | value = apic_read(APIC_LVT0); | |
1513 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1514 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1515 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1516 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1517 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1518 | apic_write(APIC_LVT0, value); | |
1519 | } else { | |
1520 | /* Disable LVT0 */ | |
1521 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1522 | } | |
b8ce3359 | 1523 | |
c177b0bc CG |
1524 | /* |
1525 | * For LVT1 make it edge triggered, active high, | |
1526 | * nmi and enabled | |
1527 | */ | |
0e078e2f TG |
1528 | value = apic_read(APIC_LVT1); |
1529 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1530 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1531 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1532 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1533 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1534 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1535 | } |
1536 | ||
be8a5685 AS |
1537 | void __cpuinit generic_processor_info(int apicid, int version) |
1538 | { | |
1539 | int cpu; | |
1540 | cpumask_t tmp_map; | |
1541 | ||
1b313f4a CG |
1542 | /* |
1543 | * Validate version | |
1544 | */ | |
1545 | if (version == 0x0) { | |
1546 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1547 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1548 | version); | |
1549 | version = 0x10; | |
be8a5685 | 1550 | } |
1b313f4a | 1551 | apic_version[apicid] = version; |
be8a5685 | 1552 | |
be8a5685 AS |
1553 | if (num_processors >= NR_CPUS) { |
1554 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1b313f4a | 1555 | " Processor ignored.\n", NR_CPUS); |
be8a5685 AS |
1556 | return; |
1557 | } | |
1558 | ||
1559 | num_processors++; | |
1560 | cpus_complement(tmp_map, cpu_present_map); | |
1561 | cpu = first_cpu(tmp_map); | |
1562 | ||
1563 | physid_set(apicid, phys_cpu_present_map); | |
1564 | if (apicid == boot_cpu_physical_apicid) { | |
1565 | /* | |
1566 | * x86_bios_cpu_apicid is required to have processors listed | |
1567 | * in same order as logical cpu numbers. Hence the first | |
1568 | * entry is BSP, and so on. | |
1569 | */ | |
1570 | cpu = 0; | |
1571 | } | |
e0da3364 YL |
1572 | if (apicid > max_physical_apicid) |
1573 | max_physical_apicid = apicid; | |
1574 | ||
1b313f4a CG |
1575 | #ifdef CONFIG_X86_32 |
1576 | /* | |
1577 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1578 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1579 | * before this can be done without some confusion. | |
1580 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1581 | * - Ashok Raj <ashok.raj@intel.com> | |
1582 | */ | |
1583 | if (max_physical_apicid >= 8) { | |
1584 | switch (boot_cpu_data.x86_vendor) { | |
1585 | case X86_VENDOR_INTEL: | |
1586 | if (!APIC_XAPIC(version)) { | |
1587 | def_to_bigsmp = 0; | |
1588 | break; | |
1589 | } | |
1590 | /* If P4 and above fall through */ | |
1591 | case X86_VENDOR_AMD: | |
1592 | def_to_bigsmp = 1; | |
1593 | } | |
1594 | } | |
1595 | #endif | |
1596 | ||
1597 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
be8a5685 | 1598 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1599 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1600 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1601 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1602 | |
1603 | cpu_to_apicid[cpu] = apicid; | |
1604 | bios_cpu_apicid[cpu] = apicid; | |
1605 | } else { | |
1606 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1607 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1608 | } | |
1b313f4a | 1609 | #endif |
be8a5685 AS |
1610 | |
1611 | cpu_set(cpu, cpu_possible_map); | |
1612 | cpu_set(cpu, cpu_present_map); | |
1613 | } | |
1614 | ||
3491998d | 1615 | #ifdef CONFIG_X86_64 |
0c81c746 SS |
1616 | int hard_smp_processor_id(void) |
1617 | { | |
1618 | return read_apic_id(); | |
1619 | } | |
3491998d | 1620 | #endif |
0c81c746 | 1621 | |
89039b37 | 1622 | /* |
0e078e2f | 1623 | * Power management |
89039b37 | 1624 | */ |
0e078e2f TG |
1625 | #ifdef CONFIG_PM |
1626 | ||
1627 | static struct { | |
274cfe59 CG |
1628 | /* |
1629 | * 'active' is true if the local APIC was enabled by us and | |
1630 | * not the BIOS; this signifies that we are also responsible | |
1631 | * for disabling it before entering apm/acpi suspend | |
1632 | */ | |
0e078e2f TG |
1633 | int active; |
1634 | /* r/w apic fields */ | |
1635 | unsigned int apic_id; | |
1636 | unsigned int apic_taskpri; | |
1637 | unsigned int apic_ldr; | |
1638 | unsigned int apic_dfr; | |
1639 | unsigned int apic_spiv; | |
1640 | unsigned int apic_lvtt; | |
1641 | unsigned int apic_lvtpc; | |
1642 | unsigned int apic_lvt0; | |
1643 | unsigned int apic_lvt1; | |
1644 | unsigned int apic_lvterr; | |
1645 | unsigned int apic_tmict; | |
1646 | unsigned int apic_tdcr; | |
1647 | unsigned int apic_thmr; | |
1648 | } apic_pm_state; | |
1649 | ||
1650 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1651 | { | |
1652 | unsigned long flags; | |
1653 | int maxlvt; | |
89039b37 | 1654 | |
0e078e2f TG |
1655 | if (!apic_pm_state.active) |
1656 | return 0; | |
89039b37 | 1657 | |
0e078e2f | 1658 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1659 | |
2d7a66d0 | 1660 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1661 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1662 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1663 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1664 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1665 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1666 | if (maxlvt >= 4) | |
1667 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1668 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1669 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1670 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1671 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1672 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1673 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1674 | if (maxlvt >= 5) |
1675 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1676 | #endif | |
24968cfd | 1677 | |
0e078e2f TG |
1678 | local_irq_save(flags); |
1679 | disable_local_APIC(); | |
1680 | local_irq_restore(flags); | |
1681 | return 0; | |
1da177e4 LT |
1682 | } |
1683 | ||
0e078e2f | 1684 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1685 | { |
0e078e2f TG |
1686 | unsigned int l, h; |
1687 | unsigned long flags; | |
1688 | int maxlvt; | |
1da177e4 | 1689 | |
0e078e2f TG |
1690 | if (!apic_pm_state.active) |
1691 | return 0; | |
89b831ef | 1692 | |
0e078e2f | 1693 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1694 | |
0e078e2f | 1695 | local_irq_save(flags); |
92206c90 | 1696 | |
49899eac | 1697 | #ifdef HAVE_X2APIC |
92206c90 CG |
1698 | if (x2apic) |
1699 | enable_x2apic(); | |
1700 | else | |
1701 | #endif | |
d5e629a6 | 1702 | { |
92206c90 CG |
1703 | /* |
1704 | * Make sure the APICBASE points to the right address | |
1705 | * | |
1706 | * FIXME! This will be wrong if we ever support suspend on | |
1707 | * SMP! We'll need to do this as part of the CPU restore! | |
1708 | */ | |
6e1cb38a SS |
1709 | rdmsr(MSR_IA32_APICBASE, l, h); |
1710 | l &= ~MSR_IA32_APICBASE_BASE; | |
1711 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1712 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 1713 | } |
6e1cb38a | 1714 | |
0e078e2f TG |
1715 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
1716 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1717 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1718 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1719 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1720 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1721 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1722 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 1723 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1724 | if (maxlvt >= 5) |
1725 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1726 | #endif | |
1727 | if (maxlvt >= 4) | |
1728 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1729 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1730 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1731 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1732 | apic_write(APIC_ESR, 0); | |
1733 | apic_read(APIC_ESR); | |
1734 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1735 | apic_write(APIC_ESR, 0); | |
1736 | apic_read(APIC_ESR); | |
92206c90 | 1737 | |
0e078e2f | 1738 | local_irq_restore(flags); |
92206c90 | 1739 | |
0e078e2f TG |
1740 | return 0; |
1741 | } | |
b8ce3359 | 1742 | |
274cfe59 CG |
1743 | /* |
1744 | * This device has no shutdown method - fully functioning local APICs | |
1745 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1746 | */ | |
1747 | ||
0e078e2f TG |
1748 | static struct sysdev_class lapic_sysclass = { |
1749 | .name = "lapic", | |
1750 | .resume = lapic_resume, | |
1751 | .suspend = lapic_suspend, | |
1752 | }; | |
b8ce3359 | 1753 | |
0e078e2f | 1754 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1755 | .id = 0, |
1756 | .cls = &lapic_sysclass, | |
0e078e2f | 1757 | }; |
b8ce3359 | 1758 | |
0e078e2f TG |
1759 | static void __cpuinit apic_pm_activate(void) |
1760 | { | |
1761 | apic_pm_state.active = 1; | |
1da177e4 LT |
1762 | } |
1763 | ||
0e078e2f | 1764 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1765 | { |
0e078e2f | 1766 | int error; |
e83a5fdc | 1767 | |
0e078e2f TG |
1768 | if (!cpu_has_apic) |
1769 | return 0; | |
1770 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1771 | |
0e078e2f TG |
1772 | error = sysdev_class_register(&lapic_sysclass); |
1773 | if (!error) | |
1774 | error = sysdev_register(&device_lapic); | |
1775 | return error; | |
1da177e4 | 1776 | } |
0e078e2f TG |
1777 | device_initcall(init_lapic_sysfs); |
1778 | ||
1779 | #else /* CONFIG_PM */ | |
1780 | ||
1781 | static void apic_pm_activate(void) { } | |
1782 | ||
1783 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1784 | |
1785 | /* | |
f8bf3c65 | 1786 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1787 | * |
1788 | * Thus far, the major user of this is IBM's Summit2 series: | |
1789 | * | |
637029c6 | 1790 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1791 | * multi-chassis. Use available data to take a good guess. |
1792 | * If in doubt, go HPET. | |
1793 | */ | |
f8bf3c65 | 1794 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1795 | { |
1796 | int i, clusters, zeros; | |
1797 | unsigned id; | |
322850af | 1798 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1799 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1800 | ||
322850af YL |
1801 | /* |
1802 | * there is not this kind of box with AMD CPU yet. | |
1803 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1804 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1805 | * vsmp box still need checking... |
322850af | 1806 | */ |
1cb68487 | 1807 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1808 | return 0; |
1809 | ||
23ca4bba | 1810 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 1811 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1812 | |
1813 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1814 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1815 | if (bios_cpu_apicid) { |
1816 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1817 | } |
1818 | else if (i < nr_cpu_ids) { | |
1819 | if (cpu_present(i)) | |
1820 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1821 | else | |
1822 | continue; | |
1823 | } | |
1824 | else | |
1825 | break; | |
1826 | ||
1da177e4 LT |
1827 | if (id != BAD_APICID) |
1828 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1829 | } | |
1830 | ||
1831 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1832 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1833 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1834 | * Since clusters are allocated sequentially, count zeros only if | |
1835 | * they are bounded by ones. | |
1da177e4 LT |
1836 | */ |
1837 | clusters = 0; | |
1838 | zeros = 0; | |
1839 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1840 | if (test_bit(i, clustermap)) { | |
1841 | clusters += 1 + zeros; | |
1842 | zeros = 0; | |
1843 | } else | |
1844 | ++zeros; | |
1845 | } | |
1846 | ||
1cb68487 RT |
1847 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1848 | * not guaranteed to be synced between boards | |
1849 | */ | |
1850 | if (is_vsmp_box() && clusters > 1) | |
1851 | return 1; | |
1852 | ||
1da177e4 | 1853 | /* |
f8bf3c65 | 1854 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1855 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1856 | * out, but AFAIK this will work even for them. | |
1857 | */ | |
1858 | return (clusters > 2); | |
1859 | } | |
1860 | ||
1861 | /* | |
0e078e2f | 1862 | * APIC command line parameters |
1da177e4 | 1863 | */ |
789fa735 | 1864 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 1865 | { |
1da177e4 | 1866 | disable_apic = 1; |
9175fc06 | 1867 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
1868 | return 0; |
1869 | } | |
1870 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1871 | |
2c8c0e6b | 1872 | /* same as disableapic, for compatibility */ |
789fa735 | 1873 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 1874 | { |
789fa735 | 1875 | return setup_disableapic(arg); |
6935d1f9 | 1876 | } |
2c8c0e6b | 1877 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1878 | |
2e7c2838 LT |
1879 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1880 | { | |
1881 | local_apic_timer_c2_ok = 1; | |
1882 | return 0; | |
1883 | } | |
1884 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1885 | ||
36fef094 | 1886 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 1887 | { |
1da177e4 | 1888 | disable_apic_timer = 1; |
36fef094 | 1889 | return 0; |
6935d1f9 | 1890 | } |
36fef094 CG |
1891 | early_param("noapictimer", parse_disable_apic_timer); |
1892 | ||
1893 | static int __init parse_nolapic_timer(char *arg) | |
1894 | { | |
1895 | disable_apic_timer = 1; | |
1896 | return 0; | |
6935d1f9 | 1897 | } |
36fef094 | 1898 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 1899 | |
79af9bec CG |
1900 | static int __init apic_set_verbosity(char *arg) |
1901 | { | |
1902 | if (!arg) { | |
1903 | #ifdef CONFIG_X86_64 | |
1904 | skip_ioapic_setup = 0; | |
79af9bec CG |
1905 | return 0; |
1906 | #endif | |
1907 | return -EINVAL; | |
1908 | } | |
1909 | ||
1910 | if (strcmp("debug", arg) == 0) | |
1911 | apic_verbosity = APIC_DEBUG; | |
1912 | else if (strcmp("verbose", arg) == 0) | |
1913 | apic_verbosity = APIC_VERBOSE; | |
1914 | else { | |
1915 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1916 | " use apic=verbose or apic=debug\n", arg); | |
1917 | return -EINVAL; | |
1918 | } | |
1919 | ||
1920 | return 0; | |
1921 | } | |
1922 | early_param("apic", apic_set_verbosity); | |
1923 | ||
1e934dda YL |
1924 | static int __init lapic_insert_resource(void) |
1925 | { | |
1926 | if (!apic_phys) | |
1927 | return -1; | |
1928 | ||
1929 | /* Put local APIC into the resource map. */ | |
1930 | lapic_resource.start = apic_phys; | |
1931 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1932 | insert_resource(&iomem_resource, &lapic_resource); | |
1933 | ||
1934 | return 0; | |
1935 | } | |
1936 | ||
1937 | /* | |
1938 | * need call insert after e820_reserve_resources() | |
1939 | * that is using request_resource | |
1940 | */ | |
1941 | late_initcall(lapic_insert_resource); |