Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
6e1cb38a | 30 | #include <linux/dmar.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
efa2559f | 36 | #include <asm/desc.h> |
e83a5fdc | 37 | #include <asm/hpet.h> |
1da177e4 | 38 | #include <asm/pgalloc.h> |
75152114 | 39 | #include <asm/nmi.h> |
95833c83 | 40 | #include <asm/idle.h> |
73dea47f AK |
41 | #include <asm/proto.h> |
42 | #include <asm/timex.h> | |
2c8c0e6b | 43 | #include <asm/apic.h> |
6e1cb38a | 44 | #include <asm/i8259.h> |
1da177e4 | 45 | |
5af5573e | 46 | #include <mach_ipi.h> |
dd46e3ca | 47 | #include <mach_apic.h> |
5af5573e | 48 | |
80e5609c CG |
49 | /* |
50 | * Sanity check | |
51 | */ | |
52 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | |
53 | # error SPURIOUS_APIC_VECTOR definition error | |
54 | #endif | |
55 | ||
36fef094 | 56 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
aa276e1c | 57 | static int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 58 | static int apic_calibrate_pmtmr __initdata; |
0e078e2f | 59 | int disable_apic; |
6e1cb38a | 60 | int disable_x2apic; |
89027d35 | 61 | int x2apic; |
1da177e4 | 62 | |
6e1cb38a SS |
63 | /* x2apic enabled before OS handover */ |
64 | int x2apic_preenabled; | |
1da177e4 | 65 | |
e83a5fdc | 66 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
67 | int local_apic_timer_c2_ok; |
68 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
69 | ||
efa2559f YL |
70 | int first_system_vector = 0xfe; |
71 | ||
72 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
73 | ||
e83a5fdc HS |
74 | /* |
75 | * Debug level, exported for io_apic.c | |
76 | */ | |
baa13188 | 77 | unsigned int apic_verbosity; |
e83a5fdc | 78 | |
89c38c28 CG |
79 | int pic_mode; |
80 | ||
bab4b27c AS |
81 | /* Have we found an MP table */ |
82 | int smp_found_config; | |
83 | ||
39928722 AD |
84 | static struct resource lapic_resource = { |
85 | .name = "Local APIC", | |
86 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
87 | }; | |
88 | ||
d03030e9 TG |
89 | static unsigned int calibration_result; |
90 | ||
ba7eda4c TG |
91 | static int lapic_next_event(unsigned long delta, |
92 | struct clock_event_device *evt); | |
93 | static void lapic_timer_setup(enum clock_event_mode mode, | |
94 | struct clock_event_device *evt); | |
ba7eda4c | 95 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 96 | static void apic_pm_activate(void); |
ba7eda4c | 97 | |
274cfe59 CG |
98 | /* |
99 | * The local apic timer can be used for any function which is CPU local. | |
100 | */ | |
ba7eda4c TG |
101 | static struct clock_event_device lapic_clockevent = { |
102 | .name = "lapic", | |
103 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
104 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
105 | .shift = 32, | |
106 | .set_mode = lapic_timer_setup, | |
107 | .set_next_event = lapic_next_event, | |
108 | .broadcast = lapic_timer_broadcast, | |
109 | .rating = 100, | |
110 | .irq = -1, | |
111 | }; | |
112 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
113 | ||
d3432896 AK |
114 | static unsigned long apic_phys; |
115 | ||
3f530709 AS |
116 | unsigned long mp_lapic_addr; |
117 | ||
0e078e2f TG |
118 | /* |
119 | * Get the LAPIC version | |
120 | */ | |
121 | static inline int lapic_get_version(void) | |
ba7eda4c | 122 | { |
0e078e2f | 123 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
124 | } |
125 | ||
0e078e2f | 126 | /* |
9c803869 | 127 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
128 | */ |
129 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 130 | { |
9c803869 | 131 | #ifdef CONFIG_X86_64 |
0e078e2f | 132 | return 1; |
9c803869 CG |
133 | #else |
134 | return APIC_INTEGRATED(lapic_get_version()); | |
135 | #endif | |
ba7eda4c TG |
136 | } |
137 | ||
138 | /* | |
0e078e2f | 139 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 140 | */ |
0e078e2f | 141 | static int modern_apic(void) |
ba7eda4c | 142 | { |
0e078e2f TG |
143 | /* AMD systems use old APIC versions, so check the CPU */ |
144 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
145 | boot_cpu_data.x86 >= 0xf) | |
146 | return 1; | |
147 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
148 | } |
149 | ||
274cfe59 CG |
150 | /* |
151 | * Paravirt kernels also might be using these below ops. So we still | |
152 | * use generic apic_read()/apic_write(), which might be pointing to different | |
153 | * ops in PARAVIRT case. | |
154 | */ | |
1b374e4d | 155 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
156 | { |
157 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
158 | cpu_relax(); | |
159 | } | |
160 | ||
1b374e4d | 161 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 162 | { |
3c6bb07a | 163 | u32 send_status; |
8339e9fb FLV |
164 | int timeout; |
165 | ||
166 | timeout = 0; | |
167 | do { | |
168 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
169 | if (!send_status) | |
170 | break; | |
171 | udelay(100); | |
172 | } while (timeout++ < 1000); | |
173 | ||
174 | return send_status; | |
175 | } | |
176 | ||
1b374e4d SS |
177 | void xapic_icr_write(u32 low, u32 id) |
178 | { | |
ed4e5ec1 | 179 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
180 | apic_write(APIC_ICR, low); |
181 | } | |
182 | ||
183 | u64 xapic_icr_read(void) | |
184 | { | |
185 | u32 icr1, icr2; | |
186 | ||
187 | icr2 = apic_read(APIC_ICR2); | |
188 | icr1 = apic_read(APIC_ICR); | |
189 | ||
cf9768d7 | 190 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
191 | } |
192 | ||
193 | static struct apic_ops xapic_ops = { | |
194 | .read = native_apic_mem_read, | |
195 | .write = native_apic_mem_write, | |
1b374e4d SS |
196 | .icr_read = xapic_icr_read, |
197 | .icr_write = xapic_icr_write, | |
198 | .wait_icr_idle = xapic_wait_icr_idle, | |
199 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
200 | }; | |
201 | ||
202 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
203 | EXPORT_SYMBOL_GPL(apic_ops); |
204 | ||
13c88fb5 SS |
205 | static void x2apic_wait_icr_idle(void) |
206 | { | |
207 | /* no need to wait for icr idle in x2apic */ | |
208 | return; | |
209 | } | |
210 | ||
211 | static u32 safe_x2apic_wait_icr_idle(void) | |
212 | { | |
213 | /* no need to wait for icr idle in x2apic */ | |
214 | return 0; | |
215 | } | |
216 | ||
217 | void x2apic_icr_write(u32 low, u32 id) | |
218 | { | |
219 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
220 | } | |
221 | ||
222 | u64 x2apic_icr_read(void) | |
223 | { | |
224 | unsigned long val; | |
225 | ||
226 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
227 | return val; | |
228 | } | |
229 | ||
230 | static struct apic_ops x2apic_ops = { | |
231 | .read = native_apic_msr_read, | |
232 | .write = native_apic_msr_write, | |
13c88fb5 SS |
233 | .icr_read = x2apic_icr_read, |
234 | .icr_write = x2apic_icr_write, | |
235 | .wait_icr_idle = x2apic_wait_icr_idle, | |
236 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
237 | }; | |
238 | ||
0e078e2f TG |
239 | /** |
240 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
241 | */ | |
e9427101 | 242 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 243 | { |
11a8e778 | 244 | unsigned int v; |
6935d1f9 TG |
245 | |
246 | /* unmask and set to NMI */ | |
247 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
248 | |
249 | /* Level triggered for 82489DX (32bit mode) */ | |
250 | if (!lapic_is_integrated()) | |
251 | v |= APIC_LVT_LEVEL_TRIGGER; | |
252 | ||
11a8e778 | 253 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
254 | } |
255 | ||
7c37e48b CG |
256 | #ifdef CONFIG_X86_32 |
257 | /** | |
258 | * get_physical_broadcast - Get number of physical broadcast IDs | |
259 | */ | |
260 | int get_physical_broadcast(void) | |
261 | { | |
262 | return modern_apic() ? 0xff : 0xf; | |
263 | } | |
264 | #endif | |
265 | ||
0e078e2f TG |
266 | /** |
267 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
268 | */ | |
37e650c7 | 269 | int lapic_get_maxlvt(void) |
1da177e4 | 270 | { |
36a028de | 271 | unsigned int v; |
1da177e4 LT |
272 | |
273 | v = apic_read(APIC_LVR); | |
36a028de CG |
274 | /* |
275 | * - we always have APIC integrated on 64bit mode | |
276 | * - 82489DXs do not report # of LVT entries | |
277 | */ | |
278 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
279 | } |
280 | ||
274cfe59 CG |
281 | /* |
282 | * Local APIC timer | |
283 | */ | |
284 | ||
c40aaec6 CG |
285 | /* Clock divisor */ |
286 | #ifdef CONFG_X86_64 | |
f07f4f90 | 287 | #define APIC_DIVISOR 1 |
c40aaec6 CG |
288 | #else |
289 | #define APIC_DIVISOR 16 | |
290 | #endif | |
f07f4f90 | 291 | |
0e078e2f TG |
292 | /* |
293 | * This function sets up the local APIC timer, with a timeout of | |
294 | * 'clocks' APIC bus clock. During calibration we actually call | |
295 | * this function twice on the boot CPU, once with a bogus timeout | |
296 | * value, second time for real. The other (noncalibrating) CPUs | |
297 | * call this function only once, with the real, calibrated value. | |
298 | * | |
299 | * We do reads before writes even if unnecessary, to get around the | |
300 | * P5 APIC double write bug. | |
301 | */ | |
0e078e2f | 302 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 303 | { |
0e078e2f | 304 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 305 | |
0e078e2f TG |
306 | lvtt_value = LOCAL_TIMER_VECTOR; |
307 | if (!oneshot) | |
308 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
309 | if (!lapic_is_integrated()) |
310 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
311 | ||
0e078e2f TG |
312 | if (!irqen) |
313 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 314 | |
0e078e2f | 315 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
316 | |
317 | /* | |
0e078e2f | 318 | * Divide PICLK by 16 |
1da177e4 | 319 | */ |
0e078e2f | 320 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
321 | apic_write(APIC_TDCR, |
322 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
323 | APIC_TDR_DIV_16); | |
0e078e2f TG |
324 | |
325 | if (!oneshot) | |
f07f4f90 | 326 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
327 | } |
328 | ||
0e078e2f | 329 | /* |
7b83dae7 RR |
330 | * Setup extended LVT, AMD specific (K8, family 10h) |
331 | * | |
332 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
333 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
334 | * |
335 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
336 | * enables the vector. See also the BKDGs. | |
0e078e2f | 337 | */ |
7b83dae7 RR |
338 | |
339 | #define APIC_EILVT_LVTOFF_MCE 0 | |
340 | #define APIC_EILVT_LVTOFF_IBS 1 | |
341 | ||
342 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 343 | { |
7b83dae7 | 344 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 345 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 346 | |
0e078e2f | 347 | apic_write(reg, v); |
1da177e4 LT |
348 | } |
349 | ||
7b83dae7 RR |
350 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
351 | { | |
352 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
353 | return APIC_EILVT_LVTOFF_MCE; | |
354 | } | |
355 | ||
356 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
357 | { | |
358 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
359 | return APIC_EILVT_LVTOFF_IBS; | |
360 | } | |
6aa360e6 | 361 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 362 | |
0e078e2f TG |
363 | /* |
364 | * Program the next event, relative to now | |
365 | */ | |
366 | static int lapic_next_event(unsigned long delta, | |
367 | struct clock_event_device *evt) | |
1da177e4 | 368 | { |
0e078e2f TG |
369 | apic_write(APIC_TMICT, delta); |
370 | return 0; | |
1da177e4 LT |
371 | } |
372 | ||
0e078e2f TG |
373 | /* |
374 | * Setup the lapic timer in periodic or oneshot mode | |
375 | */ | |
376 | static void lapic_timer_setup(enum clock_event_mode mode, | |
377 | struct clock_event_device *evt) | |
9b7711f0 HS |
378 | { |
379 | unsigned long flags; | |
0e078e2f | 380 | unsigned int v; |
9b7711f0 | 381 | |
0e078e2f TG |
382 | /* Lapic used as dummy for broadcast ? */ |
383 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
384 | return; |
385 | ||
386 | local_irq_save(flags); | |
387 | ||
0e078e2f TG |
388 | switch (mode) { |
389 | case CLOCK_EVT_MODE_PERIODIC: | |
390 | case CLOCK_EVT_MODE_ONESHOT: | |
391 | __setup_APIC_LVTT(calibration_result, | |
392 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
393 | break; | |
394 | case CLOCK_EVT_MODE_UNUSED: | |
395 | case CLOCK_EVT_MODE_SHUTDOWN: | |
396 | v = apic_read(APIC_LVTT); | |
397 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
398 | apic_write(APIC_LVTT, v); | |
399 | break; | |
400 | case CLOCK_EVT_MODE_RESUME: | |
401 | /* Nothing to do here */ | |
402 | break; | |
403 | } | |
9b7711f0 HS |
404 | |
405 | local_irq_restore(flags); | |
406 | } | |
407 | ||
1da177e4 | 408 | /* |
0e078e2f | 409 | * Local APIC timer broadcast function |
1da177e4 | 410 | */ |
0e078e2f | 411 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 412 | { |
0e078e2f TG |
413 | #ifdef CONFIG_SMP |
414 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
415 | #endif | |
416 | } | |
1da177e4 | 417 | |
0e078e2f TG |
418 | /* |
419 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
420 | * of the boot CPU and register the clock event in the framework. | |
421 | */ | |
db4b5525 | 422 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
423 | { |
424 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 425 | |
0e078e2f TG |
426 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
427 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 428 | |
0e078e2f TG |
429 | clockevents_register_device(levt); |
430 | } | |
1da177e4 | 431 | |
0e078e2f TG |
432 | /* |
433 | * In this function we calibrate APIC bus clocks to the external | |
434 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
435 | * to calibrate, since some later bootup code depends on getting | |
436 | * the first irq? Ugh. | |
437 | * | |
438 | * We want to do the calibration only once since we | |
439 | * want to have local timer irqs syncron. CPUs connected | |
440 | * by the same APIC bus have the very same bus frequency. | |
441 | * And we want to have irqs off anyways, no accidental | |
442 | * APIC irq that way. | |
443 | */ | |
444 | ||
445 | #define TICK_COUNT 100000000 | |
446 | ||
89b3b1f4 | 447 | static int __init calibrate_APIC_clock(void) |
0e078e2f TG |
448 | { |
449 | unsigned apic, apic_start; | |
450 | unsigned long tsc, tsc_start; | |
451 | int result; | |
452 | ||
453 | local_irq_disable(); | |
454 | ||
455 | /* | |
456 | * Put whatever arbitrary (but long enough) timeout | |
457 | * value into the APIC clock, we just want to get the | |
458 | * counter running for calibration. | |
459 | * | |
460 | * No interrupt enable ! | |
461 | */ | |
462 | __setup_APIC_LVTT(250000000, 0, 0); | |
463 | ||
464 | apic_start = apic_read(APIC_TMCCT); | |
465 | #ifdef CONFIG_X86_PM_TIMER | |
466 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
467 | pmtimer_wait(5000); /* 5ms wait */ | |
468 | apic = apic_read(APIC_TMCCT); | |
469 | result = (apic_start - apic) * 1000L / 5; | |
470 | } else | |
471 | #endif | |
472 | { | |
473 | rdtscll(tsc_start); | |
474 | ||
475 | do { | |
476 | apic = apic_read(APIC_TMCCT); | |
477 | rdtscll(tsc); | |
478 | } while ((tsc - tsc_start) < TICK_COUNT && | |
479 | (apic_start - apic) < TICK_COUNT); | |
480 | ||
481 | result = (apic_start - apic) * 1000L * tsc_khz / | |
482 | (tsc - tsc_start); | |
483 | } | |
484 | ||
485 | local_irq_enable(); | |
486 | ||
487 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
488 | ||
489 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
490 | result / 1000 / 1000, result / 1000 % 1000); | |
491 | ||
492 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
493 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
494 | lapic_clockevent.shift); | |
0e078e2f TG |
495 | lapic_clockevent.max_delta_ns = |
496 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
497 | lapic_clockevent.min_delta_ns = | |
498 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
499 | ||
f07f4f90 | 500 | calibration_result = (result * APIC_DIVISOR) / HZ; |
89b3b1f4 CG |
501 | |
502 | /* | |
503 | * Do a sanity check on the APIC calibration result | |
504 | */ | |
505 | if (calibration_result < (1000000 / HZ)) { | |
506 | printk(KERN_WARNING | |
507 | "APIC frequency too slow, disabling apic timer\n"); | |
508 | return -1; | |
509 | } | |
510 | ||
511 | return 0; | |
0e078e2f TG |
512 | } |
513 | ||
e83a5fdc HS |
514 | /* |
515 | * Setup the boot APIC | |
516 | * | |
517 | * Calibrate and verify the result. | |
518 | */ | |
0e078e2f TG |
519 | void __init setup_boot_APIC_clock(void) |
520 | { | |
521 | /* | |
274cfe59 CG |
522 | * The local apic timer can be disabled via the kernel |
523 | * commandline or from the CPU detection code. Register the lapic | |
524 | * timer as a dummy clock event source on SMP systems, so the | |
525 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
526 | */ |
527 | if (disable_apic_timer) { | |
528 | printk(KERN_INFO "Disabling APIC timer\n"); | |
529 | /* No broadcast on UP ! */ | |
9d09951d TG |
530 | if (num_possible_cpus() > 1) { |
531 | lapic_clockevent.mult = 1; | |
0e078e2f | 532 | setup_APIC_timer(); |
9d09951d | 533 | } |
0e078e2f TG |
534 | return; |
535 | } | |
536 | ||
274cfe59 CG |
537 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
538 | "calibrating APIC timer ...\n"); | |
539 | ||
89b3b1f4 | 540 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
541 | /* No broadcast on UP ! */ |
542 | if (num_possible_cpus() > 1) | |
543 | setup_APIC_timer(); | |
544 | return; | |
545 | } | |
546 | ||
0e078e2f TG |
547 | /* |
548 | * If nmi_watchdog is set to IO_APIC, we need the | |
549 | * PIT/HPET going. Otherwise register lapic as a dummy | |
550 | * device. | |
551 | */ | |
552 | if (nmi_watchdog != NMI_IO_APIC) | |
553 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
554 | else | |
555 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 556 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 557 | |
274cfe59 | 558 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
559 | setup_APIC_timer(); |
560 | } | |
561 | ||
0e078e2f TG |
562 | void __cpuinit setup_secondary_APIC_clock(void) |
563 | { | |
0e078e2f TG |
564 | setup_APIC_timer(); |
565 | } | |
566 | ||
567 | /* | |
568 | * The guts of the apic timer interrupt | |
569 | */ | |
570 | static void local_apic_timer_interrupt(void) | |
571 | { | |
572 | int cpu = smp_processor_id(); | |
573 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
574 | ||
575 | /* | |
576 | * Normally we should not be here till LAPIC has been initialized but | |
577 | * in some cases like kdump, its possible that there is a pending LAPIC | |
578 | * timer interrupt from previous kernel's context and is delivered in | |
579 | * new kernel the moment interrupts are enabled. | |
580 | * | |
581 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
582 | * its possible that when we get here evt->event_handler is NULL. | |
583 | * Check for event_handler being NULL and discard the interrupt as | |
584 | * spurious. | |
585 | */ | |
586 | if (!evt->event_handler) { | |
587 | printk(KERN_WARNING | |
588 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
589 | /* Switch it off */ | |
590 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
591 | return; | |
592 | } | |
593 | ||
594 | /* | |
595 | * the NMI deadlock-detector uses this. | |
596 | */ | |
0b23e8cf | 597 | #ifdef CONFIG_X86_64 |
0e078e2f | 598 | add_pda(apic_timer_irqs, 1); |
0b23e8cf CG |
599 | #else |
600 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
601 | #endif | |
0e078e2f TG |
602 | |
603 | evt->event_handler(evt); | |
604 | } | |
605 | ||
606 | /* | |
607 | * Local APIC timer interrupt. This is the most natural way for doing | |
608 | * local interrupts, but local timer interrupts can be emulated by | |
609 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
610 | * | |
611 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
612 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
613 | */ | |
614 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
615 | { | |
616 | struct pt_regs *old_regs = set_irq_regs(regs); | |
617 | ||
618 | /* | |
619 | * NOTE! We'd better ACK the irq immediately, | |
620 | * because timer handling can be slow. | |
621 | */ | |
622 | ack_APIC_irq(); | |
623 | /* | |
624 | * update_process_times() expects us to have done irq_enter(). | |
625 | * Besides, if we don't timer interrupts ignore the global | |
626 | * interrupt lock, which is the WrongThing (tm) to do. | |
627 | */ | |
6460bc73 | 628 | #ifdef CONFIG_X86_64 |
0e078e2f | 629 | exit_idle(); |
6460bc73 | 630 | #endif |
0e078e2f TG |
631 | irq_enter(); |
632 | local_apic_timer_interrupt(); | |
633 | irq_exit(); | |
274cfe59 | 634 | |
0e078e2f TG |
635 | set_irq_regs(old_regs); |
636 | } | |
637 | ||
638 | int setup_profiling_timer(unsigned int multiplier) | |
639 | { | |
640 | return -EINVAL; | |
641 | } | |
642 | ||
643 | ||
644 | /* | |
645 | * Local APIC start and shutdown | |
646 | */ | |
647 | ||
648 | /** | |
649 | * clear_local_APIC - shutdown the local APIC | |
650 | * | |
651 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
652 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
653 | * leftovers during boot. | |
654 | */ | |
655 | void clear_local_APIC(void) | |
656 | { | |
2584a82d | 657 | int maxlvt; |
0e078e2f TG |
658 | u32 v; |
659 | ||
d3432896 AK |
660 | /* APIC hasn't been mapped yet */ |
661 | if (!apic_phys) | |
662 | return; | |
663 | ||
664 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
665 | /* |
666 | * Masking an LVT entry can trigger a local APIC error | |
667 | * if the vector is zero. Mask LVTERR first to prevent this. | |
668 | */ | |
669 | if (maxlvt >= 3) { | |
670 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
671 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
672 | } | |
673 | /* | |
674 | * Careful: we have to set masks only first to deassert | |
675 | * any level-triggered sources. | |
676 | */ | |
677 | v = apic_read(APIC_LVTT); | |
678 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
679 | v = apic_read(APIC_LVT0); | |
680 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
681 | v = apic_read(APIC_LVT1); | |
682 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
683 | if (maxlvt >= 4) { | |
684 | v = apic_read(APIC_LVTPC); | |
685 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
686 | } | |
687 | ||
6764014b CG |
688 | /* lets not touch this if we didn't frob it */ |
689 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
690 | if (maxlvt >= 5) { | |
691 | v = apic_read(APIC_LVTTHMR); | |
692 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
693 | } | |
694 | #endif | |
0e078e2f TG |
695 | /* |
696 | * Clean APIC state for other OSs: | |
697 | */ | |
698 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
699 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
700 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
701 | if (maxlvt >= 3) | |
702 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
703 | if (maxlvt >= 4) | |
704 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
705 | |
706 | /* Integrated APIC (!82489DX) ? */ | |
707 | if (lapic_is_integrated()) { | |
708 | if (maxlvt > 3) | |
709 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
710 | apic_write(APIC_ESR, 0); | |
711 | apic_read(APIC_ESR); | |
712 | } | |
0e078e2f TG |
713 | } |
714 | ||
715 | /** | |
716 | * disable_local_APIC - clear and disable the local APIC | |
717 | */ | |
718 | void disable_local_APIC(void) | |
719 | { | |
720 | unsigned int value; | |
721 | ||
722 | clear_local_APIC(); | |
723 | ||
724 | /* | |
725 | * Disable APIC (implies clearing of registers | |
726 | * for 82489DX!). | |
727 | */ | |
728 | value = apic_read(APIC_SPIV); | |
729 | value &= ~APIC_SPIV_APIC_ENABLED; | |
730 | apic_write(APIC_SPIV, value); | |
990b183e CG |
731 | |
732 | #ifdef CONFIG_X86_32 | |
733 | /* | |
734 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
735 | * restore the disabled state. | |
736 | */ | |
737 | if (enabled_via_apicbase) { | |
738 | unsigned int l, h; | |
739 | ||
740 | rdmsr(MSR_IA32_APICBASE, l, h); | |
741 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
742 | wrmsr(MSR_IA32_APICBASE, l, h); | |
743 | } | |
744 | #endif | |
0e078e2f TG |
745 | } |
746 | ||
fe4024dc CG |
747 | /* |
748 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
749 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
750 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
751 | * for the case where Linux didn't enable the LAPIC. | |
752 | */ | |
0e078e2f TG |
753 | void lapic_shutdown(void) |
754 | { | |
755 | unsigned long flags; | |
756 | ||
757 | if (!cpu_has_apic) | |
758 | return; | |
759 | ||
760 | local_irq_save(flags); | |
761 | ||
fe4024dc CG |
762 | #ifdef CONFIG_X86_32 |
763 | if (!enabled_via_apicbase) | |
764 | clear_local_APIC(); | |
765 | else | |
766 | #endif | |
767 | disable_local_APIC(); | |
768 | ||
0e078e2f TG |
769 | |
770 | local_irq_restore(flags); | |
771 | } | |
772 | ||
773 | /* | |
774 | * This is to verify that we're looking at a real local APIC. | |
775 | * Check these against your board if the CPUs aren't getting | |
776 | * started for no apparent reason. | |
777 | */ | |
778 | int __init verify_local_APIC(void) | |
779 | { | |
780 | unsigned int reg0, reg1; | |
781 | ||
782 | /* | |
783 | * The version register is read-only in a real APIC. | |
784 | */ | |
785 | reg0 = apic_read(APIC_LVR); | |
786 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
787 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
788 | reg1 = apic_read(APIC_LVR); | |
789 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
790 | ||
791 | /* | |
792 | * The two version reads above should print the same | |
793 | * numbers. If the second one is different, then we | |
794 | * poke at a non-APIC. | |
795 | */ | |
796 | if (reg1 != reg0) | |
797 | return 0; | |
798 | ||
799 | /* | |
800 | * Check if the version looks reasonably. | |
801 | */ | |
802 | reg1 = GET_APIC_VERSION(reg0); | |
803 | if (reg1 == 0x00 || reg1 == 0xff) | |
804 | return 0; | |
805 | reg1 = lapic_get_maxlvt(); | |
806 | if (reg1 < 0x02 || reg1 == 0xff) | |
807 | return 0; | |
808 | ||
809 | /* | |
810 | * The ID register is read/write in a real APIC. | |
811 | */ | |
2d7a66d0 | 812 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
813 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
814 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 815 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
816 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
817 | apic_write(APIC_ID, reg0); | |
818 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
819 | return 0; | |
820 | ||
821 | /* | |
1da177e4 LT |
822 | * The next two are just to see if we have sane values. |
823 | * They're only really relevant if we're in Virtual Wire | |
824 | * compatibility mode, but most boxes are anymore. | |
825 | */ | |
826 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 827 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
828 | reg1 = apic_read(APIC_LVT1); |
829 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
830 | ||
831 | return 1; | |
832 | } | |
833 | ||
0e078e2f TG |
834 | /** |
835 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
836 | */ | |
1da177e4 LT |
837 | void __init sync_Arb_IDs(void) |
838 | { | |
296cb951 CG |
839 | /* |
840 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
841 | * needed on AMD. | |
842 | */ | |
843 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
844 | return; |
845 | ||
846 | /* | |
847 | * Wait for idle. | |
848 | */ | |
849 | apic_wait_icr_idle(); | |
850 | ||
851 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
852 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
853 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
854 | } |
855 | ||
1da177e4 LT |
856 | /* |
857 | * An initial setup of the virtual wire mode. | |
858 | */ | |
859 | void __init init_bsp_APIC(void) | |
860 | { | |
11a8e778 | 861 | unsigned int value; |
1da177e4 LT |
862 | |
863 | /* | |
864 | * Don't do the setup now if we have a SMP BIOS as the | |
865 | * through-I/O-APIC virtual wire mode might be active. | |
866 | */ | |
867 | if (smp_found_config || !cpu_has_apic) | |
868 | return; | |
869 | ||
1da177e4 LT |
870 | /* |
871 | * Do not trust the local APIC being empty at bootup. | |
872 | */ | |
873 | clear_local_APIC(); | |
874 | ||
875 | /* | |
876 | * Enable APIC. | |
877 | */ | |
878 | value = apic_read(APIC_SPIV); | |
879 | value &= ~APIC_VECTOR_MASK; | |
880 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
881 | |
882 | #ifdef CONFIG_X86_32 | |
883 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
884 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
885 | (boot_cpu_data.x86 == 15)) | |
886 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
887 | else | |
888 | #endif | |
889 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 890 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 891 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
892 | |
893 | /* | |
894 | * Set up the virtual wire mode. | |
895 | */ | |
11a8e778 | 896 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 897 | value = APIC_DM_NMI; |
638c0411 CG |
898 | if (!lapic_is_integrated()) /* 82489DX */ |
899 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 900 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
901 | } |
902 | ||
c43da2f5 CG |
903 | static void __cpuinit lapic_setup_esr(void) |
904 | { | |
905 | unsigned long oldvalue, value, maxlvt; | |
906 | if (lapic_is_integrated() && !esr_disable) { | |
907 | if (esr_disable) { | |
908 | /* | |
909 | * Something untraceable is creating bad interrupts on | |
910 | * secondary quads ... for the moment, just leave the | |
911 | * ESR disabled - we can't do anything useful with the | |
912 | * errors anyway - mbligh | |
913 | */ | |
914 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
915 | return; | |
916 | } | |
917 | /* !82489DX */ | |
918 | maxlvt = lapic_get_maxlvt(); | |
919 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
920 | apic_write(APIC_ESR, 0); | |
921 | oldvalue = apic_read(APIC_ESR); | |
922 | ||
923 | /* enables sending errors */ | |
924 | value = ERROR_APIC_VECTOR; | |
925 | apic_write(APIC_LVTERR, value); | |
926 | /* | |
927 | * spec says clear errors after enabling vector. | |
928 | */ | |
929 | if (maxlvt > 3) | |
930 | apic_write(APIC_ESR, 0); | |
931 | value = apic_read(APIC_ESR); | |
932 | if (value != oldvalue) | |
933 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
934 | "vector: 0x%08lx after: 0x%08lx\n", | |
935 | oldvalue, value); | |
936 | } else { | |
937 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
938 | } | |
939 | } | |
940 | ||
941 | ||
0e078e2f TG |
942 | /** |
943 | * setup_local_APIC - setup the local APIC | |
944 | */ | |
945 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 946 | { |
739f33b3 | 947 | unsigned int value; |
da7ed9f9 | 948 | int i, j; |
1da177e4 | 949 | |
89c38c28 CG |
950 | #ifdef CONFIG_X86_32 |
951 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
952 | if (esr_disable) { | |
953 | apic_write(APIC_ESR, 0); | |
954 | apic_write(APIC_ESR, 0); | |
955 | apic_write(APIC_ESR, 0); | |
956 | apic_write(APIC_ESR, 0); | |
957 | } | |
958 | #endif | |
959 | ||
ac23d4ee | 960 | preempt_disable(); |
1da177e4 | 961 | |
1da177e4 LT |
962 | /* |
963 | * Double-check whether this APIC is really registered. | |
964 | * This is meaningless in clustered apic mode, so we skip it. | |
965 | */ | |
966 | if (!apic_id_registered()) | |
967 | BUG(); | |
968 | ||
969 | /* | |
970 | * Intel recommends to set DFR, LDR and TPR before enabling | |
971 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
972 | * document number 292116). So here it goes... | |
973 | */ | |
974 | init_apic_ldr(); | |
975 | ||
976 | /* | |
977 | * Set Task Priority to 'accept all'. We never change this | |
978 | * later on. | |
979 | */ | |
980 | value = apic_read(APIC_TASKPRI); | |
981 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 982 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 983 | |
da7ed9f9 VG |
984 | /* |
985 | * After a crash, we no longer service the interrupts and a pending | |
986 | * interrupt from previous kernel might still have ISR bit set. | |
987 | * | |
988 | * Most probably by now CPU has serviced that pending interrupt and | |
989 | * it might not have done the ack_APIC_irq() because it thought, | |
990 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
991 | * does not clear the ISR bit and cpu thinks it has already serivced | |
992 | * the interrupt. Hence a vector might get locked. It was noticed | |
993 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
994 | */ | |
995 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
996 | value = apic_read(APIC_ISR + i*0x10); | |
997 | for (j = 31; j >= 0; j--) { | |
998 | if (value & (1<<j)) | |
999 | ack_APIC_irq(); | |
1000 | } | |
1001 | } | |
1002 | ||
1da177e4 LT |
1003 | /* |
1004 | * Now that we are all set up, enable the APIC | |
1005 | */ | |
1006 | value = apic_read(APIC_SPIV); | |
1007 | value &= ~APIC_VECTOR_MASK; | |
1008 | /* | |
1009 | * Enable APIC | |
1010 | */ | |
1011 | value |= APIC_SPIV_APIC_ENABLED; | |
1012 | ||
89c38c28 CG |
1013 | #ifdef CONFIG_X86_32 |
1014 | /* | |
1015 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1016 | * certain networking cards. If high frequency interrupts are | |
1017 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1018 | * entry is masked/unmasked at a high rate as well then sooner or | |
1019 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1020 | * from the device. If focus CPU is disabled then the hang goes | |
1021 | * away, oh well :-( | |
1022 | * | |
1023 | * [ This bug can be reproduced easily with a level-triggered | |
1024 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1025 | * BX chipset. ] | |
1026 | */ | |
1027 | /* | |
1028 | * Actually disabling the focus CPU check just makes the hang less | |
1029 | * frequent as it makes the interrupt distributon model be more | |
1030 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1031 | * See also the comment in end_level_ioapic_irq(). --macro | |
1032 | */ | |
1033 | ||
1034 | /* | |
1035 | * - enable focus processor (bit==0) | |
1036 | * - 64bit mode always use processor focus | |
1037 | * so no need to set it | |
1038 | */ | |
1039 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1040 | #endif | |
3f14c746 | 1041 | |
1da177e4 LT |
1042 | /* |
1043 | * Set spurious IRQ vector | |
1044 | */ | |
1045 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1046 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1047 | |
1048 | /* | |
1049 | * Set up LVT0, LVT1: | |
1050 | * | |
1051 | * set up through-local-APIC on the BP's LINT0. This is not | |
1052 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1053 | * we delegate interrupts to the 8259A. | |
1054 | */ | |
1055 | /* | |
1056 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1057 | */ | |
1058 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1059 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1060 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1061 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1062 | smp_processor_id()); |
1da177e4 LT |
1063 | } else { |
1064 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1065 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1066 | smp_processor_id()); |
1da177e4 | 1067 | } |
11a8e778 | 1068 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1069 | |
1070 | /* | |
1071 | * only the BP should see the LINT1 NMI signal, obviously. | |
1072 | */ | |
1073 | if (!smp_processor_id()) | |
1074 | value = APIC_DM_NMI; | |
1075 | else | |
1076 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1077 | if (!lapic_is_integrated()) /* 82489DX */ |
1078 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1079 | apic_write(APIC_LVT1, value); |
89c38c28 | 1080 | |
ac23d4ee | 1081 | preempt_enable(); |
739f33b3 | 1082 | } |
1da177e4 | 1083 | |
739f33b3 AK |
1084 | void __cpuinit end_local_APIC_setup(void) |
1085 | { | |
1086 | lapic_setup_esr(); | |
fa6b95fc CG |
1087 | |
1088 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1089 | { |
1090 | unsigned int value; | |
1091 | /* Disable the local apic timer */ | |
1092 | value = apic_read(APIC_LVTT); | |
1093 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1094 | apic_write(APIC_LVTT, value); | |
1095 | } | |
fa6b95fc CG |
1096 | #endif |
1097 | ||
f2802e7f | 1098 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1099 | apic_pm_activate(); |
1da177e4 | 1100 | } |
1da177e4 | 1101 | |
6e1cb38a SS |
1102 | void check_x2apic(void) |
1103 | { | |
1104 | int msr, msr2; | |
1105 | ||
1106 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1107 | ||
1108 | if (msr & X2APIC_ENABLE) { | |
1109 | printk("x2apic enabled by BIOS, switching to x2apic ops\n"); | |
1110 | x2apic_preenabled = x2apic = 1; | |
1111 | apic_ops = &x2apic_ops; | |
1112 | } | |
1113 | } | |
1114 | ||
1115 | void enable_x2apic(void) | |
1116 | { | |
1117 | int msr, msr2; | |
1118 | ||
1119 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1120 | if (!(msr & X2APIC_ENABLE)) { | |
1121 | printk("Enabling x2apic\n"); | |
1122 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | void enable_IR_x2apic(void) | |
1127 | { | |
1128 | #ifdef CONFIG_INTR_REMAP | |
1129 | int ret; | |
1130 | unsigned long flags; | |
1131 | ||
1132 | if (!cpu_has_x2apic) | |
1133 | return; | |
1134 | ||
1135 | if (!x2apic_preenabled && disable_x2apic) { | |
1136 | printk(KERN_INFO | |
1137 | "Skipped enabling x2apic and Interrupt-remapping " | |
1138 | "because of nox2apic\n"); | |
1139 | return; | |
1140 | } | |
1141 | ||
1142 | if (x2apic_preenabled && disable_x2apic) | |
1143 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1144 | ||
1145 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
1146 | printk(KERN_INFO | |
1147 | "Skipped enabling x2apic and Interrupt-remapping " | |
1148 | "because of skipping io-apic setup\n"); | |
1149 | return; | |
1150 | } | |
1151 | ||
1152 | ret = dmar_table_init(); | |
1153 | if (ret) { | |
1154 | printk(KERN_INFO | |
1155 | "dmar_table_init() failed with %d:\n", ret); | |
1156 | ||
1157 | if (x2apic_preenabled) | |
1158 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1159 | else | |
1160 | printk(KERN_INFO | |
1161 | "Not enabling x2apic,Intr-remapping\n"); | |
1162 | return; | |
1163 | } | |
1164 | ||
1165 | local_irq_save(flags); | |
1166 | mask_8259A(); | |
1167 | save_mask_IO_APIC_setup(); | |
1168 | ||
1169 | ret = enable_intr_remapping(1); | |
1170 | ||
1171 | if (ret && x2apic_preenabled) { | |
1172 | local_irq_restore(flags); | |
1173 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1174 | } | |
1175 | ||
1176 | if (ret) | |
1177 | goto end; | |
1178 | ||
1179 | if (!x2apic) { | |
1180 | x2apic = 1; | |
1181 | apic_ops = &x2apic_ops; | |
1182 | enable_x2apic(); | |
1183 | } | |
1184 | end: | |
1185 | if (ret) | |
1186 | /* | |
1187 | * IR enabling failed | |
1188 | */ | |
1189 | restore_IO_APIC_setup(); | |
1190 | else | |
1191 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1192 | ||
1193 | unmask_8259A(); | |
1194 | local_irq_restore(flags); | |
1195 | ||
1196 | if (!ret) { | |
1197 | if (!x2apic_preenabled) | |
1198 | printk(KERN_INFO | |
1199 | "Enabled x2apic and interrupt-remapping\n"); | |
1200 | else | |
1201 | printk(KERN_INFO | |
1202 | "Enabled Interrupt-remapping\n"); | |
1203 | } else | |
1204 | printk(KERN_ERR | |
1205 | "Failed to enable Interrupt-remapping and x2apic\n"); | |
1206 | #else | |
1207 | if (!cpu_has_x2apic) | |
1208 | return; | |
1209 | ||
1210 | if (x2apic_preenabled) | |
1211 | panic("x2apic enabled prior OS handover," | |
1212 | " enable CONFIG_INTR_REMAP"); | |
1213 | ||
1214 | printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " | |
1215 | " and x2apic\n"); | |
1216 | #endif | |
1217 | ||
1218 | return; | |
1219 | } | |
1220 | ||
1da177e4 LT |
1221 | /* |
1222 | * Detect and enable local APICs on non-SMP boards. | |
1223 | * Original code written by Keir Fraser. | |
1224 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1225 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1226 | */ |
0e078e2f | 1227 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1228 | { |
1229 | if (!cpu_has_apic) { | |
1230 | printk(KERN_INFO "No local APIC present\n"); | |
1231 | return -1; | |
1232 | } | |
1233 | ||
1234 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1235 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1236 | return 0; |
1237 | } | |
1238 | ||
8643f9d0 YL |
1239 | void __init early_init_lapic_mapping(void) |
1240 | { | |
431ee79d | 1241 | unsigned long phys_addr; |
8643f9d0 YL |
1242 | |
1243 | /* | |
1244 | * If no local APIC can be found then go out | |
1245 | * : it means there is no mpatable and MADT | |
1246 | */ | |
1247 | if (!smp_found_config) | |
1248 | return; | |
1249 | ||
431ee79d | 1250 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1251 | |
431ee79d | 1252 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1253 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1254 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1255 | |
1256 | /* | |
1257 | * Fetch the APIC ID of the BSP in case we have a | |
1258 | * default configuration (or the MP table is broken). | |
1259 | */ | |
4c9961d5 | 1260 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 YL |
1261 | } |
1262 | ||
0e078e2f TG |
1263 | /** |
1264 | * init_apic_mappings - initialize APIC mappings | |
1265 | */ | |
1da177e4 LT |
1266 | void __init init_apic_mappings(void) |
1267 | { | |
6e1cb38a | 1268 | if (x2apic) { |
4c9961d5 | 1269 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1270 | return; |
1271 | } | |
1272 | ||
1da177e4 LT |
1273 | /* |
1274 | * If no local APIC can be found then set up a fake all | |
1275 | * zeroes page to simulate the local APIC and another | |
1276 | * one for the IO-APIC. | |
1277 | */ | |
1278 | if (!smp_found_config && detect_init_APIC()) { | |
1279 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1280 | apic_phys = __pa(apic_phys); | |
1281 | } else | |
1282 | apic_phys = mp_lapic_addr; | |
1283 | ||
1284 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
1285 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
1286 | APIC_BASE, apic_phys); | |
1da177e4 LT |
1287 | |
1288 | /* | |
1289 | * Fetch the APIC ID of the BSP in case we have a | |
1290 | * default configuration (or the MP table is broken). | |
1291 | */ | |
4c9961d5 | 1292 | boot_cpu_physical_apicid = read_apic_id(); |
1da177e4 LT |
1293 | } |
1294 | ||
1295 | /* | |
0e078e2f TG |
1296 | * This initializes the IO-APIC and APIC hardware if this is |
1297 | * a UP kernel. | |
1da177e4 | 1298 | */ |
1b313f4a CG |
1299 | int apic_version[MAX_APICS]; |
1300 | ||
0e078e2f | 1301 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1302 | { |
0e078e2f TG |
1303 | if (disable_apic) { |
1304 | printk(KERN_INFO "Apic disabled\n"); | |
1305 | return -1; | |
1306 | } | |
1307 | if (!cpu_has_apic) { | |
1308 | disable_apic = 1; | |
1309 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1310 | return -1; | |
1311 | } | |
1da177e4 | 1312 | |
6e1cb38a SS |
1313 | enable_IR_x2apic(); |
1314 | setup_apic_routing(); | |
1315 | ||
0e078e2f | 1316 | verify_local_APIC(); |
1da177e4 | 1317 | |
b5841765 GC |
1318 | connect_bsp_APIC(); |
1319 | ||
b6df1b8b | 1320 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
c70dcb74 | 1321 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
1da177e4 | 1322 | |
0e078e2f | 1323 | setup_local_APIC(); |
1da177e4 | 1324 | |
739f33b3 AK |
1325 | /* |
1326 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1327 | * We need clear_IO_APIC before enabling vector on BP | |
1328 | */ | |
1329 | if (!skip_ioapic_setup && nr_ioapics) | |
1330 | enable_IO_APIC(); | |
1331 | ||
acae7d90 MR |
1332 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
1333 | localise_nmi_watchdog(); | |
739f33b3 AK |
1334 | end_local_APIC_setup(); |
1335 | ||
0e078e2f TG |
1336 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1337 | setup_IO_APIC(); | |
1338 | else | |
1339 | nr_ioapics = 0; | |
1340 | setup_boot_APIC_clock(); | |
1341 | check_nmi_watchdog(); | |
1342 | return 0; | |
1da177e4 LT |
1343 | } |
1344 | ||
1345 | /* | |
0e078e2f | 1346 | * Local APIC interrupts |
1da177e4 LT |
1347 | */ |
1348 | ||
0e078e2f TG |
1349 | /* |
1350 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1351 | */ | |
1352 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 1353 | { |
0e078e2f TG |
1354 | unsigned int v; |
1355 | exit_idle(); | |
1356 | irq_enter(); | |
1da177e4 | 1357 | /* |
0e078e2f TG |
1358 | * Check if this really is a spurious interrupt and ACK it |
1359 | * if it is a vectored one. Just in case... | |
1360 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1361 | */ |
0e078e2f TG |
1362 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1363 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1364 | ack_APIC_irq(); | |
c4d58cbd | 1365 | |
0e078e2f TG |
1366 | add_pda(irq_spurious_count, 1); |
1367 | irq_exit(); | |
1368 | } | |
1da177e4 | 1369 | |
0e078e2f TG |
1370 | /* |
1371 | * This interrupt should never happen with our APIC/SMP architecture | |
1372 | */ | |
1373 | asmlinkage void smp_error_interrupt(void) | |
1374 | { | |
1375 | unsigned int v, v1; | |
1da177e4 | 1376 | |
0e078e2f TG |
1377 | exit_idle(); |
1378 | irq_enter(); | |
1379 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1380 | v = apic_read(APIC_ESR); | |
1381 | apic_write(APIC_ESR, 0); | |
1382 | v1 = apic_read(APIC_ESR); | |
1383 | ack_APIC_irq(); | |
1384 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1385 | |
0e078e2f TG |
1386 | /* Here is what the APIC error bits mean: |
1387 | 0: Send CS error | |
1388 | 1: Receive CS error | |
1389 | 2: Send accept error | |
1390 | 3: Receive accept error | |
1391 | 4: Reserved | |
1392 | 5: Send illegal vector | |
1393 | 6: Received illegal vector | |
1394 | 7: Illegal register address | |
1395 | */ | |
1396 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1397 | smp_processor_id(), v , v1); | |
1398 | irq_exit(); | |
1da177e4 LT |
1399 | } |
1400 | ||
b5841765 | 1401 | /** |
36c9d674 CG |
1402 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1403 | */ | |
b5841765 GC |
1404 | void __init connect_bsp_APIC(void) |
1405 | { | |
36c9d674 CG |
1406 | #ifdef CONFIG_X86_32 |
1407 | if (pic_mode) { | |
1408 | /* | |
1409 | * Do not trust the local APIC being empty at bootup. | |
1410 | */ | |
1411 | clear_local_APIC(); | |
1412 | /* | |
1413 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1414 | * local APIC to INT and NMI lines. | |
1415 | */ | |
1416 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1417 | "enabling APIC mode.\n"); | |
1418 | outb(0x70, 0x22); | |
1419 | outb(0x01, 0x23); | |
1420 | } | |
1421 | #endif | |
b5841765 GC |
1422 | enable_apic_mode(); |
1423 | } | |
1424 | ||
274cfe59 CG |
1425 | /** |
1426 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1427 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1428 | * | |
1429 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1430 | * APIC is disabled. | |
1431 | */ | |
0e078e2f | 1432 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1433 | { |
1b4ee4e4 CG |
1434 | unsigned int value; |
1435 | ||
c177b0bc CG |
1436 | #ifdef CONFIG_X86_32 |
1437 | if (pic_mode) { | |
1438 | /* | |
1439 | * Put the board back into PIC mode (has an effect only on | |
1440 | * certain older boards). Note that APIC interrupts, including | |
1441 | * IPIs, won't work beyond this point! The only exception are | |
1442 | * INIT IPIs. | |
1443 | */ | |
1444 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1445 | "entering PIC mode.\n"); | |
1446 | outb(0x70, 0x22); | |
1447 | outb(0x00, 0x23); | |
1448 | return; | |
1449 | } | |
1450 | #endif | |
1451 | ||
0e078e2f | 1452 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1453 | |
0e078e2f TG |
1454 | /* For the spurious interrupt use vector F, and enable it */ |
1455 | value = apic_read(APIC_SPIV); | |
1456 | value &= ~APIC_VECTOR_MASK; | |
1457 | value |= APIC_SPIV_APIC_ENABLED; | |
1458 | value |= 0xf; | |
1459 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1460 | |
0e078e2f TG |
1461 | if (!virt_wire_setup) { |
1462 | /* | |
1463 | * For LVT0 make it edge triggered, active high, | |
1464 | * external and enabled | |
1465 | */ | |
1466 | value = apic_read(APIC_LVT0); | |
1467 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1468 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1469 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1470 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1471 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1472 | apic_write(APIC_LVT0, value); | |
1473 | } else { | |
1474 | /* Disable LVT0 */ | |
1475 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1476 | } | |
b8ce3359 | 1477 | |
c177b0bc CG |
1478 | /* |
1479 | * For LVT1 make it edge triggered, active high, | |
1480 | * nmi and enabled | |
1481 | */ | |
0e078e2f TG |
1482 | value = apic_read(APIC_LVT1); |
1483 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1484 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1485 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1486 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1487 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1488 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1489 | } |
1490 | ||
be8a5685 AS |
1491 | void __cpuinit generic_processor_info(int apicid, int version) |
1492 | { | |
1493 | int cpu; | |
1494 | cpumask_t tmp_map; | |
1495 | ||
1b313f4a CG |
1496 | /* |
1497 | * Validate version | |
1498 | */ | |
1499 | if (version == 0x0) { | |
1500 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1501 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1502 | version); | |
1503 | version = 0x10; | |
be8a5685 | 1504 | } |
1b313f4a | 1505 | apic_version[apicid] = version; |
be8a5685 | 1506 | |
be8a5685 AS |
1507 | if (num_processors >= NR_CPUS) { |
1508 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1b313f4a | 1509 | " Processor ignored.\n", NR_CPUS); |
be8a5685 AS |
1510 | return; |
1511 | } | |
1512 | ||
1513 | num_processors++; | |
1514 | cpus_complement(tmp_map, cpu_present_map); | |
1515 | cpu = first_cpu(tmp_map); | |
1516 | ||
1517 | physid_set(apicid, phys_cpu_present_map); | |
1518 | if (apicid == boot_cpu_physical_apicid) { | |
1519 | /* | |
1520 | * x86_bios_cpu_apicid is required to have processors listed | |
1521 | * in same order as logical cpu numbers. Hence the first | |
1522 | * entry is BSP, and so on. | |
1523 | */ | |
1524 | cpu = 0; | |
1525 | } | |
e0da3364 YL |
1526 | if (apicid > max_physical_apicid) |
1527 | max_physical_apicid = apicid; | |
1528 | ||
1b313f4a CG |
1529 | #ifdef CONFIG_X86_32 |
1530 | /* | |
1531 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1532 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1533 | * before this can be done without some confusion. | |
1534 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1535 | * - Ashok Raj <ashok.raj@intel.com> | |
1536 | */ | |
1537 | if (max_physical_apicid >= 8) { | |
1538 | switch (boot_cpu_data.x86_vendor) { | |
1539 | case X86_VENDOR_INTEL: | |
1540 | if (!APIC_XAPIC(version)) { | |
1541 | def_to_bigsmp = 0; | |
1542 | break; | |
1543 | } | |
1544 | /* If P4 and above fall through */ | |
1545 | case X86_VENDOR_AMD: | |
1546 | def_to_bigsmp = 1; | |
1547 | } | |
1548 | } | |
1549 | #endif | |
1550 | ||
1551 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
be8a5685 | 1552 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1553 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1554 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1555 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1556 | |
1557 | cpu_to_apicid[cpu] = apicid; | |
1558 | bios_cpu_apicid[cpu] = apicid; | |
1559 | } else { | |
1560 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1561 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1562 | } | |
1b313f4a | 1563 | #endif |
be8a5685 AS |
1564 | |
1565 | cpu_set(cpu, cpu_possible_map); | |
1566 | cpu_set(cpu, cpu_present_map); | |
1567 | } | |
1568 | ||
0c81c746 SS |
1569 | int hard_smp_processor_id(void) |
1570 | { | |
1571 | return read_apic_id(); | |
1572 | } | |
1573 | ||
89039b37 | 1574 | /* |
0e078e2f | 1575 | * Power management |
89039b37 | 1576 | */ |
0e078e2f TG |
1577 | #ifdef CONFIG_PM |
1578 | ||
1579 | static struct { | |
274cfe59 CG |
1580 | /* |
1581 | * 'active' is true if the local APIC was enabled by us and | |
1582 | * not the BIOS; this signifies that we are also responsible | |
1583 | * for disabling it before entering apm/acpi suspend | |
1584 | */ | |
0e078e2f TG |
1585 | int active; |
1586 | /* r/w apic fields */ | |
1587 | unsigned int apic_id; | |
1588 | unsigned int apic_taskpri; | |
1589 | unsigned int apic_ldr; | |
1590 | unsigned int apic_dfr; | |
1591 | unsigned int apic_spiv; | |
1592 | unsigned int apic_lvtt; | |
1593 | unsigned int apic_lvtpc; | |
1594 | unsigned int apic_lvt0; | |
1595 | unsigned int apic_lvt1; | |
1596 | unsigned int apic_lvterr; | |
1597 | unsigned int apic_tmict; | |
1598 | unsigned int apic_tdcr; | |
1599 | unsigned int apic_thmr; | |
1600 | } apic_pm_state; | |
1601 | ||
1602 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1603 | { | |
1604 | unsigned long flags; | |
1605 | int maxlvt; | |
89039b37 | 1606 | |
0e078e2f TG |
1607 | if (!apic_pm_state.active) |
1608 | return 0; | |
89039b37 | 1609 | |
0e078e2f | 1610 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1611 | |
2d7a66d0 | 1612 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1613 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1614 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1615 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1616 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1617 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1618 | if (maxlvt >= 4) | |
1619 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1620 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1621 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1622 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1623 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1624 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1625 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1626 | if (maxlvt >= 5) |
1627 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1628 | #endif | |
24968cfd | 1629 | |
0e078e2f TG |
1630 | local_irq_save(flags); |
1631 | disable_local_APIC(); | |
1632 | local_irq_restore(flags); | |
1633 | return 0; | |
1da177e4 LT |
1634 | } |
1635 | ||
0e078e2f | 1636 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1637 | { |
0e078e2f TG |
1638 | unsigned int l, h; |
1639 | unsigned long flags; | |
1640 | int maxlvt; | |
1da177e4 | 1641 | |
0e078e2f TG |
1642 | if (!apic_pm_state.active) |
1643 | return 0; | |
89b831ef | 1644 | |
0e078e2f | 1645 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1646 | |
0e078e2f | 1647 | local_irq_save(flags); |
92206c90 CG |
1648 | |
1649 | #ifdef CONFIG_X86_64 | |
1650 | if (x2apic) | |
1651 | enable_x2apic(); | |
1652 | else | |
1653 | #endif | |
d5e629a6 | 1654 | { |
92206c90 CG |
1655 | /* |
1656 | * Make sure the APICBASE points to the right address | |
1657 | * | |
1658 | * FIXME! This will be wrong if we ever support suspend on | |
1659 | * SMP! We'll need to do this as part of the CPU restore! | |
1660 | */ | |
6e1cb38a SS |
1661 | rdmsr(MSR_IA32_APICBASE, l, h); |
1662 | l &= ~MSR_IA32_APICBASE_BASE; | |
1663 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1664 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 1665 | } |
6e1cb38a | 1666 | |
0e078e2f TG |
1667 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
1668 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1669 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1670 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1671 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1672 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1673 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1674 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 1675 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1676 | if (maxlvt >= 5) |
1677 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1678 | #endif | |
1679 | if (maxlvt >= 4) | |
1680 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1681 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1682 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1683 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1684 | apic_write(APIC_ESR, 0); | |
1685 | apic_read(APIC_ESR); | |
1686 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1687 | apic_write(APIC_ESR, 0); | |
1688 | apic_read(APIC_ESR); | |
92206c90 | 1689 | |
0e078e2f | 1690 | local_irq_restore(flags); |
92206c90 | 1691 | |
0e078e2f TG |
1692 | return 0; |
1693 | } | |
b8ce3359 | 1694 | |
274cfe59 CG |
1695 | /* |
1696 | * This device has no shutdown method - fully functioning local APICs | |
1697 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1698 | */ | |
1699 | ||
0e078e2f TG |
1700 | static struct sysdev_class lapic_sysclass = { |
1701 | .name = "lapic", | |
1702 | .resume = lapic_resume, | |
1703 | .suspend = lapic_suspend, | |
1704 | }; | |
b8ce3359 | 1705 | |
0e078e2f | 1706 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1707 | .id = 0, |
1708 | .cls = &lapic_sysclass, | |
0e078e2f | 1709 | }; |
b8ce3359 | 1710 | |
0e078e2f TG |
1711 | static void __cpuinit apic_pm_activate(void) |
1712 | { | |
1713 | apic_pm_state.active = 1; | |
1da177e4 LT |
1714 | } |
1715 | ||
0e078e2f | 1716 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1717 | { |
0e078e2f | 1718 | int error; |
e83a5fdc | 1719 | |
0e078e2f TG |
1720 | if (!cpu_has_apic) |
1721 | return 0; | |
1722 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1723 | |
0e078e2f TG |
1724 | error = sysdev_class_register(&lapic_sysclass); |
1725 | if (!error) | |
1726 | error = sysdev_register(&device_lapic); | |
1727 | return error; | |
1da177e4 | 1728 | } |
0e078e2f TG |
1729 | device_initcall(init_lapic_sysfs); |
1730 | ||
1731 | #else /* CONFIG_PM */ | |
1732 | ||
1733 | static void apic_pm_activate(void) { } | |
1734 | ||
1735 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1736 | |
1737 | /* | |
f8bf3c65 | 1738 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1739 | * |
1740 | * Thus far, the major user of this is IBM's Summit2 series: | |
1741 | * | |
637029c6 | 1742 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1743 | * multi-chassis. Use available data to take a good guess. |
1744 | * If in doubt, go HPET. | |
1745 | */ | |
f8bf3c65 | 1746 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1747 | { |
1748 | int i, clusters, zeros; | |
1749 | unsigned id; | |
322850af | 1750 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1751 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1752 | ||
322850af YL |
1753 | /* |
1754 | * there is not this kind of box with AMD CPU yet. | |
1755 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1756 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1757 | * vsmp box still need checking... |
322850af | 1758 | */ |
1cb68487 | 1759 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1760 | return 0; |
1761 | ||
23ca4bba | 1762 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 1763 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1764 | |
1765 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1766 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1767 | if (bios_cpu_apicid) { |
1768 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1769 | } |
1770 | else if (i < nr_cpu_ids) { | |
1771 | if (cpu_present(i)) | |
1772 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1773 | else | |
1774 | continue; | |
1775 | } | |
1776 | else | |
1777 | break; | |
1778 | ||
1da177e4 LT |
1779 | if (id != BAD_APICID) |
1780 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1781 | } | |
1782 | ||
1783 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1784 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1785 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1786 | * Since clusters are allocated sequentially, count zeros only if | |
1787 | * they are bounded by ones. | |
1da177e4 LT |
1788 | */ |
1789 | clusters = 0; | |
1790 | zeros = 0; | |
1791 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1792 | if (test_bit(i, clustermap)) { | |
1793 | clusters += 1 + zeros; | |
1794 | zeros = 0; | |
1795 | } else | |
1796 | ++zeros; | |
1797 | } | |
1798 | ||
1cb68487 RT |
1799 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1800 | * not guaranteed to be synced between boards | |
1801 | */ | |
1802 | if (is_vsmp_box() && clusters > 1) | |
1803 | return 1; | |
1804 | ||
1da177e4 | 1805 | /* |
f8bf3c65 | 1806 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1807 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1808 | * out, but AFAIK this will work even for them. | |
1809 | */ | |
1810 | return (clusters > 2); | |
1811 | } | |
1812 | ||
6e1cb38a | 1813 | static __init int setup_nox2apic(char *str) |
1da177e4 | 1814 | { |
6e1cb38a SS |
1815 | disable_x2apic = 1; |
1816 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC); | |
1da177e4 LT |
1817 | return 0; |
1818 | } | |
6e1cb38a | 1819 | early_param("nox2apic", setup_nox2apic); |
1da177e4 | 1820 | |
1da177e4 | 1821 | |
1da177e4 | 1822 | /* |
0e078e2f | 1823 | * APIC command line parameters |
1da177e4 | 1824 | */ |
789fa735 | 1825 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 1826 | { |
1da177e4 | 1827 | disable_apic = 1; |
9175fc06 | 1828 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
1829 | return 0; |
1830 | } | |
1831 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1832 | |
2c8c0e6b | 1833 | /* same as disableapic, for compatibility */ |
789fa735 | 1834 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 1835 | { |
789fa735 | 1836 | return setup_disableapic(arg); |
6935d1f9 | 1837 | } |
2c8c0e6b | 1838 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1839 | |
2e7c2838 LT |
1840 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1841 | { | |
1842 | local_apic_timer_c2_ok = 1; | |
1843 | return 0; | |
1844 | } | |
1845 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1846 | ||
36fef094 | 1847 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 1848 | { |
1da177e4 | 1849 | disable_apic_timer = 1; |
36fef094 | 1850 | return 0; |
6935d1f9 | 1851 | } |
36fef094 CG |
1852 | early_param("noapictimer", parse_disable_apic_timer); |
1853 | ||
1854 | static int __init parse_nolapic_timer(char *arg) | |
1855 | { | |
1856 | disable_apic_timer = 1; | |
1857 | return 0; | |
6935d1f9 | 1858 | } |
36fef094 | 1859 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 1860 | |
920fa7a5 | 1861 | #ifdef CONFIG_X86_64 |
0c3749c4 AK |
1862 | static __init int setup_apicpmtimer(char *s) |
1863 | { | |
1864 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1865 | notsc_setup(NULL); |
b8ce3359 | 1866 | return 0; |
0c3749c4 AK |
1867 | } |
1868 | __setup("apicpmtimer", setup_apicpmtimer); | |
920fa7a5 | 1869 | #endif |
0c3749c4 | 1870 | |
79af9bec CG |
1871 | static int __init apic_set_verbosity(char *arg) |
1872 | { | |
1873 | if (!arg) { | |
1874 | #ifdef CONFIG_X86_64 | |
1875 | skip_ioapic_setup = 0; | |
79af9bec CG |
1876 | return 0; |
1877 | #endif | |
1878 | return -EINVAL; | |
1879 | } | |
1880 | ||
1881 | if (strcmp("debug", arg) == 0) | |
1882 | apic_verbosity = APIC_DEBUG; | |
1883 | else if (strcmp("verbose", arg) == 0) | |
1884 | apic_verbosity = APIC_VERBOSE; | |
1885 | else { | |
1886 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1887 | " use apic=verbose or apic=debug\n", arg); | |
1888 | return -EINVAL; | |
1889 | } | |
1890 | ||
1891 | return 0; | |
1892 | } | |
1893 | early_param("apic", apic_set_verbosity); | |
1894 | ||
1e934dda YL |
1895 | static int __init lapic_insert_resource(void) |
1896 | { | |
1897 | if (!apic_phys) | |
1898 | return -1; | |
1899 | ||
1900 | /* Put local APIC into the resource map. */ | |
1901 | lapic_resource.start = apic_phys; | |
1902 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1903 | insert_resource(&iomem_resource, &lapic_resource); | |
1904 | ||
1905 | return 0; | |
1906 | } | |
1907 | ||
1908 | /* | |
1909 | * need call insert after e820_reserve_resources() | |
1910 | * that is using request_resource | |
1911 | */ | |
1912 | late_initcall(lapic_insert_resource); |