Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
6e1cb38a | 30 | #include <linux/dmar.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
e83a5fdc | 36 | #include <asm/hpet.h> |
1da177e4 | 37 | #include <asm/pgalloc.h> |
75152114 | 38 | #include <asm/nmi.h> |
95833c83 | 39 | #include <asm/idle.h> |
73dea47f AK |
40 | #include <asm/proto.h> |
41 | #include <asm/timex.h> | |
2c8c0e6b | 42 | #include <asm/apic.h> |
6e1cb38a | 43 | #include <asm/i8259.h> |
1da177e4 | 44 | |
5af5573e | 45 | #include <mach_ipi.h> |
dd46e3ca | 46 | #include <mach_apic.h> |
5af5573e | 47 | |
aa276e1c | 48 | static int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 49 | static int apic_calibrate_pmtmr __initdata; |
0e078e2f | 50 | int disable_apic; |
6e1cb38a | 51 | int disable_x2apic; |
89027d35 | 52 | int x2apic; |
1da177e4 | 53 | |
6e1cb38a SS |
54 | /* x2apic enabled before OS handover */ |
55 | int x2apic_preenabled; | |
56 | ||
e83a5fdc | 57 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
58 | int local_apic_timer_c2_ok; |
59 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
60 | ||
e83a5fdc HS |
61 | /* |
62 | * Debug level, exported for io_apic.c | |
63 | */ | |
64 | int apic_verbosity; | |
65 | ||
bab4b27c AS |
66 | /* Have we found an MP table */ |
67 | int smp_found_config; | |
68 | ||
39928722 AD |
69 | static struct resource lapic_resource = { |
70 | .name = "Local APIC", | |
71 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
72 | }; | |
73 | ||
d03030e9 TG |
74 | static unsigned int calibration_result; |
75 | ||
ba7eda4c TG |
76 | static int lapic_next_event(unsigned long delta, |
77 | struct clock_event_device *evt); | |
78 | static void lapic_timer_setup(enum clock_event_mode mode, | |
79 | struct clock_event_device *evt); | |
ba7eda4c | 80 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 81 | static void apic_pm_activate(void); |
ba7eda4c TG |
82 | |
83 | static struct clock_event_device lapic_clockevent = { | |
84 | .name = "lapic", | |
85 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
86 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
87 | .shift = 32, | |
88 | .set_mode = lapic_timer_setup, | |
89 | .set_next_event = lapic_next_event, | |
90 | .broadcast = lapic_timer_broadcast, | |
91 | .rating = 100, | |
92 | .irq = -1, | |
93 | }; | |
94 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
95 | ||
d3432896 AK |
96 | static unsigned long apic_phys; |
97 | ||
3f530709 AS |
98 | unsigned long mp_lapic_addr; |
99 | ||
be8a5685 | 100 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
0e078e2f TG |
101 | /* |
102 | * Get the LAPIC version | |
103 | */ | |
104 | static inline int lapic_get_version(void) | |
ba7eda4c | 105 | { |
0e078e2f | 106 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
107 | } |
108 | ||
0e078e2f TG |
109 | /* |
110 | * Check, if the APIC is integrated or a seperate chip | |
111 | */ | |
112 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 113 | { |
0e078e2f | 114 | return 1; |
ba7eda4c TG |
115 | } |
116 | ||
117 | /* | |
0e078e2f | 118 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 119 | */ |
0e078e2f | 120 | static int modern_apic(void) |
ba7eda4c | 121 | { |
0e078e2f TG |
122 | /* AMD systems use old APIC versions, so check the CPU */ |
123 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
124 | boot_cpu_data.x86 >= 0xf) | |
125 | return 1; | |
126 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
127 | } |
128 | ||
1b374e4d | 129 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
130 | { |
131 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
132 | cpu_relax(); | |
133 | } | |
134 | ||
1b374e4d | 135 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 136 | { |
3c6bb07a | 137 | u32 send_status; |
8339e9fb FLV |
138 | int timeout; |
139 | ||
140 | timeout = 0; | |
141 | do { | |
142 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
143 | if (!send_status) | |
144 | break; | |
145 | udelay(100); | |
146 | } while (timeout++ < 1000); | |
147 | ||
148 | return send_status; | |
149 | } | |
150 | ||
1b374e4d SS |
151 | void xapic_icr_write(u32 low, u32 id) |
152 | { | |
153 | apic_write(APIC_ICR2, id << 24); | |
154 | apic_write(APIC_ICR, low); | |
155 | } | |
156 | ||
157 | u64 xapic_icr_read(void) | |
158 | { | |
159 | u32 icr1, icr2; | |
160 | ||
161 | icr2 = apic_read(APIC_ICR2); | |
162 | icr1 = apic_read(APIC_ICR); | |
163 | ||
164 | return (icr1 | ((u64)icr2 << 32)); | |
165 | } | |
166 | ||
167 | static struct apic_ops xapic_ops = { | |
168 | .read = native_apic_mem_read, | |
169 | .write = native_apic_mem_write, | |
170 | .write_atomic = native_apic_mem_write_atomic, | |
171 | .icr_read = xapic_icr_read, | |
172 | .icr_write = xapic_icr_write, | |
173 | .wait_icr_idle = xapic_wait_icr_idle, | |
174 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
175 | }; | |
176 | ||
177 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
178 | ||
179 | EXPORT_SYMBOL_GPL(apic_ops); | |
180 | ||
13c88fb5 SS |
181 | static void x2apic_wait_icr_idle(void) |
182 | { | |
183 | /* no need to wait for icr idle in x2apic */ | |
184 | return; | |
185 | } | |
186 | ||
187 | static u32 safe_x2apic_wait_icr_idle(void) | |
188 | { | |
189 | /* no need to wait for icr idle in x2apic */ | |
190 | return 0; | |
191 | } | |
192 | ||
193 | void x2apic_icr_write(u32 low, u32 id) | |
194 | { | |
195 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
196 | } | |
197 | ||
198 | u64 x2apic_icr_read(void) | |
199 | { | |
200 | unsigned long val; | |
201 | ||
202 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
203 | return val; | |
204 | } | |
205 | ||
206 | static struct apic_ops x2apic_ops = { | |
207 | .read = native_apic_msr_read, | |
208 | .write = native_apic_msr_write, | |
209 | .write_atomic = native_apic_msr_write, | |
210 | .icr_read = x2apic_icr_read, | |
211 | .icr_write = x2apic_icr_write, | |
212 | .wait_icr_idle = x2apic_wait_icr_idle, | |
213 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
214 | }; | |
215 | ||
0e078e2f TG |
216 | /** |
217 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
218 | */ | |
e9427101 | 219 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 220 | { |
11a8e778 | 221 | unsigned int v; |
6935d1f9 TG |
222 | |
223 | /* unmask and set to NMI */ | |
224 | v = APIC_DM_NMI; | |
11a8e778 | 225 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
226 | } |
227 | ||
0e078e2f TG |
228 | /** |
229 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
230 | */ | |
37e650c7 | 231 | int lapic_get_maxlvt(void) |
1da177e4 | 232 | { |
11a8e778 | 233 | unsigned int v, maxlvt; |
1da177e4 LT |
234 | |
235 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
236 | maxlvt = GET_APIC_MAXLVT(v); |
237 | return maxlvt; | |
238 | } | |
239 | ||
0e078e2f TG |
240 | /* |
241 | * This function sets up the local APIC timer, with a timeout of | |
242 | * 'clocks' APIC bus clock. During calibration we actually call | |
243 | * this function twice on the boot CPU, once with a bogus timeout | |
244 | * value, second time for real. The other (noncalibrating) CPUs | |
245 | * call this function only once, with the real, calibrated value. | |
246 | * | |
247 | * We do reads before writes even if unnecessary, to get around the | |
248 | * P5 APIC double write bug. | |
249 | */ | |
250 | ||
251 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) | |
1da177e4 | 252 | { |
0e078e2f | 253 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 254 | |
0e078e2f TG |
255 | lvtt_value = LOCAL_TIMER_VECTOR; |
256 | if (!oneshot) | |
257 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
258 | if (!irqen) | |
259 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 260 | |
0e078e2f | 261 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
262 | |
263 | /* | |
0e078e2f | 264 | * Divide PICLK by 16 |
1da177e4 | 265 | */ |
0e078e2f TG |
266 | tmp_value = apic_read(APIC_TDCR); |
267 | apic_write(APIC_TDCR, (tmp_value | |
268 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
269 | | APIC_TDR_DIV_16); | |
270 | ||
271 | if (!oneshot) | |
272 | apic_write(APIC_TMICT, clocks); | |
1da177e4 LT |
273 | } |
274 | ||
0e078e2f | 275 | /* |
7b83dae7 RR |
276 | * Setup extended LVT, AMD specific (K8, family 10h) |
277 | * | |
278 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
279 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
0e078e2f | 280 | */ |
7b83dae7 RR |
281 | |
282 | #define APIC_EILVT_LVTOFF_MCE 0 | |
283 | #define APIC_EILVT_LVTOFF_IBS 1 | |
284 | ||
285 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 286 | { |
7b83dae7 | 287 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 288 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 289 | |
0e078e2f | 290 | apic_write(reg, v); |
1da177e4 LT |
291 | } |
292 | ||
7b83dae7 RR |
293 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
294 | { | |
295 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
296 | return APIC_EILVT_LVTOFF_MCE; | |
297 | } | |
298 | ||
299 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
300 | { | |
301 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
302 | return APIC_EILVT_LVTOFF_IBS; | |
303 | } | |
304 | ||
0e078e2f TG |
305 | /* |
306 | * Program the next event, relative to now | |
307 | */ | |
308 | static int lapic_next_event(unsigned long delta, | |
309 | struct clock_event_device *evt) | |
1da177e4 | 310 | { |
0e078e2f TG |
311 | apic_write(APIC_TMICT, delta); |
312 | return 0; | |
1da177e4 LT |
313 | } |
314 | ||
0e078e2f TG |
315 | /* |
316 | * Setup the lapic timer in periodic or oneshot mode | |
317 | */ | |
318 | static void lapic_timer_setup(enum clock_event_mode mode, | |
319 | struct clock_event_device *evt) | |
9b7711f0 HS |
320 | { |
321 | unsigned long flags; | |
0e078e2f | 322 | unsigned int v; |
9b7711f0 | 323 | |
0e078e2f TG |
324 | /* Lapic used as dummy for broadcast ? */ |
325 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
326 | return; |
327 | ||
328 | local_irq_save(flags); | |
329 | ||
0e078e2f TG |
330 | switch (mode) { |
331 | case CLOCK_EVT_MODE_PERIODIC: | |
332 | case CLOCK_EVT_MODE_ONESHOT: | |
333 | __setup_APIC_LVTT(calibration_result, | |
334 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
335 | break; | |
336 | case CLOCK_EVT_MODE_UNUSED: | |
337 | case CLOCK_EVT_MODE_SHUTDOWN: | |
338 | v = apic_read(APIC_LVTT); | |
339 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
340 | apic_write(APIC_LVTT, v); | |
341 | break; | |
342 | case CLOCK_EVT_MODE_RESUME: | |
343 | /* Nothing to do here */ | |
344 | break; | |
345 | } | |
9b7711f0 HS |
346 | |
347 | local_irq_restore(flags); | |
348 | } | |
349 | ||
1da177e4 | 350 | /* |
0e078e2f | 351 | * Local APIC timer broadcast function |
1da177e4 | 352 | */ |
0e078e2f | 353 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 354 | { |
0e078e2f TG |
355 | #ifdef CONFIG_SMP |
356 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
357 | #endif | |
358 | } | |
1da177e4 | 359 | |
0e078e2f TG |
360 | /* |
361 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
362 | * of the boot CPU and register the clock event in the framework. | |
363 | */ | |
364 | static void setup_APIC_timer(void) | |
365 | { | |
366 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 367 | |
0e078e2f TG |
368 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
369 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 370 | |
0e078e2f TG |
371 | clockevents_register_device(levt); |
372 | } | |
1da177e4 | 373 | |
0e078e2f TG |
374 | /* |
375 | * In this function we calibrate APIC bus clocks to the external | |
376 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
377 | * to calibrate, since some later bootup code depends on getting | |
378 | * the first irq? Ugh. | |
379 | * | |
380 | * We want to do the calibration only once since we | |
381 | * want to have local timer irqs syncron. CPUs connected | |
382 | * by the same APIC bus have the very same bus frequency. | |
383 | * And we want to have irqs off anyways, no accidental | |
384 | * APIC irq that way. | |
385 | */ | |
386 | ||
387 | #define TICK_COUNT 100000000 | |
388 | ||
389 | static void __init calibrate_APIC_clock(void) | |
390 | { | |
391 | unsigned apic, apic_start; | |
392 | unsigned long tsc, tsc_start; | |
393 | int result; | |
394 | ||
395 | local_irq_disable(); | |
396 | ||
397 | /* | |
398 | * Put whatever arbitrary (but long enough) timeout | |
399 | * value into the APIC clock, we just want to get the | |
400 | * counter running for calibration. | |
401 | * | |
402 | * No interrupt enable ! | |
403 | */ | |
404 | __setup_APIC_LVTT(250000000, 0, 0); | |
405 | ||
406 | apic_start = apic_read(APIC_TMCCT); | |
407 | #ifdef CONFIG_X86_PM_TIMER | |
408 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
409 | pmtimer_wait(5000); /* 5ms wait */ | |
410 | apic = apic_read(APIC_TMCCT); | |
411 | result = (apic_start - apic) * 1000L / 5; | |
412 | } else | |
413 | #endif | |
414 | { | |
415 | rdtscll(tsc_start); | |
416 | ||
417 | do { | |
418 | apic = apic_read(APIC_TMCCT); | |
419 | rdtscll(tsc); | |
420 | } while ((tsc - tsc_start) < TICK_COUNT && | |
421 | (apic_start - apic) < TICK_COUNT); | |
422 | ||
423 | result = (apic_start - apic) * 1000L * tsc_khz / | |
424 | (tsc - tsc_start); | |
425 | } | |
426 | ||
427 | local_irq_enable(); | |
428 | ||
429 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
430 | ||
431 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
432 | result / 1000 / 1000, result / 1000 % 1000); | |
433 | ||
434 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
435 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
436 | lapic_clockevent.shift); | |
0e078e2f TG |
437 | lapic_clockevent.max_delta_ns = |
438 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
439 | lapic_clockevent.min_delta_ns = | |
440 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
441 | ||
442 | calibration_result = result / HZ; | |
443 | } | |
444 | ||
e83a5fdc HS |
445 | /* |
446 | * Setup the boot APIC | |
447 | * | |
448 | * Calibrate and verify the result. | |
449 | */ | |
0e078e2f TG |
450 | void __init setup_boot_APIC_clock(void) |
451 | { | |
452 | /* | |
453 | * The local apic timer can be disabled via the kernel commandline. | |
454 | * Register the lapic timer as a dummy clock event source on SMP | |
455 | * systems, so the broadcast mechanism is used. On UP systems simply | |
456 | * ignore it. | |
457 | */ | |
458 | if (disable_apic_timer) { | |
459 | printk(KERN_INFO "Disabling APIC timer\n"); | |
460 | /* No broadcast on UP ! */ | |
9d09951d TG |
461 | if (num_possible_cpus() > 1) { |
462 | lapic_clockevent.mult = 1; | |
0e078e2f | 463 | setup_APIC_timer(); |
9d09951d | 464 | } |
0e078e2f TG |
465 | return; |
466 | } | |
467 | ||
468 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); | |
469 | calibrate_APIC_clock(); | |
470 | ||
c2b84b30 TG |
471 | /* |
472 | * Do a sanity check on the APIC calibration result | |
473 | */ | |
474 | if (calibration_result < (1000000 / HZ)) { | |
475 | printk(KERN_WARNING | |
476 | "APIC frequency too slow, disabling apic timer\n"); | |
477 | /* No broadcast on UP ! */ | |
478 | if (num_possible_cpus() > 1) | |
479 | setup_APIC_timer(); | |
480 | return; | |
481 | } | |
482 | ||
0e078e2f TG |
483 | /* |
484 | * If nmi_watchdog is set to IO_APIC, we need the | |
485 | * PIT/HPET going. Otherwise register lapic as a dummy | |
486 | * device. | |
487 | */ | |
488 | if (nmi_watchdog != NMI_IO_APIC) | |
489 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
490 | else | |
491 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 492 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f TG |
493 | |
494 | setup_APIC_timer(); | |
495 | } | |
496 | ||
0e078e2f TG |
497 | void __cpuinit setup_secondary_APIC_clock(void) |
498 | { | |
0e078e2f TG |
499 | setup_APIC_timer(); |
500 | } | |
501 | ||
502 | /* | |
503 | * The guts of the apic timer interrupt | |
504 | */ | |
505 | static void local_apic_timer_interrupt(void) | |
506 | { | |
507 | int cpu = smp_processor_id(); | |
508 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
509 | ||
510 | /* | |
511 | * Normally we should not be here till LAPIC has been initialized but | |
512 | * in some cases like kdump, its possible that there is a pending LAPIC | |
513 | * timer interrupt from previous kernel's context and is delivered in | |
514 | * new kernel the moment interrupts are enabled. | |
515 | * | |
516 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
517 | * its possible that when we get here evt->event_handler is NULL. | |
518 | * Check for event_handler being NULL and discard the interrupt as | |
519 | * spurious. | |
520 | */ | |
521 | if (!evt->event_handler) { | |
522 | printk(KERN_WARNING | |
523 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
524 | /* Switch it off */ | |
525 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
526 | return; | |
527 | } | |
528 | ||
529 | /* | |
530 | * the NMI deadlock-detector uses this. | |
531 | */ | |
532 | add_pda(apic_timer_irqs, 1); | |
533 | ||
534 | evt->event_handler(evt); | |
535 | } | |
536 | ||
537 | /* | |
538 | * Local APIC timer interrupt. This is the most natural way for doing | |
539 | * local interrupts, but local timer interrupts can be emulated by | |
540 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
541 | * | |
542 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
543 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
544 | */ | |
545 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
546 | { | |
547 | struct pt_regs *old_regs = set_irq_regs(regs); | |
548 | ||
549 | /* | |
550 | * NOTE! We'd better ACK the irq immediately, | |
551 | * because timer handling can be slow. | |
552 | */ | |
553 | ack_APIC_irq(); | |
554 | /* | |
555 | * update_process_times() expects us to have done irq_enter(). | |
556 | * Besides, if we don't timer interrupts ignore the global | |
557 | * interrupt lock, which is the WrongThing (tm) to do. | |
558 | */ | |
559 | exit_idle(); | |
560 | irq_enter(); | |
561 | local_apic_timer_interrupt(); | |
562 | irq_exit(); | |
563 | set_irq_regs(old_regs); | |
564 | } | |
565 | ||
566 | int setup_profiling_timer(unsigned int multiplier) | |
567 | { | |
568 | return -EINVAL; | |
569 | } | |
570 | ||
571 | ||
572 | /* | |
573 | * Local APIC start and shutdown | |
574 | */ | |
575 | ||
576 | /** | |
577 | * clear_local_APIC - shutdown the local APIC | |
578 | * | |
579 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
580 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
581 | * leftovers during boot. | |
582 | */ | |
583 | void clear_local_APIC(void) | |
584 | { | |
2584a82d | 585 | int maxlvt; |
0e078e2f TG |
586 | u32 v; |
587 | ||
d3432896 AK |
588 | /* APIC hasn't been mapped yet */ |
589 | if (!apic_phys) | |
590 | return; | |
591 | ||
592 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
593 | /* |
594 | * Masking an LVT entry can trigger a local APIC error | |
595 | * if the vector is zero. Mask LVTERR first to prevent this. | |
596 | */ | |
597 | if (maxlvt >= 3) { | |
598 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
599 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
600 | } | |
601 | /* | |
602 | * Careful: we have to set masks only first to deassert | |
603 | * any level-triggered sources. | |
604 | */ | |
605 | v = apic_read(APIC_LVTT); | |
606 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
607 | v = apic_read(APIC_LVT0); | |
608 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
609 | v = apic_read(APIC_LVT1); | |
610 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
611 | if (maxlvt >= 4) { | |
612 | v = apic_read(APIC_LVTPC); | |
613 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
614 | } | |
615 | ||
616 | /* | |
617 | * Clean APIC state for other OSs: | |
618 | */ | |
619 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
620 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
621 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
622 | if (maxlvt >= 3) | |
623 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
624 | if (maxlvt >= 4) | |
625 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
626 | apic_write(APIC_ESR, 0); | |
627 | apic_read(APIC_ESR); | |
628 | } | |
629 | ||
630 | /** | |
631 | * disable_local_APIC - clear and disable the local APIC | |
632 | */ | |
633 | void disable_local_APIC(void) | |
634 | { | |
635 | unsigned int value; | |
636 | ||
637 | clear_local_APIC(); | |
638 | ||
639 | /* | |
640 | * Disable APIC (implies clearing of registers | |
641 | * for 82489DX!). | |
642 | */ | |
643 | value = apic_read(APIC_SPIV); | |
644 | value &= ~APIC_SPIV_APIC_ENABLED; | |
645 | apic_write(APIC_SPIV, value); | |
646 | } | |
647 | ||
648 | void lapic_shutdown(void) | |
649 | { | |
650 | unsigned long flags; | |
651 | ||
652 | if (!cpu_has_apic) | |
653 | return; | |
654 | ||
655 | local_irq_save(flags); | |
656 | ||
657 | disable_local_APIC(); | |
658 | ||
659 | local_irq_restore(flags); | |
660 | } | |
661 | ||
662 | /* | |
663 | * This is to verify that we're looking at a real local APIC. | |
664 | * Check these against your board if the CPUs aren't getting | |
665 | * started for no apparent reason. | |
666 | */ | |
667 | int __init verify_local_APIC(void) | |
668 | { | |
669 | unsigned int reg0, reg1; | |
670 | ||
671 | /* | |
672 | * The version register is read-only in a real APIC. | |
673 | */ | |
674 | reg0 = apic_read(APIC_LVR); | |
675 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
676 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
677 | reg1 = apic_read(APIC_LVR); | |
678 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
679 | ||
680 | /* | |
681 | * The two version reads above should print the same | |
682 | * numbers. If the second one is different, then we | |
683 | * poke at a non-APIC. | |
684 | */ | |
685 | if (reg1 != reg0) | |
686 | return 0; | |
687 | ||
688 | /* | |
689 | * Check if the version looks reasonably. | |
690 | */ | |
691 | reg1 = GET_APIC_VERSION(reg0); | |
692 | if (reg1 == 0x00 || reg1 == 0xff) | |
693 | return 0; | |
694 | reg1 = lapic_get_maxlvt(); | |
695 | if (reg1 < 0x02 || reg1 == 0xff) | |
696 | return 0; | |
697 | ||
698 | /* | |
699 | * The ID register is read/write in a real APIC. | |
700 | */ | |
2d7a66d0 | 701 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
702 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
703 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 704 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
705 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
706 | apic_write(APIC_ID, reg0); | |
707 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
708 | return 0; | |
709 | ||
710 | /* | |
1da177e4 LT |
711 | * The next two are just to see if we have sane values. |
712 | * They're only really relevant if we're in Virtual Wire | |
713 | * compatibility mode, but most boxes are anymore. | |
714 | */ | |
715 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 716 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
717 | reg1 = apic_read(APIC_LVT1); |
718 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
719 | ||
720 | return 1; | |
721 | } | |
722 | ||
0e078e2f TG |
723 | /** |
724 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
725 | */ | |
1da177e4 LT |
726 | void __init sync_Arb_IDs(void) |
727 | { | |
728 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
0e078e2f | 729 | if (modern_apic()) |
1da177e4 LT |
730 | return; |
731 | ||
732 | /* | |
733 | * Wait for idle. | |
734 | */ | |
735 | apic_wait_icr_idle(); | |
736 | ||
737 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 738 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
739 | | APIC_DM_INIT); |
740 | } | |
741 | ||
1da177e4 LT |
742 | /* |
743 | * An initial setup of the virtual wire mode. | |
744 | */ | |
745 | void __init init_bsp_APIC(void) | |
746 | { | |
11a8e778 | 747 | unsigned int value; |
1da177e4 LT |
748 | |
749 | /* | |
750 | * Don't do the setup now if we have a SMP BIOS as the | |
751 | * through-I/O-APIC virtual wire mode might be active. | |
752 | */ | |
753 | if (smp_found_config || !cpu_has_apic) | |
754 | return; | |
755 | ||
756 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
757 | |
758 | /* | |
759 | * Do not trust the local APIC being empty at bootup. | |
760 | */ | |
761 | clear_local_APIC(); | |
762 | ||
763 | /* | |
764 | * Enable APIC. | |
765 | */ | |
766 | value = apic_read(APIC_SPIV); | |
767 | value &= ~APIC_VECTOR_MASK; | |
768 | value |= APIC_SPIV_APIC_ENABLED; | |
769 | value |= APIC_SPIV_FOCUS_DISABLED; | |
770 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 771 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
772 | |
773 | /* | |
774 | * Set up the virtual wire mode. | |
775 | */ | |
11a8e778 | 776 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 777 | value = APIC_DM_NMI; |
11a8e778 | 778 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
779 | } |
780 | ||
0e078e2f TG |
781 | /** |
782 | * setup_local_APIC - setup the local APIC | |
783 | */ | |
784 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 785 | { |
739f33b3 | 786 | unsigned int value; |
da7ed9f9 | 787 | int i, j; |
1da177e4 | 788 | |
ac23d4ee | 789 | preempt_disable(); |
1da177e4 | 790 | value = apic_read(APIC_LVR); |
1da177e4 | 791 | |
fe7414a2 | 792 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
793 | |
794 | /* | |
795 | * Double-check whether this APIC is really registered. | |
796 | * This is meaningless in clustered apic mode, so we skip it. | |
797 | */ | |
798 | if (!apic_id_registered()) | |
799 | BUG(); | |
800 | ||
801 | /* | |
802 | * Intel recommends to set DFR, LDR and TPR before enabling | |
803 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
804 | * document number 292116). So here it goes... | |
805 | */ | |
806 | init_apic_ldr(); | |
807 | ||
808 | /* | |
809 | * Set Task Priority to 'accept all'. We never change this | |
810 | * later on. | |
811 | */ | |
812 | value = apic_read(APIC_TASKPRI); | |
813 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 814 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 815 | |
da7ed9f9 VG |
816 | /* |
817 | * After a crash, we no longer service the interrupts and a pending | |
818 | * interrupt from previous kernel might still have ISR bit set. | |
819 | * | |
820 | * Most probably by now CPU has serviced that pending interrupt and | |
821 | * it might not have done the ack_APIC_irq() because it thought, | |
822 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
823 | * does not clear the ISR bit and cpu thinks it has already serivced | |
824 | * the interrupt. Hence a vector might get locked. It was noticed | |
825 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
826 | */ | |
827 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
828 | value = apic_read(APIC_ISR + i*0x10); | |
829 | for (j = 31; j >= 0; j--) { | |
830 | if (value & (1<<j)) | |
831 | ack_APIC_irq(); | |
832 | } | |
833 | } | |
834 | ||
1da177e4 LT |
835 | /* |
836 | * Now that we are all set up, enable the APIC | |
837 | */ | |
838 | value = apic_read(APIC_SPIV); | |
839 | value &= ~APIC_VECTOR_MASK; | |
840 | /* | |
841 | * Enable APIC | |
842 | */ | |
843 | value |= APIC_SPIV_APIC_ENABLED; | |
844 | ||
3f14c746 AK |
845 | /* We always use processor focus */ |
846 | ||
1da177e4 LT |
847 | /* |
848 | * Set spurious IRQ vector | |
849 | */ | |
850 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 851 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
852 | |
853 | /* | |
854 | * Set up LVT0, LVT1: | |
855 | * | |
856 | * set up through-local-APIC on the BP's LINT0. This is not | |
857 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
858 | * we delegate interrupts to the 8259A. | |
859 | */ | |
860 | /* | |
861 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
862 | */ | |
863 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 864 | if (!smp_processor_id() && !value) { |
1da177e4 | 865 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
866 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
867 | smp_processor_id()); | |
1da177e4 LT |
868 | } else { |
869 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
870 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
871 | smp_processor_id()); | |
1da177e4 | 872 | } |
11a8e778 | 873 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
874 | |
875 | /* | |
876 | * only the BP should see the LINT1 NMI signal, obviously. | |
877 | */ | |
878 | if (!smp_processor_id()) | |
879 | value = APIC_DM_NMI; | |
880 | else | |
881 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 882 | apic_write(APIC_LVT1, value); |
ac23d4ee | 883 | preempt_enable(); |
739f33b3 | 884 | } |
1da177e4 | 885 | |
a4928cff | 886 | static void __cpuinit lapic_setup_esr(void) |
739f33b3 AK |
887 | { |
888 | unsigned maxlvt = lapic_get_maxlvt(); | |
889 | ||
890 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR); | |
1c69524c | 891 | /* |
739f33b3 | 892 | * spec says clear errors after enabling vector. |
1c69524c | 893 | */ |
739f33b3 AK |
894 | if (maxlvt > 3) |
895 | apic_write(APIC_ESR, 0); | |
896 | } | |
1da177e4 | 897 | |
739f33b3 AK |
898 | void __cpuinit end_local_APIC_setup(void) |
899 | { | |
900 | lapic_setup_esr(); | |
f2802e7f | 901 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 902 | apic_pm_activate(); |
1da177e4 | 903 | } |
1da177e4 | 904 | |
6e1cb38a SS |
905 | void check_x2apic(void) |
906 | { | |
907 | int msr, msr2; | |
908 | ||
909 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
910 | ||
911 | if (msr & X2APIC_ENABLE) { | |
912 | printk("x2apic enabled by BIOS, switching to x2apic ops\n"); | |
913 | x2apic_preenabled = x2apic = 1; | |
914 | apic_ops = &x2apic_ops; | |
915 | } | |
916 | } | |
917 | ||
918 | void enable_x2apic(void) | |
919 | { | |
920 | int msr, msr2; | |
921 | ||
922 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
923 | if (!(msr & X2APIC_ENABLE)) { | |
924 | printk("Enabling x2apic\n"); | |
925 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); | |
926 | } | |
927 | } | |
928 | ||
929 | void enable_IR_x2apic(void) | |
930 | { | |
931 | #ifdef CONFIG_INTR_REMAP | |
932 | int ret; | |
933 | unsigned long flags; | |
934 | ||
935 | if (!cpu_has_x2apic) | |
936 | return; | |
937 | ||
938 | if (!x2apic_preenabled && disable_x2apic) { | |
939 | printk(KERN_INFO | |
940 | "Skipped enabling x2apic and Interrupt-remapping " | |
941 | "because of nox2apic\n"); | |
942 | return; | |
943 | } | |
944 | ||
945 | if (x2apic_preenabled && disable_x2apic) | |
946 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
947 | ||
948 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
949 | printk(KERN_INFO | |
950 | "Skipped enabling x2apic and Interrupt-remapping " | |
951 | "because of skipping io-apic setup\n"); | |
952 | return; | |
953 | } | |
954 | ||
955 | ret = dmar_table_init(); | |
956 | if (ret) { | |
957 | printk(KERN_INFO | |
958 | "dmar_table_init() failed with %d:\n", ret); | |
959 | ||
960 | if (x2apic_preenabled) | |
961 | panic("x2apic enabled by bios. But IR enabling failed"); | |
962 | else | |
963 | printk(KERN_INFO | |
964 | "Not enabling x2apic,Intr-remapping\n"); | |
965 | return; | |
966 | } | |
967 | ||
968 | local_irq_save(flags); | |
969 | mask_8259A(); | |
970 | save_mask_IO_APIC_setup(); | |
971 | ||
972 | ret = enable_intr_remapping(1); | |
973 | ||
974 | if (ret && x2apic_preenabled) { | |
975 | local_irq_restore(flags); | |
976 | panic("x2apic enabled by bios. But IR enabling failed"); | |
977 | } | |
978 | ||
979 | if (ret) | |
980 | goto end; | |
981 | ||
982 | if (!x2apic) { | |
983 | x2apic = 1; | |
984 | apic_ops = &x2apic_ops; | |
985 | enable_x2apic(); | |
986 | } | |
987 | end: | |
988 | if (ret) | |
989 | /* | |
990 | * IR enabling failed | |
991 | */ | |
992 | restore_IO_APIC_setup(); | |
993 | else | |
994 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
995 | ||
996 | unmask_8259A(); | |
997 | local_irq_restore(flags); | |
998 | ||
999 | if (!ret) { | |
1000 | if (!x2apic_preenabled) | |
1001 | printk(KERN_INFO | |
1002 | "Enabled x2apic and interrupt-remapping\n"); | |
1003 | else | |
1004 | printk(KERN_INFO | |
1005 | "Enabled Interrupt-remapping\n"); | |
1006 | } else | |
1007 | printk(KERN_ERR | |
1008 | "Failed to enable Interrupt-remapping and x2apic\n"); | |
1009 | #else | |
1010 | if (!cpu_has_x2apic) | |
1011 | return; | |
1012 | ||
1013 | if (x2apic_preenabled) | |
1014 | panic("x2apic enabled prior OS handover," | |
1015 | " enable CONFIG_INTR_REMAP"); | |
1016 | ||
1017 | printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " | |
1018 | " and x2apic\n"); | |
1019 | #endif | |
1020 | ||
1021 | return; | |
1022 | } | |
1023 | ||
1da177e4 LT |
1024 | /* |
1025 | * Detect and enable local APICs on non-SMP boards. | |
1026 | * Original code written by Keir Fraser. | |
1027 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1028 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1029 | */ |
0e078e2f | 1030 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1031 | { |
1032 | if (!cpu_has_apic) { | |
1033 | printk(KERN_INFO "No local APIC present\n"); | |
1034 | return -1; | |
1035 | } | |
1036 | ||
1037 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1038 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1039 | return 0; |
1040 | } | |
1041 | ||
8643f9d0 YL |
1042 | void __init early_init_lapic_mapping(void) |
1043 | { | |
431ee79d | 1044 | unsigned long phys_addr; |
8643f9d0 YL |
1045 | |
1046 | /* | |
1047 | * If no local APIC can be found then go out | |
1048 | * : it means there is no mpatable and MADT | |
1049 | */ | |
1050 | if (!smp_found_config) | |
1051 | return; | |
1052 | ||
431ee79d | 1053 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1054 | |
431ee79d | 1055 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1056 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1057 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1058 | |
1059 | /* | |
1060 | * Fetch the APIC ID of the BSP in case we have a | |
1061 | * default configuration (or the MP table is broken). | |
1062 | */ | |
05f2d12c | 1063 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
8643f9d0 YL |
1064 | } |
1065 | ||
0e078e2f TG |
1066 | /** |
1067 | * init_apic_mappings - initialize APIC mappings | |
1068 | */ | |
1da177e4 LT |
1069 | void __init init_apic_mappings(void) |
1070 | { | |
6e1cb38a SS |
1071 | if (x2apic) { |
1072 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); | |
1073 | return; | |
1074 | } | |
1075 | ||
1da177e4 LT |
1076 | /* |
1077 | * If no local APIC can be found then set up a fake all | |
1078 | * zeroes page to simulate the local APIC and another | |
1079 | * one for the IO-APIC. | |
1080 | */ | |
1081 | if (!smp_found_config && detect_init_APIC()) { | |
1082 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1083 | apic_phys = __pa(apic_phys); | |
1084 | } else | |
1085 | apic_phys = mp_lapic_addr; | |
1086 | ||
1087 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
1088 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
1089 | APIC_BASE, apic_phys); | |
1da177e4 LT |
1090 | |
1091 | /* | |
1092 | * Fetch the APIC ID of the BSP in case we have a | |
1093 | * default configuration (or the MP table is broken). | |
1094 | */ | |
05f2d12c | 1095 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
1da177e4 LT |
1096 | } |
1097 | ||
1098 | /* | |
0e078e2f TG |
1099 | * This initializes the IO-APIC and APIC hardware if this is |
1100 | * a UP kernel. | |
1da177e4 | 1101 | */ |
0e078e2f | 1102 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1103 | { |
0e078e2f TG |
1104 | if (disable_apic) { |
1105 | printk(KERN_INFO "Apic disabled\n"); | |
1106 | return -1; | |
1107 | } | |
1108 | if (!cpu_has_apic) { | |
1109 | disable_apic = 1; | |
1110 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1111 | return -1; | |
1112 | } | |
1da177e4 | 1113 | |
6e1cb38a SS |
1114 | enable_IR_x2apic(); |
1115 | setup_apic_routing(); | |
1116 | ||
0e078e2f | 1117 | verify_local_APIC(); |
1da177e4 | 1118 | |
b5841765 GC |
1119 | connect_bsp_APIC(); |
1120 | ||
b6df1b8b | 1121 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
c70dcb74 | 1122 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
1da177e4 | 1123 | |
0e078e2f | 1124 | setup_local_APIC(); |
1da177e4 | 1125 | |
739f33b3 AK |
1126 | /* |
1127 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1128 | * We need clear_IO_APIC before enabling vector on BP | |
1129 | */ | |
1130 | if (!skip_ioapic_setup && nr_ioapics) | |
1131 | enable_IO_APIC(); | |
1132 | ||
acae7d90 MR |
1133 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
1134 | localise_nmi_watchdog(); | |
739f33b3 AK |
1135 | end_local_APIC_setup(); |
1136 | ||
0e078e2f TG |
1137 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1138 | setup_IO_APIC(); | |
1139 | else | |
1140 | nr_ioapics = 0; | |
1141 | setup_boot_APIC_clock(); | |
1142 | check_nmi_watchdog(); | |
1143 | return 0; | |
1da177e4 LT |
1144 | } |
1145 | ||
1146 | /* | |
0e078e2f | 1147 | * Local APIC interrupts |
1da177e4 LT |
1148 | */ |
1149 | ||
0e078e2f TG |
1150 | /* |
1151 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1152 | */ | |
1153 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 1154 | { |
0e078e2f TG |
1155 | unsigned int v; |
1156 | exit_idle(); | |
1157 | irq_enter(); | |
1da177e4 | 1158 | /* |
0e078e2f TG |
1159 | * Check if this really is a spurious interrupt and ACK it |
1160 | * if it is a vectored one. Just in case... | |
1161 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1162 | */ |
0e078e2f TG |
1163 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1164 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1165 | ack_APIC_irq(); | |
c4d58cbd | 1166 | |
0e078e2f TG |
1167 | add_pda(irq_spurious_count, 1); |
1168 | irq_exit(); | |
1169 | } | |
1da177e4 | 1170 | |
0e078e2f TG |
1171 | /* |
1172 | * This interrupt should never happen with our APIC/SMP architecture | |
1173 | */ | |
1174 | asmlinkage void smp_error_interrupt(void) | |
1175 | { | |
1176 | unsigned int v, v1; | |
1da177e4 | 1177 | |
0e078e2f TG |
1178 | exit_idle(); |
1179 | irq_enter(); | |
1180 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1181 | v = apic_read(APIC_ESR); | |
1182 | apic_write(APIC_ESR, 0); | |
1183 | v1 = apic_read(APIC_ESR); | |
1184 | ack_APIC_irq(); | |
1185 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1186 | |
0e078e2f TG |
1187 | /* Here is what the APIC error bits mean: |
1188 | 0: Send CS error | |
1189 | 1: Receive CS error | |
1190 | 2: Send accept error | |
1191 | 3: Receive accept error | |
1192 | 4: Reserved | |
1193 | 5: Send illegal vector | |
1194 | 6: Received illegal vector | |
1195 | 7: Illegal register address | |
1196 | */ | |
1197 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1198 | smp_processor_id(), v , v1); | |
1199 | irq_exit(); | |
1da177e4 LT |
1200 | } |
1201 | ||
b5841765 GC |
1202 | /** |
1203 | * * connect_bsp_APIC - attach the APIC to the interrupt system | |
1204 | * */ | |
1205 | void __init connect_bsp_APIC(void) | |
1206 | { | |
1207 | enable_apic_mode(); | |
1208 | } | |
1209 | ||
0e078e2f | 1210 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1211 | { |
0e078e2f TG |
1212 | /* Go back to Virtual Wire compatibility mode */ |
1213 | unsigned long value; | |
1da177e4 | 1214 | |
0e078e2f TG |
1215 | /* For the spurious interrupt use vector F, and enable it */ |
1216 | value = apic_read(APIC_SPIV); | |
1217 | value &= ~APIC_VECTOR_MASK; | |
1218 | value |= APIC_SPIV_APIC_ENABLED; | |
1219 | value |= 0xf; | |
1220 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1221 | |
0e078e2f TG |
1222 | if (!virt_wire_setup) { |
1223 | /* | |
1224 | * For LVT0 make it edge triggered, active high, | |
1225 | * external and enabled | |
1226 | */ | |
1227 | value = apic_read(APIC_LVT0); | |
1228 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1229 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1230 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1231 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1232 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1233 | apic_write(APIC_LVT0, value); | |
1234 | } else { | |
1235 | /* Disable LVT0 */ | |
1236 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1237 | } | |
b8ce3359 | 1238 | |
0e078e2f TG |
1239 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ |
1240 | value = apic_read(APIC_LVT1); | |
1241 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1242 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1243 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1244 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1245 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1246 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1247 | } |
1248 | ||
be8a5685 AS |
1249 | void __cpuinit generic_processor_info(int apicid, int version) |
1250 | { | |
1251 | int cpu; | |
1252 | cpumask_t tmp_map; | |
1253 | ||
1254 | if (num_processors >= NR_CPUS) { | |
1255 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1256 | " Processor ignored.\n", NR_CPUS); | |
1257 | return; | |
1258 | } | |
1259 | ||
1260 | if (num_processors >= maxcpus) { | |
1261 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
1262 | " Processor ignored.\n", maxcpus); | |
1263 | return; | |
1264 | } | |
1265 | ||
1266 | num_processors++; | |
1267 | cpus_complement(tmp_map, cpu_present_map); | |
1268 | cpu = first_cpu(tmp_map); | |
1269 | ||
1270 | physid_set(apicid, phys_cpu_present_map); | |
1271 | if (apicid == boot_cpu_physical_apicid) { | |
1272 | /* | |
1273 | * x86_bios_cpu_apicid is required to have processors listed | |
1274 | * in same order as logical cpu numbers. Hence the first | |
1275 | * entry is BSP, and so on. | |
1276 | */ | |
1277 | cpu = 0; | |
1278 | } | |
e0da3364 YL |
1279 | if (apicid > max_physical_apicid) |
1280 | max_physical_apicid = apicid; | |
1281 | ||
be8a5685 | 1282 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1283 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1284 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1285 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1286 | |
1287 | cpu_to_apicid[cpu] = apicid; | |
1288 | bios_cpu_apicid[cpu] = apicid; | |
1289 | } else { | |
1290 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1291 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1292 | } | |
1293 | ||
1294 | cpu_set(cpu, cpu_possible_map); | |
1295 | cpu_set(cpu, cpu_present_map); | |
1296 | } | |
1297 | ||
0c81c746 SS |
1298 | int hard_smp_processor_id(void) |
1299 | { | |
1300 | return read_apic_id(); | |
1301 | } | |
1302 | ||
89039b37 | 1303 | /* |
0e078e2f | 1304 | * Power management |
89039b37 | 1305 | */ |
0e078e2f TG |
1306 | #ifdef CONFIG_PM |
1307 | ||
1308 | static struct { | |
1309 | /* 'active' is true if the local APIC was enabled by us and | |
1310 | not the BIOS; this signifies that we are also responsible | |
1311 | for disabling it before entering apm/acpi suspend */ | |
1312 | int active; | |
1313 | /* r/w apic fields */ | |
1314 | unsigned int apic_id; | |
1315 | unsigned int apic_taskpri; | |
1316 | unsigned int apic_ldr; | |
1317 | unsigned int apic_dfr; | |
1318 | unsigned int apic_spiv; | |
1319 | unsigned int apic_lvtt; | |
1320 | unsigned int apic_lvtpc; | |
1321 | unsigned int apic_lvt0; | |
1322 | unsigned int apic_lvt1; | |
1323 | unsigned int apic_lvterr; | |
1324 | unsigned int apic_tmict; | |
1325 | unsigned int apic_tdcr; | |
1326 | unsigned int apic_thmr; | |
1327 | } apic_pm_state; | |
1328 | ||
1329 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1330 | { | |
1331 | unsigned long flags; | |
1332 | int maxlvt; | |
89039b37 | 1333 | |
0e078e2f TG |
1334 | if (!apic_pm_state.active) |
1335 | return 0; | |
89039b37 | 1336 | |
0e078e2f | 1337 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1338 | |
2d7a66d0 | 1339 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1340 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1341 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1342 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1343 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1344 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1345 | if (maxlvt >= 4) | |
1346 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1347 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1348 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1349 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1350 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1351 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1352 | #ifdef CONFIG_X86_MCE_INTEL | |
1353 | if (maxlvt >= 5) | |
1354 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1355 | #endif | |
1356 | local_irq_save(flags); | |
1357 | disable_local_APIC(); | |
1358 | local_irq_restore(flags); | |
1359 | return 0; | |
1da177e4 LT |
1360 | } |
1361 | ||
0e078e2f | 1362 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1363 | { |
0e078e2f TG |
1364 | unsigned int l, h; |
1365 | unsigned long flags; | |
1366 | int maxlvt; | |
1da177e4 | 1367 | |
0e078e2f TG |
1368 | if (!apic_pm_state.active) |
1369 | return 0; | |
89b831ef | 1370 | |
0e078e2f | 1371 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1372 | |
0e078e2f | 1373 | local_irq_save(flags); |
6e1cb38a SS |
1374 | if (!x2apic) { |
1375 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1376 | l &= ~MSR_IA32_APICBASE_BASE; | |
1377 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1378 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1379 | } else | |
1380 | enable_x2apic(); | |
1381 | ||
0e078e2f TG |
1382 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
1383 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1384 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1385 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1386 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1387 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1388 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1389 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1390 | #ifdef CONFIG_X86_MCE_INTEL | |
1391 | if (maxlvt >= 5) | |
1392 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1393 | #endif | |
1394 | if (maxlvt >= 4) | |
1395 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1396 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1397 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1398 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1399 | apic_write(APIC_ESR, 0); | |
1400 | apic_read(APIC_ESR); | |
1401 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1402 | apic_write(APIC_ESR, 0); | |
1403 | apic_read(APIC_ESR); | |
1404 | local_irq_restore(flags); | |
1405 | return 0; | |
1406 | } | |
b8ce3359 | 1407 | |
0e078e2f TG |
1408 | static struct sysdev_class lapic_sysclass = { |
1409 | .name = "lapic", | |
1410 | .resume = lapic_resume, | |
1411 | .suspend = lapic_suspend, | |
1412 | }; | |
b8ce3359 | 1413 | |
0e078e2f | 1414 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1415 | .id = 0, |
1416 | .cls = &lapic_sysclass, | |
0e078e2f | 1417 | }; |
b8ce3359 | 1418 | |
0e078e2f TG |
1419 | static void __cpuinit apic_pm_activate(void) |
1420 | { | |
1421 | apic_pm_state.active = 1; | |
1da177e4 LT |
1422 | } |
1423 | ||
0e078e2f | 1424 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1425 | { |
0e078e2f | 1426 | int error; |
e83a5fdc | 1427 | |
0e078e2f TG |
1428 | if (!cpu_has_apic) |
1429 | return 0; | |
1430 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1431 | |
0e078e2f TG |
1432 | error = sysdev_class_register(&lapic_sysclass); |
1433 | if (!error) | |
1434 | error = sysdev_register(&device_lapic); | |
1435 | return error; | |
1da177e4 | 1436 | } |
0e078e2f TG |
1437 | device_initcall(init_lapic_sysfs); |
1438 | ||
1439 | #else /* CONFIG_PM */ | |
1440 | ||
1441 | static void apic_pm_activate(void) { } | |
1442 | ||
1443 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1444 | |
1445 | /* | |
f8bf3c65 | 1446 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1447 | * |
1448 | * Thus far, the major user of this is IBM's Summit2 series: | |
1449 | * | |
637029c6 | 1450 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1451 | * multi-chassis. Use available data to take a good guess. |
1452 | * If in doubt, go HPET. | |
1453 | */ | |
f8bf3c65 | 1454 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1455 | { |
1456 | int i, clusters, zeros; | |
1457 | unsigned id; | |
322850af | 1458 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1459 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1460 | ||
322850af YL |
1461 | /* |
1462 | * there is not this kind of box with AMD CPU yet. | |
1463 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1464 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1465 | * vsmp box still need checking... |
322850af | 1466 | */ |
1cb68487 | 1467 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1468 | return 0; |
1469 | ||
23ca4bba | 1470 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 1471 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1472 | |
1473 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1474 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1475 | if (bios_cpu_apicid) { |
1476 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1477 | } |
1478 | else if (i < nr_cpu_ids) { | |
1479 | if (cpu_present(i)) | |
1480 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1481 | else | |
1482 | continue; | |
1483 | } | |
1484 | else | |
1485 | break; | |
1486 | ||
1da177e4 LT |
1487 | if (id != BAD_APICID) |
1488 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1489 | } | |
1490 | ||
1491 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1492 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1493 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1494 | * Since clusters are allocated sequentially, count zeros only if | |
1495 | * they are bounded by ones. | |
1da177e4 LT |
1496 | */ |
1497 | clusters = 0; | |
1498 | zeros = 0; | |
1499 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1500 | if (test_bit(i, clustermap)) { | |
1501 | clusters += 1 + zeros; | |
1502 | zeros = 0; | |
1503 | } else | |
1504 | ++zeros; | |
1505 | } | |
1506 | ||
1cb68487 RT |
1507 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1508 | * not guaranteed to be synced between boards | |
1509 | */ | |
1510 | if (is_vsmp_box() && clusters > 1) | |
1511 | return 1; | |
1512 | ||
1da177e4 | 1513 | /* |
f8bf3c65 | 1514 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1515 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1516 | * out, but AFAIK this will work even for them. | |
1517 | */ | |
1518 | return (clusters > 2); | |
1519 | } | |
1520 | ||
6e1cb38a SS |
1521 | static __init int setup_nox2apic(char *str) |
1522 | { | |
1523 | disable_x2apic = 1; | |
1524 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC); | |
1525 | return 0; | |
1526 | } | |
1527 | early_param("nox2apic", setup_nox2apic); | |
1528 | ||
1529 | ||
1da177e4 | 1530 | /* |
0e078e2f | 1531 | * APIC command line parameters |
1da177e4 | 1532 | */ |
0e078e2f | 1533 | static int __init apic_set_verbosity(char *str) |
1da177e4 | 1534 | { |
0e078e2f TG |
1535 | if (str == NULL) { |
1536 | skip_ioapic_setup = 0; | |
1537 | ioapic_force = 1; | |
1538 | return 0; | |
1da177e4 | 1539 | } |
0e078e2f TG |
1540 | if (strcmp("debug", str) == 0) |
1541 | apic_verbosity = APIC_DEBUG; | |
1542 | else if (strcmp("verbose", str) == 0) | |
1543 | apic_verbosity = APIC_VERBOSE; | |
1544 | else { | |
1545 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1546 | " use apic=verbose or apic=debug\n", str); | |
1547 | return -EINVAL; | |
1da177e4 LT |
1548 | } |
1549 | ||
1da177e4 LT |
1550 | return 0; |
1551 | } | |
0e078e2f | 1552 | early_param("apic", apic_set_verbosity); |
1da177e4 | 1553 | |
6935d1f9 TG |
1554 | static __init int setup_disableapic(char *str) |
1555 | { | |
1da177e4 | 1556 | disable_apic = 1; |
53756d37 | 1557 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
2c8c0e6b AK |
1558 | return 0; |
1559 | } | |
1560 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1561 | |
2c8c0e6b | 1562 | /* same as disableapic, for compatibility */ |
6935d1f9 TG |
1563 | static __init int setup_nolapic(char *str) |
1564 | { | |
2c8c0e6b | 1565 | return setup_disableapic(str); |
6935d1f9 | 1566 | } |
2c8c0e6b | 1567 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1568 | |
2e7c2838 LT |
1569 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1570 | { | |
1571 | local_apic_timer_c2_ok = 1; | |
1572 | return 0; | |
1573 | } | |
1574 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1575 | ||
6935d1f9 TG |
1576 | static __init int setup_noapictimer(char *str) |
1577 | { | |
73dea47f | 1578 | if (str[0] != ' ' && str[0] != 0) |
9b41046c | 1579 | return 0; |
1da177e4 | 1580 | disable_apic_timer = 1; |
9b41046c | 1581 | return 1; |
6935d1f9 | 1582 | } |
9f75e9b7 | 1583 | __setup("noapictimer", setup_noapictimer); |
73dea47f | 1584 | |
0c3749c4 AK |
1585 | static __init int setup_apicpmtimer(char *s) |
1586 | { | |
1587 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1588 | notsc_setup(NULL); |
b8ce3359 | 1589 | return 0; |
0c3749c4 AK |
1590 | } |
1591 | __setup("apicpmtimer", setup_apicpmtimer); | |
1592 | ||
1e934dda YL |
1593 | static int __init lapic_insert_resource(void) |
1594 | { | |
1595 | if (!apic_phys) | |
1596 | return -1; | |
1597 | ||
1598 | /* Put local APIC into the resource map. */ | |
1599 | lapic_resource.start = apic_phys; | |
1600 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1601 | insert_resource(&iomem_resource, &lapic_resource); | |
1602 | ||
1603 | return 0; | |
1604 | } | |
1605 | ||
1606 | /* | |
1607 | * need call insert after e820_reserve_resources() | |
1608 | * that is using request_resource | |
1609 | */ | |
1610 | late_initcall(lapic_insert_resource); |