Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
1da177e4 LT |
30 | |
31 | #include <asm/atomic.h> | |
32 | #include <asm/smp.h> | |
33 | #include <asm/mtrr.h> | |
34 | #include <asm/mpspec.h> | |
e83a5fdc | 35 | #include <asm/hpet.h> |
1da177e4 | 36 | #include <asm/pgalloc.h> |
75152114 | 37 | #include <asm/nmi.h> |
95833c83 | 38 | #include <asm/idle.h> |
73dea47f AK |
39 | #include <asm/proto.h> |
40 | #include <asm/timex.h> | |
2c8c0e6b | 41 | #include <asm/apic.h> |
1da177e4 | 42 | |
5af5573e | 43 | #include <mach_ipi.h> |
dd46e3ca | 44 | #include <mach_apic.h> |
5af5573e | 45 | |
fb79d22e | 46 | int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 47 | static int apic_calibrate_pmtmr __initdata; |
0e078e2f | 48 | int disable_apic; |
1da177e4 | 49 | |
e83a5fdc | 50 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
51 | int local_apic_timer_c2_ok; |
52 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
53 | ||
e83a5fdc HS |
54 | /* |
55 | * Debug level, exported for io_apic.c | |
56 | */ | |
57 | int apic_verbosity; | |
58 | ||
bab4b27c AS |
59 | /* Have we found an MP table */ |
60 | int smp_found_config; | |
61 | ||
39928722 AD |
62 | static struct resource lapic_resource = { |
63 | .name = "Local APIC", | |
64 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
65 | }; | |
66 | ||
d03030e9 TG |
67 | static unsigned int calibration_result; |
68 | ||
ba7eda4c TG |
69 | static int lapic_next_event(unsigned long delta, |
70 | struct clock_event_device *evt); | |
71 | static void lapic_timer_setup(enum clock_event_mode mode, | |
72 | struct clock_event_device *evt); | |
ba7eda4c | 73 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 74 | static void apic_pm_activate(void); |
ba7eda4c TG |
75 | |
76 | static struct clock_event_device lapic_clockevent = { | |
77 | .name = "lapic", | |
78 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
79 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
80 | .shift = 32, | |
81 | .set_mode = lapic_timer_setup, | |
82 | .set_next_event = lapic_next_event, | |
83 | .broadcast = lapic_timer_broadcast, | |
84 | .rating = 100, | |
85 | .irq = -1, | |
86 | }; | |
87 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
88 | ||
d3432896 AK |
89 | static unsigned long apic_phys; |
90 | ||
3f530709 AS |
91 | unsigned long mp_lapic_addr; |
92 | ||
af926a58 AS |
93 | DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID; |
94 | EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
95 | ||
be8a5685 | 96 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
0e078e2f TG |
97 | /* |
98 | * Get the LAPIC version | |
99 | */ | |
100 | static inline int lapic_get_version(void) | |
ba7eda4c | 101 | { |
0e078e2f | 102 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
103 | } |
104 | ||
0e078e2f TG |
105 | /* |
106 | * Check, if the APIC is integrated or a seperate chip | |
107 | */ | |
108 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 109 | { |
0e078e2f | 110 | return 1; |
ba7eda4c TG |
111 | } |
112 | ||
113 | /* | |
0e078e2f | 114 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 115 | */ |
0e078e2f | 116 | static int modern_apic(void) |
ba7eda4c | 117 | { |
0e078e2f TG |
118 | /* AMD systems use old APIC versions, so check the CPU */ |
119 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
120 | boot_cpu_data.x86 >= 0xf) | |
121 | return 1; | |
122 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
123 | } |
124 | ||
8339e9fb FLV |
125 | void apic_wait_icr_idle(void) |
126 | { | |
127 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
128 | cpu_relax(); | |
129 | } | |
130 | ||
3c6bb07a | 131 | u32 safe_apic_wait_icr_idle(void) |
8339e9fb | 132 | { |
3c6bb07a | 133 | u32 send_status; |
8339e9fb FLV |
134 | int timeout; |
135 | ||
136 | timeout = 0; | |
137 | do { | |
138 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
139 | if (!send_status) | |
140 | break; | |
141 | udelay(100); | |
142 | } while (timeout++ < 1000); | |
143 | ||
144 | return send_status; | |
145 | } | |
146 | ||
0e078e2f TG |
147 | /** |
148 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
149 | */ | |
e9427101 | 150 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 151 | { |
11a8e778 | 152 | unsigned int v; |
6935d1f9 TG |
153 | |
154 | /* unmask and set to NMI */ | |
155 | v = APIC_DM_NMI; | |
11a8e778 | 156 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
157 | } |
158 | ||
0e078e2f TG |
159 | /** |
160 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
161 | */ | |
37e650c7 | 162 | int lapic_get_maxlvt(void) |
1da177e4 | 163 | { |
11a8e778 | 164 | unsigned int v, maxlvt; |
1da177e4 LT |
165 | |
166 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
167 | maxlvt = GET_APIC_MAXLVT(v); |
168 | return maxlvt; | |
169 | } | |
170 | ||
0e078e2f TG |
171 | /* |
172 | * This function sets up the local APIC timer, with a timeout of | |
173 | * 'clocks' APIC bus clock. During calibration we actually call | |
174 | * this function twice on the boot CPU, once with a bogus timeout | |
175 | * value, second time for real. The other (noncalibrating) CPUs | |
176 | * call this function only once, with the real, calibrated value. | |
177 | * | |
178 | * We do reads before writes even if unnecessary, to get around the | |
179 | * P5 APIC double write bug. | |
180 | */ | |
181 | ||
182 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) | |
1da177e4 | 183 | { |
0e078e2f | 184 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 185 | |
0e078e2f TG |
186 | lvtt_value = LOCAL_TIMER_VECTOR; |
187 | if (!oneshot) | |
188 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
189 | if (!irqen) | |
190 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 191 | |
0e078e2f | 192 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
193 | |
194 | /* | |
0e078e2f | 195 | * Divide PICLK by 16 |
1da177e4 | 196 | */ |
0e078e2f TG |
197 | tmp_value = apic_read(APIC_TDCR); |
198 | apic_write(APIC_TDCR, (tmp_value | |
199 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
200 | | APIC_TDR_DIV_16); | |
201 | ||
202 | if (!oneshot) | |
203 | apic_write(APIC_TMICT, clocks); | |
1da177e4 LT |
204 | } |
205 | ||
0e078e2f | 206 | /* |
7b83dae7 RR |
207 | * Setup extended LVT, AMD specific (K8, family 10h) |
208 | * | |
209 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
210 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
0e078e2f | 211 | */ |
7b83dae7 RR |
212 | |
213 | #define APIC_EILVT_LVTOFF_MCE 0 | |
214 | #define APIC_EILVT_LVTOFF_IBS 1 | |
215 | ||
216 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 217 | { |
7b83dae7 | 218 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 219 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 220 | |
0e078e2f | 221 | apic_write(reg, v); |
1da177e4 LT |
222 | } |
223 | ||
7b83dae7 RR |
224 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
225 | { | |
226 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
227 | return APIC_EILVT_LVTOFF_MCE; | |
228 | } | |
229 | ||
230 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
231 | { | |
232 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
233 | return APIC_EILVT_LVTOFF_IBS; | |
234 | } | |
235 | ||
0e078e2f TG |
236 | /* |
237 | * Program the next event, relative to now | |
238 | */ | |
239 | static int lapic_next_event(unsigned long delta, | |
240 | struct clock_event_device *evt) | |
1da177e4 | 241 | { |
0e078e2f TG |
242 | apic_write(APIC_TMICT, delta); |
243 | return 0; | |
1da177e4 LT |
244 | } |
245 | ||
0e078e2f TG |
246 | /* |
247 | * Setup the lapic timer in periodic or oneshot mode | |
248 | */ | |
249 | static void lapic_timer_setup(enum clock_event_mode mode, | |
250 | struct clock_event_device *evt) | |
9b7711f0 HS |
251 | { |
252 | unsigned long flags; | |
0e078e2f | 253 | unsigned int v; |
9b7711f0 | 254 | |
0e078e2f TG |
255 | /* Lapic used as dummy for broadcast ? */ |
256 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
257 | return; |
258 | ||
259 | local_irq_save(flags); | |
260 | ||
0e078e2f TG |
261 | switch (mode) { |
262 | case CLOCK_EVT_MODE_PERIODIC: | |
263 | case CLOCK_EVT_MODE_ONESHOT: | |
264 | __setup_APIC_LVTT(calibration_result, | |
265 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
266 | break; | |
267 | case CLOCK_EVT_MODE_UNUSED: | |
268 | case CLOCK_EVT_MODE_SHUTDOWN: | |
269 | v = apic_read(APIC_LVTT); | |
270 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
271 | apic_write(APIC_LVTT, v); | |
272 | break; | |
273 | case CLOCK_EVT_MODE_RESUME: | |
274 | /* Nothing to do here */ | |
275 | break; | |
276 | } | |
9b7711f0 HS |
277 | |
278 | local_irq_restore(flags); | |
279 | } | |
280 | ||
1da177e4 | 281 | /* |
0e078e2f | 282 | * Local APIC timer broadcast function |
1da177e4 | 283 | */ |
0e078e2f | 284 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 285 | { |
0e078e2f TG |
286 | #ifdef CONFIG_SMP |
287 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
288 | #endif | |
289 | } | |
1da177e4 | 290 | |
0e078e2f TG |
291 | /* |
292 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
293 | * of the boot CPU and register the clock event in the framework. | |
294 | */ | |
295 | static void setup_APIC_timer(void) | |
296 | { | |
297 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 298 | |
0e078e2f TG |
299 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
300 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 301 | |
0e078e2f TG |
302 | clockevents_register_device(levt); |
303 | } | |
1da177e4 | 304 | |
0e078e2f TG |
305 | /* |
306 | * In this function we calibrate APIC bus clocks to the external | |
307 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
308 | * to calibrate, since some later bootup code depends on getting | |
309 | * the first irq? Ugh. | |
310 | * | |
311 | * We want to do the calibration only once since we | |
312 | * want to have local timer irqs syncron. CPUs connected | |
313 | * by the same APIC bus have the very same bus frequency. | |
314 | * And we want to have irqs off anyways, no accidental | |
315 | * APIC irq that way. | |
316 | */ | |
317 | ||
318 | #define TICK_COUNT 100000000 | |
319 | ||
320 | static void __init calibrate_APIC_clock(void) | |
321 | { | |
322 | unsigned apic, apic_start; | |
323 | unsigned long tsc, tsc_start; | |
324 | int result; | |
325 | ||
326 | local_irq_disable(); | |
327 | ||
328 | /* | |
329 | * Put whatever arbitrary (but long enough) timeout | |
330 | * value into the APIC clock, we just want to get the | |
331 | * counter running for calibration. | |
332 | * | |
333 | * No interrupt enable ! | |
334 | */ | |
335 | __setup_APIC_LVTT(250000000, 0, 0); | |
336 | ||
337 | apic_start = apic_read(APIC_TMCCT); | |
338 | #ifdef CONFIG_X86_PM_TIMER | |
339 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
340 | pmtimer_wait(5000); /* 5ms wait */ | |
341 | apic = apic_read(APIC_TMCCT); | |
342 | result = (apic_start - apic) * 1000L / 5; | |
343 | } else | |
344 | #endif | |
345 | { | |
346 | rdtscll(tsc_start); | |
347 | ||
348 | do { | |
349 | apic = apic_read(APIC_TMCCT); | |
350 | rdtscll(tsc); | |
351 | } while ((tsc - tsc_start) < TICK_COUNT && | |
352 | (apic_start - apic) < TICK_COUNT); | |
353 | ||
354 | result = (apic_start - apic) * 1000L * tsc_khz / | |
355 | (tsc - tsc_start); | |
356 | } | |
357 | ||
358 | local_irq_enable(); | |
359 | ||
360 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
361 | ||
362 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
363 | result / 1000 / 1000, result / 1000 % 1000); | |
364 | ||
365 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
366 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
367 | lapic_clockevent.shift); | |
0e078e2f TG |
368 | lapic_clockevent.max_delta_ns = |
369 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
370 | lapic_clockevent.min_delta_ns = | |
371 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
372 | ||
373 | calibration_result = result / HZ; | |
374 | } | |
375 | ||
e83a5fdc HS |
376 | /* |
377 | * Setup the boot APIC | |
378 | * | |
379 | * Calibrate and verify the result. | |
380 | */ | |
0e078e2f TG |
381 | void __init setup_boot_APIC_clock(void) |
382 | { | |
383 | /* | |
384 | * The local apic timer can be disabled via the kernel commandline. | |
385 | * Register the lapic timer as a dummy clock event source on SMP | |
386 | * systems, so the broadcast mechanism is used. On UP systems simply | |
387 | * ignore it. | |
388 | */ | |
389 | if (disable_apic_timer) { | |
390 | printk(KERN_INFO "Disabling APIC timer\n"); | |
391 | /* No broadcast on UP ! */ | |
9d09951d TG |
392 | if (num_possible_cpus() > 1) { |
393 | lapic_clockevent.mult = 1; | |
0e078e2f | 394 | setup_APIC_timer(); |
9d09951d | 395 | } |
0e078e2f TG |
396 | return; |
397 | } | |
398 | ||
399 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); | |
400 | calibrate_APIC_clock(); | |
401 | ||
c2b84b30 TG |
402 | /* |
403 | * Do a sanity check on the APIC calibration result | |
404 | */ | |
405 | if (calibration_result < (1000000 / HZ)) { | |
406 | printk(KERN_WARNING | |
407 | "APIC frequency too slow, disabling apic timer\n"); | |
408 | /* No broadcast on UP ! */ | |
409 | if (num_possible_cpus() > 1) | |
410 | setup_APIC_timer(); | |
411 | return; | |
412 | } | |
413 | ||
0e078e2f TG |
414 | /* |
415 | * If nmi_watchdog is set to IO_APIC, we need the | |
416 | * PIT/HPET going. Otherwise register lapic as a dummy | |
417 | * device. | |
418 | */ | |
419 | if (nmi_watchdog != NMI_IO_APIC) | |
420 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
421 | else | |
422 | printk(KERN_WARNING "APIC timer registered as dummy," | |
423 | " due to nmi_watchdog=1!\n"); | |
424 | ||
425 | setup_APIC_timer(); | |
426 | } | |
427 | ||
428 | /* | |
429 | * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the | |
430 | * C1E flag only in the secondary CPU, so when we detect the wreckage | |
431 | * we already have enabled the boot CPU local apic timer. Check, if | |
432 | * disable_apic_timer is set and the DUMMY flag is cleared. If yes, | |
433 | * set the DUMMY flag again and force the broadcast mode in the | |
434 | * clockevents layer. | |
435 | */ | |
a4928cff | 436 | static void __cpuinit check_boot_apic_timer_broadcast(void) |
0e078e2f TG |
437 | { |
438 | if (!disable_apic_timer || | |
439 | (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY)) | |
440 | return; | |
441 | ||
442 | printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n"); | |
443 | lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY; | |
444 | ||
445 | local_irq_enable(); | |
c70dcb74 GOC |
446 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
447 | &boot_cpu_physical_apicid); | |
0e078e2f TG |
448 | local_irq_disable(); |
449 | } | |
450 | ||
451 | void __cpuinit setup_secondary_APIC_clock(void) | |
452 | { | |
453 | check_boot_apic_timer_broadcast(); | |
454 | setup_APIC_timer(); | |
455 | } | |
456 | ||
457 | /* | |
458 | * The guts of the apic timer interrupt | |
459 | */ | |
460 | static void local_apic_timer_interrupt(void) | |
461 | { | |
462 | int cpu = smp_processor_id(); | |
463 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
464 | ||
465 | /* | |
466 | * Normally we should not be here till LAPIC has been initialized but | |
467 | * in some cases like kdump, its possible that there is a pending LAPIC | |
468 | * timer interrupt from previous kernel's context and is delivered in | |
469 | * new kernel the moment interrupts are enabled. | |
470 | * | |
471 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
472 | * its possible that when we get here evt->event_handler is NULL. | |
473 | * Check for event_handler being NULL and discard the interrupt as | |
474 | * spurious. | |
475 | */ | |
476 | if (!evt->event_handler) { | |
477 | printk(KERN_WARNING | |
478 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
479 | /* Switch it off */ | |
480 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
481 | return; | |
482 | } | |
483 | ||
484 | /* | |
485 | * the NMI deadlock-detector uses this. | |
486 | */ | |
487 | add_pda(apic_timer_irqs, 1); | |
488 | ||
489 | evt->event_handler(evt); | |
490 | } | |
491 | ||
492 | /* | |
493 | * Local APIC timer interrupt. This is the most natural way for doing | |
494 | * local interrupts, but local timer interrupts can be emulated by | |
495 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
496 | * | |
497 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
498 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
499 | */ | |
500 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
501 | { | |
502 | struct pt_regs *old_regs = set_irq_regs(regs); | |
503 | ||
504 | /* | |
505 | * NOTE! We'd better ACK the irq immediately, | |
506 | * because timer handling can be slow. | |
507 | */ | |
508 | ack_APIC_irq(); | |
509 | /* | |
510 | * update_process_times() expects us to have done irq_enter(). | |
511 | * Besides, if we don't timer interrupts ignore the global | |
512 | * interrupt lock, which is the WrongThing (tm) to do. | |
513 | */ | |
514 | exit_idle(); | |
515 | irq_enter(); | |
516 | local_apic_timer_interrupt(); | |
517 | irq_exit(); | |
518 | set_irq_regs(old_regs); | |
519 | } | |
520 | ||
521 | int setup_profiling_timer(unsigned int multiplier) | |
522 | { | |
523 | return -EINVAL; | |
524 | } | |
525 | ||
526 | ||
527 | /* | |
528 | * Local APIC start and shutdown | |
529 | */ | |
530 | ||
531 | /** | |
532 | * clear_local_APIC - shutdown the local APIC | |
533 | * | |
534 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
535 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
536 | * leftovers during boot. | |
537 | */ | |
538 | void clear_local_APIC(void) | |
539 | { | |
540 | int maxlvt = lapic_get_maxlvt(); | |
541 | u32 v; | |
542 | ||
d3432896 AK |
543 | /* APIC hasn't been mapped yet */ |
544 | if (!apic_phys) | |
545 | return; | |
546 | ||
547 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
548 | /* |
549 | * Masking an LVT entry can trigger a local APIC error | |
550 | * if the vector is zero. Mask LVTERR first to prevent this. | |
551 | */ | |
552 | if (maxlvt >= 3) { | |
553 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
554 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
555 | } | |
556 | /* | |
557 | * Careful: we have to set masks only first to deassert | |
558 | * any level-triggered sources. | |
559 | */ | |
560 | v = apic_read(APIC_LVTT); | |
561 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
562 | v = apic_read(APIC_LVT0); | |
563 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
564 | v = apic_read(APIC_LVT1); | |
565 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
566 | if (maxlvt >= 4) { | |
567 | v = apic_read(APIC_LVTPC); | |
568 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
569 | } | |
570 | ||
571 | /* | |
572 | * Clean APIC state for other OSs: | |
573 | */ | |
574 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
575 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
576 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
577 | if (maxlvt >= 3) | |
578 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
579 | if (maxlvt >= 4) | |
580 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
581 | apic_write(APIC_ESR, 0); | |
582 | apic_read(APIC_ESR); | |
583 | } | |
584 | ||
585 | /** | |
586 | * disable_local_APIC - clear and disable the local APIC | |
587 | */ | |
588 | void disable_local_APIC(void) | |
589 | { | |
590 | unsigned int value; | |
591 | ||
592 | clear_local_APIC(); | |
593 | ||
594 | /* | |
595 | * Disable APIC (implies clearing of registers | |
596 | * for 82489DX!). | |
597 | */ | |
598 | value = apic_read(APIC_SPIV); | |
599 | value &= ~APIC_SPIV_APIC_ENABLED; | |
600 | apic_write(APIC_SPIV, value); | |
601 | } | |
602 | ||
603 | void lapic_shutdown(void) | |
604 | { | |
605 | unsigned long flags; | |
606 | ||
607 | if (!cpu_has_apic) | |
608 | return; | |
609 | ||
610 | local_irq_save(flags); | |
611 | ||
612 | disable_local_APIC(); | |
613 | ||
614 | local_irq_restore(flags); | |
615 | } | |
616 | ||
617 | /* | |
618 | * This is to verify that we're looking at a real local APIC. | |
619 | * Check these against your board if the CPUs aren't getting | |
620 | * started for no apparent reason. | |
621 | */ | |
622 | int __init verify_local_APIC(void) | |
623 | { | |
624 | unsigned int reg0, reg1; | |
625 | ||
626 | /* | |
627 | * The version register is read-only in a real APIC. | |
628 | */ | |
629 | reg0 = apic_read(APIC_LVR); | |
630 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
631 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
632 | reg1 = apic_read(APIC_LVR); | |
633 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
634 | ||
635 | /* | |
636 | * The two version reads above should print the same | |
637 | * numbers. If the second one is different, then we | |
638 | * poke at a non-APIC. | |
639 | */ | |
640 | if (reg1 != reg0) | |
641 | return 0; | |
642 | ||
643 | /* | |
644 | * Check if the version looks reasonably. | |
645 | */ | |
646 | reg1 = GET_APIC_VERSION(reg0); | |
647 | if (reg1 == 0x00 || reg1 == 0xff) | |
648 | return 0; | |
649 | reg1 = lapic_get_maxlvt(); | |
650 | if (reg1 < 0x02 || reg1 == 0xff) | |
651 | return 0; | |
652 | ||
653 | /* | |
654 | * The ID register is read/write in a real APIC. | |
655 | */ | |
05f2d12c | 656 | reg0 = read_apic_id(); |
0e078e2f TG |
657 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
658 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
05f2d12c | 659 | reg1 = read_apic_id(); |
0e078e2f TG |
660 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
661 | apic_write(APIC_ID, reg0); | |
662 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
663 | return 0; | |
664 | ||
665 | /* | |
1da177e4 LT |
666 | * The next two are just to see if we have sane values. |
667 | * They're only really relevant if we're in Virtual Wire | |
668 | * compatibility mode, but most boxes are anymore. | |
669 | */ | |
670 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 671 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
672 | reg1 = apic_read(APIC_LVT1); |
673 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
674 | ||
675 | return 1; | |
676 | } | |
677 | ||
0e078e2f TG |
678 | /** |
679 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
680 | */ | |
1da177e4 LT |
681 | void __init sync_Arb_IDs(void) |
682 | { | |
683 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
0e078e2f | 684 | if (modern_apic()) |
1da177e4 LT |
685 | return; |
686 | ||
687 | /* | |
688 | * Wait for idle. | |
689 | */ | |
690 | apic_wait_icr_idle(); | |
691 | ||
692 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 693 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
694 | | APIC_DM_INIT); |
695 | } | |
696 | ||
1da177e4 LT |
697 | /* |
698 | * An initial setup of the virtual wire mode. | |
699 | */ | |
700 | void __init init_bsp_APIC(void) | |
701 | { | |
11a8e778 | 702 | unsigned int value; |
1da177e4 LT |
703 | |
704 | /* | |
705 | * Don't do the setup now if we have a SMP BIOS as the | |
706 | * through-I/O-APIC virtual wire mode might be active. | |
707 | */ | |
708 | if (smp_found_config || !cpu_has_apic) | |
709 | return; | |
710 | ||
711 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
712 | |
713 | /* | |
714 | * Do not trust the local APIC being empty at bootup. | |
715 | */ | |
716 | clear_local_APIC(); | |
717 | ||
718 | /* | |
719 | * Enable APIC. | |
720 | */ | |
721 | value = apic_read(APIC_SPIV); | |
722 | value &= ~APIC_VECTOR_MASK; | |
723 | value |= APIC_SPIV_APIC_ENABLED; | |
724 | value |= APIC_SPIV_FOCUS_DISABLED; | |
725 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 726 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
727 | |
728 | /* | |
729 | * Set up the virtual wire mode. | |
730 | */ | |
11a8e778 | 731 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 732 | value = APIC_DM_NMI; |
11a8e778 | 733 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
734 | } |
735 | ||
0e078e2f TG |
736 | /** |
737 | * setup_local_APIC - setup the local APIC | |
738 | */ | |
739 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 740 | { |
739f33b3 | 741 | unsigned int value; |
da7ed9f9 | 742 | int i, j; |
1da177e4 | 743 | |
ac23d4ee | 744 | preempt_disable(); |
1da177e4 | 745 | value = apic_read(APIC_LVR); |
1da177e4 | 746 | |
fe7414a2 | 747 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
748 | |
749 | /* | |
750 | * Double-check whether this APIC is really registered. | |
751 | * This is meaningless in clustered apic mode, so we skip it. | |
752 | */ | |
753 | if (!apic_id_registered()) | |
754 | BUG(); | |
755 | ||
756 | /* | |
757 | * Intel recommends to set DFR, LDR and TPR before enabling | |
758 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
759 | * document number 292116). So here it goes... | |
760 | */ | |
761 | init_apic_ldr(); | |
762 | ||
763 | /* | |
764 | * Set Task Priority to 'accept all'. We never change this | |
765 | * later on. | |
766 | */ | |
767 | value = apic_read(APIC_TASKPRI); | |
768 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 769 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 770 | |
da7ed9f9 VG |
771 | /* |
772 | * After a crash, we no longer service the interrupts and a pending | |
773 | * interrupt from previous kernel might still have ISR bit set. | |
774 | * | |
775 | * Most probably by now CPU has serviced that pending interrupt and | |
776 | * it might not have done the ack_APIC_irq() because it thought, | |
777 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
778 | * does not clear the ISR bit and cpu thinks it has already serivced | |
779 | * the interrupt. Hence a vector might get locked. It was noticed | |
780 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
781 | */ | |
782 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
783 | value = apic_read(APIC_ISR + i*0x10); | |
784 | for (j = 31; j >= 0; j--) { | |
785 | if (value & (1<<j)) | |
786 | ack_APIC_irq(); | |
787 | } | |
788 | } | |
789 | ||
1da177e4 LT |
790 | /* |
791 | * Now that we are all set up, enable the APIC | |
792 | */ | |
793 | value = apic_read(APIC_SPIV); | |
794 | value &= ~APIC_VECTOR_MASK; | |
795 | /* | |
796 | * Enable APIC | |
797 | */ | |
798 | value |= APIC_SPIV_APIC_ENABLED; | |
799 | ||
3f14c746 AK |
800 | /* We always use processor focus */ |
801 | ||
1da177e4 LT |
802 | /* |
803 | * Set spurious IRQ vector | |
804 | */ | |
805 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 806 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
807 | |
808 | /* | |
809 | * Set up LVT0, LVT1: | |
810 | * | |
811 | * set up through-local-APIC on the BP's LINT0. This is not | |
812 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
813 | * we delegate interrupts to the 8259A. | |
814 | */ | |
815 | /* | |
816 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
817 | */ | |
818 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 819 | if (!smp_processor_id() && !value) { |
1da177e4 | 820 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
821 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
822 | smp_processor_id()); | |
1da177e4 LT |
823 | } else { |
824 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
825 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
826 | smp_processor_id()); | |
1da177e4 | 827 | } |
11a8e778 | 828 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
829 | |
830 | /* | |
831 | * only the BP should see the LINT1 NMI signal, obviously. | |
832 | */ | |
833 | if (!smp_processor_id()) | |
834 | value = APIC_DM_NMI; | |
835 | else | |
836 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 837 | apic_write(APIC_LVT1, value); |
ac23d4ee | 838 | preempt_enable(); |
739f33b3 | 839 | } |
1da177e4 | 840 | |
a4928cff | 841 | static void __cpuinit lapic_setup_esr(void) |
739f33b3 AK |
842 | { |
843 | unsigned maxlvt = lapic_get_maxlvt(); | |
844 | ||
845 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR); | |
1c69524c | 846 | /* |
739f33b3 | 847 | * spec says clear errors after enabling vector. |
1c69524c | 848 | */ |
739f33b3 AK |
849 | if (maxlvt > 3) |
850 | apic_write(APIC_ESR, 0); | |
851 | } | |
1da177e4 | 852 | |
739f33b3 AK |
853 | void __cpuinit end_local_APIC_setup(void) |
854 | { | |
855 | lapic_setup_esr(); | |
1da177e4 | 856 | nmi_watchdog_default(); |
f2802e7f | 857 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 858 | apic_pm_activate(); |
1da177e4 | 859 | } |
1da177e4 LT |
860 | |
861 | /* | |
862 | * Detect and enable local APICs on non-SMP boards. | |
863 | * Original code written by Keir Fraser. | |
864 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 865 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 866 | */ |
0e078e2f | 867 | static int __init detect_init_APIC(void) |
1da177e4 LT |
868 | { |
869 | if (!cpu_has_apic) { | |
870 | printk(KERN_INFO "No local APIC present\n"); | |
871 | return -1; | |
872 | } | |
873 | ||
874 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 875 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
876 | return 0; |
877 | } | |
878 | ||
8643f9d0 YL |
879 | void __init early_init_lapic_mapping(void) |
880 | { | |
881 | unsigned long apic_phys; | |
882 | ||
883 | /* | |
884 | * If no local APIC can be found then go out | |
885 | * : it means there is no mpatable and MADT | |
886 | */ | |
887 | if (!smp_found_config) | |
888 | return; | |
889 | ||
890 | apic_phys = mp_lapic_addr; | |
891 | ||
892 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
893 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", | |
894 | APIC_BASE, apic_phys); | |
895 | ||
896 | /* | |
897 | * Fetch the APIC ID of the BSP in case we have a | |
898 | * default configuration (or the MP table is broken). | |
899 | */ | |
05f2d12c | 900 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
8643f9d0 YL |
901 | } |
902 | ||
0e078e2f TG |
903 | /** |
904 | * init_apic_mappings - initialize APIC mappings | |
905 | */ | |
1da177e4 LT |
906 | void __init init_apic_mappings(void) |
907 | { | |
1da177e4 LT |
908 | /* |
909 | * If no local APIC can be found then set up a fake all | |
910 | * zeroes page to simulate the local APIC and another | |
911 | * one for the IO-APIC. | |
912 | */ | |
913 | if (!smp_found_config && detect_init_APIC()) { | |
914 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
915 | apic_phys = __pa(apic_phys); | |
916 | } else | |
917 | apic_phys = mp_lapic_addr; | |
918 | ||
919 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
920 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
921 | APIC_BASE, apic_phys); | |
1da177e4 LT |
922 | |
923 | /* | |
924 | * Fetch the APIC ID of the BSP in case we have a | |
925 | * default configuration (or the MP table is broken). | |
926 | */ | |
05f2d12c | 927 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
1da177e4 LT |
928 | } |
929 | ||
930 | /* | |
0e078e2f TG |
931 | * This initializes the IO-APIC and APIC hardware if this is |
932 | * a UP kernel. | |
1da177e4 | 933 | */ |
0e078e2f | 934 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 935 | { |
0e078e2f TG |
936 | if (disable_apic) { |
937 | printk(KERN_INFO "Apic disabled\n"); | |
938 | return -1; | |
939 | } | |
940 | if (!cpu_has_apic) { | |
941 | disable_apic = 1; | |
942 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
943 | return -1; | |
944 | } | |
1da177e4 | 945 | |
0e078e2f | 946 | verify_local_APIC(); |
1da177e4 | 947 | |
c70dcb74 GOC |
948 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); |
949 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); | |
1da177e4 | 950 | |
0e078e2f | 951 | setup_local_APIC(); |
1da177e4 | 952 | |
739f33b3 AK |
953 | /* |
954 | * Now enable IO-APICs, actually call clear_IO_APIC | |
955 | * We need clear_IO_APIC before enabling vector on BP | |
956 | */ | |
957 | if (!skip_ioapic_setup && nr_ioapics) | |
958 | enable_IO_APIC(); | |
959 | ||
960 | end_local_APIC_setup(); | |
961 | ||
0e078e2f TG |
962 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
963 | setup_IO_APIC(); | |
964 | else | |
965 | nr_ioapics = 0; | |
966 | setup_boot_APIC_clock(); | |
967 | check_nmi_watchdog(); | |
968 | return 0; | |
1da177e4 LT |
969 | } |
970 | ||
971 | /* | |
0e078e2f | 972 | * Local APIC interrupts |
1da177e4 LT |
973 | */ |
974 | ||
0e078e2f TG |
975 | /* |
976 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
977 | */ | |
978 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 979 | { |
0e078e2f TG |
980 | unsigned int v; |
981 | exit_idle(); | |
982 | irq_enter(); | |
1da177e4 | 983 | /* |
0e078e2f TG |
984 | * Check if this really is a spurious interrupt and ACK it |
985 | * if it is a vectored one. Just in case... | |
986 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 987 | */ |
0e078e2f TG |
988 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
989 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
990 | ack_APIC_irq(); | |
c4d58cbd | 991 | |
0e078e2f TG |
992 | add_pda(irq_spurious_count, 1); |
993 | irq_exit(); | |
994 | } | |
1da177e4 | 995 | |
0e078e2f TG |
996 | /* |
997 | * This interrupt should never happen with our APIC/SMP architecture | |
998 | */ | |
999 | asmlinkage void smp_error_interrupt(void) | |
1000 | { | |
1001 | unsigned int v, v1; | |
1da177e4 | 1002 | |
0e078e2f TG |
1003 | exit_idle(); |
1004 | irq_enter(); | |
1005 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1006 | v = apic_read(APIC_ESR); | |
1007 | apic_write(APIC_ESR, 0); | |
1008 | v1 = apic_read(APIC_ESR); | |
1009 | ack_APIC_irq(); | |
1010 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1011 | |
0e078e2f TG |
1012 | /* Here is what the APIC error bits mean: |
1013 | 0: Send CS error | |
1014 | 1: Receive CS error | |
1015 | 2: Send accept error | |
1016 | 3: Receive accept error | |
1017 | 4: Reserved | |
1018 | 5: Send illegal vector | |
1019 | 6: Received illegal vector | |
1020 | 7: Illegal register address | |
1021 | */ | |
1022 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1023 | smp_processor_id(), v , v1); | |
1024 | irq_exit(); | |
1da177e4 LT |
1025 | } |
1026 | ||
0e078e2f | 1027 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1028 | { |
0e078e2f TG |
1029 | /* Go back to Virtual Wire compatibility mode */ |
1030 | unsigned long value; | |
1da177e4 | 1031 | |
0e078e2f TG |
1032 | /* For the spurious interrupt use vector F, and enable it */ |
1033 | value = apic_read(APIC_SPIV); | |
1034 | value &= ~APIC_VECTOR_MASK; | |
1035 | value |= APIC_SPIV_APIC_ENABLED; | |
1036 | value |= 0xf; | |
1037 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1038 | |
0e078e2f TG |
1039 | if (!virt_wire_setup) { |
1040 | /* | |
1041 | * For LVT0 make it edge triggered, active high, | |
1042 | * external and enabled | |
1043 | */ | |
1044 | value = apic_read(APIC_LVT0); | |
1045 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1046 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1047 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1048 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1049 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1050 | apic_write(APIC_LVT0, value); | |
1051 | } else { | |
1052 | /* Disable LVT0 */ | |
1053 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1054 | } | |
b8ce3359 | 1055 | |
0e078e2f TG |
1056 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ |
1057 | value = apic_read(APIC_LVT1); | |
1058 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1059 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1060 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1061 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1062 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1063 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1064 | } |
1065 | ||
be8a5685 AS |
1066 | void __cpuinit generic_processor_info(int apicid, int version) |
1067 | { | |
1068 | int cpu; | |
1069 | cpumask_t tmp_map; | |
1070 | ||
1071 | if (num_processors >= NR_CPUS) { | |
1072 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1073 | " Processor ignored.\n", NR_CPUS); | |
1074 | return; | |
1075 | } | |
1076 | ||
1077 | if (num_processors >= maxcpus) { | |
1078 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
1079 | " Processor ignored.\n", maxcpus); | |
1080 | return; | |
1081 | } | |
1082 | ||
1083 | num_processors++; | |
1084 | cpus_complement(tmp_map, cpu_present_map); | |
1085 | cpu = first_cpu(tmp_map); | |
1086 | ||
1087 | physid_set(apicid, phys_cpu_present_map); | |
1088 | if (apicid == boot_cpu_physical_apicid) { | |
1089 | /* | |
1090 | * x86_bios_cpu_apicid is required to have processors listed | |
1091 | * in same order as logical cpu numbers. Hence the first | |
1092 | * entry is BSP, and so on. | |
1093 | */ | |
1094 | cpu = 0; | |
1095 | } | |
e0da3364 YL |
1096 | if (apicid > max_physical_apicid) |
1097 | max_physical_apicid = apicid; | |
1098 | ||
be8a5685 AS |
1099 | /* are we being called early in kernel startup? */ |
1100 | if (x86_cpu_to_apicid_early_ptr) { | |
1101 | u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr; | |
1102 | u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr; | |
1103 | ||
1104 | cpu_to_apicid[cpu] = apicid; | |
1105 | bios_cpu_apicid[cpu] = apicid; | |
1106 | } else { | |
1107 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1108 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1109 | } | |
1110 | ||
1111 | cpu_set(cpu, cpu_possible_map); | |
1112 | cpu_set(cpu, cpu_present_map); | |
1113 | } | |
1114 | ||
89039b37 | 1115 | /* |
0e078e2f | 1116 | * Power management |
89039b37 | 1117 | */ |
0e078e2f TG |
1118 | #ifdef CONFIG_PM |
1119 | ||
1120 | static struct { | |
1121 | /* 'active' is true if the local APIC was enabled by us and | |
1122 | not the BIOS; this signifies that we are also responsible | |
1123 | for disabling it before entering apm/acpi suspend */ | |
1124 | int active; | |
1125 | /* r/w apic fields */ | |
1126 | unsigned int apic_id; | |
1127 | unsigned int apic_taskpri; | |
1128 | unsigned int apic_ldr; | |
1129 | unsigned int apic_dfr; | |
1130 | unsigned int apic_spiv; | |
1131 | unsigned int apic_lvtt; | |
1132 | unsigned int apic_lvtpc; | |
1133 | unsigned int apic_lvt0; | |
1134 | unsigned int apic_lvt1; | |
1135 | unsigned int apic_lvterr; | |
1136 | unsigned int apic_tmict; | |
1137 | unsigned int apic_tdcr; | |
1138 | unsigned int apic_thmr; | |
1139 | } apic_pm_state; | |
1140 | ||
1141 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1142 | { | |
1143 | unsigned long flags; | |
1144 | int maxlvt; | |
89039b37 | 1145 | |
0e078e2f TG |
1146 | if (!apic_pm_state.active) |
1147 | return 0; | |
89039b37 | 1148 | |
0e078e2f | 1149 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1150 | |
05f2d12c | 1151 | apic_pm_state.apic_id = read_apic_id(); |
0e078e2f TG |
1152 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1153 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1154 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1155 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1156 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1157 | if (maxlvt >= 4) | |
1158 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1159 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1160 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1161 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1162 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1163 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1164 | #ifdef CONFIG_X86_MCE_INTEL | |
1165 | if (maxlvt >= 5) | |
1166 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1167 | #endif | |
1168 | local_irq_save(flags); | |
1169 | disable_local_APIC(); | |
1170 | local_irq_restore(flags); | |
1171 | return 0; | |
1da177e4 LT |
1172 | } |
1173 | ||
0e078e2f | 1174 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1175 | { |
0e078e2f TG |
1176 | unsigned int l, h; |
1177 | unsigned long flags; | |
1178 | int maxlvt; | |
1da177e4 | 1179 | |
0e078e2f TG |
1180 | if (!apic_pm_state.active) |
1181 | return 0; | |
89b831ef | 1182 | |
0e078e2f | 1183 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1184 | |
0e078e2f TG |
1185 | local_irq_save(flags); |
1186 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1187 | l &= ~MSR_IA32_APICBASE_BASE; | |
1188 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1189 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1190 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1191 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1192 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1193 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1194 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1195 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1196 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1197 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1198 | #ifdef CONFIG_X86_MCE_INTEL | |
1199 | if (maxlvt >= 5) | |
1200 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1201 | #endif | |
1202 | if (maxlvt >= 4) | |
1203 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1204 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1205 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1206 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1207 | apic_write(APIC_ESR, 0); | |
1208 | apic_read(APIC_ESR); | |
1209 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1210 | apic_write(APIC_ESR, 0); | |
1211 | apic_read(APIC_ESR); | |
1212 | local_irq_restore(flags); | |
1213 | return 0; | |
1214 | } | |
b8ce3359 | 1215 | |
0e078e2f TG |
1216 | static struct sysdev_class lapic_sysclass = { |
1217 | .name = "lapic", | |
1218 | .resume = lapic_resume, | |
1219 | .suspend = lapic_suspend, | |
1220 | }; | |
b8ce3359 | 1221 | |
0e078e2f | 1222 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1223 | .id = 0, |
1224 | .cls = &lapic_sysclass, | |
0e078e2f | 1225 | }; |
b8ce3359 | 1226 | |
0e078e2f TG |
1227 | static void __cpuinit apic_pm_activate(void) |
1228 | { | |
1229 | apic_pm_state.active = 1; | |
1da177e4 LT |
1230 | } |
1231 | ||
0e078e2f | 1232 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1233 | { |
0e078e2f | 1234 | int error; |
e83a5fdc | 1235 | |
0e078e2f TG |
1236 | if (!cpu_has_apic) |
1237 | return 0; | |
1238 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1239 | |
0e078e2f TG |
1240 | error = sysdev_class_register(&lapic_sysclass); |
1241 | if (!error) | |
1242 | error = sysdev_register(&device_lapic); | |
1243 | return error; | |
1da177e4 | 1244 | } |
0e078e2f TG |
1245 | device_initcall(init_lapic_sysfs); |
1246 | ||
1247 | #else /* CONFIG_PM */ | |
1248 | ||
1249 | static void apic_pm_activate(void) { } | |
1250 | ||
1251 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1252 | |
1253 | /* | |
f8bf3c65 | 1254 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1255 | * |
1256 | * Thus far, the major user of this is IBM's Summit2 series: | |
1257 | * | |
637029c6 | 1258 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1259 | * multi-chassis. Use available data to take a good guess. |
1260 | * If in doubt, go HPET. | |
1261 | */ | |
f8bf3c65 | 1262 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1263 | { |
1264 | int i, clusters, zeros; | |
1265 | unsigned id; | |
322850af | 1266 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1267 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1268 | ||
322850af YL |
1269 | /* |
1270 | * there is not this kind of box with AMD CPU yet. | |
1271 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1272 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1273 | * vsmp box still need checking... |
322850af | 1274 | */ |
1cb68487 | 1275 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1276 | return 0; |
1277 | ||
1278 | bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr; | |
376ec33f | 1279 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1280 | |
1281 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1282 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1283 | if (bios_cpu_apicid) { |
1284 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1285 | } |
1286 | else if (i < nr_cpu_ids) { | |
1287 | if (cpu_present(i)) | |
1288 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1289 | else | |
1290 | continue; | |
1291 | } | |
1292 | else | |
1293 | break; | |
1294 | ||
1da177e4 LT |
1295 | if (id != BAD_APICID) |
1296 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1297 | } | |
1298 | ||
1299 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1300 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1301 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1302 | * Since clusters are allocated sequentially, count zeros only if | |
1303 | * they are bounded by ones. | |
1da177e4 LT |
1304 | */ |
1305 | clusters = 0; | |
1306 | zeros = 0; | |
1307 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1308 | if (test_bit(i, clustermap)) { | |
1309 | clusters += 1 + zeros; | |
1310 | zeros = 0; | |
1311 | } else | |
1312 | ++zeros; | |
1313 | } | |
1314 | ||
1cb68487 RT |
1315 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1316 | * not guaranteed to be synced between boards | |
1317 | */ | |
1318 | if (is_vsmp_box() && clusters > 1) | |
1319 | return 1; | |
1320 | ||
1da177e4 | 1321 | /* |
f8bf3c65 | 1322 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1323 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1324 | * out, but AFAIK this will work even for them. | |
1325 | */ | |
1326 | return (clusters > 2); | |
1327 | } | |
1328 | ||
1329 | /* | |
0e078e2f | 1330 | * APIC command line parameters |
1da177e4 | 1331 | */ |
0e078e2f | 1332 | static int __init apic_set_verbosity(char *str) |
1da177e4 | 1333 | { |
0e078e2f TG |
1334 | if (str == NULL) { |
1335 | skip_ioapic_setup = 0; | |
1336 | ioapic_force = 1; | |
1337 | return 0; | |
1da177e4 | 1338 | } |
0e078e2f TG |
1339 | if (strcmp("debug", str) == 0) |
1340 | apic_verbosity = APIC_DEBUG; | |
1341 | else if (strcmp("verbose", str) == 0) | |
1342 | apic_verbosity = APIC_VERBOSE; | |
1343 | else { | |
1344 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1345 | " use apic=verbose or apic=debug\n", str); | |
1346 | return -EINVAL; | |
1da177e4 LT |
1347 | } |
1348 | ||
1da177e4 LT |
1349 | return 0; |
1350 | } | |
0e078e2f | 1351 | early_param("apic", apic_set_verbosity); |
1da177e4 | 1352 | |
6935d1f9 TG |
1353 | static __init int setup_disableapic(char *str) |
1354 | { | |
1da177e4 | 1355 | disable_apic = 1; |
53756d37 | 1356 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
2c8c0e6b AK |
1357 | return 0; |
1358 | } | |
1359 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1360 | |
2c8c0e6b | 1361 | /* same as disableapic, for compatibility */ |
6935d1f9 TG |
1362 | static __init int setup_nolapic(char *str) |
1363 | { | |
2c8c0e6b | 1364 | return setup_disableapic(str); |
6935d1f9 | 1365 | } |
2c8c0e6b | 1366 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1367 | |
2e7c2838 LT |
1368 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1369 | { | |
1370 | local_apic_timer_c2_ok = 1; | |
1371 | return 0; | |
1372 | } | |
1373 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1374 | ||
6935d1f9 TG |
1375 | static __init int setup_noapictimer(char *str) |
1376 | { | |
73dea47f | 1377 | if (str[0] != ' ' && str[0] != 0) |
9b41046c | 1378 | return 0; |
1da177e4 | 1379 | disable_apic_timer = 1; |
9b41046c | 1380 | return 1; |
6935d1f9 | 1381 | } |
9f75e9b7 | 1382 | __setup("noapictimer", setup_noapictimer); |
73dea47f | 1383 | |
0c3749c4 AK |
1384 | static __init int setup_apicpmtimer(char *s) |
1385 | { | |
1386 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1387 | notsc_setup(NULL); |
b8ce3359 | 1388 | return 0; |
0c3749c4 AK |
1389 | } |
1390 | __setup("apicpmtimer", setup_apicpmtimer); | |
1391 | ||
1e934dda YL |
1392 | static int __init lapic_insert_resource(void) |
1393 | { | |
1394 | if (!apic_phys) | |
1395 | return -1; | |
1396 | ||
1397 | /* Put local APIC into the resource map. */ | |
1398 | lapic_resource.start = apic_phys; | |
1399 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1400 | insert_resource(&iomem_resource, &lapic_resource); | |
1401 | ||
1402 | return 0; | |
1403 | } | |
1404 | ||
1405 | /* | |
1406 | * need call insert after e820_reserve_resources() | |
1407 | * that is using request_resource | |
1408 | */ | |
1409 | late_initcall(lapic_insert_resource); |