Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
6e1cb38a | 30 | #include <linux/dmar.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
efa2559f | 36 | #include <asm/desc.h> |
e83a5fdc | 37 | #include <asm/hpet.h> |
1da177e4 | 38 | #include <asm/pgalloc.h> |
75152114 | 39 | #include <asm/nmi.h> |
95833c83 | 40 | #include <asm/idle.h> |
73dea47f AK |
41 | #include <asm/proto.h> |
42 | #include <asm/timex.h> | |
2c8c0e6b | 43 | #include <asm/apic.h> |
6e1cb38a | 44 | #include <asm/i8259.h> |
1da177e4 | 45 | |
5af5573e | 46 | #include <mach_ipi.h> |
dd46e3ca | 47 | #include <mach_apic.h> |
5af5573e | 48 | |
80e5609c CG |
49 | /* |
50 | * Sanity check | |
51 | */ | |
52 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | |
53 | # error SPURIOUS_APIC_VECTOR definition error | |
54 | #endif | |
55 | ||
b3c51170 YL |
56 | #ifdef CONFIG_X86_32 |
57 | /* | |
58 | * Knob to control our willingness to enable the local APIC. | |
59 | * | |
60 | * +1=force-enable | |
61 | */ | |
62 | static int force_enable_local_apic; | |
63 | /* | |
64 | * APIC command line parameters | |
65 | */ | |
66 | static int __init parse_lapic(char *arg) | |
67 | { | |
68 | force_enable_local_apic = 1; | |
69 | return 0; | |
70 | } | |
71 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
72 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
73 | static int enabled_via_apicbase; | |
74 | ||
b3c51170 YL |
75 | #endif |
76 | ||
77 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 78 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
79 | static __init int setup_apicpmtimer(char *s) |
80 | { | |
81 | apic_calibrate_pmtmr = 1; | |
82 | notsc_setup(NULL); | |
83 | return 0; | |
84 | } | |
85 | __setup("apicpmtimer", setup_apicpmtimer); | |
86 | #endif | |
87 | ||
49899eac YL |
88 | #ifdef CONFIG_X86_64 |
89 | #define HAVE_X2APIC | |
90 | #endif | |
91 | ||
92 | #ifdef HAVE_X2APIC | |
89027d35 | 93 | int x2apic; |
6e1cb38a SS |
94 | /* x2apic enabled before OS handover */ |
95 | int x2apic_preenabled; | |
49899eac YL |
96 | int disable_x2apic; |
97 | static __init int setup_nox2apic(char *str) | |
98 | { | |
99 | disable_x2apic = 1; | |
100 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
101 | return 0; | |
102 | } | |
103 | early_param("nox2apic", setup_nox2apic); | |
104 | #endif | |
1da177e4 | 105 | |
b3c51170 YL |
106 | unsigned long mp_lapic_addr; |
107 | int disable_apic; | |
108 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
109 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 110 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
111 | int local_apic_timer_c2_ok; |
112 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
113 | ||
efa2559f YL |
114 | int first_system_vector = 0xfe; |
115 | ||
116 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
117 | ||
e83a5fdc HS |
118 | /* |
119 | * Debug level, exported for io_apic.c | |
120 | */ | |
baa13188 | 121 | unsigned int apic_verbosity; |
e83a5fdc | 122 | |
89c38c28 CG |
123 | int pic_mode; |
124 | ||
bab4b27c AS |
125 | /* Have we found an MP table */ |
126 | int smp_found_config; | |
127 | ||
39928722 AD |
128 | static struct resource lapic_resource = { |
129 | .name = "Local APIC", | |
130 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
131 | }; | |
132 | ||
d03030e9 TG |
133 | static unsigned int calibration_result; |
134 | ||
ba7eda4c TG |
135 | static int lapic_next_event(unsigned long delta, |
136 | struct clock_event_device *evt); | |
137 | static void lapic_timer_setup(enum clock_event_mode mode, | |
138 | struct clock_event_device *evt); | |
ba7eda4c | 139 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 140 | static void apic_pm_activate(void); |
ba7eda4c | 141 | |
274cfe59 CG |
142 | /* |
143 | * The local apic timer can be used for any function which is CPU local. | |
144 | */ | |
ba7eda4c TG |
145 | static struct clock_event_device lapic_clockevent = { |
146 | .name = "lapic", | |
147 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
148 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
149 | .shift = 32, | |
150 | .set_mode = lapic_timer_setup, | |
151 | .set_next_event = lapic_next_event, | |
152 | .broadcast = lapic_timer_broadcast, | |
153 | .rating = 100, | |
154 | .irq = -1, | |
155 | }; | |
156 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
157 | ||
d3432896 AK |
158 | static unsigned long apic_phys; |
159 | ||
0e078e2f TG |
160 | /* |
161 | * Get the LAPIC version | |
162 | */ | |
163 | static inline int lapic_get_version(void) | |
ba7eda4c | 164 | { |
0e078e2f | 165 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
166 | } |
167 | ||
0e078e2f | 168 | /* |
9c803869 | 169 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
170 | */ |
171 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 172 | { |
9c803869 | 173 | #ifdef CONFIG_X86_64 |
0e078e2f | 174 | return 1; |
9c803869 CG |
175 | #else |
176 | return APIC_INTEGRATED(lapic_get_version()); | |
177 | #endif | |
ba7eda4c TG |
178 | } |
179 | ||
180 | /* | |
0e078e2f | 181 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 182 | */ |
0e078e2f | 183 | static int modern_apic(void) |
ba7eda4c | 184 | { |
0e078e2f TG |
185 | /* AMD systems use old APIC versions, so check the CPU */ |
186 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
187 | boot_cpu_data.x86 >= 0xf) | |
188 | return 1; | |
189 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
190 | } |
191 | ||
274cfe59 CG |
192 | /* |
193 | * Paravirt kernels also might be using these below ops. So we still | |
194 | * use generic apic_read()/apic_write(), which might be pointing to different | |
195 | * ops in PARAVIRT case. | |
196 | */ | |
1b374e4d | 197 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
198 | { |
199 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
200 | cpu_relax(); | |
201 | } | |
202 | ||
1b374e4d | 203 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 204 | { |
3c6bb07a | 205 | u32 send_status; |
8339e9fb FLV |
206 | int timeout; |
207 | ||
208 | timeout = 0; | |
209 | do { | |
210 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
211 | if (!send_status) | |
212 | break; | |
213 | udelay(100); | |
214 | } while (timeout++ < 1000); | |
215 | ||
216 | return send_status; | |
217 | } | |
218 | ||
1b374e4d SS |
219 | void xapic_icr_write(u32 low, u32 id) |
220 | { | |
ed4e5ec1 | 221 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
222 | apic_write(APIC_ICR, low); |
223 | } | |
224 | ||
225 | u64 xapic_icr_read(void) | |
226 | { | |
227 | u32 icr1, icr2; | |
228 | ||
229 | icr2 = apic_read(APIC_ICR2); | |
230 | icr1 = apic_read(APIC_ICR); | |
231 | ||
cf9768d7 | 232 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
233 | } |
234 | ||
235 | static struct apic_ops xapic_ops = { | |
236 | .read = native_apic_mem_read, | |
237 | .write = native_apic_mem_write, | |
1b374e4d SS |
238 | .icr_read = xapic_icr_read, |
239 | .icr_write = xapic_icr_write, | |
240 | .wait_icr_idle = xapic_wait_icr_idle, | |
241 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
242 | }; | |
243 | ||
244 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
245 | EXPORT_SYMBOL_GPL(apic_ops); |
246 | ||
49899eac | 247 | #ifdef HAVE_X2APIC |
13c88fb5 SS |
248 | static void x2apic_wait_icr_idle(void) |
249 | { | |
250 | /* no need to wait for icr idle in x2apic */ | |
251 | return; | |
252 | } | |
253 | ||
254 | static u32 safe_x2apic_wait_icr_idle(void) | |
255 | { | |
256 | /* no need to wait for icr idle in x2apic */ | |
257 | return 0; | |
258 | } | |
259 | ||
260 | void x2apic_icr_write(u32 low, u32 id) | |
261 | { | |
262 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
263 | } | |
264 | ||
265 | u64 x2apic_icr_read(void) | |
266 | { | |
267 | unsigned long val; | |
268 | ||
269 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
270 | return val; | |
271 | } | |
272 | ||
273 | static struct apic_ops x2apic_ops = { | |
274 | .read = native_apic_msr_read, | |
275 | .write = native_apic_msr_write, | |
13c88fb5 SS |
276 | .icr_read = x2apic_icr_read, |
277 | .icr_write = x2apic_icr_write, | |
278 | .wait_icr_idle = x2apic_wait_icr_idle, | |
279 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
280 | }; | |
49899eac | 281 | #endif |
13c88fb5 | 282 | |
0e078e2f TG |
283 | /** |
284 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
285 | */ | |
e9427101 | 286 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 287 | { |
11a8e778 | 288 | unsigned int v; |
6935d1f9 TG |
289 | |
290 | /* unmask and set to NMI */ | |
291 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
292 | |
293 | /* Level triggered for 82489DX (32bit mode) */ | |
294 | if (!lapic_is_integrated()) | |
295 | v |= APIC_LVT_LEVEL_TRIGGER; | |
296 | ||
11a8e778 | 297 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
298 | } |
299 | ||
7c37e48b CG |
300 | #ifdef CONFIG_X86_32 |
301 | /** | |
302 | * get_physical_broadcast - Get number of physical broadcast IDs | |
303 | */ | |
304 | int get_physical_broadcast(void) | |
305 | { | |
306 | return modern_apic() ? 0xff : 0xf; | |
307 | } | |
308 | #endif | |
309 | ||
0e078e2f TG |
310 | /** |
311 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
312 | */ | |
37e650c7 | 313 | int lapic_get_maxlvt(void) |
1da177e4 | 314 | { |
36a028de | 315 | unsigned int v; |
1da177e4 LT |
316 | |
317 | v = apic_read(APIC_LVR); | |
36a028de CG |
318 | /* |
319 | * - we always have APIC integrated on 64bit mode | |
320 | * - 82489DXs do not report # of LVT entries | |
321 | */ | |
322 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
323 | } |
324 | ||
274cfe59 CG |
325 | /* |
326 | * Local APIC timer | |
327 | */ | |
328 | ||
c40aaec6 CG |
329 | /* Clock divisor */ |
330 | #ifdef CONFG_X86_64 | |
f07f4f90 | 331 | #define APIC_DIVISOR 1 |
c40aaec6 CG |
332 | #else |
333 | #define APIC_DIVISOR 16 | |
334 | #endif | |
f07f4f90 | 335 | |
0e078e2f TG |
336 | /* |
337 | * This function sets up the local APIC timer, with a timeout of | |
338 | * 'clocks' APIC bus clock. During calibration we actually call | |
339 | * this function twice on the boot CPU, once with a bogus timeout | |
340 | * value, second time for real. The other (noncalibrating) CPUs | |
341 | * call this function only once, with the real, calibrated value. | |
342 | * | |
343 | * We do reads before writes even if unnecessary, to get around the | |
344 | * P5 APIC double write bug. | |
345 | */ | |
0e078e2f | 346 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 347 | { |
0e078e2f | 348 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 349 | |
0e078e2f TG |
350 | lvtt_value = LOCAL_TIMER_VECTOR; |
351 | if (!oneshot) | |
352 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
353 | if (!lapic_is_integrated()) |
354 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
355 | ||
0e078e2f TG |
356 | if (!irqen) |
357 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 358 | |
0e078e2f | 359 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
360 | |
361 | /* | |
0e078e2f | 362 | * Divide PICLK by 16 |
1da177e4 | 363 | */ |
0e078e2f | 364 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
365 | apic_write(APIC_TDCR, |
366 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
367 | APIC_TDR_DIV_16); | |
0e078e2f TG |
368 | |
369 | if (!oneshot) | |
f07f4f90 | 370 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
371 | } |
372 | ||
0e078e2f | 373 | /* |
7b83dae7 RR |
374 | * Setup extended LVT, AMD specific (K8, family 10h) |
375 | * | |
376 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
377 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
378 | * |
379 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
380 | * enables the vector. See also the BKDGs. | |
0e078e2f | 381 | */ |
7b83dae7 RR |
382 | |
383 | #define APIC_EILVT_LVTOFF_MCE 0 | |
384 | #define APIC_EILVT_LVTOFF_IBS 1 | |
385 | ||
386 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 387 | { |
7b83dae7 | 388 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 389 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 390 | |
0e078e2f | 391 | apic_write(reg, v); |
1da177e4 LT |
392 | } |
393 | ||
7b83dae7 RR |
394 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
395 | { | |
396 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
397 | return APIC_EILVT_LVTOFF_MCE; | |
398 | } | |
399 | ||
400 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
401 | { | |
402 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
403 | return APIC_EILVT_LVTOFF_IBS; | |
404 | } | |
6aa360e6 | 405 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 406 | |
0e078e2f TG |
407 | /* |
408 | * Program the next event, relative to now | |
409 | */ | |
410 | static int lapic_next_event(unsigned long delta, | |
411 | struct clock_event_device *evt) | |
1da177e4 | 412 | { |
0e078e2f TG |
413 | apic_write(APIC_TMICT, delta); |
414 | return 0; | |
1da177e4 LT |
415 | } |
416 | ||
0e078e2f TG |
417 | /* |
418 | * Setup the lapic timer in periodic or oneshot mode | |
419 | */ | |
420 | static void lapic_timer_setup(enum clock_event_mode mode, | |
421 | struct clock_event_device *evt) | |
9b7711f0 HS |
422 | { |
423 | unsigned long flags; | |
0e078e2f | 424 | unsigned int v; |
9b7711f0 | 425 | |
0e078e2f TG |
426 | /* Lapic used as dummy for broadcast ? */ |
427 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
428 | return; |
429 | ||
430 | local_irq_save(flags); | |
431 | ||
0e078e2f TG |
432 | switch (mode) { |
433 | case CLOCK_EVT_MODE_PERIODIC: | |
434 | case CLOCK_EVT_MODE_ONESHOT: | |
435 | __setup_APIC_LVTT(calibration_result, | |
436 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
437 | break; | |
438 | case CLOCK_EVT_MODE_UNUSED: | |
439 | case CLOCK_EVT_MODE_SHUTDOWN: | |
440 | v = apic_read(APIC_LVTT); | |
441 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
442 | apic_write(APIC_LVTT, v); | |
443 | break; | |
444 | case CLOCK_EVT_MODE_RESUME: | |
445 | /* Nothing to do here */ | |
446 | break; | |
447 | } | |
9b7711f0 HS |
448 | |
449 | local_irq_restore(flags); | |
450 | } | |
451 | ||
1da177e4 | 452 | /* |
0e078e2f | 453 | * Local APIC timer broadcast function |
1da177e4 | 454 | */ |
0e078e2f | 455 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 456 | { |
0e078e2f TG |
457 | #ifdef CONFIG_SMP |
458 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
459 | #endif | |
460 | } | |
1da177e4 | 461 | |
0e078e2f TG |
462 | /* |
463 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
464 | * of the boot CPU and register the clock event in the framework. | |
465 | */ | |
db4b5525 | 466 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
467 | { |
468 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 469 | |
0e078e2f TG |
470 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
471 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 472 | |
0e078e2f TG |
473 | clockevents_register_device(levt); |
474 | } | |
1da177e4 | 475 | |
0e078e2f TG |
476 | /* |
477 | * In this function we calibrate APIC bus clocks to the external | |
478 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
479 | * to calibrate, since some later bootup code depends on getting | |
480 | * the first irq? Ugh. | |
481 | * | |
482 | * We want to do the calibration only once since we | |
483 | * want to have local timer irqs syncron. CPUs connected | |
484 | * by the same APIC bus have the very same bus frequency. | |
485 | * And we want to have irqs off anyways, no accidental | |
486 | * APIC irq that way. | |
487 | */ | |
488 | ||
489 | #define TICK_COUNT 100000000 | |
490 | ||
89b3b1f4 | 491 | static int __init calibrate_APIC_clock(void) |
0e078e2f TG |
492 | { |
493 | unsigned apic, apic_start; | |
494 | unsigned long tsc, tsc_start; | |
495 | int result; | |
496 | ||
497 | local_irq_disable(); | |
498 | ||
499 | /* | |
500 | * Put whatever arbitrary (but long enough) timeout | |
501 | * value into the APIC clock, we just want to get the | |
502 | * counter running for calibration. | |
503 | * | |
504 | * No interrupt enable ! | |
505 | */ | |
506 | __setup_APIC_LVTT(250000000, 0, 0); | |
507 | ||
508 | apic_start = apic_read(APIC_TMCCT); | |
509 | #ifdef CONFIG_X86_PM_TIMER | |
510 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
511 | pmtimer_wait(5000); /* 5ms wait */ | |
512 | apic = apic_read(APIC_TMCCT); | |
513 | result = (apic_start - apic) * 1000L / 5; | |
514 | } else | |
515 | #endif | |
516 | { | |
517 | rdtscll(tsc_start); | |
518 | ||
519 | do { | |
520 | apic = apic_read(APIC_TMCCT); | |
521 | rdtscll(tsc); | |
522 | } while ((tsc - tsc_start) < TICK_COUNT && | |
523 | (apic_start - apic) < TICK_COUNT); | |
524 | ||
525 | result = (apic_start - apic) * 1000L * tsc_khz / | |
526 | (tsc - tsc_start); | |
527 | } | |
528 | ||
529 | local_irq_enable(); | |
530 | ||
531 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
532 | ||
533 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
534 | result / 1000 / 1000, result / 1000 % 1000); | |
535 | ||
536 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
537 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
538 | lapic_clockevent.shift); | |
0e078e2f TG |
539 | lapic_clockevent.max_delta_ns = |
540 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
541 | lapic_clockevent.min_delta_ns = | |
542 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
543 | ||
f07f4f90 | 544 | calibration_result = (result * APIC_DIVISOR) / HZ; |
89b3b1f4 CG |
545 | |
546 | /* | |
547 | * Do a sanity check on the APIC calibration result | |
548 | */ | |
549 | if (calibration_result < (1000000 / HZ)) { | |
550 | printk(KERN_WARNING | |
551 | "APIC frequency too slow, disabling apic timer\n"); | |
552 | return -1; | |
553 | } | |
554 | ||
555 | return 0; | |
0e078e2f TG |
556 | } |
557 | ||
e83a5fdc HS |
558 | /* |
559 | * Setup the boot APIC | |
560 | * | |
561 | * Calibrate and verify the result. | |
562 | */ | |
0e078e2f TG |
563 | void __init setup_boot_APIC_clock(void) |
564 | { | |
565 | /* | |
274cfe59 CG |
566 | * The local apic timer can be disabled via the kernel |
567 | * commandline or from the CPU detection code. Register the lapic | |
568 | * timer as a dummy clock event source on SMP systems, so the | |
569 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
570 | */ |
571 | if (disable_apic_timer) { | |
572 | printk(KERN_INFO "Disabling APIC timer\n"); | |
573 | /* No broadcast on UP ! */ | |
9d09951d TG |
574 | if (num_possible_cpus() > 1) { |
575 | lapic_clockevent.mult = 1; | |
0e078e2f | 576 | setup_APIC_timer(); |
9d09951d | 577 | } |
0e078e2f TG |
578 | return; |
579 | } | |
580 | ||
274cfe59 CG |
581 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
582 | "calibrating APIC timer ...\n"); | |
583 | ||
89b3b1f4 | 584 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
585 | /* No broadcast on UP ! */ |
586 | if (num_possible_cpus() > 1) | |
587 | setup_APIC_timer(); | |
588 | return; | |
589 | } | |
590 | ||
0e078e2f TG |
591 | /* |
592 | * If nmi_watchdog is set to IO_APIC, we need the | |
593 | * PIT/HPET going. Otherwise register lapic as a dummy | |
594 | * device. | |
595 | */ | |
596 | if (nmi_watchdog != NMI_IO_APIC) | |
597 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
598 | else | |
599 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 600 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 601 | |
274cfe59 | 602 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
603 | setup_APIC_timer(); |
604 | } | |
605 | ||
0e078e2f TG |
606 | void __cpuinit setup_secondary_APIC_clock(void) |
607 | { | |
0e078e2f TG |
608 | setup_APIC_timer(); |
609 | } | |
610 | ||
611 | /* | |
612 | * The guts of the apic timer interrupt | |
613 | */ | |
614 | static void local_apic_timer_interrupt(void) | |
615 | { | |
616 | int cpu = smp_processor_id(); | |
617 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
618 | ||
619 | /* | |
620 | * Normally we should not be here till LAPIC has been initialized but | |
621 | * in some cases like kdump, its possible that there is a pending LAPIC | |
622 | * timer interrupt from previous kernel's context and is delivered in | |
623 | * new kernel the moment interrupts are enabled. | |
624 | * | |
625 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
626 | * its possible that when we get here evt->event_handler is NULL. | |
627 | * Check for event_handler being NULL and discard the interrupt as | |
628 | * spurious. | |
629 | */ | |
630 | if (!evt->event_handler) { | |
631 | printk(KERN_WARNING | |
632 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
633 | /* Switch it off */ | |
634 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
635 | return; | |
636 | } | |
637 | ||
638 | /* | |
639 | * the NMI deadlock-detector uses this. | |
640 | */ | |
0b23e8cf | 641 | #ifdef CONFIG_X86_64 |
0e078e2f | 642 | add_pda(apic_timer_irqs, 1); |
0b23e8cf CG |
643 | #else |
644 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
645 | #endif | |
0e078e2f TG |
646 | |
647 | evt->event_handler(evt); | |
648 | } | |
649 | ||
650 | /* | |
651 | * Local APIC timer interrupt. This is the most natural way for doing | |
652 | * local interrupts, but local timer interrupts can be emulated by | |
653 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
654 | * | |
655 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
656 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
657 | */ | |
658 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
659 | { | |
660 | struct pt_regs *old_regs = set_irq_regs(regs); | |
661 | ||
662 | /* | |
663 | * NOTE! We'd better ACK the irq immediately, | |
664 | * because timer handling can be slow. | |
665 | */ | |
666 | ack_APIC_irq(); | |
667 | /* | |
668 | * update_process_times() expects us to have done irq_enter(). | |
669 | * Besides, if we don't timer interrupts ignore the global | |
670 | * interrupt lock, which is the WrongThing (tm) to do. | |
671 | */ | |
6460bc73 | 672 | #ifdef CONFIG_X86_64 |
0e078e2f | 673 | exit_idle(); |
6460bc73 | 674 | #endif |
0e078e2f TG |
675 | irq_enter(); |
676 | local_apic_timer_interrupt(); | |
677 | irq_exit(); | |
274cfe59 | 678 | |
0e078e2f TG |
679 | set_irq_regs(old_regs); |
680 | } | |
681 | ||
682 | int setup_profiling_timer(unsigned int multiplier) | |
683 | { | |
684 | return -EINVAL; | |
685 | } | |
686 | ||
687 | ||
688 | /* | |
689 | * Local APIC start and shutdown | |
690 | */ | |
691 | ||
692 | /** | |
693 | * clear_local_APIC - shutdown the local APIC | |
694 | * | |
695 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
696 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
697 | * leftovers during boot. | |
698 | */ | |
699 | void clear_local_APIC(void) | |
700 | { | |
2584a82d | 701 | int maxlvt; |
0e078e2f TG |
702 | u32 v; |
703 | ||
d3432896 AK |
704 | /* APIC hasn't been mapped yet */ |
705 | if (!apic_phys) | |
706 | return; | |
707 | ||
708 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
709 | /* |
710 | * Masking an LVT entry can trigger a local APIC error | |
711 | * if the vector is zero. Mask LVTERR first to prevent this. | |
712 | */ | |
713 | if (maxlvt >= 3) { | |
714 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
715 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
716 | } | |
717 | /* | |
718 | * Careful: we have to set masks only first to deassert | |
719 | * any level-triggered sources. | |
720 | */ | |
721 | v = apic_read(APIC_LVTT); | |
722 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
723 | v = apic_read(APIC_LVT0); | |
724 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
725 | v = apic_read(APIC_LVT1); | |
726 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
727 | if (maxlvt >= 4) { | |
728 | v = apic_read(APIC_LVTPC); | |
729 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
730 | } | |
731 | ||
6764014b CG |
732 | /* lets not touch this if we didn't frob it */ |
733 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
734 | if (maxlvt >= 5) { | |
735 | v = apic_read(APIC_LVTTHMR); | |
736 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
737 | } | |
738 | #endif | |
0e078e2f TG |
739 | /* |
740 | * Clean APIC state for other OSs: | |
741 | */ | |
742 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
743 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
744 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
745 | if (maxlvt >= 3) | |
746 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
747 | if (maxlvt >= 4) | |
748 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
749 | |
750 | /* Integrated APIC (!82489DX) ? */ | |
751 | if (lapic_is_integrated()) { | |
752 | if (maxlvt > 3) | |
753 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
754 | apic_write(APIC_ESR, 0); | |
755 | apic_read(APIC_ESR); | |
756 | } | |
0e078e2f TG |
757 | } |
758 | ||
759 | /** | |
760 | * disable_local_APIC - clear and disable the local APIC | |
761 | */ | |
762 | void disable_local_APIC(void) | |
763 | { | |
764 | unsigned int value; | |
765 | ||
766 | clear_local_APIC(); | |
767 | ||
768 | /* | |
769 | * Disable APIC (implies clearing of registers | |
770 | * for 82489DX!). | |
771 | */ | |
772 | value = apic_read(APIC_SPIV); | |
773 | value &= ~APIC_SPIV_APIC_ENABLED; | |
774 | apic_write(APIC_SPIV, value); | |
990b183e CG |
775 | |
776 | #ifdef CONFIG_X86_32 | |
777 | /* | |
778 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
779 | * restore the disabled state. | |
780 | */ | |
781 | if (enabled_via_apicbase) { | |
782 | unsigned int l, h; | |
783 | ||
784 | rdmsr(MSR_IA32_APICBASE, l, h); | |
785 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
786 | wrmsr(MSR_IA32_APICBASE, l, h); | |
787 | } | |
788 | #endif | |
0e078e2f TG |
789 | } |
790 | ||
fe4024dc CG |
791 | /* |
792 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
793 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
794 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
795 | * for the case where Linux didn't enable the LAPIC. | |
796 | */ | |
0e078e2f TG |
797 | void lapic_shutdown(void) |
798 | { | |
799 | unsigned long flags; | |
800 | ||
801 | if (!cpu_has_apic) | |
802 | return; | |
803 | ||
804 | local_irq_save(flags); | |
805 | ||
fe4024dc CG |
806 | #ifdef CONFIG_X86_32 |
807 | if (!enabled_via_apicbase) | |
808 | clear_local_APIC(); | |
809 | else | |
810 | #endif | |
811 | disable_local_APIC(); | |
812 | ||
0e078e2f TG |
813 | |
814 | local_irq_restore(flags); | |
815 | } | |
816 | ||
817 | /* | |
818 | * This is to verify that we're looking at a real local APIC. | |
819 | * Check these against your board if the CPUs aren't getting | |
820 | * started for no apparent reason. | |
821 | */ | |
822 | int __init verify_local_APIC(void) | |
823 | { | |
824 | unsigned int reg0, reg1; | |
825 | ||
826 | /* | |
827 | * The version register is read-only in a real APIC. | |
828 | */ | |
829 | reg0 = apic_read(APIC_LVR); | |
830 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
831 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
832 | reg1 = apic_read(APIC_LVR); | |
833 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
834 | ||
835 | /* | |
836 | * The two version reads above should print the same | |
837 | * numbers. If the second one is different, then we | |
838 | * poke at a non-APIC. | |
839 | */ | |
840 | if (reg1 != reg0) | |
841 | return 0; | |
842 | ||
843 | /* | |
844 | * Check if the version looks reasonably. | |
845 | */ | |
846 | reg1 = GET_APIC_VERSION(reg0); | |
847 | if (reg1 == 0x00 || reg1 == 0xff) | |
848 | return 0; | |
849 | reg1 = lapic_get_maxlvt(); | |
850 | if (reg1 < 0x02 || reg1 == 0xff) | |
851 | return 0; | |
852 | ||
853 | /* | |
854 | * The ID register is read/write in a real APIC. | |
855 | */ | |
2d7a66d0 | 856 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
857 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
858 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 859 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
860 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
861 | apic_write(APIC_ID, reg0); | |
862 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
863 | return 0; | |
864 | ||
865 | /* | |
1da177e4 LT |
866 | * The next two are just to see if we have sane values. |
867 | * They're only really relevant if we're in Virtual Wire | |
868 | * compatibility mode, but most boxes are anymore. | |
869 | */ | |
870 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 871 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
872 | reg1 = apic_read(APIC_LVT1); |
873 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
874 | ||
875 | return 1; | |
876 | } | |
877 | ||
0e078e2f TG |
878 | /** |
879 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
880 | */ | |
1da177e4 LT |
881 | void __init sync_Arb_IDs(void) |
882 | { | |
296cb951 CG |
883 | /* |
884 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
885 | * needed on AMD. | |
886 | */ | |
887 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
888 | return; |
889 | ||
890 | /* | |
891 | * Wait for idle. | |
892 | */ | |
893 | apic_wait_icr_idle(); | |
894 | ||
895 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
896 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
897 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
898 | } |
899 | ||
1da177e4 LT |
900 | /* |
901 | * An initial setup of the virtual wire mode. | |
902 | */ | |
903 | void __init init_bsp_APIC(void) | |
904 | { | |
11a8e778 | 905 | unsigned int value; |
1da177e4 LT |
906 | |
907 | /* | |
908 | * Don't do the setup now if we have a SMP BIOS as the | |
909 | * through-I/O-APIC virtual wire mode might be active. | |
910 | */ | |
911 | if (smp_found_config || !cpu_has_apic) | |
912 | return; | |
913 | ||
1da177e4 LT |
914 | /* |
915 | * Do not trust the local APIC being empty at bootup. | |
916 | */ | |
917 | clear_local_APIC(); | |
918 | ||
919 | /* | |
920 | * Enable APIC. | |
921 | */ | |
922 | value = apic_read(APIC_SPIV); | |
923 | value &= ~APIC_VECTOR_MASK; | |
924 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
925 | |
926 | #ifdef CONFIG_X86_32 | |
927 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
928 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
929 | (boot_cpu_data.x86 == 15)) | |
930 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
931 | else | |
932 | #endif | |
933 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 934 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 935 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
936 | |
937 | /* | |
938 | * Set up the virtual wire mode. | |
939 | */ | |
11a8e778 | 940 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 941 | value = APIC_DM_NMI; |
638c0411 CG |
942 | if (!lapic_is_integrated()) /* 82489DX */ |
943 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 944 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
945 | } |
946 | ||
c43da2f5 CG |
947 | static void __cpuinit lapic_setup_esr(void) |
948 | { | |
949 | unsigned long oldvalue, value, maxlvt; | |
950 | if (lapic_is_integrated() && !esr_disable) { | |
951 | if (esr_disable) { | |
952 | /* | |
953 | * Something untraceable is creating bad interrupts on | |
954 | * secondary quads ... for the moment, just leave the | |
955 | * ESR disabled - we can't do anything useful with the | |
956 | * errors anyway - mbligh | |
957 | */ | |
958 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
959 | return; | |
960 | } | |
961 | /* !82489DX */ | |
962 | maxlvt = lapic_get_maxlvt(); | |
963 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
964 | apic_write(APIC_ESR, 0); | |
965 | oldvalue = apic_read(APIC_ESR); | |
966 | ||
967 | /* enables sending errors */ | |
968 | value = ERROR_APIC_VECTOR; | |
969 | apic_write(APIC_LVTERR, value); | |
970 | /* | |
971 | * spec says clear errors after enabling vector. | |
972 | */ | |
973 | if (maxlvt > 3) | |
974 | apic_write(APIC_ESR, 0); | |
975 | value = apic_read(APIC_ESR); | |
976 | if (value != oldvalue) | |
977 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
978 | "vector: 0x%08lx after: 0x%08lx\n", | |
979 | oldvalue, value); | |
980 | } else { | |
981 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
982 | } | |
983 | } | |
984 | ||
985 | ||
0e078e2f TG |
986 | /** |
987 | * setup_local_APIC - setup the local APIC | |
988 | */ | |
989 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 990 | { |
739f33b3 | 991 | unsigned int value; |
da7ed9f9 | 992 | int i, j; |
1da177e4 | 993 | |
89c38c28 CG |
994 | #ifdef CONFIG_X86_32 |
995 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
996 | if (esr_disable) { | |
997 | apic_write(APIC_ESR, 0); | |
998 | apic_write(APIC_ESR, 0); | |
999 | apic_write(APIC_ESR, 0); | |
1000 | apic_write(APIC_ESR, 0); | |
1001 | } | |
1002 | #endif | |
1003 | ||
ac23d4ee | 1004 | preempt_disable(); |
1da177e4 | 1005 | |
1da177e4 LT |
1006 | /* |
1007 | * Double-check whether this APIC is really registered. | |
1008 | * This is meaningless in clustered apic mode, so we skip it. | |
1009 | */ | |
1010 | if (!apic_id_registered()) | |
1011 | BUG(); | |
1012 | ||
1013 | /* | |
1014 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1015 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1016 | * document number 292116). So here it goes... | |
1017 | */ | |
1018 | init_apic_ldr(); | |
1019 | ||
1020 | /* | |
1021 | * Set Task Priority to 'accept all'. We never change this | |
1022 | * later on. | |
1023 | */ | |
1024 | value = apic_read(APIC_TASKPRI); | |
1025 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1026 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1027 | |
da7ed9f9 VG |
1028 | /* |
1029 | * After a crash, we no longer service the interrupts and a pending | |
1030 | * interrupt from previous kernel might still have ISR bit set. | |
1031 | * | |
1032 | * Most probably by now CPU has serviced that pending interrupt and | |
1033 | * it might not have done the ack_APIC_irq() because it thought, | |
1034 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1035 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1036 | * the interrupt. Hence a vector might get locked. It was noticed | |
1037 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1038 | */ | |
1039 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1040 | value = apic_read(APIC_ISR + i*0x10); | |
1041 | for (j = 31; j >= 0; j--) { | |
1042 | if (value & (1<<j)) | |
1043 | ack_APIC_irq(); | |
1044 | } | |
1045 | } | |
1046 | ||
1da177e4 LT |
1047 | /* |
1048 | * Now that we are all set up, enable the APIC | |
1049 | */ | |
1050 | value = apic_read(APIC_SPIV); | |
1051 | value &= ~APIC_VECTOR_MASK; | |
1052 | /* | |
1053 | * Enable APIC | |
1054 | */ | |
1055 | value |= APIC_SPIV_APIC_ENABLED; | |
1056 | ||
89c38c28 CG |
1057 | #ifdef CONFIG_X86_32 |
1058 | /* | |
1059 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1060 | * certain networking cards. If high frequency interrupts are | |
1061 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1062 | * entry is masked/unmasked at a high rate as well then sooner or | |
1063 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1064 | * from the device. If focus CPU is disabled then the hang goes | |
1065 | * away, oh well :-( | |
1066 | * | |
1067 | * [ This bug can be reproduced easily with a level-triggered | |
1068 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1069 | * BX chipset. ] | |
1070 | */ | |
1071 | /* | |
1072 | * Actually disabling the focus CPU check just makes the hang less | |
1073 | * frequent as it makes the interrupt distributon model be more | |
1074 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1075 | * See also the comment in end_level_ioapic_irq(). --macro | |
1076 | */ | |
1077 | ||
1078 | /* | |
1079 | * - enable focus processor (bit==0) | |
1080 | * - 64bit mode always use processor focus | |
1081 | * so no need to set it | |
1082 | */ | |
1083 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1084 | #endif | |
3f14c746 | 1085 | |
1da177e4 LT |
1086 | /* |
1087 | * Set spurious IRQ vector | |
1088 | */ | |
1089 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1090 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1091 | |
1092 | /* | |
1093 | * Set up LVT0, LVT1: | |
1094 | * | |
1095 | * set up through-local-APIC on the BP's LINT0. This is not | |
1096 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1097 | * we delegate interrupts to the 8259A. | |
1098 | */ | |
1099 | /* | |
1100 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1101 | */ | |
1102 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1103 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1104 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1105 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1106 | smp_processor_id()); |
1da177e4 LT |
1107 | } else { |
1108 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1109 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1110 | smp_processor_id()); |
1da177e4 | 1111 | } |
11a8e778 | 1112 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1113 | |
1114 | /* | |
1115 | * only the BP should see the LINT1 NMI signal, obviously. | |
1116 | */ | |
1117 | if (!smp_processor_id()) | |
1118 | value = APIC_DM_NMI; | |
1119 | else | |
1120 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1121 | if (!lapic_is_integrated()) /* 82489DX */ |
1122 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1123 | apic_write(APIC_LVT1, value); |
89c38c28 | 1124 | |
ac23d4ee | 1125 | preempt_enable(); |
739f33b3 | 1126 | } |
1da177e4 | 1127 | |
739f33b3 AK |
1128 | void __cpuinit end_local_APIC_setup(void) |
1129 | { | |
1130 | lapic_setup_esr(); | |
fa6b95fc CG |
1131 | |
1132 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1133 | { |
1134 | unsigned int value; | |
1135 | /* Disable the local apic timer */ | |
1136 | value = apic_read(APIC_LVTT); | |
1137 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1138 | apic_write(APIC_LVTT, value); | |
1139 | } | |
fa6b95fc CG |
1140 | #endif |
1141 | ||
f2802e7f | 1142 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1143 | apic_pm_activate(); |
1da177e4 | 1144 | } |
1da177e4 | 1145 | |
49899eac | 1146 | #ifdef HAVE_X2APIC |
6e1cb38a SS |
1147 | void check_x2apic(void) |
1148 | { | |
1149 | int msr, msr2; | |
1150 | ||
1151 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1152 | ||
1153 | if (msr & X2APIC_ENABLE) { | |
1154 | printk("x2apic enabled by BIOS, switching to x2apic ops\n"); | |
1155 | x2apic_preenabled = x2apic = 1; | |
1156 | apic_ops = &x2apic_ops; | |
1157 | } | |
1158 | } | |
1159 | ||
1160 | void enable_x2apic(void) | |
1161 | { | |
1162 | int msr, msr2; | |
1163 | ||
1164 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1165 | if (!(msr & X2APIC_ENABLE)) { | |
1166 | printk("Enabling x2apic\n"); | |
1167 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); | |
1168 | } | |
1169 | } | |
1170 | ||
1171 | void enable_IR_x2apic(void) | |
1172 | { | |
1173 | #ifdef CONFIG_INTR_REMAP | |
1174 | int ret; | |
1175 | unsigned long flags; | |
1176 | ||
1177 | if (!cpu_has_x2apic) | |
1178 | return; | |
1179 | ||
1180 | if (!x2apic_preenabled && disable_x2apic) { | |
1181 | printk(KERN_INFO | |
1182 | "Skipped enabling x2apic and Interrupt-remapping " | |
1183 | "because of nox2apic\n"); | |
1184 | return; | |
1185 | } | |
1186 | ||
1187 | if (x2apic_preenabled && disable_x2apic) | |
1188 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1189 | ||
1190 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
1191 | printk(KERN_INFO | |
1192 | "Skipped enabling x2apic and Interrupt-remapping " | |
1193 | "because of skipping io-apic setup\n"); | |
1194 | return; | |
1195 | } | |
1196 | ||
1197 | ret = dmar_table_init(); | |
1198 | if (ret) { | |
1199 | printk(KERN_INFO | |
1200 | "dmar_table_init() failed with %d:\n", ret); | |
1201 | ||
1202 | if (x2apic_preenabled) | |
1203 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1204 | else | |
1205 | printk(KERN_INFO | |
1206 | "Not enabling x2apic,Intr-remapping\n"); | |
1207 | return; | |
1208 | } | |
1209 | ||
1210 | local_irq_save(flags); | |
1211 | mask_8259A(); | |
1212 | save_mask_IO_APIC_setup(); | |
1213 | ||
1214 | ret = enable_intr_remapping(1); | |
1215 | ||
1216 | if (ret && x2apic_preenabled) { | |
1217 | local_irq_restore(flags); | |
1218 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1219 | } | |
1220 | ||
1221 | if (ret) | |
1222 | goto end; | |
1223 | ||
1224 | if (!x2apic) { | |
1225 | x2apic = 1; | |
1226 | apic_ops = &x2apic_ops; | |
1227 | enable_x2apic(); | |
1228 | } | |
1229 | end: | |
1230 | if (ret) | |
1231 | /* | |
1232 | * IR enabling failed | |
1233 | */ | |
1234 | restore_IO_APIC_setup(); | |
1235 | else | |
1236 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1237 | ||
1238 | unmask_8259A(); | |
1239 | local_irq_restore(flags); | |
1240 | ||
1241 | if (!ret) { | |
1242 | if (!x2apic_preenabled) | |
1243 | printk(KERN_INFO | |
1244 | "Enabled x2apic and interrupt-remapping\n"); | |
1245 | else | |
1246 | printk(KERN_INFO | |
1247 | "Enabled Interrupt-remapping\n"); | |
1248 | } else | |
1249 | printk(KERN_ERR | |
1250 | "Failed to enable Interrupt-remapping and x2apic\n"); | |
1251 | #else | |
1252 | if (!cpu_has_x2apic) | |
1253 | return; | |
1254 | ||
1255 | if (x2apic_preenabled) | |
1256 | panic("x2apic enabled prior OS handover," | |
1257 | " enable CONFIG_INTR_REMAP"); | |
1258 | ||
1259 | printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " | |
1260 | " and x2apic\n"); | |
1261 | #endif | |
1262 | ||
1263 | return; | |
1264 | } | |
49899eac | 1265 | #endif /* HAVE_X2APIC */ |
6e1cb38a | 1266 | |
1da177e4 LT |
1267 | /* |
1268 | * Detect and enable local APICs on non-SMP boards. | |
1269 | * Original code written by Keir Fraser. | |
1270 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1271 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1272 | */ |
0e078e2f | 1273 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1274 | { |
1275 | if (!cpu_has_apic) { | |
1276 | printk(KERN_INFO "No local APIC present\n"); | |
1277 | return -1; | |
1278 | } | |
1279 | ||
1280 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1281 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1282 | return 0; |
1283 | } | |
1284 | ||
f28c0ae2 | 1285 | #ifdef CONFIG_X86_64 |
8643f9d0 YL |
1286 | void __init early_init_lapic_mapping(void) |
1287 | { | |
431ee79d | 1288 | unsigned long phys_addr; |
8643f9d0 YL |
1289 | |
1290 | /* | |
1291 | * If no local APIC can be found then go out | |
1292 | * : it means there is no mpatable and MADT | |
1293 | */ | |
1294 | if (!smp_found_config) | |
1295 | return; | |
1296 | ||
431ee79d | 1297 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1298 | |
431ee79d | 1299 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1300 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1301 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1302 | |
1303 | /* | |
1304 | * Fetch the APIC ID of the BSP in case we have a | |
1305 | * default configuration (or the MP table is broken). | |
1306 | */ | |
4c9961d5 | 1307 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 | 1308 | } |
f28c0ae2 | 1309 | #endif |
8643f9d0 | 1310 | |
0e078e2f TG |
1311 | /** |
1312 | * init_apic_mappings - initialize APIC mappings | |
1313 | */ | |
1da177e4 LT |
1314 | void __init init_apic_mappings(void) |
1315 | { | |
49899eac | 1316 | #ifdef HAVE_X2APIC |
6e1cb38a | 1317 | if (x2apic) { |
4c9961d5 | 1318 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1319 | return; |
1320 | } | |
49899eac | 1321 | #endif |
6e1cb38a | 1322 | |
1da177e4 LT |
1323 | /* |
1324 | * If no local APIC can be found then set up a fake all | |
1325 | * zeroes page to simulate the local APIC and another | |
1326 | * one for the IO-APIC. | |
1327 | */ | |
1328 | if (!smp_found_config && detect_init_APIC()) { | |
1329 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1330 | apic_phys = __pa(apic_phys); | |
1331 | } else | |
1332 | apic_phys = mp_lapic_addr; | |
1333 | ||
1334 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
1335 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
1336 | APIC_BASE, apic_phys); | |
1da177e4 LT |
1337 | |
1338 | /* | |
1339 | * Fetch the APIC ID of the BSP in case we have a | |
1340 | * default configuration (or the MP table is broken). | |
1341 | */ | |
f28c0ae2 YL |
1342 | if (boot_cpu_physical_apicid == -1U) |
1343 | boot_cpu_physical_apicid = read_apic_id(); | |
1da177e4 LT |
1344 | } |
1345 | ||
1346 | /* | |
0e078e2f TG |
1347 | * This initializes the IO-APIC and APIC hardware if this is |
1348 | * a UP kernel. | |
1da177e4 | 1349 | */ |
1b313f4a CG |
1350 | int apic_version[MAX_APICS]; |
1351 | ||
0e078e2f | 1352 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1353 | { |
fa2bd35a | 1354 | #ifdef CONFIG_X86_64 |
0e078e2f TG |
1355 | if (disable_apic) { |
1356 | printk(KERN_INFO "Apic disabled\n"); | |
1357 | return -1; | |
1358 | } | |
1359 | if (!cpu_has_apic) { | |
1360 | disable_apic = 1; | |
1361 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1362 | return -1; | |
1363 | } | |
fa2bd35a YL |
1364 | #else |
1365 | if (!smp_found_config && !cpu_has_apic) | |
1366 | return -1; | |
1367 | ||
1368 | /* | |
1369 | * Complain if the BIOS pretends there is one. | |
1370 | */ | |
1371 | if (!cpu_has_apic && | |
1372 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1373 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1374 | boot_cpu_physical_apicid); | |
1375 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1376 | return -1; | |
1377 | } | |
1378 | #endif | |
1379 | ||
49899eac | 1380 | #ifdef HAVE_X2APIC |
6e1cb38a | 1381 | enable_IR_x2apic(); |
49899eac | 1382 | #endif |
fa2bd35a | 1383 | #ifdef CONFIG_X86_64 |
6e1cb38a | 1384 | setup_apic_routing(); |
fa2bd35a | 1385 | #endif |
6e1cb38a | 1386 | |
0e078e2f | 1387 | verify_local_APIC(); |
b5841765 GC |
1388 | connect_bsp_APIC(); |
1389 | ||
fa2bd35a | 1390 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1391 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1392 | #else |
1393 | /* | |
1394 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1395 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1396 | * might be zero if read from MP tables. Get it from LAPIC. | |
1397 | */ | |
1398 | # ifdef CONFIG_CRASH_DUMP | |
1399 | boot_cpu_physical_apicid = read_apic_id(); | |
1400 | # endif | |
1401 | #endif | |
1402 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1403 | setup_local_APIC(); |
1da177e4 | 1404 | |
fa2bd35a | 1405 | #ifdef CONFIG_X86_64 |
739f33b3 AK |
1406 | /* |
1407 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1408 | * We need clear_IO_APIC before enabling vector on BP | |
1409 | */ | |
1410 | if (!skip_ioapic_setup && nr_ioapics) | |
1411 | enable_IO_APIC(); | |
fa2bd35a | 1412 | #endif |
739f33b3 | 1413 | |
fa2bd35a | 1414 | #ifdef CONFIG_X86_IO_APIC |
acae7d90 | 1415 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
fa2bd35a | 1416 | #endif |
acae7d90 | 1417 | localise_nmi_watchdog(); |
739f33b3 AK |
1418 | end_local_APIC_setup(); |
1419 | ||
fa2bd35a | 1420 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1421 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1422 | setup_IO_APIC(); | |
fa2bd35a | 1423 | # ifdef CONFIG_X86_64 |
0e078e2f TG |
1424 | else |
1425 | nr_ioapics = 0; | |
fa2bd35a YL |
1426 | # endif |
1427 | #endif | |
1428 | ||
1429 | #ifdef CONFIG_X86_64 | |
0e078e2f TG |
1430 | setup_boot_APIC_clock(); |
1431 | check_nmi_watchdog(); | |
fa2bd35a YL |
1432 | #else |
1433 | setup_boot_clock(); | |
1434 | #endif | |
1435 | ||
0e078e2f | 1436 | return 0; |
1da177e4 LT |
1437 | } |
1438 | ||
1439 | /* | |
0e078e2f | 1440 | * Local APIC interrupts |
1da177e4 LT |
1441 | */ |
1442 | ||
0e078e2f TG |
1443 | /* |
1444 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1445 | */ | |
1446 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 1447 | { |
0e078e2f TG |
1448 | unsigned int v; |
1449 | exit_idle(); | |
1450 | irq_enter(); | |
1da177e4 | 1451 | /* |
0e078e2f TG |
1452 | * Check if this really is a spurious interrupt and ACK it |
1453 | * if it is a vectored one. Just in case... | |
1454 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1455 | */ |
0e078e2f TG |
1456 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1457 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1458 | ack_APIC_irq(); | |
c4d58cbd | 1459 | |
0e078e2f TG |
1460 | add_pda(irq_spurious_count, 1); |
1461 | irq_exit(); | |
1462 | } | |
1da177e4 | 1463 | |
0e078e2f TG |
1464 | /* |
1465 | * This interrupt should never happen with our APIC/SMP architecture | |
1466 | */ | |
1467 | asmlinkage void smp_error_interrupt(void) | |
1468 | { | |
1469 | unsigned int v, v1; | |
1da177e4 | 1470 | |
0e078e2f TG |
1471 | exit_idle(); |
1472 | irq_enter(); | |
1473 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1474 | v = apic_read(APIC_ESR); | |
1475 | apic_write(APIC_ESR, 0); | |
1476 | v1 = apic_read(APIC_ESR); | |
1477 | ack_APIC_irq(); | |
1478 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1479 | |
0e078e2f TG |
1480 | /* Here is what the APIC error bits mean: |
1481 | 0: Send CS error | |
1482 | 1: Receive CS error | |
1483 | 2: Send accept error | |
1484 | 3: Receive accept error | |
1485 | 4: Reserved | |
1486 | 5: Send illegal vector | |
1487 | 6: Received illegal vector | |
1488 | 7: Illegal register address | |
1489 | */ | |
1490 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1491 | smp_processor_id(), v , v1); | |
1492 | irq_exit(); | |
1da177e4 LT |
1493 | } |
1494 | ||
b5841765 | 1495 | /** |
36c9d674 CG |
1496 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1497 | */ | |
b5841765 GC |
1498 | void __init connect_bsp_APIC(void) |
1499 | { | |
36c9d674 CG |
1500 | #ifdef CONFIG_X86_32 |
1501 | if (pic_mode) { | |
1502 | /* | |
1503 | * Do not trust the local APIC being empty at bootup. | |
1504 | */ | |
1505 | clear_local_APIC(); | |
1506 | /* | |
1507 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1508 | * local APIC to INT and NMI lines. | |
1509 | */ | |
1510 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1511 | "enabling APIC mode.\n"); | |
1512 | outb(0x70, 0x22); | |
1513 | outb(0x01, 0x23); | |
1514 | } | |
1515 | #endif | |
b5841765 GC |
1516 | enable_apic_mode(); |
1517 | } | |
1518 | ||
274cfe59 CG |
1519 | /** |
1520 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1521 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1522 | * | |
1523 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1524 | * APIC is disabled. | |
1525 | */ | |
0e078e2f | 1526 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1527 | { |
1b4ee4e4 CG |
1528 | unsigned int value; |
1529 | ||
c177b0bc CG |
1530 | #ifdef CONFIG_X86_32 |
1531 | if (pic_mode) { | |
1532 | /* | |
1533 | * Put the board back into PIC mode (has an effect only on | |
1534 | * certain older boards). Note that APIC interrupts, including | |
1535 | * IPIs, won't work beyond this point! The only exception are | |
1536 | * INIT IPIs. | |
1537 | */ | |
1538 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1539 | "entering PIC mode.\n"); | |
1540 | outb(0x70, 0x22); | |
1541 | outb(0x00, 0x23); | |
1542 | return; | |
1543 | } | |
1544 | #endif | |
1545 | ||
0e078e2f | 1546 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1547 | |
0e078e2f TG |
1548 | /* For the spurious interrupt use vector F, and enable it */ |
1549 | value = apic_read(APIC_SPIV); | |
1550 | value &= ~APIC_VECTOR_MASK; | |
1551 | value |= APIC_SPIV_APIC_ENABLED; | |
1552 | value |= 0xf; | |
1553 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1554 | |
0e078e2f TG |
1555 | if (!virt_wire_setup) { |
1556 | /* | |
1557 | * For LVT0 make it edge triggered, active high, | |
1558 | * external and enabled | |
1559 | */ | |
1560 | value = apic_read(APIC_LVT0); | |
1561 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1562 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1563 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1564 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1565 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1566 | apic_write(APIC_LVT0, value); | |
1567 | } else { | |
1568 | /* Disable LVT0 */ | |
1569 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1570 | } | |
b8ce3359 | 1571 | |
c177b0bc CG |
1572 | /* |
1573 | * For LVT1 make it edge triggered, active high, | |
1574 | * nmi and enabled | |
1575 | */ | |
0e078e2f TG |
1576 | value = apic_read(APIC_LVT1); |
1577 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1578 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1579 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1580 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1581 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1582 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1583 | } |
1584 | ||
be8a5685 AS |
1585 | void __cpuinit generic_processor_info(int apicid, int version) |
1586 | { | |
1587 | int cpu; | |
1588 | cpumask_t tmp_map; | |
1589 | ||
1b313f4a CG |
1590 | /* |
1591 | * Validate version | |
1592 | */ | |
1593 | if (version == 0x0) { | |
1594 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1595 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1596 | version); | |
1597 | version = 0x10; | |
be8a5685 | 1598 | } |
1b313f4a | 1599 | apic_version[apicid] = version; |
be8a5685 | 1600 | |
be8a5685 AS |
1601 | if (num_processors >= NR_CPUS) { |
1602 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1b313f4a | 1603 | " Processor ignored.\n", NR_CPUS); |
be8a5685 AS |
1604 | return; |
1605 | } | |
1606 | ||
1607 | num_processors++; | |
1608 | cpus_complement(tmp_map, cpu_present_map); | |
1609 | cpu = first_cpu(tmp_map); | |
1610 | ||
1611 | physid_set(apicid, phys_cpu_present_map); | |
1612 | if (apicid == boot_cpu_physical_apicid) { | |
1613 | /* | |
1614 | * x86_bios_cpu_apicid is required to have processors listed | |
1615 | * in same order as logical cpu numbers. Hence the first | |
1616 | * entry is BSP, and so on. | |
1617 | */ | |
1618 | cpu = 0; | |
1619 | } | |
e0da3364 YL |
1620 | if (apicid > max_physical_apicid) |
1621 | max_physical_apicid = apicid; | |
1622 | ||
1b313f4a CG |
1623 | #ifdef CONFIG_X86_32 |
1624 | /* | |
1625 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1626 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1627 | * before this can be done without some confusion. | |
1628 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1629 | * - Ashok Raj <ashok.raj@intel.com> | |
1630 | */ | |
1631 | if (max_physical_apicid >= 8) { | |
1632 | switch (boot_cpu_data.x86_vendor) { | |
1633 | case X86_VENDOR_INTEL: | |
1634 | if (!APIC_XAPIC(version)) { | |
1635 | def_to_bigsmp = 0; | |
1636 | break; | |
1637 | } | |
1638 | /* If P4 and above fall through */ | |
1639 | case X86_VENDOR_AMD: | |
1640 | def_to_bigsmp = 1; | |
1641 | } | |
1642 | } | |
1643 | #endif | |
1644 | ||
1645 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
be8a5685 | 1646 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1647 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1648 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1649 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1650 | |
1651 | cpu_to_apicid[cpu] = apicid; | |
1652 | bios_cpu_apicid[cpu] = apicid; | |
1653 | } else { | |
1654 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1655 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1656 | } | |
1b313f4a | 1657 | #endif |
be8a5685 AS |
1658 | |
1659 | cpu_set(cpu, cpu_possible_map); | |
1660 | cpu_set(cpu, cpu_present_map); | |
1661 | } | |
1662 | ||
3491998d | 1663 | #ifdef CONFIG_X86_64 |
0c81c746 SS |
1664 | int hard_smp_processor_id(void) |
1665 | { | |
1666 | return read_apic_id(); | |
1667 | } | |
3491998d | 1668 | #endif |
0c81c746 | 1669 | |
89039b37 | 1670 | /* |
0e078e2f | 1671 | * Power management |
89039b37 | 1672 | */ |
0e078e2f TG |
1673 | #ifdef CONFIG_PM |
1674 | ||
1675 | static struct { | |
274cfe59 CG |
1676 | /* |
1677 | * 'active' is true if the local APIC was enabled by us and | |
1678 | * not the BIOS; this signifies that we are also responsible | |
1679 | * for disabling it before entering apm/acpi suspend | |
1680 | */ | |
0e078e2f TG |
1681 | int active; |
1682 | /* r/w apic fields */ | |
1683 | unsigned int apic_id; | |
1684 | unsigned int apic_taskpri; | |
1685 | unsigned int apic_ldr; | |
1686 | unsigned int apic_dfr; | |
1687 | unsigned int apic_spiv; | |
1688 | unsigned int apic_lvtt; | |
1689 | unsigned int apic_lvtpc; | |
1690 | unsigned int apic_lvt0; | |
1691 | unsigned int apic_lvt1; | |
1692 | unsigned int apic_lvterr; | |
1693 | unsigned int apic_tmict; | |
1694 | unsigned int apic_tdcr; | |
1695 | unsigned int apic_thmr; | |
1696 | } apic_pm_state; | |
1697 | ||
1698 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1699 | { | |
1700 | unsigned long flags; | |
1701 | int maxlvt; | |
89039b37 | 1702 | |
0e078e2f TG |
1703 | if (!apic_pm_state.active) |
1704 | return 0; | |
89039b37 | 1705 | |
0e078e2f | 1706 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1707 | |
2d7a66d0 | 1708 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1709 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1710 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1711 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1712 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1713 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1714 | if (maxlvt >= 4) | |
1715 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1716 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1717 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1718 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1719 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1720 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1721 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1722 | if (maxlvt >= 5) |
1723 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1724 | #endif | |
24968cfd | 1725 | |
0e078e2f TG |
1726 | local_irq_save(flags); |
1727 | disable_local_APIC(); | |
1728 | local_irq_restore(flags); | |
1729 | return 0; | |
1da177e4 LT |
1730 | } |
1731 | ||
0e078e2f | 1732 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1733 | { |
0e078e2f TG |
1734 | unsigned int l, h; |
1735 | unsigned long flags; | |
1736 | int maxlvt; | |
1da177e4 | 1737 | |
0e078e2f TG |
1738 | if (!apic_pm_state.active) |
1739 | return 0; | |
89b831ef | 1740 | |
0e078e2f | 1741 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1742 | |
0e078e2f | 1743 | local_irq_save(flags); |
92206c90 | 1744 | |
49899eac | 1745 | #ifdef HAVE_X2APIC |
92206c90 CG |
1746 | if (x2apic) |
1747 | enable_x2apic(); | |
1748 | else | |
1749 | #endif | |
d5e629a6 | 1750 | { |
92206c90 CG |
1751 | /* |
1752 | * Make sure the APICBASE points to the right address | |
1753 | * | |
1754 | * FIXME! This will be wrong if we ever support suspend on | |
1755 | * SMP! We'll need to do this as part of the CPU restore! | |
1756 | */ | |
6e1cb38a SS |
1757 | rdmsr(MSR_IA32_APICBASE, l, h); |
1758 | l &= ~MSR_IA32_APICBASE_BASE; | |
1759 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1760 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 1761 | } |
6e1cb38a | 1762 | |
0e078e2f TG |
1763 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
1764 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1765 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1766 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1767 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1768 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1769 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1770 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 1771 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1772 | if (maxlvt >= 5) |
1773 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1774 | #endif | |
1775 | if (maxlvt >= 4) | |
1776 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1777 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1778 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1779 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1780 | apic_write(APIC_ESR, 0); | |
1781 | apic_read(APIC_ESR); | |
1782 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1783 | apic_write(APIC_ESR, 0); | |
1784 | apic_read(APIC_ESR); | |
92206c90 | 1785 | |
0e078e2f | 1786 | local_irq_restore(flags); |
92206c90 | 1787 | |
0e078e2f TG |
1788 | return 0; |
1789 | } | |
b8ce3359 | 1790 | |
274cfe59 CG |
1791 | /* |
1792 | * This device has no shutdown method - fully functioning local APICs | |
1793 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1794 | */ | |
1795 | ||
0e078e2f TG |
1796 | static struct sysdev_class lapic_sysclass = { |
1797 | .name = "lapic", | |
1798 | .resume = lapic_resume, | |
1799 | .suspend = lapic_suspend, | |
1800 | }; | |
b8ce3359 | 1801 | |
0e078e2f | 1802 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1803 | .id = 0, |
1804 | .cls = &lapic_sysclass, | |
0e078e2f | 1805 | }; |
b8ce3359 | 1806 | |
0e078e2f TG |
1807 | static void __cpuinit apic_pm_activate(void) |
1808 | { | |
1809 | apic_pm_state.active = 1; | |
1da177e4 LT |
1810 | } |
1811 | ||
0e078e2f | 1812 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1813 | { |
0e078e2f | 1814 | int error; |
e83a5fdc | 1815 | |
0e078e2f TG |
1816 | if (!cpu_has_apic) |
1817 | return 0; | |
1818 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1819 | |
0e078e2f TG |
1820 | error = sysdev_class_register(&lapic_sysclass); |
1821 | if (!error) | |
1822 | error = sysdev_register(&device_lapic); | |
1823 | return error; | |
1da177e4 | 1824 | } |
0e078e2f TG |
1825 | device_initcall(init_lapic_sysfs); |
1826 | ||
1827 | #else /* CONFIG_PM */ | |
1828 | ||
1829 | static void apic_pm_activate(void) { } | |
1830 | ||
1831 | #endif /* CONFIG_PM */ | |
1da177e4 | 1832 | |
f28c0ae2 | 1833 | #ifdef CONFIG_X86_64 |
1da177e4 | 1834 | /* |
f8bf3c65 | 1835 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1836 | * |
1837 | * Thus far, the major user of this is IBM's Summit2 series: | |
1838 | * | |
637029c6 | 1839 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1840 | * multi-chassis. Use available data to take a good guess. |
1841 | * If in doubt, go HPET. | |
1842 | */ | |
f8bf3c65 | 1843 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1844 | { |
1845 | int i, clusters, zeros; | |
1846 | unsigned id; | |
322850af | 1847 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1848 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1849 | ||
322850af YL |
1850 | /* |
1851 | * there is not this kind of box with AMD CPU yet. | |
1852 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1853 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1854 | * vsmp box still need checking... |
322850af | 1855 | */ |
1cb68487 | 1856 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1857 | return 0; |
1858 | ||
23ca4bba | 1859 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 1860 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1861 | |
1862 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1863 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1864 | if (bios_cpu_apicid) { |
1865 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1866 | } |
1867 | else if (i < nr_cpu_ids) { | |
1868 | if (cpu_present(i)) | |
1869 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1870 | else | |
1871 | continue; | |
1872 | } | |
1873 | else | |
1874 | break; | |
1875 | ||
1da177e4 LT |
1876 | if (id != BAD_APICID) |
1877 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1878 | } | |
1879 | ||
1880 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1881 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1882 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1883 | * Since clusters are allocated sequentially, count zeros only if | |
1884 | * they are bounded by ones. | |
1da177e4 LT |
1885 | */ |
1886 | clusters = 0; | |
1887 | zeros = 0; | |
1888 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1889 | if (test_bit(i, clustermap)) { | |
1890 | clusters += 1 + zeros; | |
1891 | zeros = 0; | |
1892 | } else | |
1893 | ++zeros; | |
1894 | } | |
1895 | ||
1cb68487 RT |
1896 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1897 | * not guaranteed to be synced between boards | |
1898 | */ | |
1899 | if (is_vsmp_box() && clusters > 1) | |
1900 | return 1; | |
1901 | ||
1da177e4 | 1902 | /* |
f8bf3c65 | 1903 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1904 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1905 | * out, but AFAIK this will work even for them. | |
1906 | */ | |
1907 | return (clusters > 2); | |
1908 | } | |
f28c0ae2 | 1909 | #endif |
1da177e4 LT |
1910 | |
1911 | /* | |
0e078e2f | 1912 | * APIC command line parameters |
1da177e4 | 1913 | */ |
789fa735 | 1914 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 1915 | { |
1da177e4 | 1916 | disable_apic = 1; |
9175fc06 | 1917 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
1918 | return 0; |
1919 | } | |
1920 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1921 | |
2c8c0e6b | 1922 | /* same as disableapic, for compatibility */ |
789fa735 | 1923 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 1924 | { |
789fa735 | 1925 | return setup_disableapic(arg); |
6935d1f9 | 1926 | } |
2c8c0e6b | 1927 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1928 | |
2e7c2838 LT |
1929 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1930 | { | |
1931 | local_apic_timer_c2_ok = 1; | |
1932 | return 0; | |
1933 | } | |
1934 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1935 | ||
36fef094 | 1936 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 1937 | { |
1da177e4 | 1938 | disable_apic_timer = 1; |
36fef094 | 1939 | return 0; |
6935d1f9 | 1940 | } |
36fef094 CG |
1941 | early_param("noapictimer", parse_disable_apic_timer); |
1942 | ||
1943 | static int __init parse_nolapic_timer(char *arg) | |
1944 | { | |
1945 | disable_apic_timer = 1; | |
1946 | return 0; | |
6935d1f9 | 1947 | } |
36fef094 | 1948 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 1949 | |
79af9bec CG |
1950 | static int __init apic_set_verbosity(char *arg) |
1951 | { | |
1952 | if (!arg) { | |
1953 | #ifdef CONFIG_X86_64 | |
1954 | skip_ioapic_setup = 0; | |
79af9bec CG |
1955 | return 0; |
1956 | #endif | |
1957 | return -EINVAL; | |
1958 | } | |
1959 | ||
1960 | if (strcmp("debug", arg) == 0) | |
1961 | apic_verbosity = APIC_DEBUG; | |
1962 | else if (strcmp("verbose", arg) == 0) | |
1963 | apic_verbosity = APIC_VERBOSE; | |
1964 | else { | |
1965 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1966 | " use apic=verbose or apic=debug\n", arg); | |
1967 | return -EINVAL; | |
1968 | } | |
1969 | ||
1970 | return 0; | |
1971 | } | |
1972 | early_param("apic", apic_set_verbosity); | |
1973 | ||
1e934dda YL |
1974 | static int __init lapic_insert_resource(void) |
1975 | { | |
1976 | if (!apic_phys) | |
1977 | return -1; | |
1978 | ||
1979 | /* Put local APIC into the resource map. */ | |
1980 | lapic_resource.start = apic_phys; | |
1981 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1982 | insert_resource(&iomem_resource, &lapic_resource); | |
1983 | ||
1984 | return 0; | |
1985 | } | |
1986 | ||
1987 | /* | |
1988 | * need call insert after e820_reserve_resources() | |
1989 | * that is using request_resource | |
1990 | */ | |
1991 | late_initcall(lapic_insert_resource); |