[deliverable/linux.git] / arch / x86 / kernel / cpu / addon_cpuid_features.c


/*
 *	Routines to indentify additional cpu features that are scattered in
 *	cpuid space.
 */

#include <linux/cpu.h>

#include <asm/pat.h>
#include <asm/processor.h>

struct cpuid_bit {
	u16 feature;
	u8 reg;
	u8 bit;
	u32 level;
};

enum cpuid_regs {
	CR_EAX = 0,
	CR_ECX,
	CR_EDX,
	CR_EBX
};

void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
{
	u32 max_level;
	u32 regs[4];
	const struct cpuid_bit *cb;

	static const struct cpuid_bit cpuid_bits[] = {
		{ X86_FEATURE_IDA, CR_EAX, 1, 0x00000006 },
		{ 0, 0, 0, 0 }
	};

	for (cb = cpuid_bits; cb->feature; cb++) {

		/* Verify that the level is valid */
		max_level = cpuid_eax(cb->level & 0xffff0000);
		if (max_level < cb->level ||
		    max_level > (cb->level | 0xffff))
			continue;

		cpuid(cb->level, &regs[CR_EAX], &regs[CR_EBX],
			&regs[CR_ECX], &regs[CR_EDX]);

		if (regs[cb->reg] & (1 << cb->bit))
			set_cpu_cap(c, cb->feature);
	}
}

#ifdef CONFIG_X86_PAT
void __cpuinit validate_pat_support(struct cpuinfo_x86 *c)
{
	switch (c->x86_vendor) {
	case X86_VENDOR_AMD:
		if (c->x86 >= 0xf && c->x86 <= 0x11)
			return;
		break;
	case X86_VENDOR_INTEL:
		if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
			return;
		break;
	}

	pat_disable(cpu_has_pat ?
		    "PAT disabled. Not yet verified on this CPU type." :
		    "PAT not supported by CPU.");
}
#endif
Commit	Line	Data
1d67953f VP	1
	2	/*
	3	* Routines to indentify additional cpu features that are scattered in
	4	* cpuid space.
	5	*/
	6
	7	#include <linux/cpu.h>
	8
8d4a4300	9	#include <asm/pat.h>
1d67953f VP	10	#include <asm/processor.h>
	11
	12	struct cpuid_bit {
	13	u16 feature;
	14	u8 reg;
	15	u8 bit;
	16	u32 level;
	17	};
	18
	19	enum cpuid_regs {
	20	CR_EAX = 0,
	21	CR_ECX,
	22	CR_EDX,
	23	CR_EBX
	24	};
	25
	26	void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
	27	{
	28	u32 max_level;
	29	u32 regs[4];
	30	const struct cpuid_bit *cb;
	31
	32	static const struct cpuid_bit cpuid_bits[] = {
	33	{ X86_FEATURE_IDA, CR_EAX, 1, 0x00000006 },
	34	{ 0, 0, 0, 0 }
	35	};
	36
	37	for (cb = cpuid_bits; cb->feature; cb++) {
	38
	39	/* Verify that the level is valid */
	40	max_level = cpuid_eax(cb->level & 0xffff0000);
	41	if (max_level < cb->level \|\|
	42	max_level > (cb->level \| 0xffff))
	43	continue;
	44
	45	cpuid(cb->level, &regs[CR_EAX], &regs[CR_EBX],
	46	&regs[CR_ECX], &regs[CR_EDX]);
	47
	48	if (regs[cb->reg] & (1 << cb->bit))
53756d37	49	set_cpu_cap(c, cb->feature);
1d67953f VP	50	}
1d67953f VP	51	}
8d4a4300 TG	52
	53	#ifdef CONFIG_X86_PAT
	54	void __cpuinit validate_pat_support(struct cpuinfo_x86 *c)
	55	{
	56	switch (c->x86_vendor) {
	57	case X86_VENDOR_AMD:
	58	if (c->x86 >= 0xf && c->x86 <= 0x11)
	59	return;
	60	break;
	61	case X86_VENDOR_INTEL:
	62	if (c->x86 == 0xF \|\| (c->x86 == 6 && c->x86_model >= 15))
	63	return;
	64	break;
	65	}
	66
	67	pat_disable(cpu_has_pat ?
	68	"PAT disabled. Not yet verified on this CPU type." :
	69	"PAT not supported by CPU.");
	70	}
	71	#endif