Commit | Line | Data |
---|---|---|
f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
1da177e4 | 8 | #include <linux/delay.h> |
9766cdbc JSR |
9 | #include <linux/sched.h> |
10 | #include <linux/init.h> | |
11 | #include <linux/kgdb.h> | |
1da177e4 | 12 | #include <linux/smp.h> |
9766cdbc JSR |
13 | #include <linux/io.h> |
14 | ||
15 | #include <asm/stackprotector.h> | |
cdd6c482 | 16 | #include <asm/perf_event.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
49d859d7 | 18 | #include <asm/archrandom.h> |
9766cdbc JSR |
19 | #include <asm/hypervisor.h> |
20 | #include <asm/processor.h> | |
f649e938 | 21 | #include <asm/debugreg.h> |
9766cdbc | 22 | #include <asm/sections.h> |
8bdbd962 AC |
23 | #include <linux/topology.h> |
24 | #include <linux/cpumask.h> | |
9766cdbc | 25 | #include <asm/pgtable.h> |
60063497 | 26 | #include <linux/atomic.h> |
9766cdbc JSR |
27 | #include <asm/proto.h> |
28 | #include <asm/setup.h> | |
29 | #include <asm/apic.h> | |
30 | #include <asm/desc.h> | |
31 | #include <asm/i387.h> | |
1361b83a | 32 | #include <asm/fpu-internal.h> |
27b07da7 | 33 | #include <asm/mtrr.h> |
8bdbd962 | 34 | #include <linux/numa.h> |
9766cdbc JSR |
35 | #include <asm/asm.h> |
36 | #include <asm/cpu.h> | |
a03a3e28 | 37 | #include <asm/mce.h> |
9766cdbc | 38 | #include <asm/msr.h> |
8d4a4300 | 39 | #include <asm/pat.h> |
d288e1cf FY |
40 | #include <asm/microcode.h> |
41 | #include <asm/microcode_intel.h> | |
e641f5f5 IM |
42 | |
43 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 44 | #include <asm/uv/uv.h> |
1da177e4 LT |
45 | #endif |
46 | ||
47 | #include "cpu.h" | |
48 | ||
c2d1cec1 | 49 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 50 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
51 | cpumask_var_t cpu_callout_mask; |
52 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
53 | |
54 | /* representing cpus for which sibling maps can be computed */ | |
55 | cpumask_var_t cpu_sibling_setup_mask; | |
56 | ||
2f2f52ba | 57 | /* correctly size the local cpu masks */ |
4369f1fb | 58 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
59 | { |
60 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
61 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
62 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
63 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
64 | } | |
65 | ||
148f9bb8 | 66 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
67 | { |
68 | #ifdef CONFIG_X86_64 | |
27c13ece | 69 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
70 | #else |
71 | /* Not much we can do here... */ | |
72 | /* Check if at least it has cpuid */ | |
73 | if (c->cpuid_level == -1) { | |
74 | /* No cpuid. It must be an ancient CPU */ | |
75 | if (c->x86 == 4) | |
76 | strcpy(c->x86_model_id, "486"); | |
77 | else if (c->x86 == 3) | |
78 | strcpy(c->x86_model_id, "386"); | |
79 | } | |
80 | #endif | |
81 | } | |
82 | ||
148f9bb8 | 83 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
84 | .c_init = default_init, |
85 | .c_vendor = "Unknown", | |
86 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
87 | }; | |
88 | ||
148f9bb8 | 89 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 90 | |
06deef89 | 91 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 92 | #ifdef CONFIG_X86_64 |
06deef89 BG |
93 | /* |
94 | * We need valid kernel segments for data and code in long mode too | |
95 | * IRET will check the segment types kkeil 2000/10/28 | |
96 | * Also sysret mandates a special GDT layout | |
97 | * | |
9766cdbc | 98 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
99 | * Hopefully nobody expects them at a fixed place (Wine?) |
100 | */ | |
1e5de182 AM |
101 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
102 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
103 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
104 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
105 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
106 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 107 | #else |
1e5de182 AM |
108 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
109 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
110 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
111 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
112 | /* |
113 | * Segments used for calling PnP BIOS have byte granularity. | |
114 | * They code segments and data segments have fixed 64k limits, | |
115 | * the transfer segment sizes are set at run time. | |
116 | */ | |
6842ef0e | 117 | /* 32-bit code */ |
1e5de182 | 118 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 119 | /* 16-bit code */ |
1e5de182 | 120 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 121 | /* 16-bit data */ |
1e5de182 | 122 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 123 | /* 16-bit data */ |
1e5de182 | 124 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 125 | /* 16-bit data */ |
1e5de182 | 126 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
127 | /* |
128 | * The APM segments have byte granularity and their bases | |
129 | * are set at run time. All have 64k limits. | |
130 | */ | |
6842ef0e | 131 | /* 32-bit code */ |
1e5de182 | 132 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 133 | /* 16-bit code */ |
1e5de182 | 134 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 135 | /* data */ |
72c4d853 | 136 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 137 | |
1e5de182 AM |
138 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
139 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 140 | GDT_STACK_CANARY_INIT |
950ad7ff | 141 | #endif |
06deef89 | 142 | } }; |
7a61d35d | 143 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 144 | |
0c752a93 SS |
145 | static int __init x86_xsave_setup(char *s) |
146 | { | |
147 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
6bad06b7 | 148 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); |
c6fd893d SS |
149 | setup_clear_cpu_cap(X86_FEATURE_AVX); |
150 | setup_clear_cpu_cap(X86_FEATURE_AVX2); | |
0c752a93 SS |
151 | return 1; |
152 | } | |
153 | __setup("noxsave", x86_xsave_setup); | |
154 | ||
6bad06b7 SS |
155 | static int __init x86_xsaveopt_setup(char *s) |
156 | { | |
157 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
158 | return 1; | |
159 | } | |
160 | __setup("noxsaveopt", x86_xsaveopt_setup); | |
161 | ||
ba51dced | 162 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
163 | static int cachesize_override = -1; |
164 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 165 | |
0a488a53 YL |
166 | static int __init cachesize_setup(char *str) |
167 | { | |
168 | get_option(&str, &cachesize_override); | |
169 | return 1; | |
170 | } | |
171 | __setup("cachesize=", cachesize_setup); | |
172 | ||
0a488a53 YL |
173 | static int __init x86_fxsr_setup(char *s) |
174 | { | |
175 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
176 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
177 | return 1; | |
178 | } | |
179 | __setup("nofxsr", x86_fxsr_setup); | |
180 | ||
181 | static int __init x86_sep_setup(char *s) | |
182 | { | |
183 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
184 | return 1; | |
185 | } | |
186 | __setup("nosep", x86_sep_setup); | |
187 | ||
188 | /* Standard macro to see if a specific flag is changeable */ | |
189 | static inline int flag_is_changeable_p(u32 flag) | |
190 | { | |
191 | u32 f1, f2; | |
192 | ||
94f6bac1 KH |
193 | /* |
194 | * Cyrix and IDT cpus allow disabling of CPUID | |
195 | * so the code below may return different results | |
196 | * when it is executed before and after enabling | |
197 | * the CPUID. Add "volatile" to not allow gcc to | |
198 | * optimize the subsequent calls to this function. | |
199 | */ | |
0f3fa48a IM |
200 | asm volatile ("pushfl \n\t" |
201 | "pushfl \n\t" | |
202 | "popl %0 \n\t" | |
203 | "movl %0, %1 \n\t" | |
204 | "xorl %2, %0 \n\t" | |
205 | "pushl %0 \n\t" | |
206 | "popfl \n\t" | |
207 | "pushfl \n\t" | |
208 | "popl %0 \n\t" | |
209 | "popfl \n\t" | |
210 | ||
94f6bac1 KH |
211 | : "=&r" (f1), "=&r" (f2) |
212 | : "ir" (flag)); | |
0a488a53 YL |
213 | |
214 | return ((f1^f2) & flag) != 0; | |
215 | } | |
216 | ||
217 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 218 | int have_cpuid_p(void) |
0a488a53 YL |
219 | { |
220 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
221 | } | |
222 | ||
148f9bb8 | 223 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 224 | { |
0f3fa48a IM |
225 | unsigned long lo, hi; |
226 | ||
227 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
228 | return; | |
229 | ||
230 | /* Disable processor serial number: */ | |
231 | ||
232 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
233 | lo |= 0x200000; | |
234 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
235 | ||
236 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
237 | clear_cpu_cap(c, X86_FEATURE_PN); | |
238 | ||
239 | /* Disabling the serial number may affect the cpuid level */ | |
240 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
241 | } |
242 | ||
243 | static int __init x86_serial_nr_setup(char *s) | |
244 | { | |
245 | disable_x86_serial_nr = 0; | |
246 | return 1; | |
247 | } | |
248 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 249 | #else |
102bbe3a YL |
250 | static inline int flag_is_changeable_p(u32 flag) |
251 | { | |
252 | return 1; | |
253 | } | |
102bbe3a YL |
254 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
255 | { | |
256 | } | |
ba51dced | 257 | #endif |
0a488a53 | 258 | |
de5397ad FY |
259 | static __init int setup_disable_smep(char *arg) |
260 | { | |
b2cc2a07 | 261 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
de5397ad FY |
262 | return 1; |
263 | } | |
264 | __setup("nosmep", setup_disable_smep); | |
265 | ||
b2cc2a07 | 266 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 267 | { |
b2cc2a07 PA |
268 | if (cpu_has(c, X86_FEATURE_SMEP)) |
269 | set_in_cr4(X86_CR4_SMEP); | |
de5397ad FY |
270 | } |
271 | ||
52b6179a PA |
272 | static __init int setup_disable_smap(char *arg) |
273 | { | |
b2cc2a07 | 274 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
275 | return 1; |
276 | } | |
277 | __setup("nosmap", setup_disable_smap); | |
278 | ||
b2cc2a07 PA |
279 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
280 | { | |
281 | unsigned long eflags; | |
282 | ||
283 | /* This should have been cleared long ago */ | |
284 | raw_local_save_flags(eflags); | |
285 | BUG_ON(eflags & X86_EFLAGS_AC); | |
286 | ||
287 | if (cpu_has(c, X86_FEATURE_SMAP)) | |
288 | set_in_cr4(X86_CR4_SMAP); | |
de5397ad FY |
289 | } |
290 | ||
b38b0665 PA |
291 | /* |
292 | * Some CPU features depend on higher CPUID levels, which may not always | |
293 | * be available due to CPUID level capping or broken virtualization | |
294 | * software. Add those features to this table to auto-disable them. | |
295 | */ | |
296 | struct cpuid_dependent_feature { | |
297 | u32 feature; | |
298 | u32 level; | |
299 | }; | |
0f3fa48a | 300 | |
148f9bb8 | 301 | static const struct cpuid_dependent_feature |
b38b0665 PA |
302 | cpuid_dependent_features[] = { |
303 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
304 | { X86_FEATURE_DCA, 0x00000009 }, | |
305 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
306 | { 0, 0 } | |
307 | }; | |
308 | ||
148f9bb8 | 309 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
310 | { |
311 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 312 | |
b38b0665 | 313 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
314 | |
315 | if (!cpu_has(c, df->feature)) | |
316 | continue; | |
b38b0665 PA |
317 | /* |
318 | * Note: cpuid_level is set to -1 if unavailable, but | |
319 | * extended_extended_level is set to 0 if unavailable | |
320 | * and the legitimate extended levels are all negative | |
321 | * when signed; hence the weird messing around with | |
322 | * signs here... | |
323 | */ | |
0f3fa48a | 324 | if (!((s32)df->level < 0 ? |
f6db44df | 325 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
326 | (s32)df->level > (s32)c->cpuid_level)) |
327 | continue; | |
328 | ||
329 | clear_cpu_cap(c, df->feature); | |
330 | if (!warn) | |
331 | continue; | |
332 | ||
333 | printk(KERN_WARNING | |
334 | "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", | |
335 | x86_cap_flags[df->feature], df->level); | |
b38b0665 | 336 | } |
f6db44df | 337 | } |
b38b0665 | 338 | |
102bbe3a YL |
339 | /* |
340 | * Naming convention should be: <Name> [(<Codename>)] | |
341 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
342 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
343 | * isn't used | |
102bbe3a YL |
344 | */ |
345 | ||
346 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 347 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 348 | { |
09dc68d9 JB |
349 | #ifdef CONFIG_X86_32 |
350 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
351 | |
352 | if (c->x86_model >= 16) | |
353 | return NULL; /* Range check */ | |
354 | ||
355 | if (!this_cpu) | |
356 | return NULL; | |
357 | ||
09dc68d9 | 358 | info = this_cpu->legacy_models; |
102bbe3a | 359 | |
09dc68d9 | 360 | while (info->family) { |
102bbe3a YL |
361 | if (info->family == c->x86) |
362 | return info->model_names[c->x86_model]; | |
363 | info++; | |
364 | } | |
09dc68d9 | 365 | #endif |
102bbe3a YL |
366 | return NULL; /* Not found */ |
367 | } | |
368 | ||
148f9bb8 PG |
369 | __u32 cpu_caps_cleared[NCAPINTS]; |
370 | __u32 cpu_caps_set[NCAPINTS]; | |
7d851c8d | 371 | |
11e3a840 JF |
372 | void load_percpu_segment(int cpu) |
373 | { | |
374 | #ifdef CONFIG_X86_32 | |
375 | loadsegment(fs, __KERNEL_PERCPU); | |
376 | #else | |
377 | loadsegment(gs, 0); | |
378 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
379 | #endif | |
60a5317f | 380 | load_stack_canary_segment(); |
11e3a840 JF |
381 | } |
382 | ||
0f3fa48a IM |
383 | /* |
384 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
385 | * it's on the real one. | |
386 | */ | |
552be871 | 387 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
388 | { |
389 | struct desc_ptr gdt_descr; | |
390 | ||
2697fbd5 | 391 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
392 | gdt_descr.size = GDT_SIZE - 1; |
393 | load_gdt(&gdt_descr); | |
2697fbd5 | 394 | /* Reload the per-cpu base */ |
11e3a840 JF |
395 | |
396 | load_percpu_segment(cpu); | |
9d31d35b YL |
397 | } |
398 | ||
148f9bb8 | 399 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 400 | |
148f9bb8 | 401 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
402 | { |
403 | unsigned int *v; | |
404 | char *p, *q; | |
405 | ||
3da99c97 | 406 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 407 | return; |
1da177e4 | 408 | |
0f3fa48a | 409 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
410 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
411 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
412 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
413 | c->x86_model_id[48] = 0; | |
414 | ||
0f3fa48a IM |
415 | /* |
416 | * Intel chips right-justify this string for some dumb reason; | |
417 | * undo that brain damage: | |
418 | */ | |
1da177e4 | 419 | p = q = &c->x86_model_id[0]; |
34048c9e | 420 | while (*p == ' ') |
9766cdbc | 421 | p++; |
34048c9e | 422 | if (p != q) { |
9766cdbc JSR |
423 | while (*p) |
424 | *q++ = *p++; | |
425 | while (q <= &c->x86_model_id[48]) | |
426 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 427 | } |
1da177e4 LT |
428 | } |
429 | ||
148f9bb8 | 430 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 431 | { |
9d31d35b | 432 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 433 | |
3da99c97 | 434 | n = c->extended_cpuid_level; |
1da177e4 LT |
435 | |
436 | if (n >= 0x80000005) { | |
9d31d35b | 437 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 438 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
439 | #ifdef CONFIG_X86_64 |
440 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
441 | c->x86_tlbsize = 0; | |
442 | #endif | |
1da177e4 LT |
443 | } |
444 | ||
445 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
446 | return; | |
447 | ||
0a488a53 | 448 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 449 | l2size = ecx >> 16; |
34048c9e | 450 | |
140fc727 YL |
451 | #ifdef CONFIG_X86_64 |
452 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
453 | #else | |
1da177e4 | 454 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
455 | if (this_cpu->legacy_cache_size) |
456 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
457 | |
458 | /* Allow user to override all this if necessary. */ | |
459 | if (cachesize_override != -1) | |
460 | l2size = cachesize_override; | |
461 | ||
34048c9e | 462 | if (l2size == 0) |
1da177e4 | 463 | return; /* Again, no L2 cache is possible */ |
140fc727 | 464 | #endif |
1da177e4 LT |
465 | |
466 | c->x86_cache_size = l2size; | |
1da177e4 LT |
467 | } |
468 | ||
e0ba94f1 AS |
469 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
470 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
471 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
472 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
473 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
474 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
475 | ||
c4211f42 AS |
476 | /* |
477 | * tlb_flushall_shift shows the balance point in replacing cr3 write | |
478 | * with multiple 'invlpg'. It will do this replacement when | |
479 | * flush_tlb_lines <= active_lines/2^tlb_flushall_shift. | |
480 | * If tlb_flushall_shift is -1, means the replacement will be disabled. | |
481 | */ | |
482 | s8 __read_mostly tlb_flushall_shift = -1; | |
483 | ||
148f9bb8 | 484 | void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
485 | { |
486 | if (this_cpu->c_detect_tlb) | |
487 | this_cpu->c_detect_tlb(c); | |
488 | ||
489 | printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ | |
c4211f42 | 490 | "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ |
a9ad773e | 491 | "tlb_flushall_shift: %d\n", |
e0ba94f1 AS |
492 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
493 | tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], | |
c4211f42 AS |
494 | tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], |
495 | tlb_flushall_shift); | |
e0ba94f1 AS |
496 | } |
497 | ||
148f9bb8 | 498 | void detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 499 | { |
97e4db7c | 500 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
501 | u32 eax, ebx, ecx, edx; |
502 | int index_msb, core_bits; | |
2eaad1fd | 503 | static bool printed; |
1da177e4 | 504 | |
0a488a53 | 505 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 506 | return; |
1da177e4 | 507 | |
0a488a53 YL |
508 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
509 | goto out; | |
1da177e4 | 510 | |
1cd78776 YL |
511 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
512 | return; | |
1da177e4 | 513 | |
0a488a53 | 514 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 515 | |
9d31d35b YL |
516 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
517 | ||
518 | if (smp_num_siblings == 1) { | |
2eaad1fd | 519 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
520 | goto out; |
521 | } | |
9d31d35b | 522 | |
0f3fa48a IM |
523 | if (smp_num_siblings <= 1) |
524 | goto out; | |
9d31d35b | 525 | |
0f3fa48a IM |
526 | index_msb = get_count_order(smp_num_siblings); |
527 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 528 | |
0f3fa48a | 529 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 530 | |
0f3fa48a | 531 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 532 | |
0f3fa48a | 533 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 534 | |
0f3fa48a IM |
535 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
536 | ((1 << core_bits) - 1); | |
1da177e4 | 537 | |
0a488a53 | 538 | out: |
2eaad1fd | 539 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
0a488a53 YL |
540 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
541 | c->phys_proc_id); | |
542 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
543 | c->cpu_core_id); | |
2eaad1fd | 544 | printed = 1; |
9d31d35b | 545 | } |
9d31d35b | 546 | #endif |
97e4db7c | 547 | } |
1da177e4 | 548 | |
148f9bb8 | 549 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
550 | { |
551 | char *v = c->x86_vendor_id; | |
0f3fa48a | 552 | int i; |
1da177e4 LT |
553 | |
554 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
555 | if (!cpu_devs[i]) |
556 | break; | |
557 | ||
558 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
559 | (cpu_devs[i]->c_ident[1] && | |
560 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 561 | |
10a434fc YL |
562 | this_cpu = cpu_devs[i]; |
563 | c->x86_vendor = this_cpu->c_x86_vendor; | |
564 | return; | |
1da177e4 LT |
565 | } |
566 | } | |
10a434fc | 567 | |
a9c56953 MK |
568 | printk_once(KERN_ERR |
569 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
570 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 571 | |
fe38d855 CE |
572 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
573 | this_cpu = &default_cpu; | |
1da177e4 LT |
574 | } |
575 | ||
148f9bb8 | 576 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 577 | { |
1da177e4 | 578 | /* Get vendor name */ |
4a148513 HH |
579 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
580 | (unsigned int *)&c->x86_vendor_id[0], | |
581 | (unsigned int *)&c->x86_vendor_id[8], | |
582 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 583 | |
1da177e4 | 584 | c->x86 = 4; |
9d31d35b | 585 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
586 | if (c->cpuid_level >= 0x00000001) { |
587 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 588 | |
1da177e4 | 589 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
590 | c->x86 = (tfms >> 8) & 0xf; |
591 | c->x86_model = (tfms >> 4) & 0xf; | |
592 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 593 | |
f5f786d0 | 594 | if (c->x86 == 0xf) |
1da177e4 | 595 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 596 | if (c->x86 >= 0x6) |
9d31d35b | 597 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 598 | |
d4387bd3 | 599 | if (cap0 & (1<<19)) { |
d4387bd3 | 600 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 601 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 602 | } |
1da177e4 | 603 | } |
1da177e4 | 604 | } |
3da99c97 | 605 | |
148f9bb8 | 606 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 YL |
607 | { |
608 | u32 tfms, xlvl; | |
3da99c97 | 609 | u32 ebx; |
093af8d7 | 610 | |
3da99c97 YL |
611 | /* Intel-defined flags: level 0x00000001 */ |
612 | if (c->cpuid_level >= 0x00000001) { | |
613 | u32 capability, excap; | |
0f3fa48a | 614 | |
3da99c97 YL |
615 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
616 | c->x86_capability[0] = capability; | |
617 | c->x86_capability[4] = excap; | |
618 | } | |
093af8d7 | 619 | |
bdc802dc PA |
620 | /* Additional Intel-defined flags: level 0x00000007 */ |
621 | if (c->cpuid_level >= 0x00000007) { | |
622 | u32 eax, ebx, ecx, edx; | |
623 | ||
624 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
625 | ||
2494b030 | 626 | c->x86_capability[9] = ebx; |
bdc802dc PA |
627 | } |
628 | ||
3da99c97 YL |
629 | /* AMD-defined flags: level 0x80000001 */ |
630 | xlvl = cpuid_eax(0x80000000); | |
631 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 632 | |
3da99c97 YL |
633 | if ((xlvl & 0xffff0000) == 0x80000000) { |
634 | if (xlvl >= 0x80000001) { | |
635 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
636 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 637 | } |
093af8d7 | 638 | } |
093af8d7 | 639 | |
5122c890 YL |
640 | if (c->extended_cpuid_level >= 0x80000008) { |
641 | u32 eax = cpuid_eax(0x80000008); | |
642 | ||
643 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
644 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 645 | } |
13c6c532 JB |
646 | #ifdef CONFIG_X86_32 |
647 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
648 | c->x86_phys_bits = 36; | |
5122c890 | 649 | #endif |
e3224234 YL |
650 | |
651 | if (c->extended_cpuid_level >= 0x80000007) | |
652 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 | 653 | |
1dedefd1 | 654 | init_scattered_cpuid_features(c); |
093af8d7 | 655 | } |
1da177e4 | 656 | |
148f9bb8 | 657 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
658 | { |
659 | #ifdef CONFIG_X86_32 | |
660 | int i; | |
661 | ||
662 | /* | |
663 | * First of all, decide if this is a 486 or higher | |
664 | * It's a 486 if we can modify the AC flag | |
665 | */ | |
666 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
667 | c->x86 = 4; | |
668 | else | |
669 | c->x86 = 3; | |
670 | ||
671 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
672 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
673 | c->x86_vendor_id[0] = 0; | |
674 | cpu_devs[i]->c_identify(c); | |
675 | if (c->x86_vendor_id[0]) { | |
676 | get_cpu_vendor(c); | |
677 | break; | |
678 | } | |
679 | } | |
680 | #endif | |
681 | } | |
682 | ||
34048c9e PC |
683 | /* |
684 | * Do minimum CPU detection early. | |
685 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
686 | * cache alignment. | |
687 | * The others are not touched to avoid unwanted side effects. | |
688 | * | |
689 | * WARNING: this function is only called on the BP. Don't add code here | |
690 | * that is supposed to run on all CPUs. | |
691 | */ | |
3da99c97 | 692 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 693 | { |
6627d242 YL |
694 | #ifdef CONFIG_X86_64 |
695 | c->x86_clflush_size = 64; | |
13c6c532 JB |
696 | c->x86_phys_bits = 36; |
697 | c->x86_virt_bits = 48; | |
6627d242 | 698 | #else |
d4387bd3 | 699 | c->x86_clflush_size = 32; |
13c6c532 JB |
700 | c->x86_phys_bits = 32; |
701 | c->x86_virt_bits = 32; | |
6627d242 | 702 | #endif |
0a488a53 | 703 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 704 | |
3da99c97 | 705 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 706 | c->extended_cpuid_level = 0; |
d7cd5611 | 707 | |
aef93c8b YL |
708 | if (!have_cpuid_p()) |
709 | identify_cpu_without_cpuid(c); | |
710 | ||
711 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
712 | if (!have_cpuid_p()) |
713 | return; | |
714 | ||
715 | cpu_detect(c); | |
3da99c97 | 716 | get_cpu_vendor(c); |
3da99c97 | 717 | get_cpu_cap(c); |
60e019eb | 718 | fpu_detect(c); |
12cf105c | 719 | |
10a434fc YL |
720 | if (this_cpu->c_early_init) |
721 | this_cpu->c_early_init(c); | |
093af8d7 | 722 | |
f6e9456c | 723 | c->cpu_index = 0; |
b38b0665 | 724 | filter_cpuid_features(c, false); |
de5397ad | 725 | |
a110b5ec BP |
726 | if (this_cpu->c_bsp_init) |
727 | this_cpu->c_bsp_init(c); | |
c3b83598 BP |
728 | |
729 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
d7cd5611 RR |
730 | } |
731 | ||
9d31d35b YL |
732 | void __init early_cpu_init(void) |
733 | { | |
02dde8b4 | 734 | const struct cpu_dev *const *cdev; |
10a434fc YL |
735 | int count = 0; |
736 | ||
ac23f253 | 737 | #ifdef CONFIG_PROCESSOR_SELECT |
9766cdbc | 738 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
31c997ca IM |
739 | #endif |
740 | ||
10a434fc | 741 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 742 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 743 | |
10a434fc YL |
744 | if (count >= X86_VENDOR_NUM) |
745 | break; | |
746 | cpu_devs[count] = cpudev; | |
747 | count++; | |
748 | ||
ac23f253 | 749 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
750 | { |
751 | unsigned int j; | |
752 | ||
753 | for (j = 0; j < 2; j++) { | |
754 | if (!cpudev->c_ident[j]) | |
755 | continue; | |
756 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
757 | cpudev->c_ident[j]); | |
758 | } | |
10a434fc | 759 | } |
0388423d | 760 | #endif |
10a434fc | 761 | } |
9d31d35b | 762 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 763 | } |
093af8d7 | 764 | |
b6734c35 | 765 | /* |
366d4a43 BP |
766 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
767 | * unfortunately, that's not true in practice because of early VIA | |
768 | * chips and (more importantly) broken virtualizers that are not easy | |
769 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
770 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 771 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 772 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 773 | */ |
148f9bb8 | 774 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 775 | { |
366d4a43 | 776 | #ifdef CONFIG_X86_32 |
b6734c35 | 777 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
778 | #else |
779 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
780 | #endif | |
d7cd5611 RR |
781 | } |
782 | ||
148f9bb8 | 783 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 784 | { |
aef93c8b | 785 | c->extended_cpuid_level = 0; |
1da177e4 | 786 | |
3da99c97 | 787 | if (!have_cpuid_p()) |
aef93c8b | 788 | identify_cpu_without_cpuid(c); |
1d67953f | 789 | |
aef93c8b | 790 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 791 | if (!have_cpuid_p()) |
aef93c8b | 792 | return; |
1da177e4 | 793 | |
3da99c97 | 794 | cpu_detect(c); |
1da177e4 | 795 | |
3da99c97 | 796 | get_cpu_vendor(c); |
1da177e4 | 797 | |
3da99c97 | 798 | get_cpu_cap(c); |
1da177e4 | 799 | |
3da99c97 YL |
800 | if (c->cpuid_level >= 0x00000001) { |
801 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
802 | #ifdef CONFIG_X86_32 |
803 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 804 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 805 | # else |
3da99c97 | 806 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
807 | # endif |
808 | #endif | |
b89d3b3e | 809 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 810 | } |
1da177e4 | 811 | |
1b05d60d | 812 | get_model_name(c); /* Default name */ |
1da177e4 | 813 | |
3da99c97 | 814 | detect_nopl(c); |
1da177e4 | 815 | } |
1da177e4 LT |
816 | |
817 | /* | |
818 | * This does the hard work of actually picking apart the CPU stuff... | |
819 | */ | |
148f9bb8 | 820 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
821 | { |
822 | int i; | |
823 | ||
824 | c->loops_per_jiffy = loops_per_jiffy; | |
825 | c->x86_cache_size = -1; | |
826 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
827 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
828 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
829 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 830 | c->x86_max_cores = 1; |
102bbe3a | 831 | c->x86_coreid_bits = 0; |
11fdd252 | 832 | #ifdef CONFIG_X86_64 |
102bbe3a | 833 | c->x86_clflush_size = 64; |
13c6c532 JB |
834 | c->x86_phys_bits = 36; |
835 | c->x86_virt_bits = 48; | |
102bbe3a YL |
836 | #else |
837 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 838 | c->x86_clflush_size = 32; |
13c6c532 JB |
839 | c->x86_phys_bits = 32; |
840 | c->x86_virt_bits = 32; | |
102bbe3a YL |
841 | #endif |
842 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
843 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
844 | ||
1da177e4 LT |
845 | generic_identify(c); |
846 | ||
3898534d | 847 | if (this_cpu->c_identify) |
1da177e4 LT |
848 | this_cpu->c_identify(c); |
849 | ||
2759c328 YL |
850 | /* Clear/Set all flags overriden by options, after probe */ |
851 | for (i = 0; i < NCAPINTS; i++) { | |
852 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
853 | c->x86_capability[i] |= cpu_caps_set[i]; | |
854 | } | |
855 | ||
102bbe3a | 856 | #ifdef CONFIG_X86_64 |
cb8cc442 | 857 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
858 | #endif |
859 | ||
1da177e4 LT |
860 | /* |
861 | * Vendor-specific initialization. In this section we | |
862 | * canonicalize the feature flags, meaning if there are | |
863 | * features a certain CPU supports which CPUID doesn't | |
864 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
865 | * we handle them here. | |
866 | * | |
867 | * At the end of this section, c->x86_capability better | |
868 | * indicate the features this CPU genuinely supports! | |
869 | */ | |
870 | if (this_cpu->c_init) | |
871 | this_cpu->c_init(c); | |
872 | ||
873 | /* Disable the PN if appropriate */ | |
874 | squash_the_stupid_serial_number(c); | |
875 | ||
b2cc2a07 PA |
876 | /* Set up SMEP/SMAP */ |
877 | setup_smep(c); | |
878 | setup_smap(c); | |
879 | ||
1da177e4 | 880 | /* |
0f3fa48a IM |
881 | * The vendor-specific functions might have changed features. |
882 | * Now we do "generic changes." | |
1da177e4 LT |
883 | */ |
884 | ||
b38b0665 PA |
885 | /* Filter out anything that depends on CPUID levels we don't have */ |
886 | filter_cpuid_features(c, true); | |
887 | ||
1da177e4 | 888 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 889 | if (!c->x86_model_id[0]) { |
02dde8b4 | 890 | const char *p; |
1da177e4 | 891 | p = table_lookup_model(c); |
34048c9e | 892 | if (p) |
1da177e4 LT |
893 | strcpy(c->x86_model_id, p); |
894 | else | |
895 | /* Last resort... */ | |
896 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 897 | c->x86, c->x86_model); |
1da177e4 LT |
898 | } |
899 | ||
102bbe3a YL |
900 | #ifdef CONFIG_X86_64 |
901 | detect_ht(c); | |
902 | #endif | |
903 | ||
88b094fb | 904 | init_hypervisor(c); |
49d859d7 | 905 | x86_init_rdrand(c); |
3e0c3737 YL |
906 | |
907 | /* | |
908 | * Clear/Set all flags overriden by options, need do it | |
909 | * before following smp all cpus cap AND. | |
910 | */ | |
911 | for (i = 0; i < NCAPINTS; i++) { | |
912 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
913 | c->x86_capability[i] |= cpu_caps_set[i]; | |
914 | } | |
915 | ||
1da177e4 LT |
916 | /* |
917 | * On SMP, boot_cpu_data holds the common feature set between | |
918 | * all CPUs; so make sure that we indicate which features are | |
919 | * common between the CPUs. The first time this routine gets | |
920 | * executed, c == &boot_cpu_data. | |
921 | */ | |
34048c9e | 922 | if (c != &boot_cpu_data) { |
1da177e4 | 923 | /* AND the already accumulated flags with these */ |
9d31d35b | 924 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 925 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
926 | |
927 | /* OR, i.e. replicate the bug flags */ | |
928 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
929 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
930 | } |
931 | ||
932 | /* Init Machine Check Exception if available. */ | |
5e09954a | 933 | mcheck_cpu_init(c); |
30d432df AK |
934 | |
935 | select_idle_routine(c); | |
102bbe3a | 936 | |
de2d9445 | 937 | #ifdef CONFIG_NUMA |
102bbe3a YL |
938 | numa_add_cpu(smp_processor_id()); |
939 | #endif | |
a6c4e076 | 940 | } |
31ab269a | 941 | |
e04d645f GC |
942 | #ifdef CONFIG_X86_64 |
943 | static void vgetcpu_set_mode(void) | |
944 | { | |
945 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
946 | vgetcpu_mode = VGETCPU_RDTSCP; | |
947 | else | |
948 | vgetcpu_mode = VGETCPU_LSL; | |
949 | } | |
950 | #endif | |
951 | ||
a6c4e076 JF |
952 | void __init identify_boot_cpu(void) |
953 | { | |
954 | identify_cpu(&boot_cpu_data); | |
02c68a02 | 955 | init_amd_e400_c1e_mask(); |
102bbe3a | 956 | #ifdef CONFIG_X86_32 |
a6c4e076 | 957 | sysenter_setup(); |
6fe940d6 | 958 | enable_sep_cpu(); |
e04d645f GC |
959 | #else |
960 | vgetcpu_set_mode(); | |
102bbe3a | 961 | #endif |
5b556332 | 962 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 963 | } |
3b520b23 | 964 | |
148f9bb8 | 965 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
966 | { |
967 | BUG_ON(c == &boot_cpu_data); | |
968 | identify_cpu(c); | |
102bbe3a | 969 | #ifdef CONFIG_X86_32 |
a6c4e076 | 970 | enable_sep_cpu(); |
102bbe3a | 971 | #endif |
a6c4e076 | 972 | mtrr_ap_init(); |
1da177e4 LT |
973 | } |
974 | ||
a0854a46 | 975 | struct msr_range { |
0f3fa48a IM |
976 | unsigned min; |
977 | unsigned max; | |
a0854a46 | 978 | }; |
1da177e4 | 979 | |
148f9bb8 | 980 | static const struct msr_range msr_range_array[] = { |
a0854a46 YL |
981 | { 0x00000000, 0x00000418}, |
982 | { 0xc0000000, 0xc000040b}, | |
983 | { 0xc0010000, 0xc0010142}, | |
984 | { 0xc0011000, 0xc001103b}, | |
985 | }; | |
1da177e4 | 986 | |
148f9bb8 | 987 | static void __print_cpu_msr(void) |
a0854a46 | 988 | { |
0f3fa48a | 989 | unsigned index_min, index_max; |
a0854a46 YL |
990 | unsigned index; |
991 | u64 val; | |
992 | int i; | |
a0854a46 YL |
993 | |
994 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
995 | index_min = msr_range_array[i].min; | |
996 | index_max = msr_range_array[i].max; | |
0f3fa48a | 997 | |
a0854a46 | 998 | for (index = index_min; index < index_max; index++) { |
ecd431d9 | 999 | if (rdmsrl_safe(index, &val)) |
a0854a46 YL |
1000 | continue; |
1001 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 1002 | } |
a0854a46 YL |
1003 | } |
1004 | } | |
94605eff | 1005 | |
148f9bb8 | 1006 | static int show_msr; |
0f3fa48a | 1007 | |
a0854a46 YL |
1008 | static __init int setup_show_msr(char *arg) |
1009 | { | |
1010 | int num; | |
3dd9d514 | 1011 | |
a0854a46 | 1012 | get_option(&arg, &num); |
3dd9d514 | 1013 | |
a0854a46 YL |
1014 | if (num > 0) |
1015 | show_msr = num; | |
1016 | return 1; | |
1da177e4 | 1017 | } |
a0854a46 | 1018 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 1019 | |
191679fd AK |
1020 | static __init int setup_noclflush(char *arg) |
1021 | { | |
1022 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
1023 | return 1; | |
1024 | } | |
1025 | __setup("noclflush", setup_noclflush); | |
1026 | ||
148f9bb8 | 1027 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1028 | { |
02dde8b4 | 1029 | const char *vendor = NULL; |
1da177e4 | 1030 | |
0f3fa48a | 1031 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1032 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1033 | } else { |
1034 | if (c->cpuid_level >= 0) | |
1035 | vendor = c->x86_vendor_id; | |
1036 | } | |
1da177e4 | 1037 | |
bd32a8cf | 1038 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 1039 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 1040 | |
9d31d35b | 1041 | if (c->x86_model_id[0]) |
924e101a | 1042 | printk(KERN_CONT "%s", strim(c->x86_model_id)); |
1da177e4 | 1043 | else |
9d31d35b | 1044 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 1045 | |
924e101a BP |
1046 | printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model); |
1047 | ||
34048c9e | 1048 | if (c->x86_mask || c->cpuid_level >= 0) |
924e101a | 1049 | printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask); |
1da177e4 | 1050 | else |
924e101a | 1051 | printk(KERN_CONT ")\n"); |
a0854a46 | 1052 | |
0b8b8078 | 1053 | print_cpu_msr(c); |
21c3fcf3 YL |
1054 | } |
1055 | ||
148f9bb8 | 1056 | void print_cpu_msr(struct cpuinfo_x86 *c) |
21c3fcf3 | 1057 | { |
a0854a46 | 1058 | if (c->cpu_index < show_msr) |
21c3fcf3 | 1059 | __print_cpu_msr(); |
1da177e4 LT |
1060 | } |
1061 | ||
ac72e788 AK |
1062 | static __init int setup_disablecpuid(char *arg) |
1063 | { | |
1064 | int bit; | |
0f3fa48a | 1065 | |
ac72e788 AK |
1066 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
1067 | setup_clear_cpu_cap(bit); | |
1068 | else | |
1069 | return 0; | |
0f3fa48a | 1070 | |
ac72e788 AK |
1071 | return 1; |
1072 | } | |
1073 | __setup("clearcpuid=", setup_disablecpuid); | |
1074 | ||
d5494d4f | 1075 | #ifdef CONFIG_X86_64 |
9ff80942 | 1076 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
629f4f9d SA |
1077 | struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, |
1078 | (unsigned long) debug_idt_table }; | |
d5494d4f | 1079 | |
947e76cd | 1080 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1081 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1082 | |
bdf977b3 TH |
1083 | /* |
1084 | * The following four percpu variables are hot. Align current_task to | |
1085 | * cacheline size such that all four fall in the same cacheline. | |
1086 | */ | |
1087 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1088 | &init_task; | |
1089 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1090 | |
9af45651 BG |
1091 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
1092 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
1093 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
1094 | ||
bdf977b3 TH |
1095 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1096 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1097 | ||
277d5b40 | 1098 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1099 | |
7e16838d LT |
1100 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
1101 | ||
0f3fa48a IM |
1102 | /* |
1103 | * Special IST stacks which the CPU switches to when it calls | |
1104 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1105 | * limit), all of them are 4K, except the debug stack which | |
1106 | * is 8K. | |
1107 | */ | |
1108 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1109 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1110 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1111 | }; | |
1112 | ||
92d65b23 | 1113 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1114 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1115 | |
d5494d4f YL |
1116 | /* May not be marked __init: used by software suspend */ |
1117 | void syscall_init(void) | |
1da177e4 | 1118 | { |
d5494d4f YL |
1119 | /* |
1120 | * LSTAR and STAR live in a bit strange symbiosis. | |
1121 | * They both write to the same internal register. STAR allows to | |
1122 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1123 | */ | |
1124 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1125 | wrmsrl(MSR_LSTAR, system_call); | |
1126 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 1127 | |
d5494d4f YL |
1128 | #ifdef CONFIG_IA32_EMULATION |
1129 | syscall32_cpu_init(); | |
1130 | #endif | |
03ae5768 | 1131 | |
d5494d4f YL |
1132 | /* Flags to clear on syscall */ |
1133 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a PA |
1134 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
1135 | X86_EFLAGS_IOPL|X86_EFLAGS_AC); | |
1da177e4 | 1136 | } |
62111195 | 1137 | |
d5494d4f YL |
1138 | /* |
1139 | * Copies of the original ist values from the tss are only accessed during | |
1140 | * debugging, no special alignment required. | |
1141 | */ | |
1142 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1143 | ||
228bdaa9 | 1144 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1145 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1146 | |
1147 | int is_debug_stack(unsigned long addr) | |
1148 | { | |
42181186 SR |
1149 | return __get_cpu_var(debug_stack_usage) || |
1150 | (addr <= __get_cpu_var(debug_stack_addr) && | |
1151 | addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 SR |
1152 | } |
1153 | ||
629f4f9d | 1154 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1155 | |
228bdaa9 SR |
1156 | void debug_stack_set_zero(void) |
1157 | { | |
629f4f9d SA |
1158 | this_cpu_inc(debug_idt_ctr); |
1159 | load_current_idt(); | |
228bdaa9 SR |
1160 | } |
1161 | ||
1162 | void debug_stack_reset(void) | |
1163 | { | |
629f4f9d | 1164 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1165 | return; |
629f4f9d SA |
1166 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1167 | load_current_idt(); | |
228bdaa9 SR |
1168 | } |
1169 | ||
0f3fa48a | 1170 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1171 | |
bdf977b3 TH |
1172 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1173 | EXPORT_PER_CPU_SYMBOL(current_task); | |
27e74da9 | 1174 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
bdf977b3 | 1175 | |
60a5317f | 1176 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1177 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1178 | #endif |
d5494d4f | 1179 | |
0f3fa48a | 1180 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1181 | |
9766cdbc JSR |
1182 | /* |
1183 | * Clear all 6 debug registers: | |
1184 | */ | |
1185 | static void clear_all_debug_regs(void) | |
1186 | { | |
1187 | int i; | |
1188 | ||
1189 | for (i = 0; i < 8; i++) { | |
1190 | /* Ignore db4, db5 */ | |
1191 | if ((i == 4) || (i == 5)) | |
1192 | continue; | |
1193 | ||
1194 | set_debugreg(0, i); | |
1195 | } | |
1196 | } | |
c5413fbe | 1197 | |
0bb9fef9 JW |
1198 | #ifdef CONFIG_KGDB |
1199 | /* | |
1200 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1201 | * connection established. | |
1202 | */ | |
1203 | static void dbg_restore_debug_regs(void) | |
1204 | { | |
1205 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1206 | arch_kgdb_ops.correct_hw_break(); | |
1207 | } | |
1208 | #else /* ! CONFIG_KGDB */ | |
1209 | #define dbg_restore_debug_regs() | |
1210 | #endif /* ! CONFIG_KGDB */ | |
1211 | ||
d2cbcc49 RR |
1212 | /* |
1213 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1214 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1215 | * and IDT. We reload them nevertheless, this function acts as a | |
1216 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1217 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1218 | */ |
1ba76586 | 1219 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1220 | |
148f9bb8 | 1221 | void cpu_init(void) |
1ba76586 | 1222 | { |
0fe1e009 | 1223 | struct orig_ist *oist; |
1ba76586 | 1224 | struct task_struct *me; |
0f3fa48a IM |
1225 | struct tss_struct *t; |
1226 | unsigned long v; | |
1227 | int cpu; | |
1ba76586 YL |
1228 | int i; |
1229 | ||
e6ebf5de FY |
1230 | /* |
1231 | * Load microcode on this cpu if a valid microcode is available. | |
1232 | * This is early microcode loading procedure. | |
1233 | */ | |
1234 | load_ucode_ap(); | |
1235 | ||
0f3fa48a IM |
1236 | cpu = stack_smp_processor_id(); |
1237 | t = &per_cpu(init_tss, cpu); | |
0fe1e009 | 1238 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1239 | |
e7a22c1e | 1240 | #ifdef CONFIG_NUMA |
27fd185f | 1241 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1242 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1243 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1244 | #endif |
1ba76586 YL |
1245 | |
1246 | me = current; | |
1247 | ||
c2d1cec1 | 1248 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1249 | panic("CPU#%d already initialized!\n", cpu); |
1250 | ||
2eaad1fd | 1251 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 YL |
1252 | |
1253 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1254 | ||
1255 | /* | |
1256 | * Initialize the per-CPU GDT with the boot GDT, | |
1257 | * and set up the GDT descriptor: | |
1258 | */ | |
1259 | ||
552be871 | 1260 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1261 | loadsegment(fs, 0); |
1262 | ||
cf910e83 | 1263 | load_current_idt(); |
1ba76586 YL |
1264 | |
1265 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1266 | syscall_init(); | |
1267 | ||
1268 | wrmsrl(MSR_FS_BASE, 0); | |
1269 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1270 | barrier(); | |
1271 | ||
4763ed4d | 1272 | x86_configure_nx(); |
27fd185f | 1273 | enable_x2apic(); |
1ba76586 YL |
1274 | |
1275 | /* | |
1276 | * set up and load the per-CPU TSS | |
1277 | */ | |
0fe1e009 | 1278 | if (!oist->ist[0]) { |
92d65b23 | 1279 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1280 | |
1ba76586 | 1281 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1282 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1283 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1284 | (unsigned long)estacks; |
228bdaa9 SR |
1285 | if (v == DEBUG_STACK-1) |
1286 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1287 | } |
1288 | } | |
1289 | ||
1290 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1291 | |
1ba76586 YL |
1292 | /* |
1293 | * <= is required because the CPU will access up to | |
1294 | * 8 bits beyond the end of the IO permission bitmap. | |
1295 | */ | |
1296 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1297 | t->io_bitmap[i] = ~0UL; | |
1298 | ||
1299 | atomic_inc(&init_mm.mm_count); | |
1300 | me->active_mm = &init_mm; | |
8c5dfd25 | 1301 | BUG_ON(me->mm); |
1ba76586 YL |
1302 | enter_lazy_tlb(&init_mm, me); |
1303 | ||
1304 | load_sp0(t, ¤t->thread); | |
1305 | set_tss_desc(cpu, t); | |
1306 | load_TR_desc(); | |
1307 | load_LDT(&init_mm.context); | |
1308 | ||
0bb9fef9 JW |
1309 | clear_all_debug_regs(); |
1310 | dbg_restore_debug_regs(); | |
1ba76586 YL |
1311 | |
1312 | fpu_init(); | |
1313 | ||
1ba76586 YL |
1314 | if (is_uv_system()) |
1315 | uv_cpu_init(); | |
1316 | } | |
1317 | ||
1318 | #else | |
1319 | ||
148f9bb8 | 1320 | void cpu_init(void) |
9ee79a3d | 1321 | { |
d2cbcc49 RR |
1322 | int cpu = smp_processor_id(); |
1323 | struct task_struct *curr = current; | |
34048c9e | 1324 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1325 | struct thread_struct *thread = &curr->thread; |
62111195 | 1326 | |
e6ebf5de FY |
1327 | show_ucode_info_early(); |
1328 | ||
c2d1cec1 | 1329 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 | 1330 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
9766cdbc JSR |
1331 | for (;;) |
1332 | local_irq_enable(); | |
62111195 JF |
1333 | } |
1334 | ||
1335 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1336 | ||
1337 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1338 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1339 | |
cf910e83 | 1340 | load_current_idt(); |
552be871 | 1341 | switch_to_new_gdt(cpu); |
1da177e4 | 1342 | |
1da177e4 LT |
1343 | /* |
1344 | * Set up and load the per-CPU TSS and LDT | |
1345 | */ | |
1346 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1347 | curr->active_mm = &init_mm; |
8c5dfd25 | 1348 | BUG_ON(curr->mm); |
62111195 | 1349 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1350 | |
faca6227 | 1351 | load_sp0(t, thread); |
34048c9e | 1352 | set_tss_desc(cpu, t); |
1da177e4 LT |
1353 | load_TR_desc(); |
1354 | load_LDT(&init_mm.context); | |
1355 | ||
f9a196b8 TG |
1356 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1357 | ||
22c4e308 | 1358 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1359 | /* Set up doublefault TSS pointer in the GDT */ |
1360 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1361 | #endif |
1da177e4 | 1362 | |
9766cdbc | 1363 | clear_all_debug_regs(); |
0bb9fef9 | 1364 | dbg_restore_debug_regs(); |
1da177e4 | 1365 | |
0e49bf66 | 1366 | fpu_init(); |
1da177e4 | 1367 | } |
1ba76586 | 1368 | #endif |
5700f743 BP |
1369 | |
1370 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS | |
1371 | void warn_pre_alternatives(void) | |
1372 | { | |
1373 | WARN(1, "You're using static_cpu_has before alternatives have run!\n"); | |
1374 | } | |
1375 | EXPORT_SYMBOL_GPL(warn_pre_alternatives); | |
1376 | #endif | |
4a90a99c BP |
1377 | |
1378 | inline bool __static_cpu_has_safe(u16 bit) | |
1379 | { | |
1380 | return boot_cpu_has(bit); | |
1381 | } | |
1382 | EXPORT_SYMBOL_GPL(__static_cpu_has_safe); |