Commit | Line | Data |
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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
b6734c35 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
b342797c | 23 | #include <asm/smp.h> |
f472cdba | 24 | #include <asm/cpu.h> |
06879033 | 25 | #include <asm/cpumask.h> |
1da177e4 LT |
26 | #ifdef CONFIG_X86_LOCAL_APIC |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/apic.h> | |
29 | #include <mach_apic.h> | |
f0fc4aff | 30 | #include <asm/genapic.h> |
bdbcdd48 | 31 | #include <asm/uv/uv.h> |
1da177e4 LT |
32 | #endif |
33 | ||
f0fc4aff YL |
34 | #include <asm/pgtable.h> |
35 | #include <asm/processor.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/atomic.h> | |
38 | #include <asm/proto.h> | |
39 | #include <asm/sections.h> | |
40 | #include <asm/setup.h> | |
88b094fb | 41 | #include <asm/hypervisor.h> |
f0fc4aff | 42 | |
1da177e4 LT |
43 | #include "cpu.h" |
44 | ||
c2d1cec1 MT |
45 | #ifdef CONFIG_X86_64 |
46 | ||
47 | /* all of these masks are initialized in setup_cpu_local_masks() */ | |
48 | cpumask_var_t cpu_callin_mask; | |
49 | cpumask_var_t cpu_callout_mask; | |
50 | cpumask_var_t cpu_initialized_mask; | |
51 | ||
52 | /* representing cpus for which sibling maps can be computed */ | |
53 | cpumask_var_t cpu_sibling_setup_mask; | |
54 | ||
2f2f52ba BG |
55 | /* correctly size the local cpu masks */ |
56 | void setup_cpu_local_masks(void) | |
57 | { | |
58 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
59 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
60 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
61 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
62 | } | |
63 | ||
c2d1cec1 MT |
64 | #else /* CONFIG_X86_32 */ |
65 | ||
66 | cpumask_t cpu_callin_map; | |
67 | cpumask_t cpu_callout_map; | |
68 | cpumask_t cpu_initialized; | |
69 | cpumask_t cpu_sibling_setup_map; | |
70 | ||
71 | #endif /* CONFIG_X86_32 */ | |
72 | ||
73 | ||
0a488a53 YL |
74 | static struct cpu_dev *this_cpu __cpuinitdata; |
75 | ||
06deef89 | 76 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 77 | #ifdef CONFIG_X86_64 |
06deef89 BG |
78 | /* |
79 | * We need valid kernel segments for data and code in long mode too | |
80 | * IRET will check the segment types kkeil 2000/10/28 | |
81 | * Also sysret mandates a special GDT layout | |
82 | * | |
83 | * The TLS descriptors are currently at a different place compared to i386. | |
84 | * Hopefully nobody expects them at a fixed place (Wine?) | |
85 | */ | |
950ad7ff YL |
86 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
87 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
88 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
89 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
90 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
91 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
950ad7ff | 92 | #else |
6842ef0e GOC |
93 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
94 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
95 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
96 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
97 | /* |
98 | * Segments used for calling PnP BIOS have byte granularity. | |
99 | * They code segments and data segments have fixed 64k limits, | |
100 | * the transfer segment sizes are set at run time. | |
101 | */ | |
6842ef0e GOC |
102 | /* 32-bit code */ |
103 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
104 | /* 16-bit code */ | |
105 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
106 | /* 16-bit data */ | |
107 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
108 | /* 16-bit data */ | |
109 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
110 | /* 16-bit data */ | |
111 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
112 | /* |
113 | * The APM segments have byte granularity and their bases | |
114 | * are set at run time. All have 64k limits. | |
115 | */ | |
6842ef0e GOC |
116 | /* 32-bit code */ |
117 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 118 | /* 16-bit code */ |
6842ef0e GOC |
119 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
120 | /* data */ | |
121 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 122 | |
6842ef0e | 123 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
0dd76d73 | 124 | [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, |
950ad7ff | 125 | #endif |
06deef89 | 126 | } }; |
7a61d35d | 127 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 128 | |
ba51dced | 129 | #ifdef CONFIG_X86_32 |
3bc9b76b | 130 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 131 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 132 | |
0a488a53 YL |
133 | static int __init cachesize_setup(char *str) |
134 | { | |
135 | get_option(&str, &cachesize_override); | |
136 | return 1; | |
137 | } | |
138 | __setup("cachesize=", cachesize_setup); | |
139 | ||
0a488a53 YL |
140 | static int __init x86_fxsr_setup(char *s) |
141 | { | |
142 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
143 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
144 | return 1; | |
145 | } | |
146 | __setup("nofxsr", x86_fxsr_setup); | |
147 | ||
148 | static int __init x86_sep_setup(char *s) | |
149 | { | |
150 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
151 | return 1; | |
152 | } | |
153 | __setup("nosep", x86_sep_setup); | |
154 | ||
155 | /* Standard macro to see if a specific flag is changeable */ | |
156 | static inline int flag_is_changeable_p(u32 flag) | |
157 | { | |
158 | u32 f1, f2; | |
159 | ||
94f6bac1 KH |
160 | /* |
161 | * Cyrix and IDT cpus allow disabling of CPUID | |
162 | * so the code below may return different results | |
163 | * when it is executed before and after enabling | |
164 | * the CPUID. Add "volatile" to not allow gcc to | |
165 | * optimize the subsequent calls to this function. | |
166 | */ | |
167 | asm volatile ("pushfl\n\t" | |
168 | "pushfl\n\t" | |
169 | "popl %0\n\t" | |
170 | "movl %0,%1\n\t" | |
171 | "xorl %2,%0\n\t" | |
172 | "pushl %0\n\t" | |
173 | "popfl\n\t" | |
174 | "pushfl\n\t" | |
175 | "popl %0\n\t" | |
176 | "popfl\n\t" | |
177 | : "=&r" (f1), "=&r" (f2) | |
178 | : "ir" (flag)); | |
0a488a53 YL |
179 | |
180 | return ((f1^f2) & flag) != 0; | |
181 | } | |
182 | ||
183 | /* Probe for the CPUID instruction */ | |
184 | static int __cpuinit have_cpuid_p(void) | |
185 | { | |
186 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
187 | } | |
188 | ||
189 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
190 | { | |
191 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
192 | /* Disable processor serial number */ | |
193 | unsigned long lo, hi; | |
194 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
195 | lo |= 0x200000; | |
196 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
197 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
198 | clear_cpu_cap(c, X86_FEATURE_PN); | |
199 | ||
200 | /* Disabling the serial number may affect the cpuid level */ | |
201 | c->cpuid_level = cpuid_eax(0); | |
202 | } | |
203 | } | |
204 | ||
205 | static int __init x86_serial_nr_setup(char *s) | |
206 | { | |
207 | disable_x86_serial_nr = 0; | |
208 | return 1; | |
209 | } | |
210 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 211 | #else |
102bbe3a YL |
212 | static inline int flag_is_changeable_p(u32 flag) |
213 | { | |
214 | return 1; | |
215 | } | |
ba51dced YL |
216 | /* Probe for the CPUID instruction */ |
217 | static inline int have_cpuid_p(void) | |
218 | { | |
219 | return 1; | |
220 | } | |
102bbe3a YL |
221 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
222 | { | |
223 | } | |
ba51dced | 224 | #endif |
0a488a53 | 225 | |
102bbe3a YL |
226 | /* |
227 | * Naming convention should be: <Name> [(<Codename>)] | |
228 | * This table only is used unless init_<vendor>() below doesn't set it; | |
229 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
230 | * | |
231 | */ | |
232 | ||
233 | /* Look up CPU names by table lookup. */ | |
234 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
235 | { | |
236 | struct cpu_model_info *info; | |
237 | ||
238 | if (c->x86_model >= 16) | |
239 | return NULL; /* Range check */ | |
240 | ||
241 | if (!this_cpu) | |
242 | return NULL; | |
243 | ||
244 | info = this_cpu->c_models; | |
245 | ||
246 | while (info && info->family) { | |
247 | if (info->family == c->x86) | |
248 | return info->model_names[c->x86_model]; | |
249 | info++; | |
250 | } | |
251 | return NULL; /* Not found */ | |
252 | } | |
253 | ||
7d851c8d AK |
254 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
255 | ||
9d31d35b YL |
256 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
257 | * it's on the real one. */ | |
258 | void switch_to_new_gdt(void) | |
259 | { | |
260 | struct desc_ptr gdt_descr; | |
261 | ||
262 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
263 | gdt_descr.size = GDT_SIZE - 1; | |
264 | load_gdt(&gdt_descr); | |
fab334c1 | 265 | #ifdef CONFIG_X86_32 |
9d31d35b | 266 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); |
fab334c1 | 267 | #endif |
9d31d35b YL |
268 | } |
269 | ||
10a434fc | 270 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 271 | |
34048c9e | 272 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 273 | { |
b9e67f00 YL |
274 | #ifdef CONFIG_X86_64 |
275 | display_cacheinfo(c); | |
276 | #else | |
1da177e4 LT |
277 | /* Not much we can do here... */ |
278 | /* Check if at least it has cpuid */ | |
279 | if (c->cpuid_level == -1) { | |
280 | /* No cpuid. It must be an ancient CPU */ | |
281 | if (c->x86 == 4) | |
282 | strcpy(c->x86_model_id, "486"); | |
283 | else if (c->x86 == 3) | |
284 | strcpy(c->x86_model_id, "386"); | |
285 | } | |
b9e67f00 | 286 | #endif |
1da177e4 LT |
287 | } |
288 | ||
95414930 | 289 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 290 | .c_init = default_init, |
fe38d855 | 291 | .c_vendor = "Unknown", |
10a434fc | 292 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 293 | }; |
1da177e4 | 294 | |
1b05d60d | 295 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
296 | { |
297 | unsigned int *v; | |
298 | char *p, *q; | |
299 | ||
3da99c97 | 300 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 301 | return; |
1da177e4 LT |
302 | |
303 | v = (unsigned int *) c->x86_model_id; | |
304 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
305 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
306 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
307 | c->x86_model_id[48] = 0; | |
308 | ||
309 | /* Intel chips right-justify this string for some dumb reason; | |
310 | undo that brain damage */ | |
311 | p = q = &c->x86_model_id[0]; | |
34048c9e | 312 | while (*p == ' ') |
1da177e4 | 313 | p++; |
34048c9e PC |
314 | if (p != q) { |
315 | while (*p) | |
1da177e4 | 316 | *q++ = *p++; |
34048c9e | 317 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
318 | *q++ = '\0'; /* Zero-pad the rest */ |
319 | } | |
1da177e4 LT |
320 | } |
321 | ||
3bc9b76b | 322 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 323 | { |
9d31d35b | 324 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 325 | |
3da99c97 | 326 | n = c->extended_cpuid_level; |
1da177e4 LT |
327 | |
328 | if (n >= 0x80000005) { | |
9d31d35b | 329 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 330 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
331 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
332 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
333 | #ifdef CONFIG_X86_64 |
334 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
335 | c->x86_tlbsize = 0; | |
336 | #endif | |
1da177e4 LT |
337 | } |
338 | ||
339 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
340 | return; | |
341 | ||
0a488a53 | 342 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 343 | l2size = ecx >> 16; |
34048c9e | 344 | |
140fc727 YL |
345 | #ifdef CONFIG_X86_64 |
346 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
347 | #else | |
1da177e4 LT |
348 | /* do processor-specific cache resizing */ |
349 | if (this_cpu->c_size_cache) | |
34048c9e | 350 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
351 | |
352 | /* Allow user to override all this if necessary. */ | |
353 | if (cachesize_override != -1) | |
354 | l2size = cachesize_override; | |
355 | ||
34048c9e | 356 | if (l2size == 0) |
1da177e4 | 357 | return; /* Again, no L2 cache is possible */ |
140fc727 | 358 | #endif |
1da177e4 LT |
359 | |
360 | c->x86_cache_size = l2size; | |
361 | ||
362 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 363 | l2size, ecx & 0xFF); |
1da177e4 LT |
364 | } |
365 | ||
9d31d35b | 366 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 367 | { |
97e4db7c | 368 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
369 | u32 eax, ebx, ecx, edx; |
370 | int index_msb, core_bits; | |
1da177e4 | 371 | |
0a488a53 | 372 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 373 | return; |
1da177e4 | 374 | |
0a488a53 YL |
375 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
376 | goto out; | |
1da177e4 | 377 | |
1cd78776 YL |
378 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
379 | return; | |
1da177e4 | 380 | |
0a488a53 | 381 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 382 | |
9d31d35b YL |
383 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
384 | ||
385 | if (smp_num_siblings == 1) { | |
386 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
387 | } else if (smp_num_siblings > 1) { | |
388 | ||
9628937d | 389 | if (smp_num_siblings > nr_cpu_ids) { |
9d31d35b YL |
390 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", |
391 | smp_num_siblings); | |
392 | smp_num_siblings = 1; | |
393 | return; | |
394 | } | |
395 | ||
396 | index_msb = get_count_order(smp_num_siblings); | |
1cd78776 YL |
397 | #ifdef CONFIG_X86_64 |
398 | c->phys_proc_id = phys_pkg_id(index_msb); | |
399 | #else | |
9d31d35b | 400 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); |
1cd78776 | 401 | #endif |
9d31d35b YL |
402 | |
403 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
404 | ||
405 | index_msb = get_count_order(smp_num_siblings); | |
406 | ||
407 | core_bits = get_count_order(c->x86_max_cores); | |
408 | ||
1cd78776 YL |
409 | #ifdef CONFIG_X86_64 |
410 | c->cpu_core_id = phys_pkg_id(index_msb) & | |
411 | ((1 << core_bits) - 1); | |
412 | #else | |
9d31d35b YL |
413 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & |
414 | ((1 << core_bits) - 1); | |
1cd78776 | 415 | #endif |
1da177e4 | 416 | } |
1da177e4 | 417 | |
0a488a53 YL |
418 | out: |
419 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
420 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
421 | c->phys_proc_id); | |
422 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
423 | c->cpu_core_id); | |
9d31d35b | 424 | } |
9d31d35b | 425 | #endif |
97e4db7c | 426 | } |
1da177e4 | 427 | |
3da99c97 | 428 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
429 | { |
430 | char *v = c->x86_vendor_id; | |
431 | int i; | |
fe38d855 | 432 | static int printed; |
1da177e4 LT |
433 | |
434 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
435 | if (!cpu_devs[i]) |
436 | break; | |
437 | ||
438 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
439 | (cpu_devs[i]->c_ident[1] && | |
440 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
441 | this_cpu = cpu_devs[i]; | |
442 | c->x86_vendor = this_cpu->c_x86_vendor; | |
443 | return; | |
1da177e4 LT |
444 | } |
445 | } | |
10a434fc | 446 | |
fe38d855 CE |
447 | if (!printed) { |
448 | printed++; | |
43603c8d | 449 | printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); |
fe38d855 CE |
450 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
451 | } | |
10a434fc | 452 | |
fe38d855 CE |
453 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
454 | this_cpu = &default_cpu; | |
1da177e4 LT |
455 | } |
456 | ||
9d31d35b | 457 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 458 | { |
1da177e4 | 459 | /* Get vendor name */ |
4a148513 HH |
460 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
461 | (unsigned int *)&c->x86_vendor_id[0], | |
462 | (unsigned int *)&c->x86_vendor_id[8], | |
463 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 464 | |
1da177e4 | 465 | c->x86 = 4; |
9d31d35b | 466 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
467 | if (c->cpuid_level >= 0x00000001) { |
468 | u32 junk, tfms, cap0, misc; | |
469 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
470 | c->x86 = (tfms >> 8) & 0xf; |
471 | c->x86_model = (tfms >> 4) & 0xf; | |
472 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 473 | if (c->x86 == 0xf) |
1da177e4 | 474 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 475 | if (c->x86 >= 0x6) |
9d31d35b | 476 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 477 | if (cap0 & (1<<19)) { |
d4387bd3 | 478 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 479 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 480 | } |
1da177e4 | 481 | } |
1da177e4 | 482 | } |
3da99c97 YL |
483 | |
484 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
485 | { |
486 | u32 tfms, xlvl; | |
3da99c97 | 487 | u32 ebx; |
093af8d7 | 488 | |
3da99c97 YL |
489 | /* Intel-defined flags: level 0x00000001 */ |
490 | if (c->cpuid_level >= 0x00000001) { | |
491 | u32 capability, excap; | |
492 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
493 | c->x86_capability[0] = capability; | |
494 | c->x86_capability[4] = excap; | |
495 | } | |
093af8d7 | 496 | |
3da99c97 YL |
497 | /* AMD-defined flags: level 0x80000001 */ |
498 | xlvl = cpuid_eax(0x80000000); | |
499 | c->extended_cpuid_level = xlvl; | |
500 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
501 | if (xlvl >= 0x80000001) { | |
502 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
503 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 504 | } |
093af8d7 | 505 | } |
093af8d7 | 506 | |
5122c890 | 507 | #ifdef CONFIG_X86_64 |
5122c890 YL |
508 | if (c->extended_cpuid_level >= 0x80000008) { |
509 | u32 eax = cpuid_eax(0x80000008); | |
510 | ||
511 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
512 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 513 | } |
5122c890 | 514 | #endif |
e3224234 YL |
515 | |
516 | if (c->extended_cpuid_level >= 0x80000007) | |
517 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
518 | |
519 | } | |
1da177e4 | 520 | |
aef93c8b YL |
521 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
522 | { | |
523 | #ifdef CONFIG_X86_32 | |
524 | int i; | |
525 | ||
526 | /* | |
527 | * First of all, decide if this is a 486 or higher | |
528 | * It's a 486 if we can modify the AC flag | |
529 | */ | |
530 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
531 | c->x86 = 4; | |
532 | else | |
533 | c->x86 = 3; | |
534 | ||
535 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
536 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
537 | c->x86_vendor_id[0] = 0; | |
538 | cpu_devs[i]->c_identify(c); | |
539 | if (c->x86_vendor_id[0]) { | |
540 | get_cpu_vendor(c); | |
541 | break; | |
542 | } | |
543 | } | |
544 | #endif | |
545 | } | |
546 | ||
34048c9e PC |
547 | /* |
548 | * Do minimum CPU detection early. | |
549 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
550 | * cache alignment. | |
551 | * The others are not touched to avoid unwanted side effects. | |
552 | * | |
553 | * WARNING: this function is only called on the BP. Don't add code here | |
554 | * that is supposed to run on all CPUs. | |
555 | */ | |
3da99c97 | 556 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 557 | { |
6627d242 YL |
558 | #ifdef CONFIG_X86_64 |
559 | c->x86_clflush_size = 64; | |
560 | #else | |
d4387bd3 | 561 | c->x86_clflush_size = 32; |
6627d242 | 562 | #endif |
0a488a53 | 563 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 564 | |
3da99c97 | 565 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 566 | c->extended_cpuid_level = 0; |
d7cd5611 | 567 | |
aef93c8b YL |
568 | if (!have_cpuid_p()) |
569 | identify_cpu_without_cpuid(c); | |
570 | ||
571 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
572 | if (!have_cpuid_p()) |
573 | return; | |
574 | ||
575 | cpu_detect(c); | |
576 | ||
3da99c97 | 577 | get_cpu_vendor(c); |
2b16a235 | 578 | |
3da99c97 | 579 | get_cpu_cap(c); |
12cf105c | 580 | |
10a434fc YL |
581 | if (this_cpu->c_early_init) |
582 | this_cpu->c_early_init(c); | |
093af8d7 | 583 | |
3da99c97 | 584 | validate_pat_support(c); |
bfcb4c1b | 585 | |
1c4acdb4 | 586 | #ifdef CONFIG_SMP |
bfcb4c1b | 587 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 588 | #endif |
d7cd5611 RR |
589 | } |
590 | ||
9d31d35b YL |
591 | void __init early_cpu_init(void) |
592 | { | |
10a434fc YL |
593 | struct cpu_dev **cdev; |
594 | int count = 0; | |
595 | ||
596 | printk("KERNEL supported cpus:\n"); | |
597 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
598 | struct cpu_dev *cpudev = *cdev; | |
599 | unsigned int j; | |
9d31d35b | 600 | |
10a434fc YL |
601 | if (count >= X86_VENDOR_NUM) |
602 | break; | |
603 | cpu_devs[count] = cpudev; | |
604 | count++; | |
605 | ||
606 | for (j = 0; j < 2; j++) { | |
607 | if (!cpudev->c_ident[j]) | |
608 | continue; | |
609 | printk(" %s %s\n", cpudev->c_vendor, | |
610 | cpudev->c_ident[j]); | |
611 | } | |
612 | } | |
9d31d35b | 613 | |
9d31d35b | 614 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 615 | } |
093af8d7 | 616 | |
b6734c35 PA |
617 | /* |
618 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 619 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 620 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
621 | * are not easy to detect. In the latter case it doesn't even *fail* |
622 | * reliably, so probing for it doesn't even work. Disable it completely | |
623 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
624 | */ |
625 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
626 | { | |
b6734c35 | 627 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
628 | } |
629 | ||
34048c9e | 630 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 631 | { |
aef93c8b | 632 | c->extended_cpuid_level = 0; |
1da177e4 | 633 | |
3da99c97 | 634 | if (!have_cpuid_p()) |
aef93c8b | 635 | identify_cpu_without_cpuid(c); |
1d67953f | 636 | |
aef93c8b | 637 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 638 | if (!have_cpuid_p()) |
aef93c8b | 639 | return; |
1da177e4 | 640 | |
3da99c97 | 641 | cpu_detect(c); |
1da177e4 | 642 | |
3da99c97 | 643 | get_cpu_vendor(c); |
1da177e4 | 644 | |
3da99c97 | 645 | get_cpu_cap(c); |
1da177e4 | 646 | |
3da99c97 YL |
647 | if (c->cpuid_level >= 0x00000001) { |
648 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
649 | #ifdef CONFIG_X86_32 |
650 | # ifdef CONFIG_X86_HT | |
3da99c97 | 651 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 652 | # else |
3da99c97 | 653 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
654 | # endif |
655 | #endif | |
1da177e4 | 656 | |
b89d3b3e YL |
657 | #ifdef CONFIG_X86_HT |
658 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 659 | #endif |
3da99c97 | 660 | } |
1da177e4 | 661 | |
1b05d60d | 662 | get_model_name(c); /* Default name */ |
1da177e4 | 663 | |
3da99c97 YL |
664 | init_scattered_cpuid_features(c); |
665 | detect_nopl(c); | |
1da177e4 | 666 | } |
1da177e4 LT |
667 | |
668 | /* | |
669 | * This does the hard work of actually picking apart the CPU stuff... | |
670 | */ | |
9a250347 | 671 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
672 | { |
673 | int i; | |
674 | ||
675 | c->loops_per_jiffy = loops_per_jiffy; | |
676 | c->x86_cache_size = -1; | |
677 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
678 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
679 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
680 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 681 | c->x86_max_cores = 1; |
102bbe3a | 682 | c->x86_coreid_bits = 0; |
11fdd252 | 683 | #ifdef CONFIG_X86_64 |
102bbe3a YL |
684 | c->x86_clflush_size = 64; |
685 | #else | |
686 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 687 | c->x86_clflush_size = 32; |
102bbe3a YL |
688 | #endif |
689 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
690 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
691 | ||
1da177e4 LT |
692 | generic_identify(c); |
693 | ||
3898534d | 694 | if (this_cpu->c_identify) |
1da177e4 LT |
695 | this_cpu->c_identify(c); |
696 | ||
102bbe3a YL |
697 | #ifdef CONFIG_X86_64 |
698 | c->apicid = phys_pkg_id(0); | |
699 | #endif | |
700 | ||
1da177e4 LT |
701 | /* |
702 | * Vendor-specific initialization. In this section we | |
703 | * canonicalize the feature flags, meaning if there are | |
704 | * features a certain CPU supports which CPUID doesn't | |
705 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
706 | * we handle them here. | |
707 | * | |
708 | * At the end of this section, c->x86_capability better | |
709 | * indicate the features this CPU genuinely supports! | |
710 | */ | |
711 | if (this_cpu->c_init) | |
712 | this_cpu->c_init(c); | |
713 | ||
714 | /* Disable the PN if appropriate */ | |
715 | squash_the_stupid_serial_number(c); | |
716 | ||
717 | /* | |
718 | * The vendor-specific functions might have changed features. Now | |
719 | * we do "generic changes." | |
720 | */ | |
721 | ||
1da177e4 | 722 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 723 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
724 | char *p; |
725 | p = table_lookup_model(c); | |
34048c9e | 726 | if (p) |
1da177e4 LT |
727 | strcpy(c->x86_model_id, p); |
728 | else | |
729 | /* Last resort... */ | |
730 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 731 | c->x86, c->x86_model); |
1da177e4 LT |
732 | } |
733 | ||
102bbe3a YL |
734 | #ifdef CONFIG_X86_64 |
735 | detect_ht(c); | |
736 | #endif | |
737 | ||
88b094fb | 738 | init_hypervisor(c); |
1da177e4 LT |
739 | /* |
740 | * On SMP, boot_cpu_data holds the common feature set between | |
741 | * all CPUs; so make sure that we indicate which features are | |
742 | * common between the CPUs. The first time this routine gets | |
743 | * executed, c == &boot_cpu_data. | |
744 | */ | |
34048c9e | 745 | if (c != &boot_cpu_data) { |
1da177e4 | 746 | /* AND the already accumulated flags with these */ |
9d31d35b | 747 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
748 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
749 | } | |
750 | ||
7d851c8d AK |
751 | /* Clear all flags overriden by options */ |
752 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 753 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 754 | |
102bbe3a | 755 | #ifdef CONFIG_X86_MCE |
1da177e4 | 756 | /* Init Machine Check Exception if available. */ |
1da177e4 | 757 | mcheck_init(c); |
102bbe3a | 758 | #endif |
30d432df AK |
759 | |
760 | select_idle_routine(c); | |
102bbe3a YL |
761 | |
762 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
763 | numa_add_cpu(smp_processor_id()); | |
764 | #endif | |
a6c4e076 | 765 | } |
31ab269a | 766 | |
e04d645f GC |
767 | #ifdef CONFIG_X86_64 |
768 | static void vgetcpu_set_mode(void) | |
769 | { | |
770 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
771 | vgetcpu_mode = VGETCPU_RDTSCP; | |
772 | else | |
773 | vgetcpu_mode = VGETCPU_LSL; | |
774 | } | |
775 | #endif | |
776 | ||
a6c4e076 JF |
777 | void __init identify_boot_cpu(void) |
778 | { | |
779 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 780 | #ifdef CONFIG_X86_32 |
a6c4e076 | 781 | sysenter_setup(); |
6fe940d6 | 782 | enable_sep_cpu(); |
e04d645f GC |
783 | #else |
784 | vgetcpu_set_mode(); | |
102bbe3a | 785 | #endif |
a6c4e076 | 786 | } |
3b520b23 | 787 | |
a6c4e076 JF |
788 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
789 | { | |
790 | BUG_ON(c == &boot_cpu_data); | |
791 | identify_cpu(c); | |
102bbe3a | 792 | #ifdef CONFIG_X86_32 |
a6c4e076 | 793 | enable_sep_cpu(); |
102bbe3a | 794 | #endif |
a6c4e076 | 795 | mtrr_ap_init(); |
1da177e4 LT |
796 | } |
797 | ||
a0854a46 YL |
798 | struct msr_range { |
799 | unsigned min; | |
800 | unsigned max; | |
801 | }; | |
1da177e4 | 802 | |
a0854a46 YL |
803 | static struct msr_range msr_range_array[] __cpuinitdata = { |
804 | { 0x00000000, 0x00000418}, | |
805 | { 0xc0000000, 0xc000040b}, | |
806 | { 0xc0010000, 0xc0010142}, | |
807 | { 0xc0011000, 0xc001103b}, | |
808 | }; | |
1da177e4 | 809 | |
a0854a46 YL |
810 | static void __cpuinit print_cpu_msr(void) |
811 | { | |
812 | unsigned index; | |
813 | u64 val; | |
814 | int i; | |
815 | unsigned index_min, index_max; | |
816 | ||
817 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
818 | index_min = msr_range_array[i].min; | |
819 | index_max = msr_range_array[i].max; | |
820 | for (index = index_min; index < index_max; index++) { | |
821 | if (rdmsrl_amd_safe(index, &val)) | |
822 | continue; | |
823 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 824 | } |
a0854a46 YL |
825 | } |
826 | } | |
94605eff | 827 | |
a0854a46 YL |
828 | static int show_msr __cpuinitdata; |
829 | static __init int setup_show_msr(char *arg) | |
830 | { | |
831 | int num; | |
3dd9d514 | 832 | |
a0854a46 | 833 | get_option(&arg, &num); |
3dd9d514 | 834 | |
a0854a46 YL |
835 | if (num > 0) |
836 | show_msr = num; | |
837 | return 1; | |
1da177e4 | 838 | } |
a0854a46 | 839 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 840 | |
191679fd AK |
841 | static __init int setup_noclflush(char *arg) |
842 | { | |
843 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
844 | return 1; | |
845 | } | |
846 | __setup("noclflush", setup_noclflush); | |
847 | ||
3bc9b76b | 848 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
849 | { |
850 | char *vendor = NULL; | |
851 | ||
852 | if (c->x86_vendor < X86_VENDOR_NUM) | |
853 | vendor = this_cpu->c_vendor; | |
854 | else if (c->cpuid_level >= 0) | |
855 | vendor = c->x86_vendor_id; | |
856 | ||
bd32a8cf | 857 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 858 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 859 | |
9d31d35b YL |
860 | if (c->x86_model_id[0]) |
861 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 862 | else |
9d31d35b | 863 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 864 | |
34048c9e | 865 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 866 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 867 | else |
9d31d35b | 868 | printk(KERN_CONT "\n"); |
a0854a46 YL |
869 | |
870 | #ifdef CONFIG_SMP | |
871 | if (c->cpu_index < show_msr) | |
872 | print_cpu_msr(); | |
873 | #else | |
874 | if (show_msr) | |
875 | print_cpu_msr(); | |
876 | #endif | |
1da177e4 LT |
877 | } |
878 | ||
ac72e788 AK |
879 | static __init int setup_disablecpuid(char *arg) |
880 | { | |
881 | int bit; | |
882 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
883 | setup_clear_cpu_cap(bit); | |
884 | else | |
885 | return 0; | |
886 | return 1; | |
887 | } | |
888 | __setup("clearcpuid=", setup_disablecpuid); | |
889 | ||
d5494d4f | 890 | #ifdef CONFIG_X86_64 |
d5494d4f YL |
891 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; |
892 | ||
947e76cd BG |
893 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
894 | irq_stack_union) __aligned(PAGE_SIZE); | |
26f80bd6 BG |
895 | #ifdef CONFIG_SMP |
896 | DEFINE_PER_CPU(char *, irq_stack_ptr); /* will be set during per cpu init */ | |
897 | #else | |
898 | DEFINE_PER_CPU(char *, irq_stack_ptr) = | |
947e76cd | 899 | per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; |
26f80bd6 | 900 | #endif |
d5494d4f | 901 | |
9af45651 BG |
902 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
903 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
904 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
905 | ||
56895530 BG |
906 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
907 | ||
92d65b23 BG |
908 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
909 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) | |
910 | __aligned(PAGE_SIZE); | |
d5494d4f YL |
911 | |
912 | extern asmlinkage void ignore_sysret(void); | |
913 | ||
914 | /* May not be marked __init: used by software suspend */ | |
915 | void syscall_init(void) | |
1da177e4 | 916 | { |
d5494d4f YL |
917 | /* |
918 | * LSTAR and STAR live in a bit strange symbiosis. | |
919 | * They both write to the same internal register. STAR allows to | |
920 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
921 | */ | |
922 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
923 | wrmsrl(MSR_LSTAR, system_call); | |
924 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 925 | |
d5494d4f YL |
926 | #ifdef CONFIG_IA32_EMULATION |
927 | syscall32_cpu_init(); | |
928 | #endif | |
03ae5768 | 929 | |
d5494d4f YL |
930 | /* Flags to clear on syscall */ |
931 | wrmsrl(MSR_SYSCALL_MASK, | |
932 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 933 | } |
62111195 | 934 | |
d5494d4f YL |
935 | unsigned long kernel_eflags; |
936 | ||
937 | /* | |
938 | * Copies of the original ist values from the tss are only accessed during | |
939 | * debugging, no special alignment required. | |
940 | */ | |
941 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
942 | ||
943 | #else | |
944 | ||
7c3576d2 | 945 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 946 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
947 | { |
948 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 949 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
950 | return regs; |
951 | } | |
d5494d4f | 952 | #endif |
c5413fbe | 953 | |
d2cbcc49 RR |
954 | /* |
955 | * cpu_init() initializes state that is per-CPU. Some data is already | |
956 | * initialized (naturally) in the bootstrap process, such as the GDT | |
957 | * and IDT. We reload them nevertheless, this function acts as a | |
958 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 959 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 960 | */ |
1ba76586 YL |
961 | #ifdef CONFIG_X86_64 |
962 | void __cpuinit cpu_init(void) | |
963 | { | |
964 | int cpu = stack_smp_processor_id(); | |
965 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
966 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
967 | unsigned long v; | |
1ba76586 YL |
968 | struct task_struct *me; |
969 | int i; | |
970 | ||
8ce03197 BG |
971 | loadsegment(fs, 0); |
972 | loadsegment(gs, 0); | |
947e76cd | 973 | load_gs_base(cpu); |
1ba76586 | 974 | |
e7a22c1e BG |
975 | #ifdef CONFIG_NUMA |
976 | if (cpu != 0 && percpu_read(node_number) == 0 && | |
977 | cpu_to_node(cpu) != NUMA_NO_NODE) | |
978 | percpu_write(node_number, cpu_to_node(cpu)); | |
979 | #endif | |
980 | ||
1ba76586 YL |
981 | me = current; |
982 | ||
c2d1cec1 | 983 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
984 | panic("CPU#%d already initialized!\n", cpu); |
985 | ||
986 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
987 | ||
988 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
989 | ||
990 | /* | |
991 | * Initialize the per-CPU GDT with the boot GDT, | |
992 | * and set up the GDT descriptor: | |
993 | */ | |
994 | ||
995 | switch_to_new_gdt(); | |
996 | load_idt((const struct desc_ptr *)&idt_descr); | |
997 | ||
998 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
999 | syscall_init(); | |
1000 | ||
1001 | wrmsrl(MSR_FS_BASE, 0); | |
1002 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1003 | barrier(); | |
1004 | ||
1005 | check_efer(); | |
1006 | if (cpu != 0 && x2apic) | |
1007 | enable_x2apic(); | |
1008 | ||
1009 | /* | |
1010 | * set up and load the per-CPU TSS | |
1011 | */ | |
1012 | if (!orig_ist->ist[0]) { | |
92d65b23 BG |
1013 | static const unsigned int sizes[N_EXCEPTION_STACKS] = { |
1014 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1015 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1ba76586 | 1016 | }; |
92d65b23 | 1017 | char *estacks = per_cpu(exception_stacks, cpu); |
1ba76586 | 1018 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
92d65b23 | 1019 | estacks += sizes[v]; |
1ba76586 YL |
1020 | orig_ist->ist[v] = t->x86_tss.ist[v] = |
1021 | (unsigned long)estacks; | |
1022 | } | |
1023 | } | |
1024 | ||
1025 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1026 | /* | |
1027 | * <= is required because the CPU will access up to | |
1028 | * 8 bits beyond the end of the IO permission bitmap. | |
1029 | */ | |
1030 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1031 | t->io_bitmap[i] = ~0UL; | |
1032 | ||
1033 | atomic_inc(&init_mm.mm_count); | |
1034 | me->active_mm = &init_mm; | |
1035 | if (me->mm) | |
1036 | BUG(); | |
1037 | enter_lazy_tlb(&init_mm, me); | |
1038 | ||
1039 | load_sp0(t, ¤t->thread); | |
1040 | set_tss_desc(cpu, t); | |
1041 | load_TR_desc(); | |
1042 | load_LDT(&init_mm.context); | |
1043 | ||
1044 | #ifdef CONFIG_KGDB | |
1045 | /* | |
1046 | * If the kgdb is connected no debug regs should be altered. This | |
1047 | * is only applicable when KGDB and a KGDB I/O module are built | |
1048 | * into the kernel and you are using early debugging with | |
1049 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1050 | */ | |
1051 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1052 | arch_kgdb_ops.correct_hw_break(); | |
1053 | else { | |
1054 | #endif | |
1055 | /* | |
1056 | * Clear all 6 debug registers: | |
1057 | */ | |
1058 | ||
1059 | set_debugreg(0UL, 0); | |
1060 | set_debugreg(0UL, 1); | |
1061 | set_debugreg(0UL, 2); | |
1062 | set_debugreg(0UL, 3); | |
1063 | set_debugreg(0UL, 6); | |
1064 | set_debugreg(0UL, 7); | |
1065 | #ifdef CONFIG_KGDB | |
1066 | /* If the kgdb is connected no debug regs should be altered. */ | |
1067 | } | |
1068 | #endif | |
1069 | ||
1070 | fpu_init(); | |
1071 | ||
1072 | raw_local_save_flags(kernel_eflags); | |
1073 | ||
1074 | if (is_uv_system()) | |
1075 | uv_cpu_init(); | |
1076 | } | |
1077 | ||
1078 | #else | |
1079 | ||
d2cbcc49 | 1080 | void __cpuinit cpu_init(void) |
9ee79a3d | 1081 | { |
d2cbcc49 RR |
1082 | int cpu = smp_processor_id(); |
1083 | struct task_struct *curr = current; | |
34048c9e | 1084 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1085 | struct thread_struct *thread = &curr->thread; |
62111195 | 1086 | |
c2d1cec1 | 1087 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 JF |
1088 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
1089 | for (;;) local_irq_enable(); | |
1090 | } | |
1091 | ||
1092 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1093 | ||
1094 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1095 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1096 | |
4d37e7e3 | 1097 | load_idt(&idt_descr); |
c5413fbe | 1098 | switch_to_new_gdt(); |
1da177e4 | 1099 | |
1da177e4 LT |
1100 | /* |
1101 | * Set up and load the per-CPU TSS and LDT | |
1102 | */ | |
1103 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1104 | curr->active_mm = &init_mm; |
1105 | if (curr->mm) | |
1106 | BUG(); | |
1107 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1108 | |
faca6227 | 1109 | load_sp0(t, thread); |
34048c9e | 1110 | set_tss_desc(cpu, t); |
1da177e4 LT |
1111 | load_TR_desc(); |
1112 | load_LDT(&init_mm.context); | |
1113 | ||
22c4e308 | 1114 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1115 | /* Set up doublefault TSS pointer in the GDT */ |
1116 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1117 | #endif |
1da177e4 | 1118 | |
464d1a78 JF |
1119 | /* Clear %gs. */ |
1120 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
1121 | |
1122 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
1123 | set_debugreg(0, 0); |
1124 | set_debugreg(0, 1); | |
1125 | set_debugreg(0, 2); | |
1126 | set_debugreg(0, 3); | |
1127 | set_debugreg(0, 6); | |
1128 | set_debugreg(0, 7); | |
1da177e4 LT |
1129 | |
1130 | /* | |
1131 | * Force FPU initialization: | |
1132 | */ | |
b359e8a4 SS |
1133 | if (cpu_has_xsave) |
1134 | current_thread_info()->status = TS_XSAVE; | |
1135 | else | |
1136 | current_thread_info()->status = 0; | |
1da177e4 LT |
1137 | clear_used_math(); |
1138 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1139 | |
1140 | /* | |
1141 | * Boot processor to setup the FP and extended state context info. | |
1142 | */ | |
b3572e36 | 1143 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1144 | init_thread_xstate(); |
1145 | ||
1146 | xsave_init(); | |
1da177e4 | 1147 | } |
e1367daf | 1148 | |
1ba76586 YL |
1149 | |
1150 | #endif |