Commit | Line | Data |
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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
b6734c35 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
1da177e4 LT |
23 | #ifdef CONFIG_X86_LOCAL_APIC |
24 | #include <asm/mpspec.h> | |
25 | #include <asm/apic.h> | |
26 | #include <mach_apic.h> | |
f0fc4aff | 27 | #include <asm/genapic.h> |
1da177e4 LT |
28 | #endif |
29 | ||
f0fc4aff YL |
30 | #include <asm/pda.h> |
31 | #include <asm/pgtable.h> | |
32 | #include <asm/processor.h> | |
33 | #include <asm/desc.h> | |
34 | #include <asm/atomic.h> | |
35 | #include <asm/proto.h> | |
36 | #include <asm/sections.h> | |
37 | #include <asm/setup.h> | |
38 | ||
1da177e4 LT |
39 | #include "cpu.h" |
40 | ||
0a488a53 YL |
41 | static struct cpu_dev *this_cpu __cpuinitdata; |
42 | ||
950ad7ff YL |
43 | #ifdef CONFIG_X86_64 |
44 | /* We need valid kernel segments for data and code in long mode too | |
45 | * IRET will check the segment types kkeil 2000/10/28 | |
46 | * Also sysret mandates a special GDT layout | |
47 | */ | |
48 | /* The TLS descriptors are currently at a different place compared to i386. | |
49 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
7a61d35d | 50 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff YL |
51 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
52 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
53 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
54 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
55 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
56 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
57 | } }; | |
58 | #else | |
63cc8c75 | 59 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
60 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
61 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
62 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
63 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
64 | /* |
65 | * Segments used for calling PnP BIOS have byte granularity. | |
66 | * They code segments and data segments have fixed 64k limits, | |
67 | * the transfer segment sizes are set at run time. | |
68 | */ | |
6842ef0e GOC |
69 | /* 32-bit code */ |
70 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
71 | /* 16-bit code */ | |
72 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
73 | /* 16-bit data */ | |
74 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
75 | /* 16-bit data */ | |
76 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
77 | /* 16-bit data */ | |
78 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
79 | /* |
80 | * The APM segments have byte granularity and their bases | |
81 | * are set at run time. All have 64k limits. | |
82 | */ | |
6842ef0e GOC |
83 | /* 32-bit code */ |
84 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 85 | /* 16-bit code */ |
6842ef0e GOC |
86 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
87 | /* data */ | |
88 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 89 | |
6842ef0e GOC |
90 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
91 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d | 92 | } }; |
950ad7ff | 93 | #endif |
7a61d35d | 94 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 95 | |
ba51dced | 96 | #ifdef CONFIG_X86_32 |
3bc9b76b | 97 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 98 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 99 | |
0a488a53 YL |
100 | static int __init cachesize_setup(char *str) |
101 | { | |
102 | get_option(&str, &cachesize_override); | |
103 | return 1; | |
104 | } | |
105 | __setup("cachesize=", cachesize_setup); | |
106 | ||
0a488a53 YL |
107 | static int __init x86_fxsr_setup(char *s) |
108 | { | |
109 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
110 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
111 | return 1; | |
112 | } | |
113 | __setup("nofxsr", x86_fxsr_setup); | |
114 | ||
115 | static int __init x86_sep_setup(char *s) | |
116 | { | |
117 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
118 | return 1; | |
119 | } | |
120 | __setup("nosep", x86_sep_setup); | |
121 | ||
122 | /* Standard macro to see if a specific flag is changeable */ | |
123 | static inline int flag_is_changeable_p(u32 flag) | |
124 | { | |
125 | u32 f1, f2; | |
126 | ||
94f6bac1 KH |
127 | /* |
128 | * Cyrix and IDT cpus allow disabling of CPUID | |
129 | * so the code below may return different results | |
130 | * when it is executed before and after enabling | |
131 | * the CPUID. Add "volatile" to not allow gcc to | |
132 | * optimize the subsequent calls to this function. | |
133 | */ | |
134 | asm volatile ("pushfl\n\t" | |
135 | "pushfl\n\t" | |
136 | "popl %0\n\t" | |
137 | "movl %0,%1\n\t" | |
138 | "xorl %2,%0\n\t" | |
139 | "pushl %0\n\t" | |
140 | "popfl\n\t" | |
141 | "pushfl\n\t" | |
142 | "popl %0\n\t" | |
143 | "popfl\n\t" | |
144 | : "=&r" (f1), "=&r" (f2) | |
145 | : "ir" (flag)); | |
0a488a53 YL |
146 | |
147 | return ((f1^f2) & flag) != 0; | |
148 | } | |
149 | ||
150 | /* Probe for the CPUID instruction */ | |
151 | static int __cpuinit have_cpuid_p(void) | |
152 | { | |
153 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
154 | } | |
155 | ||
156 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
157 | { | |
158 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
159 | /* Disable processor serial number */ | |
160 | unsigned long lo, hi; | |
161 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
162 | lo |= 0x200000; | |
163 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
164 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
165 | clear_cpu_cap(c, X86_FEATURE_PN); | |
166 | ||
167 | /* Disabling the serial number may affect the cpuid level */ | |
168 | c->cpuid_level = cpuid_eax(0); | |
169 | } | |
170 | } | |
171 | ||
172 | static int __init x86_serial_nr_setup(char *s) | |
173 | { | |
174 | disable_x86_serial_nr = 0; | |
175 | return 1; | |
176 | } | |
177 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 178 | #else |
102bbe3a YL |
179 | static inline int flag_is_changeable_p(u32 flag) |
180 | { | |
181 | return 1; | |
182 | } | |
ba51dced YL |
183 | /* Probe for the CPUID instruction */ |
184 | static inline int have_cpuid_p(void) | |
185 | { | |
186 | return 1; | |
187 | } | |
102bbe3a YL |
188 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
189 | { | |
190 | } | |
ba51dced | 191 | #endif |
0a488a53 | 192 | |
102bbe3a YL |
193 | /* |
194 | * Naming convention should be: <Name> [(<Codename>)] | |
195 | * This table only is used unless init_<vendor>() below doesn't set it; | |
196 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
197 | * | |
198 | */ | |
199 | ||
200 | /* Look up CPU names by table lookup. */ | |
201 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
202 | { | |
203 | struct cpu_model_info *info; | |
204 | ||
205 | if (c->x86_model >= 16) | |
206 | return NULL; /* Range check */ | |
207 | ||
208 | if (!this_cpu) | |
209 | return NULL; | |
210 | ||
211 | info = this_cpu->c_models; | |
212 | ||
213 | while (info && info->family) { | |
214 | if (info->family == c->x86) | |
215 | return info->model_names[c->x86_model]; | |
216 | info++; | |
217 | } | |
218 | return NULL; /* Not found */ | |
219 | } | |
220 | ||
7d851c8d AK |
221 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
222 | ||
9d31d35b YL |
223 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
224 | * it's on the real one. */ | |
225 | void switch_to_new_gdt(void) | |
226 | { | |
227 | struct desc_ptr gdt_descr; | |
228 | ||
229 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
230 | gdt_descr.size = GDT_SIZE - 1; | |
231 | load_gdt(&gdt_descr); | |
fab334c1 | 232 | #ifdef CONFIG_X86_32 |
9d31d35b | 233 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); |
fab334c1 | 234 | #endif |
9d31d35b YL |
235 | } |
236 | ||
10a434fc | 237 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 238 | |
34048c9e | 239 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 240 | { |
b9e67f00 YL |
241 | #ifdef CONFIG_X86_64 |
242 | display_cacheinfo(c); | |
243 | #else | |
1da177e4 LT |
244 | /* Not much we can do here... */ |
245 | /* Check if at least it has cpuid */ | |
246 | if (c->cpuid_level == -1) { | |
247 | /* No cpuid. It must be an ancient CPU */ | |
248 | if (c->x86 == 4) | |
249 | strcpy(c->x86_model_id, "486"); | |
250 | else if (c->x86 == 3) | |
251 | strcpy(c->x86_model_id, "386"); | |
252 | } | |
b9e67f00 | 253 | #endif |
1da177e4 LT |
254 | } |
255 | ||
95414930 | 256 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 257 | .c_init = default_init, |
fe38d855 | 258 | .c_vendor = "Unknown", |
10a434fc | 259 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 260 | }; |
1da177e4 | 261 | |
1b05d60d | 262 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
263 | { |
264 | unsigned int *v; | |
265 | char *p, *q; | |
266 | ||
3da99c97 | 267 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 268 | return; |
1da177e4 LT |
269 | |
270 | v = (unsigned int *) c->x86_model_id; | |
271 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
272 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
273 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
274 | c->x86_model_id[48] = 0; | |
275 | ||
276 | /* Intel chips right-justify this string for some dumb reason; | |
277 | undo that brain damage */ | |
278 | p = q = &c->x86_model_id[0]; | |
34048c9e | 279 | while (*p == ' ') |
1da177e4 | 280 | p++; |
34048c9e PC |
281 | if (p != q) { |
282 | while (*p) | |
1da177e4 | 283 | *q++ = *p++; |
34048c9e | 284 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
285 | *q++ = '\0'; /* Zero-pad the rest */ |
286 | } | |
1da177e4 LT |
287 | } |
288 | ||
3bc9b76b | 289 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 290 | { |
9d31d35b | 291 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 292 | |
3da99c97 | 293 | n = c->extended_cpuid_level; |
1da177e4 LT |
294 | |
295 | if (n >= 0x80000005) { | |
9d31d35b | 296 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 297 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
298 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
299 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
300 | #ifdef CONFIG_X86_64 |
301 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
302 | c->x86_tlbsize = 0; | |
303 | #endif | |
1da177e4 LT |
304 | } |
305 | ||
306 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
307 | return; | |
308 | ||
0a488a53 | 309 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 310 | l2size = ecx >> 16; |
34048c9e | 311 | |
140fc727 YL |
312 | #ifdef CONFIG_X86_64 |
313 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
314 | #else | |
1da177e4 LT |
315 | /* do processor-specific cache resizing */ |
316 | if (this_cpu->c_size_cache) | |
34048c9e | 317 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
318 | |
319 | /* Allow user to override all this if necessary. */ | |
320 | if (cachesize_override != -1) | |
321 | l2size = cachesize_override; | |
322 | ||
34048c9e | 323 | if (l2size == 0) |
1da177e4 | 324 | return; /* Again, no L2 cache is possible */ |
140fc727 | 325 | #endif |
1da177e4 LT |
326 | |
327 | c->x86_cache_size = l2size; | |
328 | ||
329 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 330 | l2size, ecx & 0xFF); |
1da177e4 LT |
331 | } |
332 | ||
9d31d35b | 333 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 334 | { |
97e4db7c | 335 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
336 | u32 eax, ebx, ecx, edx; |
337 | int index_msb, core_bits; | |
1da177e4 | 338 | |
0a488a53 | 339 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 340 | return; |
1da177e4 | 341 | |
0a488a53 YL |
342 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
343 | goto out; | |
1da177e4 | 344 | |
1cd78776 YL |
345 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
346 | return; | |
1da177e4 | 347 | |
0a488a53 | 348 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 349 | |
9d31d35b YL |
350 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
351 | ||
352 | if (smp_num_siblings == 1) { | |
353 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
354 | } else if (smp_num_siblings > 1) { | |
355 | ||
356 | if (smp_num_siblings > NR_CPUS) { | |
357 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", | |
358 | smp_num_siblings); | |
359 | smp_num_siblings = 1; | |
360 | return; | |
361 | } | |
362 | ||
363 | index_msb = get_count_order(smp_num_siblings); | |
1cd78776 YL |
364 | #ifdef CONFIG_X86_64 |
365 | c->phys_proc_id = phys_pkg_id(index_msb); | |
366 | #else | |
9d31d35b | 367 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); |
1cd78776 | 368 | #endif |
9d31d35b YL |
369 | |
370 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
371 | ||
372 | index_msb = get_count_order(smp_num_siblings); | |
373 | ||
374 | core_bits = get_count_order(c->x86_max_cores); | |
375 | ||
1cd78776 YL |
376 | #ifdef CONFIG_X86_64 |
377 | c->cpu_core_id = phys_pkg_id(index_msb) & | |
378 | ((1 << core_bits) - 1); | |
379 | #else | |
9d31d35b YL |
380 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & |
381 | ((1 << core_bits) - 1); | |
1cd78776 | 382 | #endif |
1da177e4 | 383 | } |
1da177e4 | 384 | |
0a488a53 YL |
385 | out: |
386 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
387 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
388 | c->phys_proc_id); | |
389 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
390 | c->cpu_core_id); | |
9d31d35b | 391 | } |
9d31d35b | 392 | #endif |
97e4db7c | 393 | } |
1da177e4 | 394 | |
3da99c97 | 395 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
396 | { |
397 | char *v = c->x86_vendor_id; | |
398 | int i; | |
fe38d855 | 399 | static int printed; |
1da177e4 LT |
400 | |
401 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
402 | if (!cpu_devs[i]) |
403 | break; | |
404 | ||
405 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
406 | (cpu_devs[i]->c_ident[1] && | |
407 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
408 | this_cpu = cpu_devs[i]; | |
409 | c->x86_vendor = this_cpu->c_x86_vendor; | |
410 | return; | |
1da177e4 LT |
411 | } |
412 | } | |
10a434fc | 413 | |
fe38d855 CE |
414 | if (!printed) { |
415 | printed++; | |
43603c8d | 416 | printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); |
fe38d855 CE |
417 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
418 | } | |
10a434fc | 419 | |
fe38d855 CE |
420 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
421 | this_cpu = &default_cpu; | |
1da177e4 LT |
422 | } |
423 | ||
9d31d35b | 424 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 425 | { |
1da177e4 | 426 | /* Get vendor name */ |
4a148513 HH |
427 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
428 | (unsigned int *)&c->x86_vendor_id[0], | |
429 | (unsigned int *)&c->x86_vendor_id[8], | |
430 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 431 | |
1da177e4 | 432 | c->x86 = 4; |
9d31d35b | 433 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
434 | if (c->cpuid_level >= 0x00000001) { |
435 | u32 junk, tfms, cap0, misc; | |
436 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
437 | c->x86 = (tfms >> 8) & 0xf; |
438 | c->x86_model = (tfms >> 4) & 0xf; | |
439 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 440 | if (c->x86 == 0xf) |
1da177e4 | 441 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 442 | if (c->x86 >= 0x6) |
9d31d35b | 443 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 444 | if (cap0 & (1<<19)) { |
d4387bd3 | 445 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 446 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 447 | } |
1da177e4 | 448 | } |
1da177e4 | 449 | } |
3da99c97 YL |
450 | |
451 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
452 | { |
453 | u32 tfms, xlvl; | |
3da99c97 | 454 | u32 ebx; |
093af8d7 | 455 | |
3da99c97 YL |
456 | /* Intel-defined flags: level 0x00000001 */ |
457 | if (c->cpuid_level >= 0x00000001) { | |
458 | u32 capability, excap; | |
459 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
460 | c->x86_capability[0] = capability; | |
461 | c->x86_capability[4] = excap; | |
462 | } | |
093af8d7 | 463 | |
3da99c97 YL |
464 | /* AMD-defined flags: level 0x80000001 */ |
465 | xlvl = cpuid_eax(0x80000000); | |
466 | c->extended_cpuid_level = xlvl; | |
467 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
468 | if (xlvl >= 0x80000001) { | |
469 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
470 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 471 | } |
093af8d7 | 472 | } |
093af8d7 | 473 | |
5122c890 | 474 | #ifdef CONFIG_X86_64 |
5122c890 YL |
475 | if (c->extended_cpuid_level >= 0x80000008) { |
476 | u32 eax = cpuid_eax(0x80000008); | |
477 | ||
478 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
479 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 480 | } |
5122c890 | 481 | #endif |
e3224234 YL |
482 | |
483 | if (c->extended_cpuid_level >= 0x80000007) | |
484 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
485 | |
486 | } | |
1da177e4 | 487 | |
aef93c8b YL |
488 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
489 | { | |
490 | #ifdef CONFIG_X86_32 | |
491 | int i; | |
492 | ||
493 | /* | |
494 | * First of all, decide if this is a 486 or higher | |
495 | * It's a 486 if we can modify the AC flag | |
496 | */ | |
497 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
498 | c->x86 = 4; | |
499 | else | |
500 | c->x86 = 3; | |
501 | ||
502 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
503 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
504 | c->x86_vendor_id[0] = 0; | |
505 | cpu_devs[i]->c_identify(c); | |
506 | if (c->x86_vendor_id[0]) { | |
507 | get_cpu_vendor(c); | |
508 | break; | |
509 | } | |
510 | } | |
511 | #endif | |
512 | } | |
513 | ||
34048c9e PC |
514 | /* |
515 | * Do minimum CPU detection early. | |
516 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
517 | * cache alignment. | |
518 | * The others are not touched to avoid unwanted side effects. | |
519 | * | |
520 | * WARNING: this function is only called on the BP. Don't add code here | |
521 | * that is supposed to run on all CPUs. | |
522 | */ | |
3da99c97 | 523 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 524 | { |
6627d242 YL |
525 | #ifdef CONFIG_X86_64 |
526 | c->x86_clflush_size = 64; | |
527 | #else | |
d4387bd3 | 528 | c->x86_clflush_size = 32; |
6627d242 | 529 | #endif |
0a488a53 | 530 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 531 | |
3da99c97 | 532 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 533 | c->extended_cpuid_level = 0; |
d7cd5611 | 534 | |
aef93c8b YL |
535 | if (!have_cpuid_p()) |
536 | identify_cpu_without_cpuid(c); | |
537 | ||
538 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
539 | if (!have_cpuid_p()) |
540 | return; | |
541 | ||
542 | cpu_detect(c); | |
543 | ||
3da99c97 | 544 | get_cpu_vendor(c); |
2b16a235 | 545 | |
3da99c97 | 546 | get_cpu_cap(c); |
12cf105c | 547 | |
10a434fc YL |
548 | if (this_cpu->c_early_init) |
549 | this_cpu->c_early_init(c); | |
093af8d7 | 550 | |
3da99c97 | 551 | validate_pat_support(c); |
bfcb4c1b JB |
552 | |
553 | c->cpu_index = boot_cpu_id; | |
d7cd5611 RR |
554 | } |
555 | ||
9d31d35b YL |
556 | void __init early_cpu_init(void) |
557 | { | |
10a434fc YL |
558 | struct cpu_dev **cdev; |
559 | int count = 0; | |
560 | ||
561 | printk("KERNEL supported cpus:\n"); | |
562 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
563 | struct cpu_dev *cpudev = *cdev; | |
564 | unsigned int j; | |
9d31d35b | 565 | |
10a434fc YL |
566 | if (count >= X86_VENDOR_NUM) |
567 | break; | |
568 | cpu_devs[count] = cpudev; | |
569 | count++; | |
570 | ||
571 | for (j = 0; j < 2; j++) { | |
572 | if (!cpudev->c_ident[j]) | |
573 | continue; | |
574 | printk(" %s %s\n", cpudev->c_vendor, | |
575 | cpudev->c_ident[j]); | |
576 | } | |
577 | } | |
9d31d35b | 578 | |
9d31d35b | 579 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 580 | } |
093af8d7 | 581 | |
b6734c35 PA |
582 | /* |
583 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 584 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 585 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
586 | * are not easy to detect. In the latter case it doesn't even *fail* |
587 | * reliably, so probing for it doesn't even work. Disable it completely | |
588 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
589 | */ |
590 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
591 | { | |
b6734c35 | 592 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
593 | } |
594 | ||
34048c9e | 595 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 596 | { |
aef93c8b | 597 | c->extended_cpuid_level = 0; |
1da177e4 | 598 | |
3da99c97 | 599 | if (!have_cpuid_p()) |
aef93c8b | 600 | identify_cpu_without_cpuid(c); |
1d67953f | 601 | |
aef93c8b | 602 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 603 | if (!have_cpuid_p()) |
aef93c8b | 604 | return; |
1da177e4 | 605 | |
3da99c97 | 606 | cpu_detect(c); |
1da177e4 | 607 | |
3da99c97 | 608 | get_cpu_vendor(c); |
1da177e4 | 609 | |
3da99c97 | 610 | get_cpu_cap(c); |
1da177e4 | 611 | |
3da99c97 YL |
612 | if (c->cpuid_level >= 0x00000001) { |
613 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
614 | #ifdef CONFIG_X86_32 |
615 | # ifdef CONFIG_X86_HT | |
3da99c97 | 616 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 617 | # else |
3da99c97 | 618 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
619 | # endif |
620 | #endif | |
1da177e4 | 621 | |
b89d3b3e YL |
622 | #ifdef CONFIG_X86_HT |
623 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 624 | #endif |
3da99c97 | 625 | } |
1da177e4 | 626 | |
1b05d60d | 627 | get_model_name(c); /* Default name */ |
1da177e4 | 628 | |
3da99c97 YL |
629 | init_scattered_cpuid_features(c); |
630 | detect_nopl(c); | |
1da177e4 | 631 | } |
1da177e4 LT |
632 | |
633 | /* | |
634 | * This does the hard work of actually picking apart the CPU stuff... | |
635 | */ | |
9a250347 | 636 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
637 | { |
638 | int i; | |
639 | ||
640 | c->loops_per_jiffy = loops_per_jiffy; | |
641 | c->x86_cache_size = -1; | |
642 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
643 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
644 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
645 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 646 | c->x86_max_cores = 1; |
102bbe3a | 647 | c->x86_coreid_bits = 0; |
11fdd252 | 648 | #ifdef CONFIG_X86_64 |
102bbe3a YL |
649 | c->x86_clflush_size = 64; |
650 | #else | |
651 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 652 | c->x86_clflush_size = 32; |
102bbe3a YL |
653 | #endif |
654 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
655 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
656 | ||
1da177e4 LT |
657 | generic_identify(c); |
658 | ||
3898534d | 659 | if (this_cpu->c_identify) |
1da177e4 LT |
660 | this_cpu->c_identify(c); |
661 | ||
102bbe3a YL |
662 | #ifdef CONFIG_X86_64 |
663 | c->apicid = phys_pkg_id(0); | |
664 | #endif | |
665 | ||
1da177e4 LT |
666 | /* |
667 | * Vendor-specific initialization. In this section we | |
668 | * canonicalize the feature flags, meaning if there are | |
669 | * features a certain CPU supports which CPUID doesn't | |
670 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
671 | * we handle them here. | |
672 | * | |
673 | * At the end of this section, c->x86_capability better | |
674 | * indicate the features this CPU genuinely supports! | |
675 | */ | |
676 | if (this_cpu->c_init) | |
677 | this_cpu->c_init(c); | |
678 | ||
679 | /* Disable the PN if appropriate */ | |
680 | squash_the_stupid_serial_number(c); | |
681 | ||
682 | /* | |
683 | * The vendor-specific functions might have changed features. Now | |
684 | * we do "generic changes." | |
685 | */ | |
686 | ||
1da177e4 | 687 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 688 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
689 | char *p; |
690 | p = table_lookup_model(c); | |
34048c9e | 691 | if (p) |
1da177e4 LT |
692 | strcpy(c->x86_model_id, p); |
693 | else | |
694 | /* Last resort... */ | |
695 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 696 | c->x86, c->x86_model); |
1da177e4 LT |
697 | } |
698 | ||
102bbe3a YL |
699 | #ifdef CONFIG_X86_64 |
700 | detect_ht(c); | |
701 | #endif | |
702 | ||
1da177e4 LT |
703 | /* |
704 | * On SMP, boot_cpu_data holds the common feature set between | |
705 | * all CPUs; so make sure that we indicate which features are | |
706 | * common between the CPUs. The first time this routine gets | |
707 | * executed, c == &boot_cpu_data. | |
708 | */ | |
34048c9e | 709 | if (c != &boot_cpu_data) { |
1da177e4 | 710 | /* AND the already accumulated flags with these */ |
9d31d35b | 711 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
712 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
713 | } | |
714 | ||
7d851c8d AK |
715 | /* Clear all flags overriden by options */ |
716 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 717 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 718 | |
102bbe3a | 719 | #ifdef CONFIG_X86_MCE |
1da177e4 | 720 | /* Init Machine Check Exception if available. */ |
1da177e4 | 721 | mcheck_init(c); |
102bbe3a | 722 | #endif |
30d432df AK |
723 | |
724 | select_idle_routine(c); | |
102bbe3a YL |
725 | |
726 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
727 | numa_add_cpu(smp_processor_id()); | |
728 | #endif | |
a6c4e076 | 729 | } |
31ab269a | 730 | |
e04d645f GC |
731 | #ifdef CONFIG_X86_64 |
732 | static void vgetcpu_set_mode(void) | |
733 | { | |
734 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
735 | vgetcpu_mode = VGETCPU_RDTSCP; | |
736 | else | |
737 | vgetcpu_mode = VGETCPU_LSL; | |
738 | } | |
739 | #endif | |
740 | ||
a6c4e076 JF |
741 | void __init identify_boot_cpu(void) |
742 | { | |
743 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 744 | #ifdef CONFIG_X86_32 |
a6c4e076 | 745 | sysenter_setup(); |
6fe940d6 | 746 | enable_sep_cpu(); |
e04d645f GC |
747 | #else |
748 | vgetcpu_set_mode(); | |
102bbe3a | 749 | #endif |
a6c4e076 | 750 | } |
3b520b23 | 751 | |
a6c4e076 JF |
752 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
753 | { | |
754 | BUG_ON(c == &boot_cpu_data); | |
755 | identify_cpu(c); | |
102bbe3a | 756 | #ifdef CONFIG_X86_32 |
a6c4e076 | 757 | enable_sep_cpu(); |
102bbe3a | 758 | #endif |
a6c4e076 | 759 | mtrr_ap_init(); |
1da177e4 LT |
760 | } |
761 | ||
a0854a46 YL |
762 | struct msr_range { |
763 | unsigned min; | |
764 | unsigned max; | |
765 | }; | |
1da177e4 | 766 | |
a0854a46 YL |
767 | static struct msr_range msr_range_array[] __cpuinitdata = { |
768 | { 0x00000000, 0x00000418}, | |
769 | { 0xc0000000, 0xc000040b}, | |
770 | { 0xc0010000, 0xc0010142}, | |
771 | { 0xc0011000, 0xc001103b}, | |
772 | }; | |
1da177e4 | 773 | |
a0854a46 YL |
774 | static void __cpuinit print_cpu_msr(void) |
775 | { | |
776 | unsigned index; | |
777 | u64 val; | |
778 | int i; | |
779 | unsigned index_min, index_max; | |
780 | ||
781 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
782 | index_min = msr_range_array[i].min; | |
783 | index_max = msr_range_array[i].max; | |
784 | for (index = index_min; index < index_max; index++) { | |
785 | if (rdmsrl_amd_safe(index, &val)) | |
786 | continue; | |
787 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 788 | } |
a0854a46 YL |
789 | } |
790 | } | |
94605eff | 791 | |
a0854a46 YL |
792 | static int show_msr __cpuinitdata; |
793 | static __init int setup_show_msr(char *arg) | |
794 | { | |
795 | int num; | |
3dd9d514 | 796 | |
a0854a46 | 797 | get_option(&arg, &num); |
3dd9d514 | 798 | |
a0854a46 YL |
799 | if (num > 0) |
800 | show_msr = num; | |
801 | return 1; | |
1da177e4 | 802 | } |
a0854a46 | 803 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 804 | |
191679fd AK |
805 | static __init int setup_noclflush(char *arg) |
806 | { | |
807 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
808 | return 1; | |
809 | } | |
810 | __setup("noclflush", setup_noclflush); | |
811 | ||
3bc9b76b | 812 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
813 | { |
814 | char *vendor = NULL; | |
815 | ||
816 | if (c->x86_vendor < X86_VENDOR_NUM) | |
817 | vendor = this_cpu->c_vendor; | |
818 | else if (c->cpuid_level >= 0) | |
819 | vendor = c->x86_vendor_id; | |
820 | ||
bd32a8cf | 821 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 822 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 823 | |
9d31d35b YL |
824 | if (c->x86_model_id[0]) |
825 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 826 | else |
9d31d35b | 827 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 828 | |
34048c9e | 829 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 830 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 831 | else |
9d31d35b | 832 | printk(KERN_CONT "\n"); |
a0854a46 YL |
833 | |
834 | #ifdef CONFIG_SMP | |
835 | if (c->cpu_index < show_msr) | |
836 | print_cpu_msr(); | |
837 | #else | |
838 | if (show_msr) | |
839 | print_cpu_msr(); | |
840 | #endif | |
1da177e4 LT |
841 | } |
842 | ||
ac72e788 AK |
843 | static __init int setup_disablecpuid(char *arg) |
844 | { | |
845 | int bit; | |
846 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
847 | setup_clear_cpu_cap(bit); | |
848 | else | |
849 | return 0; | |
850 | return 1; | |
851 | } | |
852 | __setup("clearcpuid=", setup_disablecpuid); | |
853 | ||
3bc9b76b | 854 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 855 | |
d5494d4f YL |
856 | #ifdef CONFIG_X86_64 |
857 | struct x8664_pda **_cpu_pda __read_mostly; | |
858 | EXPORT_SYMBOL(_cpu_pda); | |
859 | ||
860 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; | |
861 | ||
862 | char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; | |
863 | ||
2d9cd6c2 | 864 | void __cpuinit pda_init(int cpu) |
d5494d4f YL |
865 | { |
866 | struct x8664_pda *pda = cpu_pda(cpu); | |
867 | ||
868 | /* Setup up data that may be needed in __get_free_pages early */ | |
869 | loadsegment(fs, 0); | |
870 | loadsegment(gs, 0); | |
871 | /* Memory clobbers used to order PDA accessed */ | |
872 | mb(); | |
873 | wrmsrl(MSR_GS_BASE, pda); | |
874 | mb(); | |
875 | ||
876 | pda->cpunumber = cpu; | |
877 | pda->irqcount = -1; | |
878 | pda->kernelstack = (unsigned long)stack_thread_info() - | |
879 | PDA_STACKOFFSET + THREAD_SIZE; | |
880 | pda->active_mm = &init_mm; | |
881 | pda->mmu_state = 0; | |
882 | ||
883 | if (cpu == 0) { | |
884 | /* others are initialized in smpboot.c */ | |
885 | pda->pcurrent = &init_task; | |
886 | pda->irqstackptr = boot_cpu_stack; | |
887 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
888 | } else { | |
889 | if (!pda->irqstackptr) { | |
890 | pda->irqstackptr = (char *) | |
891 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
892 | if (!pda->irqstackptr) | |
893 | panic("cannot allocate irqstack for cpu %d", | |
894 | cpu); | |
895 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
896 | } | |
897 | ||
898 | if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) | |
899 | pda->nodenumber = cpu_to_node(cpu); | |
900 | } | |
901 | } | |
902 | ||
903 | char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + | |
904 | DEBUG_STKSZ] __page_aligned_bss; | |
905 | ||
906 | extern asmlinkage void ignore_sysret(void); | |
907 | ||
908 | /* May not be marked __init: used by software suspend */ | |
909 | void syscall_init(void) | |
1da177e4 | 910 | { |
d5494d4f YL |
911 | /* |
912 | * LSTAR and STAR live in a bit strange symbiosis. | |
913 | * They both write to the same internal register. STAR allows to | |
914 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
915 | */ | |
916 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
917 | wrmsrl(MSR_LSTAR, system_call); | |
918 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 919 | |
d5494d4f YL |
920 | #ifdef CONFIG_IA32_EMULATION |
921 | syscall32_cpu_init(); | |
922 | #endif | |
03ae5768 | 923 | |
d5494d4f YL |
924 | /* Flags to clear on syscall */ |
925 | wrmsrl(MSR_SYSCALL_MASK, | |
926 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 927 | } |
62111195 | 928 | |
d5494d4f YL |
929 | unsigned long kernel_eflags; |
930 | ||
931 | /* | |
932 | * Copies of the original ist values from the tss are only accessed during | |
933 | * debugging, no special alignment required. | |
934 | */ | |
935 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
936 | ||
937 | #else | |
938 | ||
7c3576d2 | 939 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 940 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
941 | { |
942 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 943 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
944 | return regs; |
945 | } | |
d5494d4f | 946 | #endif |
c5413fbe | 947 | |
d2cbcc49 RR |
948 | /* |
949 | * cpu_init() initializes state that is per-CPU. Some data is already | |
950 | * initialized (naturally) in the bootstrap process, such as the GDT | |
951 | * and IDT. We reload them nevertheless, this function acts as a | |
952 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 953 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 954 | */ |
1ba76586 YL |
955 | #ifdef CONFIG_X86_64 |
956 | void __cpuinit cpu_init(void) | |
957 | { | |
958 | int cpu = stack_smp_processor_id(); | |
959 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
960 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
961 | unsigned long v; | |
962 | char *estacks = NULL; | |
963 | struct task_struct *me; | |
964 | int i; | |
965 | ||
966 | /* CPU 0 is initialised in head64.c */ | |
967 | if (cpu != 0) | |
968 | pda_init(cpu); | |
969 | else | |
970 | estacks = boot_exception_stacks; | |
971 | ||
972 | me = current; | |
973 | ||
974 | if (cpu_test_and_set(cpu, cpu_initialized)) | |
975 | panic("CPU#%d already initialized!\n", cpu); | |
976 | ||
977 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
978 | ||
979 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
980 | ||
981 | /* | |
982 | * Initialize the per-CPU GDT with the boot GDT, | |
983 | * and set up the GDT descriptor: | |
984 | */ | |
985 | ||
986 | switch_to_new_gdt(); | |
987 | load_idt((const struct desc_ptr *)&idt_descr); | |
988 | ||
989 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
990 | syscall_init(); | |
991 | ||
992 | wrmsrl(MSR_FS_BASE, 0); | |
993 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
994 | barrier(); | |
995 | ||
996 | check_efer(); | |
997 | if (cpu != 0 && x2apic) | |
998 | enable_x2apic(); | |
999 | ||
1000 | /* | |
1001 | * set up and load the per-CPU TSS | |
1002 | */ | |
1003 | if (!orig_ist->ist[0]) { | |
1004 | static const unsigned int order[N_EXCEPTION_STACKS] = { | |
1005 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, | |
1006 | [DEBUG_STACK - 1] = DEBUG_STACK_ORDER | |
1007 | }; | |
1008 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
1009 | if (cpu) { | |
1010 | estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); | |
1011 | if (!estacks) | |
1012 | panic("Cannot allocate exception " | |
1013 | "stack %ld %d\n", v, cpu); | |
1014 | } | |
1015 | estacks += PAGE_SIZE << order[v]; | |
1016 | orig_ist->ist[v] = t->x86_tss.ist[v] = | |
1017 | (unsigned long)estacks; | |
1018 | } | |
1019 | } | |
1020 | ||
1021 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1022 | /* | |
1023 | * <= is required because the CPU will access up to | |
1024 | * 8 bits beyond the end of the IO permission bitmap. | |
1025 | */ | |
1026 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1027 | t->io_bitmap[i] = ~0UL; | |
1028 | ||
1029 | atomic_inc(&init_mm.mm_count); | |
1030 | me->active_mm = &init_mm; | |
1031 | if (me->mm) | |
1032 | BUG(); | |
1033 | enter_lazy_tlb(&init_mm, me); | |
1034 | ||
1035 | load_sp0(t, ¤t->thread); | |
1036 | set_tss_desc(cpu, t); | |
1037 | load_TR_desc(); | |
1038 | load_LDT(&init_mm.context); | |
1039 | ||
1040 | #ifdef CONFIG_KGDB | |
1041 | /* | |
1042 | * If the kgdb is connected no debug regs should be altered. This | |
1043 | * is only applicable when KGDB and a KGDB I/O module are built | |
1044 | * into the kernel and you are using early debugging with | |
1045 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1046 | */ | |
1047 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1048 | arch_kgdb_ops.correct_hw_break(); | |
1049 | else { | |
1050 | #endif | |
1051 | /* | |
1052 | * Clear all 6 debug registers: | |
1053 | */ | |
1054 | ||
1055 | set_debugreg(0UL, 0); | |
1056 | set_debugreg(0UL, 1); | |
1057 | set_debugreg(0UL, 2); | |
1058 | set_debugreg(0UL, 3); | |
1059 | set_debugreg(0UL, 6); | |
1060 | set_debugreg(0UL, 7); | |
1061 | #ifdef CONFIG_KGDB | |
1062 | /* If the kgdb is connected no debug regs should be altered. */ | |
1063 | } | |
1064 | #endif | |
1065 | ||
1066 | fpu_init(); | |
1067 | ||
1068 | raw_local_save_flags(kernel_eflags); | |
1069 | ||
1070 | if (is_uv_system()) | |
1071 | uv_cpu_init(); | |
1072 | } | |
1073 | ||
1074 | #else | |
1075 | ||
d2cbcc49 | 1076 | void __cpuinit cpu_init(void) |
9ee79a3d | 1077 | { |
d2cbcc49 RR |
1078 | int cpu = smp_processor_id(); |
1079 | struct task_struct *curr = current; | |
34048c9e | 1080 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1081 | struct thread_struct *thread = &curr->thread; |
62111195 JF |
1082 | |
1083 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
1084 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
1085 | for (;;) local_irq_enable(); | |
1086 | } | |
1087 | ||
1088 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1089 | ||
1090 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1091 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1092 | |
4d37e7e3 | 1093 | load_idt(&idt_descr); |
c5413fbe | 1094 | switch_to_new_gdt(); |
1da177e4 | 1095 | |
1da177e4 LT |
1096 | /* |
1097 | * Set up and load the per-CPU TSS and LDT | |
1098 | */ | |
1099 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1100 | curr->active_mm = &init_mm; |
1101 | if (curr->mm) | |
1102 | BUG(); | |
1103 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1104 | |
faca6227 | 1105 | load_sp0(t, thread); |
34048c9e | 1106 | set_tss_desc(cpu, t); |
1da177e4 LT |
1107 | load_TR_desc(); |
1108 | load_LDT(&init_mm.context); | |
1109 | ||
22c4e308 | 1110 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1111 | /* Set up doublefault TSS pointer in the GDT */ |
1112 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1113 | #endif |
1da177e4 | 1114 | |
464d1a78 JF |
1115 | /* Clear %gs. */ |
1116 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
1117 | |
1118 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
1119 | set_debugreg(0, 0); |
1120 | set_debugreg(0, 1); | |
1121 | set_debugreg(0, 2); | |
1122 | set_debugreg(0, 3); | |
1123 | set_debugreg(0, 6); | |
1124 | set_debugreg(0, 7); | |
1da177e4 LT |
1125 | |
1126 | /* | |
1127 | * Force FPU initialization: | |
1128 | */ | |
b359e8a4 SS |
1129 | if (cpu_has_xsave) |
1130 | current_thread_info()->status = TS_XSAVE; | |
1131 | else | |
1132 | current_thread_info()->status = 0; | |
1da177e4 LT |
1133 | clear_used_math(); |
1134 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1135 | |
1136 | /* | |
1137 | * Boot processor to setup the FP and extended state context info. | |
1138 | */ | |
b3572e36 | 1139 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1140 | init_thread_xstate(); |
1141 | ||
1142 | xsave_init(); | |
1da177e4 | 1143 | } |
e1367daf | 1144 | |
1ba76586 YL |
1145 | |
1146 | #endif |