Commit | Line | Data |
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f580366f | 1 | #include <linux/init.h> |
0f0124fa YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
4 | #include <linux/string.h> | |
5 | #include <linux/bootmem.h> | |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
f580366f YL |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
f580366f | 12 | #include <linux/percpu.h> |
f580366f YL |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
cbcd79c2 | 16 | #include <asm/linkage.h> |
f580366f YL |
17 | #include <asm/mmu_context.h> |
18 | #include <asm/mtrr.h> | |
19 | #include <asm/mce.h> | |
20 | #include <asm/pat.h> | |
7e00df58 | 21 | #include <asm/asm.h> |
f580366f YL |
22 | #include <asm/numa.h> |
23 | #ifdef CONFIG_X86_LOCAL_APIC | |
24 | #include <asm/mpspec.h> | |
25 | #include <asm/apic.h> | |
26 | #include <mach_apic.h> | |
27 | #endif | |
0f0124fa YL |
28 | #include <asm/pda.h> |
29 | #include <asm/pgtable.h> | |
30 | #include <asm/processor.h> | |
31 | #include <asm/desc.h> | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/proto.h> | |
34 | #include <asm/sections.h> | |
35 | #include <asm/setup.h> | |
36 | #include <asm/genapic.h> | |
f580366f YL |
37 | |
38 | #include "cpu.h" | |
39 | ||
0a488a53 YL |
40 | static struct cpu_dev *this_cpu __cpuinitdata; |
41 | ||
f580366f YL |
42 | /* We need valid kernel segments for data and code in long mode too |
43 | * IRET will check the segment types kkeil 2000/10/28 | |
44 | * Also sysret mandates a special GDT layout | |
45 | */ | |
46 | /* The TLS descriptors are currently at a different place compared to i386. | |
47 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
48 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { | |
49 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, | |
50 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
51 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
52 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
53 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
54 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
55 | } }; | |
56 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); | |
57 | ||
58 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; | |
59 | ||
60 | /* Current gdt points %fs at the "master" per-cpu area: after this, | |
61 | * it's on the real one. */ | |
62 | void switch_to_new_gdt(void) | |
63 | { | |
64 | struct desc_ptr gdt_descr; | |
65 | ||
66 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
67 | gdt_descr.size = GDT_SIZE - 1; | |
68 | load_gdt(&gdt_descr); | |
69 | } | |
70 | ||
10a434fc | 71 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
f580366f YL |
72 | |
73 | static void __cpuinit default_init(struct cpuinfo_x86 *c) | |
74 | { | |
75 | display_cacheinfo(c); | |
76 | } | |
77 | ||
78 | static struct cpu_dev __cpuinitdata default_cpu = { | |
79 | .c_init = default_init, | |
80 | .c_vendor = "Unknown", | |
10a434fc | 81 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
f580366f | 82 | }; |
f580366f YL |
83 | |
84 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) | |
85 | { | |
86 | unsigned int *v; | |
01b2e16a | 87 | char *p, *q; |
f580366f YL |
88 | |
89 | if (c->extended_cpuid_level < 0x80000004) | |
90 | return 0; | |
91 | ||
92 | v = (unsigned int *) c->x86_model_id; | |
93 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
94 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
95 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
96 | c->x86_model_id[48] = 0; | |
01b2e16a YL |
97 | |
98 | /* Intel chips right-justify this string for some dumb reason; | |
99 | undo that brain damage */ | |
100 | p = q = &c->x86_model_id[0]; | |
101 | while (*p == ' ') | |
102 | p++; | |
103 | if (p != q) { | |
104 | while (*p) | |
105 | *q++ = *p++; | |
106 | while (q <= &c->x86_model_id[48]) | |
107 | *q++ = '\0'; /* Zero-pad the rest */ | |
108 | } | |
109 | ||
f580366f YL |
110 | return 1; |
111 | } | |
112 | ||
113 | ||
114 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) | |
115 | { | |
0a488a53 | 116 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
f580366f YL |
117 | |
118 | n = c->extended_cpuid_level; | |
119 | ||
120 | if (n >= 0x80000005) { | |
121 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); | |
9d31d35b YL |
122 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
123 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
f580366f YL |
124 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
125 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
126 | c->x86_tlbsize = 0; | |
127 | } | |
128 | ||
0a488a53 YL |
129 | if (n < 0x80000006) /* Some chips just has a large L1. */ |
130 | return; | |
f580366f | 131 | |
0a488a53 YL |
132 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
133 | l2size = ecx >> 16; | |
134 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
135 | ||
136 | c->x86_cache_size = l2size; | |
137 | ||
138 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
139 | l2size, ecx & 0xFF); | |
f580366f YL |
140 | } |
141 | ||
142 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) | |
143 | { | |
144 | #ifdef CONFIG_SMP | |
145 | u32 eax, ebx, ecx, edx; | |
146 | int index_msb, core_bits; | |
147 | ||
f580366f YL |
148 | if (!cpu_has(c, X86_FEATURE_HT)) |
149 | return; | |
150 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) | |
151 | goto out; | |
152 | ||
0a488a53 YL |
153 | cpuid(1, &eax, &ebx, &ecx, &edx); |
154 | ||
f580366f YL |
155 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
156 | ||
157 | if (smp_num_siblings == 1) { | |
158 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
159 | } else if (smp_num_siblings > 1) { | |
160 | ||
161 | if (smp_num_siblings > NR_CPUS) { | |
9d31d35b YL |
162 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", |
163 | smp_num_siblings); | |
f580366f YL |
164 | smp_num_siblings = 1; |
165 | return; | |
166 | } | |
167 | ||
168 | index_msb = get_count_order(smp_num_siblings); | |
169 | c->phys_proc_id = phys_pkg_id(index_msb); | |
170 | ||
171 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
172 | ||
173 | index_msb = get_count_order(smp_num_siblings); | |
174 | ||
175 | core_bits = get_count_order(c->x86_max_cores); | |
176 | ||
177 | c->cpu_core_id = phys_pkg_id(index_msb) & | |
178 | ((1 << core_bits) - 1); | |
179 | } | |
0a488a53 | 180 | |
f580366f YL |
181 | out: |
182 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
183 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
184 | c->phys_proc_id); | |
185 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
186 | c->cpu_core_id); | |
187 | } | |
f580366f YL |
188 | #endif |
189 | } | |
190 | ||
191 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) | |
192 | { | |
193 | char *v = c->x86_vendor_id; | |
194 | int i; | |
195 | static int printed; | |
196 | ||
197 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
198 | if (!cpu_devs[i]) |
199 | break; | |
200 | ||
201 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
202 | (cpu_devs[i]->c_ident[1] && | |
203 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
204 | this_cpu = cpu_devs[i]; | |
205 | c->x86_vendor = this_cpu->c_x86_vendor; | |
206 | return; | |
f580366f YL |
207 | } |
208 | } | |
10a434fc | 209 | |
f580366f YL |
210 | if (!printed) { |
211 | printed++; | |
212 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
213 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
214 | } | |
10a434fc | 215 | |
f580366f | 216 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
3da99c97 | 217 | this_cpu = &default_cpu; |
f580366f YL |
218 | } |
219 | ||
3da99c97 | 220 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
f580366f | 221 | { |
f580366f YL |
222 | /* Get vendor name */ |
223 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, | |
224 | (unsigned int *)&c->x86_vendor_id[0], | |
225 | (unsigned int *)&c->x86_vendor_id[8], | |
226 | (unsigned int *)&c->x86_vendor_id[4]); | |
227 | ||
9d31d35b | 228 | c->x86 = 4; |
f580366f YL |
229 | /* Intel-defined flags: level 0x00000001 */ |
230 | if (c->cpuid_level >= 0x00000001) { | |
3da99c97 YL |
231 | u32 junk, tfms, cap0, misc; |
232 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
f580366f YL |
233 | c->x86 = (tfms >> 8) & 0xf; |
234 | c->x86_model = (tfms >> 4) & 0xf; | |
235 | c->x86_mask = tfms & 0xf; | |
236 | if (c->x86 == 0xf) | |
237 | c->x86 += (tfms >> 20) & 0xff; | |
238 | if (c->x86 >= 0x6) | |
9d31d35b YL |
239 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
240 | if (cap0 & (1<<19)) { | |
f580366f | 241 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b YL |
242 | c->x86_cache_alignment = c->x86_clflush_size; |
243 | } | |
f580366f | 244 | } |
3da99c97 YL |
245 | } |
246 | ||
247 | ||
248 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
249 | { | |
250 | u32 tfms, xlvl; | |
251 | u32 ebx; | |
252 | ||
3da99c97 YL |
253 | /* Intel-defined flags: level 0x00000001 */ |
254 | if (c->cpuid_level >= 0x00000001) { | |
255 | u32 capability, excap; | |
256 | ||
257 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
258 | c->x86_capability[0] = capability; | |
259 | c->x86_capability[4] = excap; | |
260 | } | |
f580366f | 261 | |
f580366f YL |
262 | /* AMD-defined flags: level 0x80000001 */ |
263 | xlvl = cpuid_eax(0x80000000); | |
264 | c->extended_cpuid_level = xlvl; | |
265 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
266 | if (xlvl >= 0x80000001) { | |
267 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
268 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
269 | } | |
f580366f YL |
270 | } |
271 | ||
272 | /* Transmeta-defined flags: level 0x80860001 */ | |
273 | xlvl = cpuid_eax(0x80860000); | |
274 | if ((xlvl & 0xffff0000) == 0x80860000) { | |
275 | /* Don't set x86_cpuid_level here for now to not confuse. */ | |
276 | if (xlvl >= 0x80860001) | |
277 | c->x86_capability[2] = cpuid_edx(0x80860001); | |
278 | } | |
279 | ||
f580366f YL |
280 | if (c->extended_cpuid_level >= 0x80000007) |
281 | c->x86_power = cpuid_edx(0x80000007); | |
282 | ||
87a1c441 YL |
283 | if (c->extended_cpuid_level >= 0x80000008) { |
284 | u32 eax = cpuid_eax(0x80000008); | |
285 | ||
286 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
287 | c->x86_phys_bits = eax & 0xff; | |
288 | } | |
3da99c97 | 289 | } |
87a1c441 | 290 | |
3da99c97 YL |
291 | /* Do some early cpuid on the boot CPU to get some parameter that are |
292 | needed before check_bugs. Everything advanced is in identify_cpu | |
293 | below. */ | |
294 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) | |
295 | { | |
296 | ||
297 | c->x86_clflush_size = 64; | |
298 | c->x86_cache_alignment = c->x86_clflush_size; | |
299 | ||
300 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
301 | ||
302 | c->extended_cpuid_level = 0; | |
303 | ||
304 | cpu_detect(c); | |
305 | ||
306 | get_cpu_vendor(c); | |
307 | ||
308 | get_cpu_cap(c); | |
7e00df58 | 309 | |
10a434fc YL |
310 | if (this_cpu->c_early_init) |
311 | this_cpu->c_early_init(c); | |
f580366f YL |
312 | |
313 | validate_pat_support(c); | |
f580366f YL |
314 | } |
315 | ||
3da99c97 YL |
316 | void __init early_cpu_init(void) |
317 | { | |
10a434fc YL |
318 | struct cpu_dev **cdev; |
319 | int count = 0; | |
320 | ||
321 | printk("KERNEL supported cpus:\n"); | |
322 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
323 | struct cpu_dev *cpudev = *cdev; | |
324 | unsigned int j; | |
3da99c97 | 325 | |
10a434fc YL |
326 | if (count >= X86_VENDOR_NUM) |
327 | break; | |
328 | cpu_devs[count] = cpudev; | |
329 | count++; | |
330 | ||
331 | for (j = 0; j < 2; j++) { | |
332 | if (!cpudev->c_ident[j]) | |
333 | continue; | |
334 | printk(" %s %s\n", cpudev->c_vendor, | |
335 | cpudev->c_ident[j]); | |
336 | } | |
337 | } | |
3da99c97 | 338 | |
3da99c97 YL |
339 | early_identify_cpu(&boot_cpu_data); |
340 | } | |
341 | ||
9d31d35b YL |
342 | /* |
343 | * The NOPL instruction is supposed to exist on all CPUs with | |
344 | * family >= 6, unfortunately, that's not true in practice because | |
345 | * of early VIA chips and (more importantly) broken virtualizers that | |
346 | * are not easy to detect. Hence, probe for it based on first | |
347 | * principles. | |
348 | * | |
349 | * Note: no 64-bit chip is known to lack these, but put the code here | |
350 | * for consistency with 32 bits, and to make it utterly trivial to | |
351 | * diagnose the problem should it ever surface. | |
352 | */ | |
353 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
354 | { | |
355 | const u32 nopl_signature = 0x888c53b1; /* Random number */ | |
356 | u32 has_nopl = nopl_signature; | |
357 | ||
358 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
359 | if (c->x86 >= 6) { | |
360 | asm volatile("\n" | |
361 | "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */ | |
362 | "2:\n" | |
363 | " .section .fixup,\"ax\"\n" | |
364 | "3: xor %0,%0\n" | |
365 | " jmp 2b\n" | |
366 | " .previous\n" | |
367 | _ASM_EXTABLE(1b,3b) | |
368 | : "+a" (has_nopl)); | |
369 | ||
370 | if (has_nopl == nopl_signature) | |
371 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
372 | } | |
373 | } | |
374 | ||
3da99c97 YL |
375 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
376 | { | |
377 | c->extended_cpuid_level = 0; | |
378 | ||
379 | cpu_detect(c); | |
380 | ||
381 | get_cpu_vendor(c); | |
382 | ||
383 | get_cpu_cap(c); | |
384 | ||
385 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff; | |
386 | #ifdef CONFIG_SMP | |
387 | c->phys_proc_id = c->initial_apicid; | |
388 | #endif | |
389 | ||
390 | if (c->extended_cpuid_level >= 0x80000004) | |
391 | get_model_name(c); /* Default name */ | |
392 | ||
393 | init_scattered_cpuid_features(c); | |
394 | detect_nopl(c); | |
395 | } | |
396 | ||
f580366f YL |
397 | /* |
398 | * This does the hard work of actually picking apart the CPU stuff... | |
399 | */ | |
9a250347 | 400 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
f580366f YL |
401 | { |
402 | int i; | |
403 | ||
3da99c97 YL |
404 | c->loops_per_jiffy = loops_per_jiffy; |
405 | c->x86_cache_size = -1; | |
406 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
407 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
408 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
409 | c->x86_model_id[0] = '\0'; /* Unset */ | |
3da99c97 YL |
410 | c->x86_max_cores = 1; |
411 | c->x86_coreid_bits = 0; | |
0a488a53 YL |
412 | c->x86_clflush_size = 64; |
413 | c->x86_cache_alignment = c->x86_clflush_size; | |
3da99c97 | 414 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
f580366f | 415 | |
3da99c97 | 416 | generic_identify(c); |
f580366f YL |
417 | |
418 | c->apicid = phys_pkg_id(0); | |
419 | ||
420 | /* | |
421 | * Vendor-specific initialization. In this section we | |
422 | * canonicalize the feature flags, meaning if there are | |
423 | * features a certain CPU supports which CPUID doesn't | |
424 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
425 | * we handle them here. | |
426 | * | |
427 | * At the end of this section, c->x86_capability better | |
428 | * indicate the features this CPU genuinely supports! | |
429 | */ | |
430 | if (this_cpu->c_init) | |
431 | this_cpu->c_init(c); | |
432 | ||
433 | detect_ht(c); | |
434 | ||
435 | /* | |
436 | * On SMP, boot_cpu_data holds the common feature set between | |
437 | * all CPUs; so make sure that we indicate which features are | |
438 | * common between the CPUs. The first time this routine gets | |
439 | * executed, c == &boot_cpu_data. | |
440 | */ | |
441 | if (c != &boot_cpu_data) { | |
442 | /* AND the already accumulated flags with these */ | |
443 | for (i = 0; i < NCAPINTS; i++) | |
444 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
445 | } | |
446 | ||
447 | /* Clear all flags overriden by options */ | |
448 | for (i = 0; i < NCAPINTS; i++) | |
449 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; | |
450 | ||
451 | #ifdef CONFIG_X86_MCE | |
452 | mcheck_init(c); | |
453 | #endif | |
454 | select_idle_routine(c); | |
455 | ||
456 | #ifdef CONFIG_NUMA | |
457 | numa_add_cpu(smp_processor_id()); | |
458 | #endif | |
459 | ||
460 | } | |
461 | ||
9d31d35b | 462 | void __init identify_boot_cpu(void) |
f580366f YL |
463 | { |
464 | identify_cpu(&boot_cpu_data); | |
465 | } | |
466 | ||
467 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) | |
468 | { | |
469 | BUG_ON(c == &boot_cpu_data); | |
470 | identify_cpu(c); | |
471 | mtrr_ap_init(); | |
472 | } | |
473 | ||
b05f78f5 YL |
474 | struct msr_range { |
475 | unsigned min; | |
476 | unsigned max; | |
477 | }; | |
478 | ||
479 | static struct msr_range msr_range_array[] __cpuinitdata = { | |
480 | { 0x00000000, 0x00000418}, | |
481 | { 0xc0000000, 0xc000040b}, | |
482 | { 0xc0010000, 0xc0010142}, | |
483 | { 0xc0011000, 0xc001103b}, | |
484 | }; | |
485 | ||
486 | static void __cpuinit print_cpu_msr(void) | |
487 | { | |
488 | unsigned index; | |
489 | u64 val; | |
490 | int i; | |
491 | unsigned index_min, index_max; | |
492 | ||
493 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
494 | index_min = msr_range_array[i].min; | |
495 | index_max = msr_range_array[i].max; | |
496 | for (index = index_min; index < index_max; index++) { | |
497 | if (rdmsrl_amd_safe(index, &val)) | |
498 | continue; | |
499 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
500 | } | |
501 | } | |
502 | } | |
503 | ||
504 | static int show_msr __cpuinitdata; | |
505 | static __init int setup_show_msr(char *arg) | |
506 | { | |
507 | int num; | |
508 | ||
509 | get_option(&arg, &num); | |
510 | ||
511 | if (num > 0) | |
512 | show_msr = num; | |
513 | return 1; | |
514 | } | |
515 | __setup("show_msr=", setup_show_msr); | |
516 | ||
9d31d35b YL |
517 | static __init int setup_noclflush(char *arg) |
518 | { | |
519 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
520 | return 1; | |
521 | } | |
522 | __setup("noclflush", setup_noclflush); | |
523 | ||
f580366f YL |
524 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
525 | { | |
526 | if (c->x86_model_id[0]) | |
527 | printk(KERN_CONT "%s", c->x86_model_id); | |
528 | ||
529 | if (c->x86_mask || c->cpuid_level >= 0) | |
530 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); | |
531 | else | |
532 | printk(KERN_CONT "\n"); | |
b05f78f5 YL |
533 | |
534 | #ifdef CONFIG_SMP | |
535 | if (c->cpu_index < show_msr) | |
536 | print_cpu_msr(); | |
537 | #else | |
538 | if (show_msr) | |
539 | print_cpu_msr(); | |
540 | #endif | |
f580366f YL |
541 | } |
542 | ||
543 | static __init int setup_disablecpuid(char *arg) | |
544 | { | |
545 | int bit; | |
546 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
547 | setup_clear_cpu_cap(bit); | |
548 | else | |
549 | return 0; | |
550 | return 1; | |
551 | } | |
552 | __setup("clearcpuid=", setup_disablecpuid); | |
0f0124fa | 553 | |
0f0124fa YL |
554 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
555 | ||
556 | struct x8664_pda **_cpu_pda __read_mostly; | |
557 | EXPORT_SYMBOL(_cpu_pda); | |
558 | ||
559 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; | |
560 | ||
561 | char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; | |
562 | ||
563 | unsigned long __supported_pte_mask __read_mostly = ~0UL; | |
564 | EXPORT_SYMBOL_GPL(__supported_pte_mask); | |
565 | ||
566 | static int do_not_nx __cpuinitdata; | |
567 | ||
568 | /* noexec=on|off | |
569 | Control non executable mappings for 64bit processes. | |
570 | ||
571 | on Enable(default) | |
572 | off Disable | |
573 | */ | |
574 | static int __init nonx_setup(char *str) | |
575 | { | |
576 | if (!str) | |
577 | return -EINVAL; | |
578 | if (!strncmp(str, "on", 2)) { | |
579 | __supported_pte_mask |= _PAGE_NX; | |
580 | do_not_nx = 0; | |
581 | } else if (!strncmp(str, "off", 3)) { | |
582 | do_not_nx = 1; | |
583 | __supported_pte_mask &= ~_PAGE_NX; | |
584 | } | |
585 | return 0; | |
586 | } | |
587 | early_param("noexec", nonx_setup); | |
588 | ||
589 | int force_personality32; | |
590 | ||
591 | /* noexec32=on|off | |
592 | Control non executable heap for 32bit processes. | |
593 | To control the stack too use noexec=off | |
594 | ||
595 | on PROT_READ does not imply PROT_EXEC for 32bit processes (default) | |
596 | off PROT_READ implies PROT_EXEC | |
597 | */ | |
598 | static int __init nonx32_setup(char *str) | |
599 | { | |
600 | if (!strcmp(str, "on")) | |
601 | force_personality32 &= ~READ_IMPLIES_EXEC; | |
602 | else if (!strcmp(str, "off")) | |
603 | force_personality32 |= READ_IMPLIES_EXEC; | |
604 | return 1; | |
605 | } | |
606 | __setup("noexec32=", nonx32_setup); | |
607 | ||
608 | void pda_init(int cpu) | |
609 | { | |
610 | struct x8664_pda *pda = cpu_pda(cpu); | |
611 | ||
612 | /* Setup up data that may be needed in __get_free_pages early */ | |
ada85708 JF |
613 | loadsegment(fs, 0); |
614 | loadsegment(gs, 0); | |
0f0124fa YL |
615 | /* Memory clobbers used to order PDA accessed */ |
616 | mb(); | |
617 | wrmsrl(MSR_GS_BASE, pda); | |
618 | mb(); | |
619 | ||
620 | pda->cpunumber = cpu; | |
621 | pda->irqcount = -1; | |
622 | pda->kernelstack = (unsigned long)stack_thread_info() - | |
623 | PDA_STACKOFFSET + THREAD_SIZE; | |
624 | pda->active_mm = &init_mm; | |
625 | pda->mmu_state = 0; | |
626 | ||
627 | if (cpu == 0) { | |
628 | /* others are initialized in smpboot.c */ | |
629 | pda->pcurrent = &init_task; | |
630 | pda->irqstackptr = boot_cpu_stack; | |
631 | } else { | |
632 | pda->irqstackptr = (char *) | |
633 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
634 | if (!pda->irqstackptr) | |
635 | panic("cannot allocate irqstack for cpu %d", cpu); | |
636 | ||
637 | if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) | |
638 | pda->nodenumber = cpu_to_node(cpu); | |
639 | } | |
640 | ||
641 | pda->irqstackptr += IRQSTACKSIZE-64; | |
642 | } | |
643 | ||
644 | char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + | |
cbcd79c2 | 645 | DEBUG_STKSZ] __page_aligned_bss; |
0f0124fa YL |
646 | |
647 | extern asmlinkage void ignore_sysret(void); | |
648 | ||
649 | /* May not be marked __init: used by software suspend */ | |
650 | void syscall_init(void) | |
651 | { | |
652 | /* | |
653 | * LSTAR and STAR live in a bit strange symbiosis. | |
654 | * They both write to the same internal register. STAR allows to | |
655 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
656 | */ | |
657 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
658 | wrmsrl(MSR_LSTAR, system_call); | |
659 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
660 | ||
661 | #ifdef CONFIG_IA32_EMULATION | |
662 | syscall32_cpu_init(); | |
663 | #endif | |
664 | ||
665 | /* Flags to clear on syscall */ | |
666 | wrmsrl(MSR_SYSCALL_MASK, | |
667 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
668 | } | |
669 | ||
670 | void __cpuinit check_efer(void) | |
671 | { | |
672 | unsigned long efer; | |
673 | ||
674 | rdmsrl(MSR_EFER, efer); | |
675 | if (!(efer & EFER_NX) || do_not_nx) | |
676 | __supported_pte_mask &= ~_PAGE_NX; | |
677 | } | |
678 | ||
679 | unsigned long kernel_eflags; | |
680 | ||
681 | /* | |
682 | * Copies of the original ist values from the tss are only accessed during | |
683 | * debugging, no special alignment required. | |
684 | */ | |
685 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
686 | ||
687 | /* | |
688 | * cpu_init() initializes state that is per-CPU. Some data is already | |
689 | * initialized (naturally) in the bootstrap process, such as the GDT | |
690 | * and IDT. We reload them nevertheless, this function acts as a | |
691 | * 'CPU state barrier', nothing should get across. | |
692 | * A lot of state is already set up in PDA init. | |
693 | */ | |
694 | void __cpuinit cpu_init(void) | |
695 | { | |
696 | int cpu = stack_smp_processor_id(); | |
697 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
698 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
699 | unsigned long v; | |
700 | char *estacks = NULL; | |
701 | struct task_struct *me; | |
702 | int i; | |
703 | ||
704 | /* CPU 0 is initialised in head64.c */ | |
705 | if (cpu != 0) | |
706 | pda_init(cpu); | |
707 | else | |
708 | estacks = boot_exception_stacks; | |
709 | ||
710 | me = current; | |
711 | ||
712 | if (cpu_test_and_set(cpu, cpu_initialized)) | |
713 | panic("CPU#%d already initialized!\n", cpu); | |
714 | ||
715 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
716 | ||
717 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
718 | ||
719 | /* | |
720 | * Initialize the per-CPU GDT with the boot GDT, | |
721 | * and set up the GDT descriptor: | |
722 | */ | |
723 | ||
724 | switch_to_new_gdt(); | |
725 | load_idt((const struct desc_ptr *)&idt_descr); | |
726 | ||
727 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
728 | syscall_init(); | |
729 | ||
730 | wrmsrl(MSR_FS_BASE, 0); | |
731 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
732 | barrier(); | |
733 | ||
734 | check_efer(); | |
735 | ||
736 | /* | |
737 | * set up and load the per-CPU TSS | |
738 | */ | |
739 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
740 | static const unsigned int order[N_EXCEPTION_STACKS] = { | |
741 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, | |
742 | [DEBUG_STACK - 1] = DEBUG_STACK_ORDER | |
743 | }; | |
744 | if (cpu) { | |
745 | estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); | |
746 | if (!estacks) | |
747 | panic("Cannot allocate exception stack %ld %d\n", | |
748 | v, cpu); | |
749 | } | |
750 | estacks += PAGE_SIZE << order[v]; | |
751 | orig_ist->ist[v] = t->x86_tss.ist[v] = (unsigned long)estacks; | |
752 | } | |
753 | ||
754 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
755 | /* | |
756 | * <= is required because the CPU will access up to | |
757 | * 8 bits beyond the end of the IO permission bitmap. | |
758 | */ | |
759 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
760 | t->io_bitmap[i] = ~0UL; | |
761 | ||
762 | atomic_inc(&init_mm.mm_count); | |
763 | me->active_mm = &init_mm; | |
764 | if (me->mm) | |
765 | BUG(); | |
766 | enter_lazy_tlb(&init_mm, me); | |
767 | ||
768 | load_sp0(t, ¤t->thread); | |
769 | set_tss_desc(cpu, t); | |
770 | load_TR_desc(); | |
771 | load_LDT(&init_mm.context); | |
772 | ||
773 | #ifdef CONFIG_KGDB | |
774 | /* | |
775 | * If the kgdb is connected no debug regs should be altered. This | |
776 | * is only applicable when KGDB and a KGDB I/O module are built | |
777 | * into the kernel and you are using early debugging with | |
778 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
779 | */ | |
780 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
781 | arch_kgdb_ops.correct_hw_break(); | |
782 | else { | |
783 | #endif | |
784 | /* | |
785 | * Clear all 6 debug registers: | |
786 | */ | |
787 | ||
788 | set_debugreg(0UL, 0); | |
789 | set_debugreg(0UL, 1); | |
790 | set_debugreg(0UL, 2); | |
791 | set_debugreg(0UL, 3); | |
792 | set_debugreg(0UL, 6); | |
793 | set_debugreg(0UL, 7); | |
794 | #ifdef CONFIG_KGDB | |
795 | /* If the kgdb is connected no debug regs should be altered. */ | |
796 | } | |
797 | #endif | |
798 | ||
799 | fpu_init(); | |
800 | ||
801 | raw_local_save_flags(kernel_eflags); | |
802 | ||
803 | if (is_uv_system()) | |
804 | uv_cpu_init(); | |
805 | } |