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x86: cpu/common.c, merge default_init()
[deliverable/linux.git] / arch / x86 / kernel / cpu / common_64.c
CommitLineData
f580366f 1#include <linux/init.h>
0f0124fa
YL		 2#include <linux/kernel.h>
3#include <linux/sched.h>
4#include <linux/string.h>
5#include <linux/bootmem.h>
6#include <linux/bitops.h>
7#include <linux/module.h>
8#include <linux/kgdb.h>
9#include <linux/topology.h>
f580366f
YL		 10#include <linux/delay.h>
11#include <linux/smp.h>
f580366f 12#include <linux/percpu.h>
f580366f
YL		 13#include <asm/i387.h>
14#include <asm/msr.h>
15#include <asm/io.h>
cbcd79c2 16#include <asm/linkage.h>
f580366f
YL		 17#include <asm/mmu_context.h>
18#include <asm/mtrr.h>
19#include <asm/mce.h>
20#include <asm/pat.h>
7e00df58 21#include <asm/asm.h>
f580366f
YL		 22#include <asm/numa.h>
23#ifdef CONFIG_X86_LOCAL_APIC
24#include <asm/mpspec.h>
25#include <asm/apic.h>
26#include <mach_apic.h>
f0fc4aff 27#include <asm/genapic.h>
f580366f 28#endif
0f0124fa
YL		 29#include <asm/pda.h>
30#include <asm/pgtable.h>
31#include <asm/processor.h>
32#include <asm/desc.h>
33#include <asm/atomic.h>
34#include <asm/proto.h>
35#include <asm/sections.h>
36#include <asm/setup.h>
f580366f
YL		 37
38#include "cpu.h"
39
0a488a53
YL		 40static struct cpu_dev *this_cpu __cpuinitdata;
41
950ad7ff 42#ifdef CONFIG_X86_64
f580366f
YL		 43/* We need valid kernel segments for data and code in long mode too
44 * IRET will check the segment types kkeil 2000/10/28
45 * Also sysret mandates a special GDT layout
46 */
47/* The TLS descriptors are currently at a different place compared to i386.
48 Hopefully nobody expects them at a fixed place (Wine?) */
49DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
50 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
51 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
52 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
53 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
54 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
55 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
56} };
950ad7ff
YL		 57#else
58DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
59 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
60 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
61 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
62 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
63 /*
64 * Segments used for calling PnP BIOS have byte granularity.
65 * They code segments and data segments have fixed 64k limits,
66 * the transfer segment sizes are set at run time.
67 */
68 /* 32-bit code */
69 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
70 /* 16-bit code */
71 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
72 /* 16-bit data */
73 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
74 /* 16-bit data */
75 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
76 /* 16-bit data */
77 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
78 /*
79 * The APM segments have byte granularity and their bases
80 * are set at run time. All have 64k limits.
81 */
82 /* 32-bit code */
83 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
84 /* 16-bit code */
85 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
86 /* data */
87 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
88
89 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
90 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
91} };
92#endif
f580366f
YL		 93EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
94
ba51dced
YL		 95#ifdef CONFIG_X86_32
96static int cachesize_override __cpuinitdata = -1;
97static int disable_x86_serial_nr __cpuinitdata = 1;
98
99static int __init cachesize_setup(char *str)
100{
101 get_option(&str, &cachesize_override);
102 return 1;
103}
104__setup("cachesize=", cachesize_setup);
105
106/*
107 * Naming convention should be: <Name> [(<Codename>)]
108 * This table only is used unless init_<vendor>() below doesn't set it;
109 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
110 *
111 */
112
113/* Look up CPU names by table lookup. */
114static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
115{
116 struct cpu_model_info *info;
117
118 if (c->x86_model >= 16)
119 return NULL; /* Range check */
120
121 if (!this_cpu)
122 return NULL;
123
124 info = this_cpu->c_models;
125
126 while (info && info->family) {
127 if (info->family == c->x86)
128 return info->model_names[c->x86_model];
129 info++;
130 }
131 return NULL; /* Not found */
132}
133
134static int __init x86_fxsr_setup(char *s)
135{
136 setup_clear_cpu_cap(X86_FEATURE_FXSR);
137 setup_clear_cpu_cap(X86_FEATURE_XMM);
138 return 1;
139}
140__setup("nofxsr", x86_fxsr_setup);
141
142static int __init x86_sep_setup(char *s)
143{
144 setup_clear_cpu_cap(X86_FEATURE_SEP);
145 return 1;
146}
147__setup("nosep", x86_sep_setup);
148
149/* Standard macro to see if a specific flag is changeable */
150static inline int flag_is_changeable_p(u32 flag)
151{
152 u32 f1, f2;
153
154 asm("pushfl\n\t"
155 "pushfl\n\t"
156 "popl %0\n\t"
157 "movl %0,%1\n\t"
158 "xorl %2,%0\n\t"
159 "pushl %0\n\t"
160 "popfl\n\t"
161 "pushfl\n\t"
162 "popl %0\n\t"
163 "popfl\n\t"
164 : "=&r" (f1), "=&r" (f2)
165 : "ir" (flag));
166
167 return ((f1^f2) & flag) != 0;
168}
169
170/* Probe for the CPUID instruction */
171static int __cpuinit have_cpuid_p(void)
172{
173 return flag_is_changeable_p(X86_EFLAGS_ID);
174}
175
176static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
177{
178 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
179 /* Disable processor serial number */
180 unsigned long lo, hi;
181 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
182 lo |= 0x200000;
183 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
184 printk(KERN_NOTICE "CPU serial number disabled.\n");
185 clear_cpu_cap(c, X86_FEATURE_PN);
186
187 /* Disabling the serial number may affect the cpuid level */
188 c->cpuid_level = cpuid_eax(0);
189 }
190}
191
192static int __init x86_serial_nr_setup(char *s)
193{
194 disable_x86_serial_nr = 0;
195 return 1;
196}
197__setup("serialnumber", x86_serial_nr_setup);
198#else
199/* Probe for the CPUID instruction */
200static inline int have_cpuid_p(void)
201{
202 return 1;
203}
204#endif
205
f580366f
YL		 206__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
207
208/* Current gdt points %fs at the "master" per-cpu area: after this,
209 * it's on the real one. */
210void switch_to_new_gdt(void)
211{
212 struct desc_ptr gdt_descr;
213
214 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
215 gdt_descr.size = GDT_SIZE - 1;
216 load_gdt(&gdt_descr);
fab334c1
YL		 217#ifdef CONFIG_X86_32
218 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
219#endif
f580366f
YL		 220}
221
10a434fc 222static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
f580366f
YL		 223
224static void __cpuinit default_init(struct cpuinfo_x86 *c)
225{
b9e67f00 226#ifdef CONFIG_X86_64
f580366f 227 display_cacheinfo(c);
b9e67f00
YL		 228#else
229 /* Not much we can do here... */
230 /* Check if at least it has cpuid */
231 if (c->cpuid_level == -1) {
232 /* No cpuid. It must be an ancient CPU */
233 if (c->x86 == 4)
234 strcpy(c->x86_model_id, "486");
235 else if (c->x86 == 3)
236 strcpy(c->x86_model_id, "386");
237 }
238#endif
f580366f
YL		 239}
240
241static struct cpu_dev __cpuinitdata default_cpu = {
242 .c_init = default_init,
243 .c_vendor = "Unknown",
10a434fc 244 .c_x86_vendor = X86_VENDOR_UNKNOWN,
f580366f 245};
f580366f
YL		 246
247int __cpuinit get_model_name(struct cpuinfo_x86 *c)
248{
249 unsigned int *v;
01b2e16a 250 char *p, *q;
f580366f
YL		 251
252 if (c->extended_cpuid_level < 0x80000004)
253 return 0;
254
255 v = (unsigned int *) c->x86_model_id;
256 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
257 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
258 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
259 c->x86_model_id[48] = 0;
01b2e16a
YL		 260
261 /* Intel chips right-justify this string for some dumb reason;
262 undo that brain damage */
263 p = q = &c->x86_model_id[0];
264 while (*p == ' ')
265 p++;
266 if (p != q) {
267 while (*p)
268 *q++ = *p++;
269 while (q <= &c->x86_model_id[48])
270 *q++ = '\0'; /* Zero-pad the rest */
271 }
272
f580366f
YL		 273 return 1;
274}
275
276
277void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
278{
0a488a53 279 unsigned int n, dummy, ebx, ecx, edx, l2size;
f580366f
YL		 280
281 n = c->extended_cpuid_level;
282
283 if (n >= 0x80000005) {
284 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
9d31d35b
YL		 285 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
286 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
f580366f
YL		 287 c->x86_cache_size = (ecx>>24) + (edx>>24);
288 /* On K8 L1 TLB is inclusive, so don't count it */
289 c->x86_tlbsize = 0;
290 }
291
0a488a53
YL		 292 if (n < 0x80000006) /* Some chips just has a large L1. */
293 return;
f580366f 294
0a488a53
YL		 295 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
296 l2size = ecx >> 16;
297 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
298
299 c->x86_cache_size = l2size;
300
301 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
302 l2size, ecx & 0xFF);
f580366f
YL		 303}
304
305void __cpuinit detect_ht(struct cpuinfo_x86 *c)
306{
97e4db7c 307#ifdef CONFIG_X86_HT
f580366f
YL		 308 u32 eax, ebx, ecx, edx;
309 int index_msb, core_bits;
310
f580366f
YL		 311 if (!cpu_has(c, X86_FEATURE_HT))
312 return;
313 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
314 goto out;
315
90427638
IM		 316 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
317 return;
318
0a488a53
YL		 319 cpuid(1, &eax, &ebx, &ecx, &edx);
320
f580366f
YL		 321 smp_num_siblings = (ebx & 0xff0000) >> 16;
322
323 if (smp_num_siblings == 1) {
324 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
325 } else if (smp_num_siblings > 1) {
326
327 if (smp_num_siblings > NR_CPUS) {
9d31d35b
YL		 328 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
329 smp_num_siblings);
f580366f
YL		 330 smp_num_siblings = 1;
331 return;
332 }
333
334 index_msb = get_count_order(smp_num_siblings);
335 c->phys_proc_id = phys_pkg_id(index_msb);
336
337 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
338
339 index_msb = get_count_order(smp_num_siblings);
340
341 core_bits = get_count_order(c->x86_max_cores);
342
343 c->cpu_core_id = phys_pkg_id(index_msb) &
344 ((1 << core_bits) - 1);
345 }
0a488a53 346
f580366f
YL		 347out:
348 if ((c->x86_max_cores * smp_num_siblings) > 1) {
349 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
350 c->phys_proc_id);
351 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
352 c->cpu_core_id);
353 }
f580366f
YL		 354#endif
355}
356
357static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
358{
359 char *v = c->x86_vendor_id;
360 int i;
361 static int printed;
362
363 for (i = 0; i < X86_VENDOR_NUM; i++) {
10a434fc
YL		 364 if (!cpu_devs[i])
365 break;
366
367 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
368 (cpu_devs[i]->c_ident[1] &&
369 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
370 this_cpu = cpu_devs[i];
371 c->x86_vendor = this_cpu->c_x86_vendor;
372 return;
f580366f
YL		 373 }
374 }
10a434fc 375
f580366f
YL		 376 if (!printed) {
377 printed++;
378 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
379 printk(KERN_ERR "CPU: Your system may be unstable.\n");
380 }
10a434fc 381
f580366f 382 c->x86_vendor = X86_VENDOR_UNKNOWN;
3da99c97 383 this_cpu = &default_cpu;
f580366f
YL		 384}
385
3da99c97 386void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
f580366f 387{
f580366f
YL		 388 /* Get vendor name */
389 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
390 (unsigned int *)&c->x86_vendor_id[0],
391 (unsigned int *)&c->x86_vendor_id[8],
392 (unsigned int *)&c->x86_vendor_id[4]);
393
9d31d35b 394 c->x86 = 4;
f580366f
YL		 395 /* Intel-defined flags: level 0x00000001 */
396 if (c->cpuid_level >= 0x00000001) {
3da99c97
YL		 397 u32 junk, tfms, cap0, misc;
398 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
f580366f
YL		 399 c->x86 = (tfms >> 8) & 0xf;
400 c->x86_model = (tfms >> 4) & 0xf;
401 c->x86_mask = tfms & 0xf;
402 if (c->x86 == 0xf)
403 c->x86 += (tfms >> 20) & 0xff;
404 if (c->x86 >= 0x6)
9d31d35b
YL		 405 c->x86_model += ((tfms >> 16) & 0xf) << 4;
406 if (cap0 & (1<<19)) {
f580366f 407 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
9d31d35b
YL		 408 c->x86_cache_alignment = c->x86_clflush_size;
409 }
f580366f 410 }
3da99c97
YL		 411}
412
413
414static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
415{
416 u32 tfms, xlvl;
417 u32 ebx;
418
3da99c97
YL		 419 /* Intel-defined flags: level 0x00000001 */
420 if (c->cpuid_level >= 0x00000001) {
421 u32 capability, excap;
422
423 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
424 c->x86_capability[0] = capability;
425 c->x86_capability[4] = excap;
426 }
f580366f 427
f580366f
YL		 428 /* AMD-defined flags: level 0x80000001 */
429 xlvl = cpuid_eax(0x80000000);
430 c->extended_cpuid_level = xlvl;
431 if ((xlvl & 0xffff0000) == 0x80000000) {
432 if (xlvl >= 0x80000001) {
433 c->x86_capability[1] = cpuid_edx(0x80000001);
434 c->x86_capability[6] = cpuid_ecx(0x80000001);
435 }
f580366f
YL		 436 }
437
438 /* Transmeta-defined flags: level 0x80860001 */
439 xlvl = cpuid_eax(0x80860000);
440 if ((xlvl & 0xffff0000) == 0x80860000) {
441 /* Don't set x86_cpuid_level here for now to not confuse. */
442 if (xlvl >= 0x80860001)
443 c->x86_capability[2] = cpuid_edx(0x80860001);
444 }
445
f580366f
YL		 446 if (c->extended_cpuid_level >= 0x80000007)
447 c->x86_power = cpuid_edx(0x80000007);
448
87a1c441
YL		 449 if (c->extended_cpuid_level >= 0x80000008) {
450 u32 eax = cpuid_eax(0x80000008);
451
452 c->x86_virt_bits = (eax >> 8) & 0xff;
453 c->x86_phys_bits = eax & 0xff;
454 }
f580366f
YL		 455}
456
3da99c97
YL		 457/* Do some early cpuid on the boot CPU to get some parameter that are
458 needed before check_bugs. Everything advanced is in identify_cpu
459 below. */
460static void __init early_identify_cpu(struct cpuinfo_x86 *c)
f580366f 461{
3da99c97
YL		 462
463 c->x86_clflush_size = 64;
464 c->x86_cache_alignment = c->x86_clflush_size;
465
466 memset(&c->x86_capability, 0, sizeof c->x86_capability);
467
468 c->extended_cpuid_level = 0;
469
470 cpu_detect(c);
471
472 get_cpu_vendor(c);
473
474 get_cpu_cap(c);
7e00df58 475
10a434fc
YL		 476 if (this_cpu->c_early_init)
477 this_cpu->c_early_init(c);
f580366f
YL		 478
479 validate_pat_support(c);
f580366f
YL		 480}
481
3da99c97
YL		 482void __init early_cpu_init(void)
483{
10a434fc
YL		 484 struct cpu_dev **cdev;
485 int count = 0;
f580366f
YL		 486
487 printk("KERNEL supported cpus:\n");
10a434fc
YL		 488 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
489 struct cpu_dev *cpudev = *cdev;
490 unsigned int j;
3da99c97 491
10a434fc
YL		 492 if (count >= X86_VENDOR_NUM)
493 break;
494 cpu_devs[count] = cpudev;
495 count++;
496
f580366f 497 for (j = 0; j < 2; j++) {
10a434fc 498 if (!cpudev->c_ident[j])
f580366f 499 continue;
10a434fc
YL		 500 printk(" %s %s\n", cpudev->c_vendor,
501 cpudev->c_ident[j]);
f580366f
YL		 502 }
503 }
3da99c97 504
3da99c97 505 early_identify_cpu(&boot_cpu_data);
f580366f
YL		 506}
507
7e00df58
PA		 508/*
509 * The NOPL instruction is supposed to exist on all CPUs with
510 * family >= 6, unfortunately, that's not true in practice because
511 * of early VIA chips and (more importantly) broken virtualizers that
512 * are not easy to detect. Hence, probe for it based on first
513 * principles.
514 *
515 * Note: no 64-bit chip is known to lack these, but put the code here
516 * for consistency with 32 bits, and to make it utterly trivial to
517 * diagnose the problem should it ever surface.
518 */
519static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
520{
521 const u32 nopl_signature = 0x888c53b1; /* Random number */
522 u32 has_nopl = nopl_signature;
523
524 clear_cpu_cap(c, X86_FEATURE_NOPL);
525 if (c->x86 >= 6) {
526 asm volatile("\n"
527 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
528 "2:\n"
529 " .section .fixup,\"ax\"\n"
530 "3: xor %0,%0\n"
531 " jmp 2b\n"
532 " .previous\n"
533 _ASM_EXTABLE(1b,3b)
534 : "+a" (has_nopl));
535
536 if (has_nopl == nopl_signature)
537 set_cpu_cap(c, X86_FEATURE_NOPL);
538 }
539}
540
3da99c97 541static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
f580366f 542{
f580366f 543 c->extended_cpuid_level = 0;
f580366f 544
3da99c97 545 cpu_detect(c);
f580366f
YL		 546
547 get_cpu_vendor(c);
548
3da99c97 549 get_cpu_cap(c);
f580366f
YL		 550
551 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
552#ifdef CONFIG_SMP
553 c->phys_proc_id = c->initial_apicid;
554#endif
f580366f 555
3da99c97
YL		 556 if (c->extended_cpuid_level >= 0x80000004)
557 get_model_name(c); /* Default name */
87a1c441 558
3da99c97 559 init_scattered_cpuid_features(c);
7e00df58 560 detect_nopl(c);
f580366f
YL		 561}
562
563/*
564 * This does the hard work of actually picking apart the CPU stuff...
565 */
9a250347 566static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
f580366f
YL		 567{
568 int i;
569
3da99c97
YL		 570 c->loops_per_jiffy = loops_per_jiffy;
571 c->x86_cache_size = -1;
572 c->x86_vendor = X86_VENDOR_UNKNOWN;
573 c->x86_model = c->x86_mask = 0; /* So far unknown... */
574 c->x86_vendor_id[0] = '\0'; /* Unset */
575 c->x86_model_id[0] = '\0'; /* Unset */
3da99c97
YL		 576 c->x86_max_cores = 1;
577 c->x86_coreid_bits = 0;
0a488a53
YL		 578 c->x86_clflush_size = 64;
579 c->x86_cache_alignment = c->x86_clflush_size;
3da99c97 580 memset(&c->x86_capability, 0, sizeof c->x86_capability);
f580366f 581
3da99c97 582 generic_identify(c);
f580366f
YL		 583
584 c->apicid = phys_pkg_id(0);
585
586 /*
587 * Vendor-specific initialization. In this section we
588 * canonicalize the feature flags, meaning if there are
589 * features a certain CPU supports which CPUID doesn't
590 * tell us, CPUID claiming incorrect flags, or other bugs,
591 * we handle them here.
592 *
593 * At the end of this section, c->x86_capability better
594 * indicate the features this CPU genuinely supports!
595 */
596 if (this_cpu->c_init)
597 this_cpu->c_init(c);
598
599 detect_ht(c);
600
601 /*
602 * On SMP, boot_cpu_data holds the common feature set between
603 * all CPUs; so make sure that we indicate which features are
604 * common between the CPUs. The first time this routine gets
605 * executed, c == &boot_cpu_data.
606 */
607 if (c != &boot_cpu_data) {
608 /* AND the already accumulated flags with these */
609 for (i = 0; i < NCAPINTS; i++)
610 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
611 }
612
613 /* Clear all flags overriden by options */
614 for (i = 0; i < NCAPINTS; i++)
615 c->x86_capability[i] &= ~cleared_cpu_caps[i];
616
617#ifdef CONFIG_X86_MCE
618 mcheck_init(c);
619#endif
620 select_idle_routine(c);
621
622#ifdef CONFIG_NUMA
623 numa_add_cpu(smp_processor_id());
624#endif
625
626}
627
9d31d35b 628void __init identify_boot_cpu(void)
f580366f
YL		 629{
630 identify_cpu(&boot_cpu_data);
631}
632
633void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
634{
635 BUG_ON(c == &boot_cpu_data);
636 identify_cpu(c);
637 mtrr_ap_init();
638}
639
b05f78f5
YL		 640struct msr_range {
641 unsigned min;
642 unsigned max;
643};
644
645static struct msr_range msr_range_array[] __cpuinitdata = {
646 { 0x00000000, 0x00000418},
647 { 0xc0000000, 0xc000040b},
648 { 0xc0010000, 0xc0010142},
649 { 0xc0011000, 0xc001103b},
650};
651
652static void __cpuinit print_cpu_msr(void)
653{
654 unsigned index;
655 u64 val;
656 int i;
657 unsigned index_min, index_max;
658
659 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
660 index_min = msr_range_array[i].min;
661 index_max = msr_range_array[i].max;
662 for (index = index_min; index < index_max; index++) {
663 if (rdmsrl_amd_safe(index, &val))
664 continue;
665 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
666 }
667 }
668}
669
670static int show_msr __cpuinitdata;
671static __init int setup_show_msr(char *arg)
672{
673 int num;
674
675 get_option(&arg, &num);
676
677 if (num > 0)
678 show_msr = num;
679 return 1;
680}
681__setup("show_msr=", setup_show_msr);
682
f580366f
YL		 683static __init int setup_noclflush(char *arg)
684{
685 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
686 return 1;
687}
688__setup("noclflush", setup_noclflush);
689
690void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
691{
692 if (c->x86_model_id[0])
693 printk(KERN_CONT "%s", c->x86_model_id);
694
695 if (c->x86_mask || c->cpuid_level >= 0)
696 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
697 else
698 printk(KERN_CONT "\n");
b05f78f5
YL		 699
700#ifdef CONFIG_SMP
701 if (c->cpu_index < show_msr)
702 print_cpu_msr();
703#else
704 if (show_msr)
705 print_cpu_msr();
706#endif
f580366f
YL		 707}
708
709static __init int setup_disablecpuid(char *arg)
710{
711 int bit;
712 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
713 setup_clear_cpu_cap(bit);
714 else
715 return 0;
716 return 1;
717}
718__setup("clearcpuid=", setup_disablecpuid);
0f0124fa 719
0f0124fa
YL		 720cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
721
d5494d4f 722#ifdef CONFIG_X86_64
0f0124fa
YL		 723struct x8664_pda **_cpu_pda __read_mostly;
724EXPORT_SYMBOL(_cpu_pda);
725
726struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
727
728char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
729
730unsigned long __supported_pte_mask __read_mostly = ~0UL;
731EXPORT_SYMBOL_GPL(__supported_pte_mask);
732
733static int do_not_nx __cpuinitdata;
734
735/* noexec=on|off
736Control non executable mappings for 64bit processes.
737
738on Enable(default)
739off Disable
740*/
741static int __init nonx_setup(char *str)
742{
743 if (!str)
744 return -EINVAL;
745 if (!strncmp(str, "on", 2)) {
746 __supported_pte_mask |= _PAGE_NX;
747 do_not_nx = 0;
748 } else if (!strncmp(str, "off", 3)) {
749 do_not_nx = 1;
750 __supported_pte_mask &= ~_PAGE_NX;
751 }
752 return 0;
753}
754early_param("noexec", nonx_setup);
755
756int force_personality32;
757
758/* noexec32=on|off
759Control non executable heap for 32bit processes.
760To control the stack too use noexec=off
761
762on PROT_READ does not imply PROT_EXEC for 32bit processes (default)
763off PROT_READ implies PROT_EXEC
764*/
765static int __init nonx32_setup(char *str)
766{
767 if (!strcmp(str, "on"))
768 force_personality32 &= ~READ_IMPLIES_EXEC;
769 else if (!strcmp(str, "off"))
770 force_personality32 |= READ_IMPLIES_EXEC;
771 return 1;
772}
773__setup("noexec32=", nonx32_setup);
774
775void pda_init(int cpu)
776{
777 struct x8664_pda *pda = cpu_pda(cpu);
778
779 /* Setup up data that may be needed in __get_free_pages early */
ada85708
JF		 780 loadsegment(fs, 0);
781 loadsegment(gs, 0);
0f0124fa
YL		 782 /* Memory clobbers used to order PDA accessed */
783 mb();
784 wrmsrl(MSR_GS_BASE, pda);
785 mb();
786
787 pda->cpunumber = cpu;
788 pda->irqcount = -1;
789 pda->kernelstack = (unsigned long)stack_thread_info() -
790 PDA_STACKOFFSET + THREAD_SIZE;
791 pda->active_mm = &init_mm;
792 pda->mmu_state = 0;
793
794 if (cpu == 0) {
795 /* others are initialized in smpboot.c */
796 pda->pcurrent = &init_task;
797 pda->irqstackptr = boot_cpu_stack;
49800efc 798 pda->irqstackptr += IRQSTACKSIZE - 64;
0f0124fa 799 } else {
49800efc
AH		 800 if (!pda->irqstackptr) {
801 pda->irqstackptr = (char *)
802 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
803 if (!pda->irqstackptr)
804 panic("cannot allocate irqstack for cpu %d",
805 cpu);
806 pda->irqstackptr += IRQSTACKSIZE - 64;
807 }
0f0124fa
YL		 808
809 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
810 pda->nodenumber = cpu_to_node(cpu);
811 }
0f0124fa
YL		 812}
813
814char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
cbcd79c2 815 DEBUG_STKSZ] __page_aligned_bss;
0f0124fa
YL		 816
817extern asmlinkage void ignore_sysret(void);
818
819/* May not be marked __init: used by software suspend */
820void syscall_init(void)
821{
822 /*
823 * LSTAR and STAR live in a bit strange symbiosis.
824 * They both write to the same internal register. STAR allows to
825 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
826 */
827 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
828 wrmsrl(MSR_LSTAR, system_call);
829 wrmsrl(MSR_CSTAR, ignore_sysret);
830
831#ifdef CONFIG_IA32_EMULATION
832 syscall32_cpu_init();
833#endif
834
835 /* Flags to clear on syscall */
836 wrmsrl(MSR_SYSCALL_MASK,
837 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
838}
839
840void __cpuinit check_efer(void)
841{
842 unsigned long efer;
843
844 rdmsrl(MSR_EFER, efer);
845 if (!(efer & EFER_NX) || do_not_nx)
846 __supported_pte_mask &= ~_PAGE_NX;
847}
848
849unsigned long kernel_eflags;
850
851/*
852 * Copies of the original ist values from the tss are only accessed during
853 * debugging, no special alignment required.
854 */
855DEFINE_PER_CPU(struct orig_ist, orig_ist);
856
d5494d4f
YL		 857#else
858
859/* Make sure %fs is initialized properly in idle threads */
860struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
861{
862 memset(regs, 0, sizeof(struct pt_regs));
863 regs->fs = __KERNEL_PERCPU;
864 return regs;
865}
866#endif
867
0f0124fa
YL		 868/*
869 * cpu_init() initializes state that is per-CPU. Some data is already
870 * initialized (naturally) in the bootstrap process, such as the GDT
871 * and IDT. We reload them nevertheless, this function acts as a
872 * 'CPU state barrier', nothing should get across.
1ba76586 873 * A lot of state is already set up in PDA init for 64 bit
0f0124fa 874 */
1ba76586 875#ifdef CONFIG_X86_64
0f0124fa
YL		 876void __cpuinit cpu_init(void)
877{
878 int cpu = stack_smp_processor_id();
879 struct tss_struct *t = &per_cpu(init_tss, cpu);
880 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
881 unsigned long v;
882 char *estacks = NULL;
883 struct task_struct *me;
884 int i;
885
886 /* CPU 0 is initialised in head64.c */
887 if (cpu != 0)
888 pda_init(cpu);
889 else
890 estacks = boot_exception_stacks;
891
892 me = current;
893
894 if (cpu_test_and_set(cpu, cpu_initialized))
895 panic("CPU#%d already initialized!\n", cpu);
896
897 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
898
899 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
900
901 /*
902 * Initialize the per-CPU GDT with the boot GDT,
903 * and set up the GDT descriptor:
904 */
905
906 switch_to_new_gdt();
907 load_idt((const struct desc_ptr *)&idt_descr);
908
909 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
910 syscall_init();
911
912 wrmsrl(MSR_FS_BASE, 0);
913 wrmsrl(MSR_KERNEL_GS_BASE, 0);
914 barrier();
915
916 check_efer();
6e1cb38a
SS		 917 if (cpu != 0 && x2apic)
918 enable_x2apic();
0f0124fa
YL		 919
920 /*
921 * set up and load the per-CPU TSS
922 */
b55793f7 923 if (!orig_ist->ist[0]) {
0f0124fa 924 static const unsigned int order[N_EXCEPTION_STACKS] = {
b55793f7
AH		 925 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
926 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
0f0124fa 927 };
b55793f7
AH		 928 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
929 if (cpu) {
930 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
931 if (!estacks)
932 panic("Cannot allocate exception "
933 "stack %ld %d\n", v, cpu);
934 }
935 estacks += PAGE_SIZE << order[v];
936 orig_ist->ist[v] = t->x86_tss.ist[v] =
937 (unsigned long)estacks;
0f0124fa 938 }
0f0124fa
YL		 939 }
940
941 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
942 /*
943 * <= is required because the CPU will access up to
944 * 8 bits beyond the end of the IO permission bitmap.
945 */
946 for (i = 0; i <= IO_BITMAP_LONGS; i++)
947 t->io_bitmap[i] = ~0UL;
948
949 atomic_inc(&init_mm.mm_count);
950 me->active_mm = &init_mm;
951 if (me->mm)
952 BUG();
953 enter_lazy_tlb(&init_mm, me);
954
955 load_sp0(t, &current->thread);
956 set_tss_desc(cpu, t);
957 load_TR_desc();
958 load_LDT(&init_mm.context);
959
960#ifdef CONFIG_KGDB
961 /*
962 * If the kgdb is connected no debug regs should be altered. This
963 * is only applicable when KGDB and a KGDB I/O module are built
964 * into the kernel and you are using early debugging with
965 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
966 */
967 if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
968 arch_kgdb_ops.correct_hw_break();
969 else {
970#endif
971 /*
972 * Clear all 6 debug registers:
973 */
974
975 set_debugreg(0UL, 0);
976 set_debugreg(0UL, 1);
977 set_debugreg(0UL, 2);
978 set_debugreg(0UL, 3);
979 set_debugreg(0UL, 6);
980 set_debugreg(0UL, 7);
981#ifdef CONFIG_KGDB
982 /* If the kgdb is connected no debug regs should be altered. */
983 }
984#endif
985
986 fpu_init();
987
988 raw_local_save_flags(kernel_eflags);
989
990 if (is_uv_system())
991 uv_cpu_init();
992}
1ba76586
YL		 993
994#else
995
996void __cpuinit cpu_init(void)
997{
998 int cpu = smp_processor_id();
999 struct task_struct *curr = current;
1000 struct tss_struct *t = &per_cpu(init_tss, cpu);
1001 struct thread_struct *thread = &curr->thread;
1002
1003 if (cpu_test_and_set(cpu, cpu_initialized)) {
1004 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1005 for (;;) local_irq_enable();
1006 }
1007
1008 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1009
1010 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1011 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1012
1013 load_idt(&idt_descr);
1014 switch_to_new_gdt();
1015
1016 /*
1017 * Set up and load the per-CPU TSS and LDT
1018 */
1019 atomic_inc(&init_mm.mm_count);
1020 curr->active_mm = &init_mm;
1021 if (curr->mm)
1022 BUG();
1023 enter_lazy_tlb(&init_mm, curr);
1024
1025 load_sp0(t, thread);
1026 set_tss_desc(cpu, t);
1027 load_TR_desc();
1028 load_LDT(&init_mm.context);
1029
1030#ifdef CONFIG_DOUBLEFAULT
1031 /* Set up doublefault TSS pointer in the GDT */
1032 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1033#endif
1034
1035 /* Clear %gs. */
1036 asm volatile ("mov %0, %%gs" : : "r" (0));
1037
1038 /* Clear all 6 debug registers: */
1039 set_debugreg(0, 0);
1040 set_debugreg(0, 1);
1041 set_debugreg(0, 2);
1042 set_debugreg(0, 3);
1043 set_debugreg(0, 6);
1044 set_debugreg(0, 7);
1045
1046 /*
1047 * Force FPU initialization:
1048 */
1049 if (cpu_has_xsave)
1050 current_thread_info()->status = TS_XSAVE;
1051 else
1052 current_thread_info()->status = 0;
1053 clear_used_math();
1054 mxcsr_feature_mask_init();
1055
1056 /*
1057 * Boot processor to setup the FP and extended state context info.
1058 */
1059 if (!smp_processor_id())
1060 init_thread_xstate();
1061
1062 xsave_init();
1063}
1064
1065#ifdef CONFIG_HOTPLUG_CPU
1066void __cpuinit cpu_uninit(void)
1067{
1068 int cpu = raw_smp_processor_id();
1069 cpu_clear(cpu, cpu_initialized);
1070
1071 /* lazy TLB state */
1072 per_cpu(cpu_tlbstate, cpu).state = 0;
1073 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
1074}
1075#endif
1076
1077#endif
Linux kernel - Deliverables
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