Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Pentium 4/Xeon CPU on demand clock modulation/speed scaling | |
3 | * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de> | |
4 | * (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com> | |
5 | * (C) 2002 Arjan van de Ven <arjanv@redhat.com> | |
6 | * (C) 2002 Tora T. Engstad | |
7 | * All Rights Reserved | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * The author(s) of this software shall not be held liable for damages | |
15 | * of any nature resulting due to the use of this software. This | |
16 | * software is provided AS-IS with no warranties. | |
32ee8c3e | 17 | * |
1da177e4 LT |
18 | * Date Errata Description |
19 | * 20020525 N44, O17 12.5% or 25% DC causes lockup | |
20 | * | |
21 | */ | |
22 | ||
1da177e4 | 23 | #include <linux/kernel.h> |
32ee8c3e | 24 | #include <linux/module.h> |
1da177e4 LT |
25 | #include <linux/init.h> |
26 | #include <linux/smp.h> | |
27 | #include <linux/cpufreq.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/cpumask.h> | |
bbfebd66 | 30 | #include <linux/timex.h> |
1da177e4 | 31 | |
32ee8c3e | 32 | #include <asm/processor.h> |
1da177e4 | 33 | #include <asm/msr.h> |
199785ea | 34 | #include <asm/timer.h> |
1da177e4 LT |
35 | |
36 | #include "speedstep-lib.h" | |
37 | ||
38 | #define PFX "p4-clockmod: " | |
bbfebd66 DJ |
39 | #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \ |
40 | "p4-clockmod", msg) | |
1da177e4 LT |
41 | |
42 | /* | |
43 | * Duty Cycle (3bits), note DC_DISABLE is not specified in | |
44 | * intel docs i just use it to mean disable | |
45 | */ | |
46 | enum { | |
47 | DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT, | |
48 | DC_64PT, DC_75PT, DC_88PT, DC_DISABLE | |
49 | }; | |
50 | ||
51 | #define DC_ENTRIES 8 | |
52 | ||
53 | ||
54 | static int has_N44_O17_errata[NR_CPUS]; | |
55 | static unsigned int stock_freq; | |
56 | static struct cpufreq_driver p4clockmod_driver; | |
57 | static unsigned int cpufreq_p4_get(unsigned int cpu); | |
58 | ||
59 | static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate) | |
60 | { | |
61 | u32 l, h; | |
62 | ||
bbfebd66 DJ |
63 | if (!cpu_online(cpu) || |
64 | (newstate > DC_DISABLE) || (newstate == DC_RESV)) | |
1da177e4 LT |
65 | return -EINVAL; |
66 | ||
551948bc | 67 | rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h); |
1da177e4 LT |
68 | |
69 | if (l & 0x01) | |
70 | dprintk("CPU#%d currently thermal throttled\n", cpu); | |
71 | ||
bbfebd66 DJ |
72 | if (has_N44_O17_errata[cpu] && |
73 | (newstate == DC_25PT || newstate == DC_DFLT)) | |
1da177e4 LT |
74 | newstate = DC_38PT; |
75 | ||
551948bc | 76 | rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h); |
1da177e4 LT |
77 | if (newstate == DC_DISABLE) { |
78 | dprintk("CPU#%d disabling modulation\n", cpu); | |
551948bc | 79 | wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h); |
1da177e4 LT |
80 | } else { |
81 | dprintk("CPU#%d setting duty cycle to %d%%\n", | |
82 | cpu, ((125 * newstate) / 10)); | |
32ee8c3e | 83 | /* bits 63 - 5 : reserved |
1da177e4 LT |
84 | * bit 4 : enable/disable |
85 | * bits 3-1 : duty cycle | |
86 | * bit 0 : reserved | |
87 | */ | |
88 | l = (l & ~14); | |
89 | l = l | (1<<4) | ((newstate & 0x7)<<1); | |
551948bc | 90 | wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h); |
1da177e4 LT |
91 | } |
92 | ||
93 | return 0; | |
94 | } | |
95 | ||
96 | ||
97 | static struct cpufreq_frequency_table p4clockmod_table[] = { | |
98 | {DC_RESV, CPUFREQ_ENTRY_INVALID}, | |
99 | {DC_DFLT, 0}, | |
100 | {DC_25PT, 0}, | |
101 | {DC_38PT, 0}, | |
102 | {DC_50PT, 0}, | |
103 | {DC_64PT, 0}, | |
104 | {DC_75PT, 0}, | |
105 | {DC_88PT, 0}, | |
106 | {DC_DISABLE, 0}, | |
107 | {DC_RESV, CPUFREQ_TABLE_END}, | |
108 | }; | |
109 | ||
110 | ||
111 | static int cpufreq_p4_target(struct cpufreq_policy *policy, | |
112 | unsigned int target_freq, | |
113 | unsigned int relation) | |
114 | { | |
115 | unsigned int newstate = DC_RESV; | |
116 | struct cpufreq_freqs freqs; | |
1da177e4 LT |
117 | int i; |
118 | ||
bbfebd66 DJ |
119 | if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0], |
120 | target_freq, relation, &newstate)) | |
1da177e4 LT |
121 | return -EINVAL; |
122 | ||
123 | freqs.old = cpufreq_p4_get(policy->cpu); | |
124 | freqs.new = stock_freq * p4clockmod_table[newstate].index / 8; | |
125 | ||
126 | if (freqs.new == freqs.old) | |
127 | return 0; | |
128 | ||
129 | /* notifiers */ | |
835481d9 | 130 | for_each_cpu(i, policy->cpus) { |
1da177e4 LT |
131 | freqs.cpu = i; |
132 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
133 | } | |
134 | ||
bbfebd66 DJ |
135 | /* run on each logical CPU, |
136 | * see section 13.15.3 of IA32 Intel Architecture Software | |
32ee8c3e | 137 | * Developer's Manual, Volume 3 |
1da177e4 | 138 | */ |
835481d9 | 139 | for_each_cpu(i, policy->cpus) |
1da177e4 | 140 | cpufreq_p4_setdc(i, p4clockmod_table[newstate].index); |
1da177e4 LT |
141 | |
142 | /* notifiers */ | |
835481d9 | 143 | for_each_cpu(i, policy->cpus) { |
1da177e4 LT |
144 | freqs.cpu = i; |
145 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
146 | } | |
147 | ||
148 | return 0; | |
149 | } | |
150 | ||
151 | ||
152 | static int cpufreq_p4_verify(struct cpufreq_policy *policy) | |
153 | { | |
154 | return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]); | |
155 | } | |
156 | ||
157 | ||
158 | static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c) | |
159 | { | |
4e74663c DB |
160 | if (c->x86 == 0x06) { |
161 | if (cpu_has(c, X86_FEATURE_EST)) | |
bbfebd66 DJ |
162 | printk(KERN_WARNING PFX "Warning: EST-capable CPU " |
163 | "detected. The acpi-cpufreq module offers " | |
164 | "voltage scaling in addition of frequency " | |
165 | "scaling. You should use that instead of " | |
166 | "p4-clockmod, if possible.\n"); | |
4e74663c DB |
167 | switch (c->x86_model) { |
168 | case 0x0E: /* Core */ | |
169 | case 0x0F: /* Core Duo */ | |
8529154e | 170 | case 0x16: /* Celeron Core */ |
4e74663c | 171 | p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS; |
bbfebd66 | 172 | return speedstep_get_frequency(SPEEDSTEP_CPU_PCORE); |
4e74663c DB |
173 | case 0x0D: /* Pentium M (Dothan) */ |
174 | p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS; | |
175 | /* fall through */ | |
176 | case 0x09: /* Pentium M (Banias) */ | |
bbfebd66 | 177 | return speedstep_get_frequency(SPEEDSTEP_CPU_PM); |
4e74663c | 178 | } |
1da177e4 LT |
179 | } |
180 | ||
181 | if (c->x86 != 0xF) { | |
10db2e5c | 182 | if (!cpu_has(c, X86_FEATURE_EST)) |
bbfebd66 DJ |
183 | printk(KERN_WARNING PFX "Unknown CPU. " |
184 | "Please send an e-mail to " | |
185 | "<cpufreq@vger.kernel.org>\n"); | |
1da177e4 LT |
186 | return 0; |
187 | } | |
188 | ||
189 | /* on P-4s, the TSC runs with constant frequency independent whether | |
190 | * throttling is active or not. */ | |
191 | p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS; | |
192 | ||
bbfebd66 | 193 | if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4M) { |
1da177e4 LT |
194 | printk(KERN_WARNING PFX "Warning: Pentium 4-M detected. " |
195 | "The speedstep-ich or acpi cpufreq modules offer " | |
196 | "voltage scaling in addition of frequency scaling. " | |
197 | "You should use either one instead of p4-clockmod, " | |
198 | "if possible.\n"); | |
bbfebd66 | 199 | return speedstep_get_frequency(SPEEDSTEP_CPU_P4M); |
1da177e4 LT |
200 | } |
201 | ||
bbfebd66 | 202 | return speedstep_get_frequency(SPEEDSTEP_CPU_P4D); |
1da177e4 LT |
203 | } |
204 | ||
32ee8c3e | 205 | |
1da177e4 LT |
206 | |
207 | static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy) | |
208 | { | |
92cb7612 | 209 | struct cpuinfo_x86 *c = &cpu_data(policy->cpu); |
1da177e4 LT |
210 | int cpuid = 0; |
211 | unsigned int i; | |
212 | ||
213 | #ifdef CONFIG_SMP | |
835481d9 | 214 | cpumask_copy(policy->cpus, &per_cpu(cpu_sibling_map, policy->cpu)); |
1da177e4 LT |
215 | #endif |
216 | ||
217 | /* Errata workaround */ | |
218 | cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask; | |
219 | switch (cpuid) { | |
220 | case 0x0f07: | |
221 | case 0x0f0a: | |
222 | case 0x0f11: | |
223 | case 0x0f12: | |
224 | has_N44_O17_errata[policy->cpu] = 1; | |
225 | dprintk("has errata -- disabling low frequencies\n"); | |
226 | } | |
32ee8c3e | 227 | |
199785ea MCO |
228 | if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4D && |
229 | c->x86_model < 2) { | |
230 | /* switch to maximum frequency and measure result */ | |
231 | cpufreq_p4_setdc(policy->cpu, DC_DISABLE); | |
232 | recalibrate_cpu_khz(); | |
233 | } | |
1da177e4 LT |
234 | /* get max frequency */ |
235 | stock_freq = cpufreq_p4_get_frequency(c); | |
236 | if (!stock_freq) | |
237 | return -EINVAL; | |
238 | ||
239 | /* table init */ | |
bbfebd66 DJ |
240 | for (i = 1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) { |
241 | if ((i < 2) && (has_N44_O17_errata[policy->cpu])) | |
1da177e4 LT |
242 | p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID; |
243 | else | |
244 | p4clockmod_table[i].frequency = (stock_freq * i)/8; | |
245 | } | |
246 | cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu); | |
32ee8c3e | 247 | |
1da177e4 | 248 | /* cpuinfo and default policy values */ |
1da177e4 LT |
249 | policy->cpuinfo.transition_latency = 1000000; /* assumed */ |
250 | policy->cur = stock_freq; | |
251 | ||
252 | return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]); | |
253 | } | |
254 | ||
255 | ||
256 | static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy) | |
257 | { | |
32ee8c3e | 258 | cpufreq_frequency_table_put_attr(policy->cpu); |
1da177e4 LT |
259 | return 0; |
260 | } | |
261 | ||
262 | static unsigned int cpufreq_p4_get(unsigned int cpu) | |
263 | { | |
1da177e4 LT |
264 | u32 l, h; |
265 | ||
551948bc | 266 | rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h); |
1da177e4 LT |
267 | |
268 | if (l & 0x10) { | |
269 | l = l >> 1; | |
270 | l &= 0x7; | |
271 | } else | |
272 | l = DC_DISABLE; | |
273 | ||
274 | if (l != DC_DISABLE) | |
bbfebd66 | 275 | return stock_freq * l / 8; |
1da177e4 LT |
276 | |
277 | return stock_freq; | |
278 | } | |
279 | ||
bbfebd66 | 280 | static struct freq_attr *p4clockmod_attr[] = { |
1da177e4 LT |
281 | &cpufreq_freq_attr_scaling_available_freqs, |
282 | NULL, | |
283 | }; | |
284 | ||
285 | static struct cpufreq_driver p4clockmod_driver = { | |
32ee8c3e | 286 | .verify = cpufreq_p4_verify, |
1da177e4 LT |
287 | .target = cpufreq_p4_target, |
288 | .init = cpufreq_p4_cpu_init, | |
289 | .exit = cpufreq_p4_cpu_exit, | |
290 | .get = cpufreq_p4_get, | |
291 | .name = "p4-clockmod", | |
292 | .owner = THIS_MODULE, | |
293 | .attr = p4clockmod_attr, | |
e088e4c9 | 294 | .hide_interface = 1, |
1da177e4 LT |
295 | }; |
296 | ||
297 | ||
298 | static int __init cpufreq_p4_init(void) | |
32ee8c3e | 299 | { |
92cb7612 | 300 | struct cpuinfo_x86 *c = &cpu_data(0); |
1da177e4 LT |
301 | int ret; |
302 | ||
303 | /* | |
32ee8c3e | 304 | * THERM_CONTROL is architectural for IA32 now, so |
1da177e4 LT |
305 | * we can rely on the capability checks |
306 | */ | |
307 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
308 | return -ENODEV; | |
309 | ||
8ce116e5 IM |
310 | if (!test_cpu_cap(c, X86_FEATURE_ACPI) || |
311 | !test_cpu_cap(c, X86_FEATURE_ACC)) | |
1da177e4 LT |
312 | return -ENODEV; |
313 | ||
314 | ret = cpufreq_register_driver(&p4clockmod_driver); | |
315 | if (!ret) | |
bbfebd66 DJ |
316 | printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock " |
317 | "Modulation available\n"); | |
1da177e4 | 318 | |
bbfebd66 | 319 | return ret; |
1da177e4 LT |
320 | } |
321 | ||
322 | ||
323 | static void __exit cpufreq_p4_exit(void) | |
324 | { | |
325 | cpufreq_unregister_driver(&p4clockmod_driver); | |
326 | } | |
327 | ||
328 | ||
bbfebd66 DJ |
329 | MODULE_AUTHOR("Zwane Mwaikambo <zwane@commfireservices.com>"); |
330 | MODULE_DESCRIPTION("cpufreq driver for Pentium(TM) 4/Xeon(TM)"); | |
331 | MODULE_LICENSE("GPL"); | |
1da177e4 LT |
332 | |
333 | late_initcall(cpufreq_p4_init); | |
334 | module_exit(cpufreq_p4_exit); |